DDR2-533 Memory Design Guide for Two-DIMM

TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Overview
Technical Note
DDR2-533 Memory Design Guide for Two-DIMM Unbuffered Systems
Overview
DDR2 memory busses vary depending on the intended market for the finished product.
Some products must support four or more registered DIMMs, while some are point-topoint topologies. This document focuses on solutions requiring two unbuffered DIMMs
operating at a data rate of 533 megabits per second (Mb/s) and is intended to assist
board designers with the development and implementation of their products.
The document consists of two sections. The first section uses data gathered from a
chipset and motherboard designed by Micron to provide a set of board-design rules.
These rules are meant to be a starting point for a board design. The second section
details the process of determining the portion of the total timing budget allotted to the
board interconnect. The intent is that board designers will use the first section to
develop a set of general rules and then, through simulation, verify the design in their
particular environments.
Introduction
Systems using unbuffered DIMMs can implement the address and command bus using
various configurations. For example, some controllers have two copies of the address
and command bus, so the system can have one or two DIMMs per copy, but never more
than two DIMMs total. Further, the address bus can be clocked using 1T or 2T clocking.
With 1T, a new command can be issued on every clock cycle. 2T timing will hold the
address and command bus valid for two clock cycles. This reduces the efficiency of the
bus to one command per two clocks, but it doubles the amount of setup and hold time.
The data bus remains the same for all of the variations in the address bus.
This design guide covers a DDR2 system using two unbuffered DIMMs, operating at a
533Mb/s data rate and two variations of the address and command bus. The first variation covered is a system with one DIMM per copy of the address and command bus
using 1T clocking. A block diagram of this topology is shown in Figure 1 on page 2. The
second variation is a system with two DIMMs on the address and command bus using
2T clocking topology, as shown in Figure 2 on page 3. Please note that the guidelines
provided in this section are intended to provide a set of rules for board designers to
follow, but it is always advisable to simulate the final implementation to ensure proper
functionality.
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All
information discussed herein is provided on an “as is” basis, without warranties of any kind. Products and specifications
discussed herein are subject to change by Micron without notice.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Introduction
Figure 1:
Two-DIMM Unbuffered DDR2-533 MHz Topology 1T Address and Command Bus
Command/Address Copy 2
S#[1:0], CKE[1:0], ODT[1:0]
S#[3:2], CKE[3:2], ODT[3:2]
CLK1, CLK1#
CLK2, CLK2#
CLK3, CLK3#
CLK4, CLK4#
DDR2 DIMM
CLK0, CLK0#
DDR2 DIMM
DDR2
Memory
Controller
VTT
Regulator
Command/Address Copy 1
Parallel Termination Resistors
VREF
CLK5, CLK5#
DQS[8:0]/DQS#[8:0]
DQS[63:0], DM[8:0], CB[7:0]
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Introduction
Figure 2:
Two-DIMM Unbuffered DDR2-533 MHz Topology 2T Address and Command Bus
S#[3:2], CKE[3:2], ODT[3:2]
CLK1, CLK1#
CLK2, CLK2#
CLK3, CLK3#
CLK4, CLK4#
DDR2 DIMM
CLK0, CLK0#
DDR2 DIMM
DDR2
Memory
Controller
VTT
S#[1:0], CKE[1:0], ODT[1:0]
Regulator
Command/Address
Parallel Termination Resistors
VREF
CLK5, CLK5#
DQS[8:0]/DQS#[8:0]
DQS[63:0], DM[8:0], CB[7:0]
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Signal Grouping
DDR2 Signal Grouping
The signals that compose a DDR2 memory bus can be divided into four unique groupings, each with its own configuration and routing rules.
• Data Group: Data Strobe DQS[8:0], Data Strobe Complement DQS#[8:0](Optional),
Data Mask DM[8:0], Data DQ[63:0], and Check Bits CB[7:0]
• Address and Command Group: Bank Address BA[2:0], Address A[15:0], and
Command Inputs RAS#, CAS#, and WE#.
• Control Group: Chip Select S[3:0]#, Clock Enable CKE[3:0], and On-die Termination
ODT[3:0]
• Clock Group: Differential Clocks CK[5:0] and CK#[5:0]
Board Stackup
A two-DIMM DDR2 channel can be routed on a four-layer board. The layout should be
done using controlled impedance traces of Zo = 50Ω (±10%) characteristic impedance. A
sample stackup is shown in Figure 3. The trace impedance is based on a 5-mil-wide trace
and 1/2 oz. copper with a dielectric constant of 4.2 for the FR4 prepreg material. This
stackup assumes that the 1/2 oz. copper on the outer layers is plated, for a total thickness of 2.1 mils. Other solutions exist for achiving a 50Ω characteristic impedance, so
board designers should work with their PCB vendors to specify a stackup.
Figure 3:
Sample Board Stackup
Component Side - Signal Layer 1
(0.5 oz. cu.)
3.5 mil Prepreg
Ground Plane
(1 oz. cu.)
~42 mil Core
3.5 mil Prepreg
Power Plane
(1 oz. cu.)
Solder Side - Signal Layer 2
(0.5 oz. cu.)
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Address and Command Signals - 2T Clocking
Address and Command Signals - 2T Clocking
On a DDR2 memory bus, the address and command signals are unidirectional signals
driven by the memory controller. For DDR2-533 using 2T on the address and command
signals, the address and command bus runs at a max switching rate of 133 MHz. The
address and command signals are captured at the DRAM using the memory clocks. For a
system with two unbuffered DIMMs on a single address and command bus, the loading
on these signals will differ greatly depending on the type and number of DIMMs
installed. A two-DIMM channel loaded with two double-sided DIMMs has 36 loads on
the address and command signals. Under this heavy loading, the slew rate on the
address bus is slow. The reduced slew rate makes it difficult, if not impossible, to meet
the setup and hold times at the DRAM. To address this issue, the controller can use 2T
address timing—increasing the time available for the address command bus by one
clock period. Note that S#, ODT, and CKE timing does not change between 1T and 2T
addressing.
2T Address and Command Routing Rules
It is important that the address and command lines be referenced to a solid VDD power
plane. VDD is the 1.8V supply that also supplies power to the DRAM on the DIMM. On a
four-layer board, the address and command would typically be routed on the second
signal layer referenced to a solid power plane. The system address and command signals
should be power referenced over the entire bus to provide a low-impedance current
return path. The DDR2 Unbuffered DIMMs also reference the address and control
signals to VDD so the power reference is maintained onto the module. The address and
command signals should be routed away from the data group signals, from the
controller to the first DIMM. Address and command signals are captured at the DIMM
using the clock signals, so they must maintain a length relationship to the clock signals
at the DIMM.
Figure 4:
DDR2 Address and Command Signal Group 2T Routing Topology
Pad on Die
Pin on Package
DIMM 1
DIMM 2
VTT
Address and
Control
A
Rp
B
C
D
DDR2
Memory
Controller
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Address and Command Signals - 2T Clocking
Table 1:
Address and Command Group 2T Routing Rules
Length
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the ASIC package.)
B = 1.9in.–4.5in.
C = 0.425in.
D = 0.2in.–0.55in.
Total: A + B + C = 2.5in.–5.0in.
Length Matching
+200 mils of memory clock length at the DIMM1
Trace
Trace width = 5 mils–target 50 or 60Ω impedance
Trace space = 12–15 mils reducing to 11.5 mils going between the pins of the DIMM
Trace space from DIMM pins = 7 mils
Trace space to other signal groups = 20–25 mils
Notes:
1. This value is controller-dependent; see “Clock Signal Routing Rules” on page 16.
Parallel/Pull-up Resistor (Rp) Termination Resistor
• Location: The parallel termination resistors should be placed behind the last DIMM
slot and attached to the VTT power island.
• Value: The value of the parallel resistor can vary depending on the bus topology.
• Range: 36Ω–56Ω
• Recommended: 47Ω
Note:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
These are recommended values. A range of values is provided for simulation when
there is a need to deviate from the recommendation.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Address and Command Signals - 1T Clocking
Address and Command Signals - 1T Clocking
On a DDR2 memory bus, the address and command signals are unidirectional signals
that are always driven by the memory controller. For DDR2-533, the address runs at a
clock rate of 266 MHz. The address and command signals are captured at the DRAM
using the memory clocks. For a system with two unbuffered DIMMs on a single address
and command bus, the loading on these signals will differ greatly depending on the type
and number of DIMMs installed. A two-DIMM channel loaded with two double-sided
DIMMs has 36 loads on the address and command signals. The heavy capacitive load
causes a significant reduction in signal slew rate and voltage margin at the DRAM. The
reduced voltage margin causes a reduction in timing margin. As a result, setup and hold
times at the DRAM may not be met.
To increase the timing margin, the loading on the address and command bus must be
reduced. Some controllers will provide two copies of the address and command bus.
One copy is connected to each DIMM, reducing the total maximum load on the bus to 18
loads. By reducing the maximum loading, the timing margin is increased to a point that
1T timing of the address bus is achievable. Figure 5 on page 7 shows a block diagram of
the address and command bus for 1T timing.
The addition of an extra copy of address and command signals helps improve the
signaling but the reduction in loading alone may not be enough to meet setup and hold
times for 1T signals. The addition of a compensation capacitor to the address and
command signals will further improve the signal quality. Figure 6 on page 8 shows the
difference in signal quality between a system with the compensation capacitor and one
without it. These simulation results clearly show the improvements in signal quality and
as a result improved address valid window when the compensation capacitor is added to
the address and command signals.
Figure 5:
DDR2 Address and Command Signal Group 1T Routing Topology
Pad on Die
Pin on Package
DIMM 1
DIMM 2
VTT
Address and
Command Copy 1
A
Rp
B
C
D
Ccomp
A
DDR2
Memory
Controller
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
B
Rp
C
Address and
Command Copy 2
D
Ccomp
Note: Each copy of the
Address and Command bus
only goes to one DIMM
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Address and Command Signals - 1T Clocking
Figure 6:
DDR2 Address Compensation Capacitor Signal Quality Improvements
With Compensation Capacitor
No Compensation Capacitor
Table 2:
Address and Command Group 1T Routing Rules
Length
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the ASIC package.)
B = 1.9in.–4.5in.
C = 0.425in.
D = 0.2in.–0.55in.
Total: A + B + C = 2.5in.–5.0in.
Length Matching
+200 mils of memory clock length at the DIMM1
Trace
Trace width = 5 mils–target 50Ω impedance
Trace space = 12–15 mils reducing to 11.5 mils going between the pins of the DIMM
Trace space from DIMM pins = 7 mils
Trace space to other signal groups = 20–25 mils
Notes:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
1. This value is controller-dependent; see “Clock Signal Routing Rules” on page 16.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Address and Command Signals - 1T Clocking
1T Address and Command Routing Rules
It is important that the address and command lines be referenced to a solid power or
ground plane. On a four-layer board, the address and command would typically be
routed on the second signal layer referenced to a solid power plane. The system address
and command signals should be power-referenced over the entire bus to provide a lowimpedance current-return path. The address and command signals should be kept from
the data group signals, from the controller to the first DIMM. Address and command
signals are captured at the DIMM using the clock signals, so they must maintain a length
relationship to the clock signals at the DIMM.
Compensation Capacitor
•
•
•
•
Note:
(Ccomp)
Location: Ccomp is placed 0.5in. to 1.0in. from the first DIMM slot.
Value: The value of Ccomp can vary depending on the bus topology.
Recommended: 24pF
Range: 18-27pF
These are recommended values. A range of values is provided for simulation when
there is a need to deviate from the recommendation.
Parallel/Pull-Up Resistor (Rp) Termination Resistor
• Location: The parallel termination resistors should be placed behind the last DIMM
slot and attached to the VTT power island.
• Value: The value of the parallel resistor can vary depending on the bus topology.
• Range: 36Ω–56Ω
• Recommended: 47Ω
Note:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
These are recommended values. A range of values is provided for simulation when
there is a need to deviate from the recommendation.
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Control Signals
Control Signals
The control signals in a DDR2 system differ from the address in two ways. First, the
control signals must use 1T timing. Second, each DIMM rank has its own copy of the
control signals. A new feature introduced with DDR2 is on-die termination (ODT)
signals.
ODT signals are used to control the termination of the data group signals in the DDR2
DRAM device. DDR2 no longer uses the serial and parallel termination resistors on the
data group signals that are used in DDR systems. DDR2 uses a new termination scheme,
with the signals terminated in the DRAM device and the controller by internal termination resistors. ODT signals are used to enable or disable the termination in the DRAM
depending on the type of bus transition and the system load. Table 3 on page 10 and
Table 4 on page 10 show the termination values used for reads and writes. Figure 7 on
page 11 shows a block diagram of the topology used for the control signals. A compensation capacitor is not required on the motherboard for the control signals. The compensation capacitor for the control signals has been placed on the unbuffered DIMMs.
Table 3:
DDR2 ODT Control for Write Case
Configuration
Write to
Controller
Module 1
Module 2
1 slot populated
Slot 1
Slot 2
Slot 1
Slot 2
Infinite
Infinite
Infinite
Infinite
150Ω
Empty
Infinite
75Ω
Empty
150Ω
75Ω
Infinite
2 slots populated
Table 4:
DDR2 ODT Control for Write Case
Configuration
Write to
Controller
Module 1
Module 2
1 slot populated
Slot 1
Slot 2
Slot 1
Slot 2
75Ω
75Ω
150Ω
150Ω
Infinite
Empty
Infinite
75Ω
Empty
Infinite
75Ω
Infinite
2 slots populated
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Control Signals
Figure 7:
DDR2 Control Signal Group Routing Topology
Pad on Die
Pin on Package
DIMM 1
DIMM 2
CS[3:2], CKE[3:2], ODT[3:2]
A
B
VTT
Rp
C
D
Rp
A
B
C
D
CS[1:0], CKE[1:0], ODT[1:0]
DDR2
Memory
Controller
Table 5:
Control Group Routing Rules
Length
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the ASIC package.)
B = 1.9in.–4.5in.
C = 0.425in.
D = 0.2in.–0.55in.
Total: A + B + C = 2.5in.–6.0in.
Length Matching
+200 mils of memory clock length at the DIMM1
Trace
Trace width = 5 mils–target 50Ω impedance
Trace space = 12–15 mils reducing to 11.5 mils going between the pins of the DIMM
Trace space from DIMM pins = 7 mils
Trace space to other signal groups = 20–25 mils
Notes:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
1. This value is controller-dependent; see “Clock Signal Routing Rules” on page 16.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Control Signals
Control Signal Routing Rules
Like the address signals, the control signals must be referenced to a solid power or
ground plane. On a four-layer board, the control signals would typically be routed on the
second signal layer referenced to a solid power plane. The system control signals must
be power-referenced over the entire bus to provide a low-impedance current-return
path. Unlike the address signals, the control signals are routed point-to-point from the
controller to the DIMM. The control signals do not require any series or parallel resistance. The control signals must be routed with clearance from the data group signals,
from the controller to the first DIMM. Control signals are captured at the DIMM using
the clock signals, so they must maintain a length relationship to the clock signals at the
DIMM.
Parallel/Pull-Up Resistor (Rp) Termination Resistor
• Location: The parallel termination resistors should be placed behind the last DIMM
slot and attached to the VTT power island.
• Value: The value of the parallel resistor can vary depending on the bus topology.
• Range: 36Ω–56Ω
• Recommended: 47Ω
Note:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
These are recommended values. A range of values is provided for simulation when
there is a need to deviate from the recommendation.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Data Signals
Data Signals
In a DDR2 system, the data is captured by the memory and the controller using the data
strobe rather than the clock. DDR2 also has the option of having data strobe complement (DQS#) signals. If the data strobe complement signals are implemented, they must
be routed as a differential pair with the data strobe. To achieve the double data rate, data
is captured on the rising and falling edges of the data strobe (DQS) or each crossing
point if using DQS/DQS# pairs. Each 8 bits of data has an associated data strobe (DQS),
optional data strobe complement (DQS#), and a data mask bit (DM). Because the data is
captured off the strobe, the data bits associated with the strobe must be length-matched
closely to their strobe bit. This group of data and data strobe is referred to as a byte lane.
The length-matching between byte lanes is not as tight as it is within the byte lane.
Table 6 shows the data and data strobe byte lane groups. Figure 8 on page 15 shows the
signals in a single-byte lane and the bus topology for the data signals.
Data Signal Routing Rules
It is important that the data lines be referenced to a solid ground plane. These highspeed data signals require a good ground-return path to avoid degradation of signal
quality due to inductance in the signal-return path. The system data signals should be
ground-referenced from the memory controller to the DIMM connectors and from
DIMM connector to DIMM connector to provide a low-impedance current-return path.
This is accomplished by routing the data signals on the top layer for the entire length of
the signal. The data signals should not have any vias.
Table 6:
Data to Data Strobe Grouping
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
Data
Data Strobe
Data Strobe Complement
Data Mask
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
DQ[39:32]
DQ[47:40]
DQ[55:48]
DQ[63:56]
CB[7:0]
DQS 0
DQS 1
DQS 2
DQS 3
DQS 4
DQS 5
DQS 6
DQS 7
DQS 8
DQS# 0
DQS# 1
DQS# 2
DQS# 3
DQS# 4
DQS# 5
DQS# 6
DQS# 7
DQS# 8
DM 0
DM 1
DM 2
DM 3
DM 4
DM 5
DM 6
DM 7
DM 8
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Data Signals
Table 7:
Data Group Routing Rules
Length
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the ASIC package.)
B = 1.9in.–4.5in.
C = 0.425in.
D = 0.2in.–0.55in.
Total: A + B + C = 2.5in.–5.0in.
Length Matching in Data/Strobe Byte Lane
+50 mils from data strobe1
Length Matching Byte Lane to Byte Lane
±0.5in. of memory clock length
Trace
Data:
Trace width = 5 mils–target 50Ω impedance
Trace space = 12–15 mils reducing to 11.5 mils going between the pins of the DIMM
Trace space from DIMM pins = 7 mils
Trace space to other signal groups = 20–25 mils
Differential strobe:
Trace width = 5 mils–target 50Ω impedance
Trace space = 5 mils between pairs
Trace space to other signals = 25 mils
Notes:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
1. This value assumes differential strobes are used. Differential signals have a faster propagation time than single-ended signals, so if the data signals are routed equal to or longer than
the data strobe, the data strobe signal will arrive at the DRAM in the center of its associated
data signals. The propagation delay can vary with design parameters, so simulation of these
signals is recommended.
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Clock Signals
Clock Signals
The memory clocks CK[5:0] and CK#[5:0] are used by the DRAM on a DDR2 bus to
capture the address and command data. Unbuffered DIMMs require three clock pairs
per DIMM. Some DDR2 memory controllers will drive all of these clocks, while others
will require an external clock driver to generate these signals. In this example, it is
assumed that the memory controller will drive the six clock pairs required for a twoDIMM unbuffered system.
Clocks do not get connected to VTT like the address signals of a DDR2 bus. The clocks are
differential pairs and must be routed as a differential pair. Each clock pair is differentially terminated on the DIMM. Figure 9 on page 16 shows the routing topology used for
the clocks. In this figure, only one of the three clock pairs required by each DIMM is
shown.
Figure 9 on page 16 also shows a capacitor placed between the clock pairs. This capacitor can improve the clock slew rates and signal quality at the DRAM. The ability of the
capacitor to improve the clock signals is dependent on the clock driver. Some drivers will
benefit from the addition of the capacitor more than others. Designers should check
with their chipset provider to see if having a capacitor on the clocks is beneficial. If the
capacitor is implemented, place it 0.5in. away from the first DIMM connector. The best
value for the capacitor is 5pF.
Figure 8:
DDR2 Data Byte Lane Routing Topology
Pad on Die
Pin on Package
DIMM 1
DIMM 2
DQ Byte Group X
A
B
C
DQS[X]
A
B
C
DQS#[X](Optional)
A
B
C
DM[X]
A
B
C
DDR2
Memory
Controller
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Clock Signals
Figure 9:
DDR2 Clock Signal Group Routing Topology
Pad on Die
Pin on Package
DIMM 1
DIMM 2
CK[2:0]
A
A
B
CK#[2:0]
B
5pF
CK[5:3]
A
A
DDR2
Memory
Controller
B2
CK#[5:3]
B2
5pF
Optional
Clock Signal Routing Rules
The clocks are routed as a differential pair from the controller to the DIMM. The clocks
are used to capture the address and control signals at the DRAM on the DIMM, so they
must maintain a length relationship to the address and control signals at the DIMM to
which they are connected. Most controllers have the ability to prelaunch the address
and control signals. The prelaunch is used to center the clock in the address valid eye. It
is required because the clocks are loaded lighter than the address signals and as a result
have a shorter flight time from the controller to the DRAM on the DIMM. Differentially
routed signals like the clock also have a shorter flight time than single-ended signals.
This effect causes the clock signals to arrive at the DRAM even sooner than the address,
command, and control signals. To compensate for the difference in propagating delay, it
is recommended that the clock signals be roughly equal to or shorter than the address,
command, and control signals.
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Clock Signals
Table 8:
Clock Group Routing Rules
Length
A = Obtain from DRAM controller vendor.
(A is the length from the die pad to the ball on the ASIC package.)
B = 1.9in.–5.0in.
B2= 2.325in.–5.425in.
Length Matching
±10 mils for CK to CK#
±25 mils clock pair to clock pair at the DIMM
Trace
Trace width = 8 mils–target 40Ω trace impedance, 70Ω differential impedance
Trace space = 5 mils
Trace space to other signal groups = 20 mils
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Memory Power Supply Requirements
DDR2 Memory Power Supply Requirements
A DDR2 bus implementation requires three separate power supplies. The DRAM and the
memory portion of the controller require a 1.8-volt supply. The 1.8 volt supply provides
power for the DRAM core and I/O as well as at least the I/O of the DRAM controller. The
second power supply is VREF, which is used as a reference voltage by the DRAM and the
controller. The third supply is VTT, which is the termination supply of the bus. Table 9 on
page 19 lists the tolerances of each of these supplies.
MVTT Voltage
The memory termination voltage, MVTT, requires current at a voltage level of 900
mV(DC). See Figure 7 on page 11 for the VTT tolerance. VTT must be generated by a regulator that is able to sink and source current while still maintaining the tight voltage regulation.
• VREF and VTT must track variations in VDD over voltage, temperature, and noise
ranges.
• VTT of the transmitting device must track VREF of the receiving device.
MVTT Layout Recommendations
• Place the MVTT island on the component-side signals layer at the end of the bus
behind the last DIMM slot.
• Use a wide-island trace for current capacity.
• Place the VTT generator as close to the termination resistors as possible to minimize
impedance (inductance).
• Place one or two 0.1µf decoupling caps by each termination RPACK on the MVTT
island to minimize the noise on VTT. Other bulk (10µf–22µf ) decoupling is also recommended to be placed on the MVTT island.
MVREF Voltage
The memory reference voltage, MVREF, requires a voltage level of one-half VDD with a
tolerance as shown in Table 9. VREF can be generated using a simple resistor divider with
1% or better accuracy. VREF must track one-half of VDD over voltage, noise, and temperature changes.
• Peak-to-peak AC noise on VREF may not exceed ±2% VREF(DC).
MVREF Layout Recommendations
•
•
•
•
•
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
Use 30 mil trace between decoupling cap and destination.
Maintain a 25 mil clearance from other nets.
Simplify implementation by routing VREF on the top signal trace layer.
Isolate VREF and/or shield with ground.
Decouple using distributed 0.01µf and 0.1µf capacitors by the regulator, controller,
and DIMM slots. Place one 0.01µf and 0.1µf near the VREF PIN of each DIMM. Place
one 0.1µf near the source of VREF, one near the VREF pin on the controller, and two
between the controller and the first DIMM.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Memory Power Supply Requirements
Table 9:
Symbol
VDD
VREF
VTT
Required Voltages
Parameter
Device supply voltage
Memory reference voltage
Memory termination voltage
MIN
Typical
MAX
Unit
1.7
VDD * 0.49
VREF - 40mV
1.8
VDD * 0.5
VREF
1.9
VDD * 0.51
VREF + 40mV
V
V
V
Timing Budget
The previous section is useful for getting an idea of how the DDR2 memory bus functions and the general relationship between the signals on the bus. However, if a design
should deviate from the given example, the routing rules for the design can change.
Since it is unlikely that every design will follow the given example exactly, it is important
to simulate the design. One of the objectives of simulation is to determine if the design
will meet the signal timing requirements of the DRAM and DDR2 controller. To meet this
objective, a timing budget must be generated. This section shows how to use the data
provided in the DDR2 DRAM and DDR2 controller data sheets to determine the amount
of the total timing budget that the board interconnect can consume.
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Data Write Budget
DDR2 Data Write Budget
Table 10 on page 20 gives specifics of the timing budget for DDR2 WRITEs at 533 MT/s.
The portion of the budget consumed by the DRAM device and by the DDR2 controller is
fixed and cannot be influenced by the board designer. The amount of the total budget
remaining after subtracting the portion consumed by the DRAM and the controller is
what remains for the board interconnect. This is the portion that is used to determine
the bus routing rules. The different components of the board interconnect are outlined.
The board designer can make trade-offs with trace spacing, length matching, resistor
tolerance, etc., to determine the best interconnect solution.
Table 10:
DDR2 Write Budget1
Element
Skew Component
Transmitter
Clock
DRAM device
(from spec)
Interconnect
Total interconnect
Total budget
Total budget consumed by
controller and DRAM
Interconnect budget
Notes:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
Setup
Hold
Units
Total skew at transmitter
Data/strobe PLL jitter
325
25
325
25
ps
ps
tDH/tDS
Total device
XTK (cross talk) - DQ
100
350
55
225
350
55
ps
ps
ps
XTK (cross talk) - DQS
40
40
ps
ISI - DQ
ISI - DQS
Input capacitance matching
30
5
25
30
5
25
ps
ps
ps
REFF mismatch
Input eye reduction (VREF)
10
25
10
25
ps
ps
Path matching (board)
25
25
ps
10
225
937.5
925
10
225
937.5
925
ps
ps
ps
ps
12.5
12.5
ps
Path matching (module)
Interconnect skew
1875/2 @ 533 MHz
Transmitter + DRAM +
Interconnect
Total - (transmitter + DRAM +
interconnect)
Comments
From data sheet
May be included in
transmitter setup and hold
From data sheet
4 aggressors (a pair on each
side of the victim); victim
(1010); aggressors (PRBS)
1 shielded victim, 2 aggressors
(PRBS)
PBRS
1010...
3.5pF and 4.0pF loads, strobe
and data shift differently
+/- 3.75%
±20mV included in DRAM
skew; additional = (±25mV)/
(1.0 V/ns); this includes DQ
and DQS
Within byte lane: 165 ps/in. ×
0.1in.; impedance mismatch
within DQ to DQS
Module routing skew
Must be greater than 0
1. These are worst-case slow numbers (85°C, 1.7V, slow process).
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Data Write Budget
Determining DRAM Write Budget Consumption
The amount of the write budget consumed by the DRAM is easily obtained from the data
sheets. The DRAM data sheet provides the data input hold time relative to strobe (tDH)
and the data input setup time relative to strobe (tDS). These numbers are entered
directly into the timing budgets for setup and hold. They account for all of the write
timing budget consumed by the DRAM.
Determining DDR2 Controller Write Budget Consumption
To calculate the amount of the setup timing budget consumed by the DDR2 controller
on a DRAM WRITE, find the value for tDQSU minimum. This is the minimum amount of
time all data will be valid before the data strobe transitions shown in Figure 10. tDQSU
should take clock asymmetry into account. In an ideal situation, tDQSU would be equal
to 1/4 × tCK. The difference between 1/4 × tCK and tDQSU is the amount of the write
timing budget consumed by the controller for setup. From this, the following equation is
derived:
Controller setup data valid reduction = 1/4 × tCK -tDQSU
To calculate the hold time, use the same equation, but use tDQHD in place of tDQSU.
Figure 10:
Memory Write and ADDR/CMD Timing
T0
T1
T2
T3
T4
T5
T6
tDQSS
tADSU
tADHD
CK
ADDR/
CK
tDSH
tDSS
tWPST
DQS
DQ
tDQSU
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
A
A
21
A
A
tDQHD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Data Read Budget
DDR2 Data Read Budget
Table 11 gives specifics of the timing budget for DDR2 reads at 533 MT/s. The portion of
the budget consumed by the DRAM device and by the DDR2 controller is fixed and
cannot be influenced by the board designer. The amount of the total budget remaining
after subtracting the portion consumed by the DRAM and the controller is what remains
for the board interconnect.
Table 11:
DDR2 Read Budget1
Element
Skew Component
Setup
t
DRAM device
(from spec)
Hold
3.75
1.763
300
400
1.363
1.063
Units
ns
ns
ps
ps
ns
ns
Comments
406
406
406
406
ps
ps
From data sheet.
Receiver
(controller)
Clock
Clock CK
HP (tCL/tCH[MIN] at 47/53)
tDQSQ
tQHS
tQH (tHP - tQHS)
t
DV (tHP - tDQSQ - tQHS, or tQH
- tDQSQ)
(tCK/2 - tDV)/2
Total DRAM data valid
reduction
Total skew at receiver
275
275
ps
From data sheet
Data/strobe chip PLL jitter
25
25
ps
Interconnect
XTK (cross talk) - DQ
70
70
ps
XTK (cross talk) - DQS
40
40
ps
ISI - DQ
ISI - DQS
Path matching (board)
20
5
25
20
5
25
ps
ps
ps
Path matching (module)
REFF mismatch
Input eye reduction (VREF)
10
10
25
10
10
25
ps
ps
ps
Capacitive mismatch
10
10
Total skew at interconnect
1875/2 @ 533 MHz
Receiver + DRAM +
Interconnect
215
937.5
921
215
937.5
921
ps
ps
ps
DRAM tester includes 50pS
jitter margin
Aggressors (a pair on each side
of the victim); victim (1010);
aggressors (PRBS)
1 shielded victim, 2 aggressors
(PRBS)
Spice-generated eye diagram
1010...
Within byte lane: 165 ps/in. ×
0.1in.; impedance mismatch
within DQ to DQS
Module routing skew
+/- 3.75%
±20mV included in DRAM skew;
additional = (±25mV)/(1.0 V/ns);
this includes DQ and DQS
Capacitive load differences at
the receiver in a byte
From simulation
Total - (receiver + DRAM +
interconnect)
16.5
16.5
ps
t
DRAM total
Total interconnect
Total budget
Total budget consumed by
controller, DRAM, and
interconnect
Interconnect budget
Notes:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
533 MT/s data rate
+/- 3% clock duty cycle
Must be greater than 0
1. These are worst-case slow numbers (85°C, 1.7V, slow process).
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Data Read Budget
Figure 11:
DRAM Read Data Valid
tCK/2
tHP
= 1.7625ns
([email protected]/53)
tQH
tDQSQ = 300ps
= 1.875ns
Clock Duty Cyle = 47/53%
tQHS
= 1.3625ns
= 400ps
DVW = 1.0625ns
DQS
DQ (last data valid)
DQ (first data no longer valid)
All DQs and DQS, collectively
Figure 12:
Data Valid Window
Read Data Timing
T1
T0
T2
T3
T4
CK
tHP
tHP
tHP
tDQSQ
tHP
tDQSQ
tHP
tDQSQ
tHP
tHP
tDQSQ
DQS
D
DQ (last data valid)
D
D
D
D
D
D
DQ (byte), collectively
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
tQH
tDV
tDV
23
D
D
D
tQH
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DQ (first data no
longer valid)
D
D
D
D
D
tQH
tDV
tQH
tDV
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
DDR2 Data Read Budget
Determining DRAM Read Budget Consumption
Figure 11 shows how the information from the DRAM data sheet affects the total data
valid window as the data is driven from the DRAM device. This information is used in the
timing budget to determine the amount of the total data timing budget that is consumed
by the DRAM device. The total budget for the data is half the clock period. This time is
halved again to determine the time allowed for setup and hold. Using the DRAM data
sheet and filling in numbers for the timing parameters in Figure 11, the total data valid
window at the DRAM can be calculated using the following equation:
DVW = tHP - tDQSQ - tQHS
t
CK/2 - DVW/2 = DRAM data valid reduction
The DRAM data valid reduction is used in the timing budget for setup and hold.
Determining DDR2 Controller Read Budget Consumption
When read data is received at the controller from the DRAM, the strobe is edge-aligned
with the data. It is the responsibility of the controller to delay the strobe and then use the
delayed strobe to capture the read data. The controller will have a minimum value it can
accept for a data valid window. Internally, the controller has a minimum setup and hold
time that the data must maintain from the internally delayed strobe. Half the data valid
window is the setup or hold time required by the controller plus any controller-introduced signal skew and strobe centering uncertainty. The timing diagram example in
Figure 12 on page 23 shows the timing parameters required for calculating the data valid
window. tDQSQ is the maximum delay from the last data signal to go valid after the
strobe transitions. tQH is the minimum time all data must remain valid after strobe transitions. Use the following equation to obtain tDV:
t
DV = tQH - tDQSQ
Assuming tDV is split evenly between setup and hold, the portion of the timing budget
consumed by the controller for setup and hold is one-half tDV. For the controller used in
this example, an even split between setup and hold can be assumed because the
controller is determining the center of the data eye during the boot up routine, and the
DLL maintains this relationship over temperature and voltage variations.
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
2T Address Timing Budget
2T Address Timing Budget
Table 12 on page 25 gives specifics of the timing budget for a 2T address and command
at a 266 MHz clock rate. Running the address and command at T2 with a 266 MHz clock
results in a address frequency of 67 Mhz. The portion of the budget consumed by the
DRAM device and the DDR2 controller is fixed and cannot be influenced by the board
designer. The amount of the total budget remaining after subtracting the portion
consumed by the DRAM and the controller is what remains for the board interconnect.
Determining DRAM Address Budget Consumption
The portion of the address budget consumed by the DRAM is obtained by getting the
value of tIS for setup and tIH for hold. tIH and tIS are the setup and hold times required
by the DRAM inputs. For systems with heavy loading on the address and command
lines, the value in the data sheet must be derated depending on the slew rate. See the
DRAM data sheet for information about derating.
Determining Controller Address Budget Consumption
The DRAM controller will provide a minimum setup and hold time for the address and
command signals with respect to clock. This is the amount of the setup and hold budget
consumed by the controller.
Table 12:
2T Address Timing Budget1
Element
Skew Component
Transmitter
Receiver
Interconnect
Total interconnect
Total budget
Total budget
consumed by
controller and DRAM
Interconnect budget
Notes:
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
Setup
Hold
Units
Comments
Memory controller transmitter
DRAM skew
550
250
550
375
ps
ps
Cross talk: address
250
250
ps
ISI: address
Cross talk: clock
VREF: reduction
335
25
100
335
25
100
ps
ps
ps
Path matching
25
25
ps
DIMM config/loading
mismatch
Rterm VOH/VOL skew (5%)
370
370
ps
25
25
ps
Total skew at interconnect
7500 @ 133 MHz
Transmitter + DRAM +
interconnect
1130
3750
1930
1130
3750
2055
ps
ps
ps
133 MHz bit width
Total - (transmitter + DRAM)
1820
1695
ps
Must be greater than 0.
Chipset
tIS, tIH from DRAM spec (0.3V/
ns to 1V/ns) (see derating table
if outside this range)
1 victim (1010...), 4 aggressors
(PRBS)
(PRBS)
Spec
±75mV included in DRAM
skew; additional = (±30mV)/
(0.3 V/ns)
Within byte lane: 165 ps/in. ×
0.15in.; MB routes account for
MC package skew
Config: DIMM0/DIMM1 = 5/18
vs. 18/18 vs. 5/0.
Estimator tool (slew = 0.3V/ns,
Rp = 47, VOUT = 1.63V)
1. These are worst-case slow numbers (85°C, 1.7V, slow process).
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
2T Address Timing Budget
Figure 13:
Control and 2T Address Timing
tADsu
tADhd
T1
T0
T2
T3
T4
CK
tHP
tHP
tHP
tHP
tHP
tHP
tHP
Control
Address /
Command
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Control Signal Timing Budget
Control Signal Timing Budget
The control signals always operate with 1T timing, regardless of the address signals
using 1T or 2T. Even when using 2T on the address signals, careful attention to the
control signals is required. As shown in the timing diagram in Figure 13 on page 26, the
control signals will have half the time of the 2T address signals to meet setup and hold
times. Because the loading on the control signals is much less than the address signals,
the task of closing timing is possible.
The timing budget for the control signals is derived in the same manner as the address
signals. The only difference is the amount of time per cycle. For a 266 MHz clock
frequency, the control signal period is 3.75ns. Table 13 on page 28 shows the timing
budget for the control signals. Two items stand out as being very different from the
address timing budget. First, the portion of the budget consumed by the DRAM is
reduced for the control signals. The reduced loading on the control signals results in
increased edge rates. The edge rates are fast enough that derating of the setup and hold
time is not required. Second, the portion on the timing budget consumed by variation in
the DIMM configuration and loading conditions is greatly reduced. Each rank in the
system has its own copy of the control signals, so the loading on these signals is not
affected by changes in total system loading in the same way as the address bus. These
two differences make the task of closing the control signal timing budget possible.
In the timing of all the signal groups in a system, the control signals valid eye falls within
the 2T address valid eye. Figure 14 shows a timing diagram that illustrates the timing
relationships. The address signals have a longer transitioning time due to the slower slew
rates. This relationship will hold true so long as the address signals and the control
signals are held to the same setup and hold timing rules. So long as this relationship
holds true, a closed 1T control timing budget will result in a closed 2T address budget. To
make this relationship remain true, system designers must subject all control, address,
and command signals to the same length-matching rules. When designing the relationship of the clock to the control, address, and command signals, it must be centered with
respect to the 1T signals. This is accomplished with controller prelaunch and/or board
routing.
Figure 14:
Control, Address, and Command Timing Relationship
tIS
tIH
CK#
CK
COMMAND
2T ADDRESS
TRANSITIONING DATA
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
TN-47-01 DDR2 DESIGN GUIDE FOR TWO-DIMM SYSTEMS
Control Signal Timing Budget
Table 13:
Control Signals Timing Budget1
Element
Skew Component
Setup
Hold
Units
Transmitter
Receiver
Memory controller transmitter
DRAM skew
550
250
550
375
ps
ps
Interconnect
Cross talk: address
250
250
ps
ISI: address
Cross talk: clock
VREF: reduction
325
50
50
325
50
50
ps
ps
ps
Path matching
25
25
ps
DIMM config/loading
mismatch
Rterm VOH/VOL skew (5%)
50
50
ps
15
15
ps
Total skew at interconnect
3750 @ 266 MHz
Transmitter + DRAM +
interconnect
765
1875
1565
765
1875
1690
ps
ps
ps
266 MHz bit width
Total - (transmitter + DRAM +
interconnect)
310
185
ps
Must be greater than 0
Total interconnect
Total budget
Total budget
consumed by
controller and DRAM
Interconnect budget
Notes:
Comments
Chipset
IS, tIH from DRAM spec (0.3V/ns
to 1V/ns) (see derating table if
outside this range)
1 victim (1010...), 4 aggressors
(PRBS)
(PRBS)
Spec.
±75mV included in DRAM skew;
additional = (±30mV)/(0.3 V/ns)
Within byte lane: 165 ps/in. ×
0.15in.; MB routes account for
MC package skew
Config: DIMM0/DIMM1 = 5/18
vs. 18/18 vs. 5/0
Estimator tool (slew = 0.3V/ns,
Rp=47, VOUT=1.63V)
t
1. These are worst-case slow numbers (85°C, 1.7V, slow process).
Clock to Data Strobe Relationship
The DDR2 DRAM and the DDR2 controller must move the data from the data strobe
clocking domain into the DDR2 clock domain when the data is latched internally. Due to
this requirement, the data strobe must maintain a relationship to the DDR2 clock. For
the DDR2 DRAM, this relationship is specified by tDQSS. This timing parameter states
that after a WRITE command, the data strobe must transition 0.75 to 1.25 × tCK.
Figure 10 on page 21 shows the DDR2 controller also specifies a tDQSS timing parameter. This is the time after the WRITE command that the data strobe will transition. For
the controller in this example, tDQSS = ±0.06 × tCK. The following equation is used to
calculate the amount of clock to data strobe skew that is left for consumption by the
board interconnect:
Interconnect budget = DRAM tDQSS - Controller tDQSS
This equation shows that clock to data strobe is not one of the strict timing requirements
of a DDR2 channel. If the clocks are routed so that they are between the shortest and
longest strobe lengths, designers gain some leeway in the data strobe to data strobe byte
lane routing restrictions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
09005aef80cc3dce
TN_47_01.fm - Rev. B 12/09 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.