TN-47-14: DDR2 tCKE Power-Down Introduction Technical Note DDR2 tCKE Power-Down Requirement Introduction In DDR2 SDRAM devices, power-down occurs when CKE is registered LOW with a DESELECT or NOP command. However, unlike DDR SDRAM, power-down entry and exit in DDR2 SDRAM requires CKE to remain LOW (for power-down entry) or HIGH (for powerdown exit) in order to preserve the viability of signals in the DRAM. This technical note describes the tCKE timing parameter of DDR2 SDRAM. Power-Down Overview There are 3 power-down modes for DDR2, including IDD2P (precharge power-down), IDD3P (active power-down, slow exit), and IDD3P (active power-down, fast exit). Precharge power-down occurs when all banks are idle and is the lowest power state other than self refresh mode (IDD6). If power-down occurs when there is a row active in any bank, the mode is referred to as active power-down. For active power-down, fast or slow exit is determined by the configuration of the mode register (MR12 = 0 for fast or MR12 = 1 for slow). The advantage of the slow exit is less device power consumption. Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum power savings, the DLL generally is frozen during precharge power-down. Exiting active power-down requires the device to be at the same voltage and frequency as when it entered power-down. Exiting precharge power-down requires the device to be at the same voltage as when it entered power-down; however, the clock frequency is allowed to change as specified within Micron data sheets. Maximum power-down duration is governed by the refresh requirements of the device. DDR tCKE Timing Definition DDR SDRAM devices allow CKE to change states on each new clock cycle. As such, the device can toggle between precharge power-down, active power-down, or other active states on every other clock cycle. The only requirements for CKE are the pulse width, setup time, and hold time in reference to the rising clock edge. Note that upon exit of self refresh mode or after a DLL reset, CKE is required to remain HIGH for 200 clock cycles. DDR2 tCKE Timing Definition To ensure signal stability and synchronization, CKE in DDR2 SDRAM must remain LOW or HIGH for at least tCKE (MIN) = 3 x tCK any time there is a CKE signal transition. Unlike DDR SDRAM, CKE may no longer toggle back and forth on each successive clock cycle. PDF: 09005aef8166fff9/Source: 09005aef8166ffd1 TN4714.fm - Rev. B 3/10 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. Products and specifications discussed herein are subject to change by Micron without notice. TN-47-14: DDR2 tCKE Power-Down Figure 1: DDR1 Power-Down T0 T1 T2 CK# CK tCK tIS tIH tCH tIS CKE tIS tIS ADDR Ta1 Ta2 tIS (( )) tIH VALID1 COMMAND tCL Ta0 (( )) (( )) NOP tIH (( )) (( )) NOP (( )) (( )) VALID DQS (( )) (( )) DQ (( )) (( )) DM (( )) (( )) VALID VALID tREFC Enter 2 Power-Down Mode Exit Power-Down Mode DON’T CARE Notes: PDF: 09005aef8166fff9/Source: 09005aef8166ffd1 TN4714.fm - Rev. B 3/10 EN 1. Once initialized, VREF must always be powered within specified range. 2. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least 1 row is already active), then the power-down mode shown is active power-down. 3. No column accesses are allowed to be in progress at the time power-down is entered. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. TN-47-14: DDR2 tCKE Power-Down Conclusion Figure 2: DDR2 Power-Down T0 CK CKE tIS ADDRESS tIH VALID1 tIS tIS tIH tIH VALID Ta1 tCH CK tIS COMMAND Ta0 (( )) (( )t ) CK# Tb0 Tb1 Tc0 Td0 Td1 tCL tIH tIH tIS tIS tIH (( )) (( )) (( )) (( )) NOP NOP VALID tCKE(MIN)3 VALID DQ (( )) (( )) DM (( )) (( )) Enter 2 Power-Down Mode Notes: VALID VALID tXP4, tXARD5, tXARDS6 tCKE(MIN)3 (( )) (( )) VALID tCKE (MIN)3 (( )) (( )) DQS,DQS# VALID Exit Power-Down Mode DON’T CARE 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least 1 row is already active), then the power-down mode shown is active power-down. 2. No column accesses are allowed to be in progress at the time power-down is entered. 3. tCKE (MIN) = 3 x tCK. 4. tXP timing is used for exit precharge power-down to any non-READ command. 5. tXARD timing is used for exit active power-down to READ command if Fast Exit is selected via MRS (bit12 = 0). 6. tXARDS timing is used for exit active power-down to READ command if Slow Exit is selected via MRS (bit12 = 1). Conclusion When designing for DDR2 memory, it is important to pay attention to the new t CKE(MIN) parameter. Holding CKE at a steady state for 3 clock cycles is required whenever CKE has changed states (HIGH to LOW or LOW to HIGH). 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8166fff9/Source: 09005aef8166ffd1 TN4714.fm - Rev. B 3/10 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.