4Gb: x4, x8, x16 DDR3L SDRAM

4Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
EDJ4204EFBG – 128 Meg x 4 x 8 banks
EDJ4208EFBG – 64 Meg x 8 x 8 banks
EDJ4216EFBG – 32 Meg x 16 x 8 banks
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Description
DDR3L SDRAM (1.35V) is a low-voltage version of the
DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V)
SDRAM data sheet specifications when running in
1.5V compatible mode.
Features
• VDD = V DDQ = 1.35V (1.283–1.45V)
• Backward compatible to V DD = V DDQ = 1.5V ±0.075V
– Supports DDR3L devices to be backward compatible in 1.5V applications
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• Programmable partial array self refresh (PASR)
Options
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (9mm x 10.6mm) Rev. F
• FBGA package (Pb-free) – x16
– 96-ball (9.0 mm x 13.5mm) Rev. F
• Timing – cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
• Operating temperature1
– Commercial (0°C ≤ T C ≤ +95°C)
• Revision
Note:
1. No guarantee on industrial and automotive
temperature ranges.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-GN1
1600
11-11-11
13.75
13.75
13.75
-DJ
1333
9-9-9
13.5
13.5
13.5
Note:
tRCD
(ns)
tRP
(ns)
CL (ns)
1. Backward compatible to 1333, CL = 9 (-DJ).
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Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
1 Gig x 4
512 Meg x 8
256 Meg x 16
128 Meg x 4 x 8 banks
64 Meg x 8 x 8 banks
32 Meg x 16 x 8 banks
Refresh count
8K
8K
8K
Row address
64K (A[15:0])
64K (A[15:0])
32K (A[14:0])
Bank address
8 (BA[2:0])
8 (BA[2:0])
8 (BA[2:0])
2K (A[11, 9:0])
1K (A[9:0])
1K (A[9:0])
1KB
1KB
2KB
Column address
Page size
Figure 1: DDR3L Part Numbers
E
D
J
42 04
E
F
BG - GN - F - D
Packing Media
Micron Technology
(Micron Japan)
D = Dry Pack (Tray)
R = Tape and Reel
Type
D = Packaged device
Environment Code
Product Family
F = Lead-free (RoHS-compliant)
and halogen-free
J = DDR3 SDRAM
Speed
Density/Bank
42 = 4Gb/8-bank
GN = DDR3L-1600K (11-11-11)
DJ = DDR3L-1333H (9-9-9)
Organization
Package
04 = x4
08 = x8
16 = x16
BG = FBGA
Revision
Power Supply
E = 1.35V
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 24
Absolute Ratings ......................................................................................................................................... 24
Input/Output Capacitance .......................................................................................................................... 25
Thermal Characteristics .................................................................................................................................. 26
Electrical Specifications – IDD Specifications and Conditions ............................................................................ 27
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications ........................................................... 38
Electrical Specifications – DC and AC .............................................................................................................. 39
DC Operating Conditions ........................................................................................................................... 39
Input Operating Conditions ........................................................................................................................ 40
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 44
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 47
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 49
ODT Characteristics ....................................................................................................................................... 50
1.35V ODT Resistors ................................................................................................................................... 51
ODT Sensitivity .......................................................................................................................................... 52
ODT Timing Definitions ............................................................................................................................. 52
Output Driver Impedance ............................................................................................................................... 56
34 Ohm Output Driver Impedance .............................................................................................................. 57
DDR3L 34 Ohm Driver ................................................................................................................................ 58
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 59
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 60
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 60
Output Characteristics and Operating Conditions ............................................................................................ 62
Reference Output Load ............................................................................................................................... 64
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 64
Slew Rate Definitions for Differential Output Signals .................................................................................... 66
Speed Bin Tables ............................................................................................................................................ 67
Electrical Characteristics and AC Operating Conditions ................................................................................... 71
Command and Address Setup, Hold, and Derating ........................................................................................... 91
Data Setup, Hold, and Derating ....................................................................................................................... 98
Commands – Truth Tables ............................................................................................................................. 106
Commands ................................................................................................................................................... 109
DESELECT ................................................................................................................................................ 109
NO OPERATION ........................................................................................................................................ 109
ZQ CALIBRATION LONG ........................................................................................................................... 109
ZQ CALIBRATION SHORT .......................................................................................................................... 109
ACTIVATE ................................................................................................................................................. 109
READ ........................................................................................................................................................ 109
WRITE ...................................................................................................................................................... 110
PRECHARGE ............................................................................................................................................. 111
REFRESH .................................................................................................................................................. 111
SELF REFRESH .......................................................................................................................................... 112
DLL Disable Mode ..................................................................................................................................... 113
Input Clock Frequency Change ...................................................................................................................... 117
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Write Leveling ............................................................................................................................................... 119
Write Leveling Procedure ........................................................................................................................... 121
Write Leveling Mode Exit Procedure ........................................................................................................... 123
Initialization ................................................................................................................................................. 124
Voltage Initialization / Change ....................................................................................................................... 126
VDD Voltage Switching ............................................................................................................................... 127
Mode Registers .............................................................................................................................................. 128
Mode Register 0 (MR0) ................................................................................................................................... 129
Burst Length ............................................................................................................................................. 129
Burst Type ................................................................................................................................................. 130
DLL RESET ................................................................................................................................................ 131
Write Recovery .......................................................................................................................................... 131
Precharge Power-Down (Precharge PD) ...................................................................................................... 132
CAS Latency (CL) ....................................................................................................................................... 132
Mode Register 1 (MR1) ................................................................................................................................... 133
DLL Enable/DLL Disable ........................................................................................................................... 133
Output Drive Strength ............................................................................................................................... 134
OUTPUT ENABLE/DISABLE ...................................................................................................................... 134
TDQS Enable ............................................................................................................................................. 134
On-Die Termination .................................................................................................................................. 135
WRITE LEVELING ..................................................................................................................................... 135
POSTED CAS ADDITIVE Latency ................................................................................................................ 135
Mode Register 2 (MR2) ................................................................................................................................... 136
CAS Write Latency (CWL) ........................................................................................................................... 137
AUTO SELF REFRESH (ASR) ....................................................................................................................... 137
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 138
SRT vs. ASR ............................................................................................................................................... 138
DYNAMIC ODT ......................................................................................................................................... 138
Mode Register 3 (MR3) ................................................................................................................................... 139
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 139
MPR Functional Description ...................................................................................................................... 140
MPR Register Address Definitions and Bursting Order ................................................................................. 141
MPR Read Predefined Pattern .................................................................................................................... 146
MODE REGISTER SET (MRS) Command ........................................................................................................ 146
ZQ CALIBRATION Operation ......................................................................................................................... 147
ACTIVATE Operation ..................................................................................................................................... 148
READ Operation ............................................................................................................................................ 150
WRITE Operation .......................................................................................................................................... 161
DQ Input Timing ....................................................................................................................................... 169
PRECHARGE Operation ................................................................................................................................. 171
SELF REFRESH Operation .............................................................................................................................. 171
Extended Temperature Usage ........................................................................................................................ 173
Power-Down Mode ........................................................................................................................................ 174
RESET Operation ........................................................................................................................................... 182
On-Die Termination (ODT) ............................................................................................................................ 184
Functional Representation of ODT ............................................................................................................. 184
Nominal ODT ............................................................................................................................................ 184
Dynamic ODT ............................................................................................................................................... 186
Dynamic ODT Special Use Case ................................................................................................................. 186
Functional Description .............................................................................................................................. 186
Synchronous ODT Mode ................................................................................................................................ 192
ODT Latency and Posted ODT .................................................................................................................... 192
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Timing Parameters .................................................................................................................................... 192
ODT Off During READs .............................................................................................................................. 195
Asynchronous ODT Mode .............................................................................................................................. 197
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 199
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 201
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 203
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
List of Figures
Figure 1: DDR3L Part Numbers ........................................................................................................................ 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 1 Gig x 4 Functional Block Diagram .................................................................................................. 14
Figure 4: 512 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 256 Meg x 16 Functional Block Diagram ........................................................................................... 15
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17
Figure 8: 78-Ball FBGA – x4, x8 ....................................................................................................................... 22
Figure 9: 96-Ball FBGA – x16 .......................................................................................................................... 23
Figure 10: Thermal Measurement Point ......................................................................................................... 26
Figure 11: DDR3L 1.35V Input Signal .............................................................................................................. 43
Figure 12: Overshoot ..................................................................................................................................... 44
Figure 13: Undershoot ................................................................................................................................... 44
Figure 14: V IX for Differential Signals .............................................................................................................. 45
Figure 15: Single-Ended Requirements for Differential Signals ........................................................................ 45
Figure 16: Definition of Differential AC-Swing and tDVAC ............................................................................... 46
Figure 17: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 48
Figure 18: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .............. 49
Figure 19: ODT Levels and I-V Characteristics ................................................................................................ 50
Figure 20: ODT Timing Reference Load .......................................................................................................... 53
Figure 21: tAON and tAOF Definitions ............................................................................................................ 54
Figure 22: tAONPD and tAOFPD Definitions ................................................................................................... 54
Figure 23: tADC Definition ............................................................................................................................. 55
Figure 24: Output Driver ................................................................................................................................ 56
Figure 25: DQ Output Signal .......................................................................................................................... 63
Figure 26: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 64
Figure 27: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 65
Figure 28: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 66
Figure 29: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) .............................................. 94
Figure 30: Nominal Slew Rate for tIH (Command and Address – Clock) ............................................................ 95
Figure 31: Tangent Line for tIS (Command and Address – Clock) ..................................................................... 96
Figure 32: Tangent Line for tIH (Command and Address – Clock) ..................................................................... 97
Figure 33: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 102
Figure 34: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 103
Figure 35: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 104
Figure 36: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 105
Figure 37: Refresh Mode ............................................................................................................................... 112
Figure 38: DLL Enable Mode to DLL Disable Mode ........................................................................................ 114
Figure 39: DLL Disable Mode to DLL Enable Mode ........................................................................................ 115
Figure 40: DLL Disable tDQSCK .................................................................................................................... 116
Figure 41: Change Frequency During Precharge Power-Down ........................................................................ 118
Figure 42: Write Leveling Concept ................................................................................................................. 119
Figure 43: Write Leveling Sequence ............................................................................................................... 122
Figure 44: Write Leveling Exit Procedure ....................................................................................................... 123
Figure 45: Initialization Sequence ................................................................................................................. 125
Figure 46: V DD Voltage Switching .................................................................................................................. 127
Figure 47: MRS to MRS Command Timing ( tMRD) ......................................................................................... 128
Figure 48: MRS to nonMRS Command Timing ( tMOD) .................................................................................. 129
Figure 49: Mode Register 0 (MR0) Definitions ................................................................................................ 130
Figure 50: READ Latency .............................................................................................................................. 132
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Figure 51: Mode Register 1 (MR1) Definition ................................................................................................. 133
Figure 52: READ Latency (AL = 5, CL = 6) ....................................................................................................... 136
Figure 53: Mode Register 2 (MR2) Definition ................................................................................................. 136
Figure 54: CAS Write Latency ........................................................................................................................ 137
Figure 55: Mode Register 3 (MR3) Definition ................................................................................................. 139
Figure 56: Multipurpose Register (MPR) Block Diagram ................................................................................. 140
Figure 57: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 142
Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 143
Figure 59: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 144
Figure 60: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 145
Figure 61: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 147
Figure 62: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 148
Figure 63: Example: tFAW ............................................................................................................................. 149
Figure 64: READ Latency .............................................................................................................................. 150
Figure 65: Consecutive READ Bursts (BL8) .................................................................................................... 152
Figure 66: Consecutive READ Bursts (BC4) .................................................................................................... 152
Figure 67: Nonconsecutive READ Bursts ....................................................................................................... 153
Figure 68: READ (BL8) to WRITE (BL8) .......................................................................................................... 153
Figure 69: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 154
Figure 70: READ to PRECHARGE (BL8) .......................................................................................................... 154
Figure 71: READ to PRECHARGE (BC4) ......................................................................................................... 155
Figure 72: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 155
Figure 73: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 155
Figure 74: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 157
Figure 75: Data Strobe Timing – READs ......................................................................................................... 158
Figure 76: Method for Calculating tLZ and tHZ ............................................................................................... 159
Figure 77: tRPRE Timing ............................................................................................................................... 159
Figure 78: tRPST Timing ............................................................................................................................... 160
Figure 79: tWPRE Timing .............................................................................................................................. 162
Figure 80: tWPST Timing .............................................................................................................................. 162
Figure 81: WRITE Burst ................................................................................................................................ 163
Figure 82: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 164
Figure 83: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 164
Figure 84: Nonconsecutive WRITE to WRITE ................................................................................................. 165
Figure 85: WRITE (BL8) to READ (BL8) .......................................................................................................... 165
Figure 86: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 166
Figure 87: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 167
Figure 88: WRITE (BL8) to PRECHARGE ........................................................................................................ 168
Figure 89: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 168
Figure 90: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 169
Figure 91: Data Input Timing ........................................................................................................................ 170
Figure 92: Self Refresh Entry/Exit Timing ...................................................................................................... 172
Figure 93: Active Power-Down Entry and Exit ................................................................................................ 176
Figure 94: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 176
Figure 95: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 177
Figure 96: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 177
Figure 97: Power-Down Entry After WRITE .................................................................................................... 178
Figure 98: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 178
Figure 99: REFRESH to Power-Down Entry .................................................................................................... 179
Figure 100: ACTIVATE to Power-Down Entry ................................................................................................. 179
Figure 101: PRECHARGE to Power-Down Entry ............................................................................................. 180
Figure 102: MRS Command to Power-Down Entry ......................................................................................... 180
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Figure 103:
Figure 104:
Figure 105:
Figure 106:
Figure 107:
Figure 108:
Figure 109:
Figure 110:
Figure 111:
Figure 112:
Figure 113:
Figure 114:
Figure 115:
Figure 116:
Figure 117:
Figure 118:
Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 181
RESET Sequence ......................................................................................................................... 183
On-Die Termination ................................................................................................................... 184
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 189
Dynamic ODT: Without WRITE Command .................................................................................. 189
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 190
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 191
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 191
Synchronous ODT ...................................................................................................................... 193
Synchronous ODT (BC4) ............................................................................................................. 194
ODT During READs .................................................................................................................... 196
Asynchronous ODT Timing with Fast ODT Transition .................................................................. 198
Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 200
Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 202
Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 204
Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 204
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18
Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20
Table 5: Absolute Maximum Ratings .............................................................................................................. 24
Table 6: DDR3L Input/Output Capacitance .................................................................................................... 25
Table 7: Thermal Characteristics .................................................................................................................... 26
Table 8: DDR3L Timing Parameters Used for I DD Measurements – Clock Units ................................................. 27
Table 9: DDR3L IDD0 Measurement Loop ........................................................................................................ 28
Table 10: DDR3L IDD1 Measurement Loop ...................................................................................................... 29
Table 11: DDR3L IDD Measurement Conditions for Power-Down Currents ....................................................... 30
Table 12: DDR3L IDD2N and IDD3N Measurement Loop .................................................................................... 31
Table 13: DDR3L IDD2NT Measurement Loop .................................................................................................. 31
Table 14: DDR3L IDD4R Measurement Loop .................................................................................................... 32
Table 15: DDR3L IDD4W Measurement Loop .................................................................................................... 33
Table 16: DDR3L IDD5B Measurement Loop .................................................................................................... 34
Table 17: DDR3L IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 ........................................................ 35
Table 18: DDR3L IDD7 Measurement Loop ...................................................................................................... 36
Table 19: IDD Maximum Limits - Die Rev F ...................................................................................................... 38
Table 20: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 39
Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 40
Table 22: DDR3L 1.35V Input Switching Conditions - Command and Address .................................................. 41
Table 23: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 42
Table 24: DDR3L Control and Address Pins ..................................................................................................... 44
Table 25: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 44
Table 26: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...
46
Table 27: Single-Ended Input Slew Rate Definition .......................................................................................... 47
Table 28: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 49
Table 29: On-Die Termination DC Electrical Characteristics ............................................................................ 50
Table 30: 1.35V RTT Effective Impedance ........................................................................................................ 51
Table 31: ODT Sensitivity Definition .............................................................................................................. 52
Table 32: ODT Temperature and Voltage Sensitivity ........................................................................................ 52
Table 33: ODT Timing Definitions .................................................................................................................. 53
Table 34: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 53
Table 35: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 57
Table 36: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 58
Table 37: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.35V ..................................... 58
Table 38: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.45V ..................................... 58
Table 39: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.283 ..................................... 59
Table 40: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 59
Table 41: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 59
Table 42: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 60
Table 43: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 60
Table 44: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 61
Table 45: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 62
Table 46: DDR3L Differential Output Driver Characteristics ............................................................................ 63
Table 47: Single-Ended Output Slew Rate Definition ....................................................................................... 64
Table 48: Differential Output Slew Rate Definition .......................................................................................... 66
Table 49: DDR3L-1066 Speed Bins .................................................................................................................. 67
Table 50: DDR3L-1333 Speed Bins .................................................................................................................. 68
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 51:
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Table 87:
Table 88:
DDR3L-1600 Speed Bins .................................................................................................................. 69
DDR3L-1866 Speed Bins .................................................................................................................. 70
Electrical Characteristics and AC Operating Conditions .................................................................... 71
Electrical Characteristics and AC Operating Conditions .................................................................... 73
Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 83
DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based ................ 92
DDR3L-800/1066/1333/1600 Derating Values tIS/tIH – AC160/DC90-Based ...................................... 92
DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC135/DC90-Based ................................. 92
DDR3L-1866 Derating Values for tIS/tIH – AC125/DC90-Based ......................................................... 93
DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL[AC]) for Valid ADD/CMD Transition .. 93
DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ........................ 99
DDR3L Derating Values for tDS/tDH – AC160/DC90-Based ............................................................... 99
DDR3L Derating Values for tDS/tDH – AC135/DC100-Based ............................................................. 99
DDR3L Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns ............................................... 100
DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition ............. 101
Truth Table – Command ................................................................................................................. 106
Truth Table – CKE .......................................................................................................................... 108
READ Command Summary ............................................................................................................ 110
WRITE Command Summary .......................................................................................................... 110
READ Electrical Characteristics, DLL Disable Mode ......................................................................... 116
Write Leveling Matrix ..................................................................................................................... 120
Burst Order .................................................................................................................................... 131
MPR Functional Description of MR3 Bits ........................................................................................ 140
MPR Readouts and Burst Order Bit Mapping ................................................................................... 141
Self Refresh Temperature and Auto Self Refresh Description ............................................................ 173
Self Refresh Mode Summary ........................................................................................................... 173
Command to Power-Down Entry Parameters .................................................................................. 174
Power-Down Modes ....................................................................................................................... 175
Truth Table – ODT (Nominal) ......................................................................................................... 185
ODT Parameters ............................................................................................................................ 185
Write Leveling with Dynamic ODT Special Case .............................................................................. 186
Dynamic ODT Specific Parameters ................................................................................................. 187
Mode Registers for RTT,nom ............................................................................................................. 187
Mode Registers for RTT(WR) ............................................................................................................. 188
Timing Diagrams for Dynamic ODT ................................................................................................ 188
Synchronous ODT Parameters ........................................................................................................ 193
Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 198
ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 200
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10
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4Gb: x4, x8, x16 DDR3L SDRAM
State Diagram
State Diagram
Figure 2: Simplified State Diagram
CKE L
Power
applied
MRS, MPR,
write
leveling
Initialization
Reset
procedure
Power
on
Self
refresh
SRE
ZQCL
From any
state
RESET
ZQ
calibration
MRS
SRX
REF
ZQCL/ZQCS
Refreshing
Idle
PDE
ACT
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
CKE L
CKE L
PDE
Bank
active
WRITE
WRITE
READ
WRITE AP
Writing
READ
READ AP
READ
WRITE
WRITE AP
Reading
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Precharging
Automatic
sequence
Command
sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
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PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
11
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Functional Description
Functional Description
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation.
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4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Functional Description
• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,
x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,
x8).
• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a
single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
–
–
–
–
Connect UDQS to ground via 1kΩ* resistor.
Connect UDQS# to V DD via 1kΩ* resistor.
Connect UDM to V DD via 1kΩ* resistor.
Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1kΩ resistors,* or float
DQ[15:8].
*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 1 Gig x 4 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQCL, ZQCS
CKE
VSSQ
To pull-up/pull-down
networks
ZQ CAL
RESET#
Control
logic
A12
CK, CK#
VDDQ/2
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
19
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
16
16
Bank 0
rowaddress
latch
and
decoder
65,536
DLL
(1 . . . 4)
Bank 0
memory
array
(65,536 x 256 x 32)
32
READ
FIFO
and
data
MUX
4
DQ[3:0]
READ
drivers
BC4
RTT,nom
8,192
BC4
OTF
A[15:0]
BA[2:0]
19
Address
register
3
sw1
sw2
DM
(1, 2)
Columnaddress
counter/
latch
DQS, DQS#
VDDQ/2
32
Data
interface
Column
decoder
4
Data
WRITE
drivers
and
input
logic
8
RTT,nom
sw1
RTT(WR)
sw2
DM
3
Columns 0, 1, and 2
CK, CK#
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RTT(WR)
Bank
control
logic
256
(x32)
11
DQ[3:0]
DQS, DQS#
VDDQ/2
32
I/O gating
DM mask logic
sw2
sw1
Sense amplifiers
3
RTT(WR)
CK, CK#
16
Rowaddress
MUX
RTT,nom
14
Column 2
(select upper or
lower nibble for BC4)
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
Figure 4: 512 Meg x 8 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQ CAL
RESET#
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
CK, CK#
sw1
(1 . . . 8)
19
Bank 0
Memory
array
(65,536 x 128 x 64)
Bank 0
rowaddress
65,536
latch
and
decoder
16
16
Sense amplifiers
sw2
DLL
16
Rowaddress
MUX
64
DQ8
READ
FIFO
and
data
MUX
8
19
Address
register
DQ[7:0]
DQS, DQS#
VDDQ/2
64
BC4
OTF
RTT,nom
sw1
RTT(WR)
sw2
I/O gating
DM mask logic
3
A[15:0]
BA[2:0]
TDQS#
DQ[7:0]
Read
drivers
BC4
8,192
RTT(WR)
RTT,nom
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
(1, 2)
Bank
control
logic
3
VDDQ/2
(128
x64)
64
8
Data
interface
Data
Column
decoder
Columnaddress
counter/
latch
10
DQS/DQS#
Write
drivers
and
input
logic
RTT,nom
sw1
RTT(WR)
sw2
7
DM/TDQS
(shared pin)
3
Columns 0, 1, and 2
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
Figure 5: 256 Meg x 16 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQ CAL
RESET#
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
18
Column 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
15
15
Bank 0
rowaddress
latch
and
decoder
32,768
DLL
(1 . . . 16)
128
READ
FIFO
and
data
MUX
16
DQ[15:0]
READ
drivers
LDQS, LDQS#, UDQS, UDQS#
BC4
128
18
Address
register
3
sw2
LDQS, LDQS#
Bank
control
logic
(1 . . . 4)
Columnaddress
counter/
latch
UDQS, UDQS#
VDDQ/2
128
Data
interface
Column
decoder
16
Data
WRITE
drivers
and
input
logic
RTT,nom
sw1
RTT(WR)
sw2
7
(1, 2)
LDM/UDM
3
Columns 0, 1, and 2
CK, CK#
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RTT(WR)
I/O gating
DM mask logic
(128
x128)
10
RTT,nom
sw1
BC4
OTF
3
DQ[15:0]
VDDQ/2
Sense amplifiers
A[14:0]
BA[2:0]
sw2
sw1
Bank 0
memory
array
(32,768 x 128 x 128)
16,384
RTT(WR)
CK, CK#
13
Rowaddress
MUX
RTT,nom
15
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 6: 78-Ball FBGA – x4, x8 (Top View)
1
2
3
VSS
VDD
VSS
VDDQ
4
5
6
7
8
9
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
A
B
C
D
VSSQ
E
VREFDQ
NF, DQ7 NF, DQ5
VDDQ NF, DQ4
VDDQ
F
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
A15
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
G
H
J
K
L
M
N
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).
16
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Figure 7: 96-Ball FBGA – x16 (Top View)
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. Ball descriptions listed in Table 4 (page 20) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).
17
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol
Type
Description
A[15:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 66 (page 106).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW)
internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/
disabled is dependent upon the DDR3 SDRAM configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on
the x8.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
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4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol
Type
DQ[3:0]
I/O
Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS#
Output
Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.
VDD
Supply
Power supply: 1.35V; 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V; 1.283–1.45V operational; compatible to 1.5V operation.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference
NC
–
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
NF
–
No function: When configured as a x4 device, these balls are NF. When configured
as a x8 device, these balls are defined as TDQS#, DQ[7:4].
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4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
Description
External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
19
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A[14:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 66 (page 106).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
20
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
Type
UDM
Input
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD
Supply
Power supply: 1.35V; 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V; 1.283–1.45V operational; compatible to 1.5V operation.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference
NC
–
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
Description
Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
21
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Package Dimensions
Figure 8: 78-Ball FBGA – x4, x8
9.0 ±0.1
0.20 S B
10.6 ±0.1
Index mark
0.20 S A
0.20 S
1.20 MAX
S
0.35 ±0.05
0.10 S
B
0.15 M S A B
0.8
78- 0.45 ±0.05
Index mark
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
9.6
A
1.6
6.4
0.8
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
22
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Figure 9: 96-Ball FBGA – x16
9.0 ±0.1
0.20 S B
13.5 ±0.1
Index mark
0.20 S A
0.20 S
1.20 MAX
S
0.35 ±0.05
0.10 S
B
0.15 M S A B
0.8
96- 0.45 ±0.05
0.4
12.0
A
Index mark
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1.6
6.4
0.8
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
23
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
1
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
VDD supply voltage relative to VSSQ
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
0
95
°C
–55
100
°C
TC
TSTG
Operating case temperature – Commercial
Storage temperature
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
2, 3
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ≤300mV.
2. MAX operating case temperature. TC is measured in the center of the package.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
24
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications
Input/Output Capacitance
Table 6: DDR3L Input/Output Capacitance
Note 1 applies to the entire table; gray-shaded cells are DDR3L unique values; all other values are the same for both
DDR3L and DDR3
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Capacitance
Parameters
Symbol Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit Notes
CK and CK#
CCK
0.8
1.6
0.8
1.6
0.8
1.4
0.8
1.4
0.8
1.3
pF
ΔC: CK to CK#
CDCK
0.0
0.15
0.0
0.15
0.0
0.15
0.0
0.15
0.0
0.15
pF
Single-end I/O: DQ, DM
CIO
1.4
2.5
1.4
2.5
1.4
2.3
1.4
2.2
1.4
2.1
pF
Differential I/O: DQS,
DQS#, TDQS, TDQS#
CIO
1.4
2.5
1.4
2.5
1.4
2.3
1.4
2.2
1.4
2.1
pF
0.0
0.2
0.0
0.2
0.0
0.15
0.0
0.15
0.0
0.15
CDIO
–0.5
0.3
–0.5
0.3
–0.5
0.3
–0.5
0.3
–0.5
0.3
pF
CI
0.75
1.3
0.75
1.3
0.75
1.3
0.75
1.2
0.75
1.2
pF
ΔC: CTRL to CK
CDI_CTRL
–0.5
0.3
–0.5
0.3
–0.4
0.2
–0.4
0.2
–0.4
0.2
pF
ΔC: CMD_ADDR to CK
CDI_CMD_
–0.5
0.5
–0.5
0.5
–0.4
0.4
–0.4
0.4
–0.4
0.4
ΔC: DQS to DQS#,
TDQS, TDQS#
CDDQS
ΔC: DQ to DQS
Inputs (CTRL, CMD,
ADDR)
pF
pF
2
3
3
4
5
6
7
ADDR
ZQ pin capacitance
CZQ
–
3.0
–
3.0
–
3.0
–
3.0
–
3.0
pF
Reset pin capacitance
CRE
–
3.0
–
3.0
–
3.0
–
3.0
–
3.0
pF
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. VDD = 1.35V (1.283–1.45V), VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5
× VDDQ, VOUT = 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. CDIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. CDI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)).
7. CDI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)).
25
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4Gb: x4, x8, x16 DDR3L SDRAM
Thermal Characteristics
Thermal Characteristics
Table 7: Thermal Characteristics
Parameter/Condition
Operating case temperature Commercial
Value
Units
Symbol
Notes
0 to +85
°C
TC
1, 2, 3
0 to +95
°C
TC
1, 2, 3, 4
1. MAX operating case temperature. TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs
interval refresh rate. The use of SRT or ASR (if available) must be enabled.
Notes:
Figure 10: Thermal Measurement Point
(L/2)
Tc test point
L
(W/2)
W
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
Electrical Specifications – IDD Specifications and Conditions
Within the following IDD measurement tables, the following definitions and conditions
are used, unless stated otherwise:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
LOW: V IN ≤ V IL(AC)max; HIGH: V IN ≥ V IH(AC)min.
Midlevel: Inputs are V REF = V DD/2.
RON set to RZQ/7 (34Ω
RTT,nom set to RZQ/6 (40Ω
RTT(WR) set to RZQ/2 (120Ω
QOFF is enabled in MR1.
ODT is enabled in MR1 (RTT,nom) and MR2 (RTT(WR)).
TDQS is disabled in MR1.
External DQ/DQS/DM load resistor is 25Ω to V DDQ/2.
Burst lengths are BL8 fixed.
AL equals 0 (except in IDD7).
IDD specifications are tested after the device is properly initialized.
Input slew rate is specified by AC parametric test conditions.
Optional ASR is disabled.
Read burst type uses nibble sequential (MR0[3] = 0).
Loop patterns must be executed at least once before current measurements begin.
Table 8: DDR3L Timing Parameters Used for IDD Measurements – Clock Units
DDR3L-800
IDD
Parameter
tCK
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
-25E
-25
-187E
-187
-15E
-15
-125E
-125
-107
5-5-5
6-6-6
7-7-7
8-8-8
9-9-9
10-10-10
10-10-10
11-11-11
13-13-13
Unit
1.071
ns
(MIN) IDD
2.5
1.875
1.5
1.25
CL IDD
5
6
7
8
9
10
10
11
13
CK
tRCD
5
6
7
8
9
10
10
11
13
CK
20
21
27
28
33
34
38
39
45
CK
15
15
20
20
24
24
28
28
32
CK
tRC
(MIN) IDD
tRAS
tRP
(MIN) IDD
(MIN) IDD
(MIN)
tFAW
5
6
7
8
9
10
10
11
13
CK
x4, x8
16
16
20
20
20
20
24
24
26
CK
x16
20
20
27
27
30
30
32
32
33
CK
tRRD
x4, x8
4
4
4
4
4
4
5
5
5
CK
IDD
x16
4
4
6
6
5
5
6
6
6
CK
tRFC
1Gb
44
44
59
59
74
74
88
88
103
CK
2Gb
64
64
86
86
107
107
128
128
150
CK
4Gb
104
104
139
139
174
174
208
208
243
CK
8Gb
140
140
187
187
234
234
280
280
328
CK
PDF: 09005aef8591e091
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
0
0
–
0
0
0
–
2
D
1
0
0
0
0
0
0
0
0
0
0
–
3
D#
1
1
1
1
0
0
0
0
0
0
0
–
4
D#
1
1
1
1
0
0
0
0
0
0
0
–
Data
0
0
A[2:0]
0
0
A[6:3]
0
0
A[9:7]
0
0
A[10]
0
0
A[15:11]
1
0
BA[2:0]
1
0
ODT
0
1
WE#
0
D
CAS#
ACT
1
RAS#
Command
0
CS#
Cycle
Number
SubLoop
CKE
CK, CK#
Table 9: DDR3L IDD0 Measurement Loop
Repeat cycles 1 through 4 until nRAS - 1; truncate if needed
nRAS
Static HIGH
0
0
1
0
0
0
0
0
0
0
0
–
Repeat cycles 1 through 4 until nRC - 1; truncate if needed
0
Toggling
PRE
nRC
ACT
0
0
1
1
0
0
0
0
0
F
0
–
nRC + 1
D
1
0
0
0
0
0
0
0
0
F
0
–
nRC + 2
D
1
0
0
0
0
0
0
0
0
F
0
–
nRC + 3
D#
1
1
1
1
0
0
0
0
0
F
0
–
D#
1
1
1
1
0
0
0
0
0
F
0
–
nRC + 4
Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1; truncate if needed
nRC + nRAS
PRE
0
0
1
0
0
0
0
0
0
F
0
–
Repeat cycles nRC + 1 through nRC + 4 until 2 × RC - 1; truncate if needed
1
2 × nRC
Repeat sub-loop 0, use BA[2:0] = 1
2
4 × nRC
Repeat sub-loop 0, use BA[2:0] = 2
3
6 × nRC
Repeat sub-loop 0, use BA[2:0] = 3
4
8 × nRC
Repeat sub-loop 0, use BA[2:0] = 4
5
10 × nRC
Repeat sub-loop 0, use BA[2:0] = 5
6
12 × nRC
Repeat sub-loop 0, use BA[2:0] = 6
7
14 × nRC
Repeat sub-loop 0, use BA[2:0] = 7
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. Only selected bank (single) active.
28
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
0
0
0
–
0
0
0
0
–
2
D
1
0
0
0
0
0
0
0
0
0
0
–
3
D#
1
1
1
1
0
0
0
0
0
0
0
–
4
D#
1
1
1
1
0
0
0
0
0
0
0
–
Data2
A[2:0]
0
0
A[6:3]
0
0
A[9:7]
0
0
A[10]
0
0
A[15:11]
1
0
BA[2:0]
1
0
ODT
0
1
WE#
0
D
CAS#
ACT
1
RAS#
Command
0
CS#
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 10: DDR3L IDD1 Measurement Loop
Repeat cycles 1 through 4 until nRCD - 1; truncate if needed
nRCD
RD
0
1
0
1
0
0
0
0
0
0
0
00000000
Repeat cycles 1 through 4 until nRAS - 1; truncate if needed
nRAS
Static HIGH
0
0
1
0
0
0
0
0
0
0
0
–
Repeat cycles 1 through 4 until nRC - 1; truncate if needed
0
Toggling
PRE
nRC
ACT
0
0
1
1
0
0
0
0
0
F
0
–
nRC + 1
D
1
0
0
0
0
0
0
0
0
F
0
–
nRC + 2
D
1
0
0
0
0
0
0
0
0
F
0
–
nRC + 3
D#
1
1
1
1
0
0
0
0
0
F
0
–
nRC + 4
D#
1
1
1
1
0
0
0
0
0
F
0
–
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1; truncate if needed
nRC + nRCD
RD
0
1
0
1
0
0
0
0
0
F
0
00110011
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1; truncate if needed
nRC + nRAS
PRE
0
0
1
0
0
0
0
0
0
F
0
–
Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1; truncate if needed
1
2 × nRC
Repeat sub-loop 0, use BA[2:0] = 1
2
4 × nRC
Repeat sub-loop 0, use BA[2:0] = 2
3
6 × nRC
Repeat sub-loop 0, use BA[2:0] = 3
4
8 × nRC
Repeat sub-loop 0, use BA[2:0] = 4
5
10 × nRC
Repeat sub-loop 0, use BA[2:0] = 5
6
12 × nRC
Repeat sub-loop 0, use BA[2:0] = 6
7
14 × nRC
Repeat sub-loop 0, use BA[2:0] = 7
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1.
2.
3.
4.
DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
DM is LOW.
Burst sequence is driven on each DQ signal by the RD command.
Only selected bank (single) active.
29
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 11: DDR3L IDD Measurement Conditions for Power-Down Currents
Name
IDD2P0 Precharge
Power-Down
Current (Slow Exit)1
IDD2P1 Precharge
Power-Down
Current (Fast Exit)1
IDD2Q Precharge
Quiet
Standby Current
IDD3P Active
Power-Down
Current
N/A
N/A
N/A
N/A
Timing pattern
CKE
External clock
tCK
LOW
LOW
HIGH
LOW
Toggling
Toggling
Toggling
Toggling
tCK
tRC
(MIN) IDD
N/A
tCK
(MIN) IDD
N/A
tCK
(MIN) IDD
N/A
tCK
(MIN) IDD
N/A
tRAS
N/A
N/A
N/A
N/A
tRCD
N/A
N/A
N/A
N/A
tRRD
N/A
N/A
N/A
N/A
tRC
N/A
N/A
N/A
N/A
CL
N/A
N/A
N/A
N/A
AL
N/A
N/A
N/A
N/A
CS#
HIGH
HIGH
HIGH
HIGH
Command inputs
LOW
LOW
LOW
LOW
Row/column addr
LOW
LOW
LOW
LOW
Bank addresses
LOW
LOW
LOW
LOW
DM
LOW
LOW
LOW
LOW
Midlevel
Midlevel
Midlevel
Midlevel
Data I/O
Output buffer DQ, DQS
Enabled
Enabled
Enabled
Enabled
Enabled, off
Enabled, off
Enabled, off
Enabled, off
Burst length
8
8
8
8
Active banks
None
None
None
All
ODT2
Idle banks
All
All
All
None
Special notes
N/A
N/A
N/A
N/A
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast
exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).
2. “Enabled, off” means the MR bits are enabled, but the signal is LOW.
30
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
Static HIGH
Toggling
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
0
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 12: DDR3L IDD2N and IDD3N Measurement Loop
0
D
1
0
0
0
0
0
0
0
0
0
0
–
1
D
1
0
0
0
0
0
0
0
0
0
0
–
2
D#
1
1
1
1
0
0
0
0
0
F
0
–
3
D#
1
1
1
1
0
0
0
0
0
F
0
–
1
4–7
Repeat sub-loop 0, use BA[2:0] = 1
2
8–11
Repeat sub-loop 0, use BA[2:0] = 2
3
12–15
Repeat sub-loop 0, use BA[2:0] = 3
4
16–19
Repeat sub-loop 0, use BA[2:0] = 4
5
20–23
Repeat sub-loop 0, use BA[2:0] = 5
6
24–27
Repeat sub-loop 0, use BA[2:0] = 6
7
28–31
Repeat sub-loop 0, use BA[2:0] = 7
Notes:
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed during IDD2N; all banks open during IDD3N.
Static HIGH
Toggling
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data
0
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 13: DDR3L IDD2NT Measurement Loop
0
D
1
0
0
0
0
0
0
0
0
0
0
–
1
D
1
0
0
0
0
0
0
0
0
0
0
–
2
D#
1
1
1
1
0
0
0
0
0
F
0
–
3
D#
1
1
1
1
0
0
0
0
0
F
0
–
1
4–7
Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0
2
8–11
Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1
3
12–15
Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1
4
16–19
Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0
5
20–23
Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0
6
24–27
Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1
7
28–31
Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
3. All banks closed.
31
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
A[2:0]
Data3
0
0
0
0
0
0
0
00000000
0
0
0
0
0
0
0
0
–
2
D#
1
1
1
1
0
0
0
0
0
0
0
–
3
D#
1
1
1
1
0
0
0
0
0
0
0
–
4
RD
0
1
0
1
0
0
0
0
0
F
0
00110011
5
D
1
0
0
0
0
0
0
0
0
F
0
–
6
D#
1
1
1
1
0
0
0
0
0
F
0
–
7
D#
1
1
1
1
0
0
0
0
0
F
0
–
1
8–15
Repeat sub-loop 0, use BA[2:0] = 1
2
16–23
Repeat sub-loop 0, use BA[2:0] = 2
3
24–31
Repeat sub-loop 0, use BA[2:0] = 3
4
32–39
Repeat sub-loop 0, use BA[2:0] = 4
5
40–47
Repeat sub-loop 0, use BA[2:0] = 5
6
48–55
Repeat sub-loop 0, use BA[2:0] = 6
7
56–63
Repeat sub-loop 0, use BA[2:0] = 7
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1.
2.
3.
4.
A[6:3]
1
0
A[9:7]
0
0
A[10]
1
1
A[15:11]
CAS#
0
D
BA[2:0]
RAS#
RD
1
ODT
CS#
0
WE#
Command
Static HIGH
Toggling
0
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 14: DDR3L IDD4R Measurement Loop
DQ, DQS, DQS# are midlevel when not driving in burst sequence.
DM is LOW.
Burst sequence is driven on each DQ signal by the RD command.
All banks open.
32
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
A[2:0]
Data3
1
0
0
0
0
0
0
00000000
0
1
0
0
0
0
0
0
–
2
D#
1
1
1
1
1
0
0
0
0
0
0
–
3
D#
1
1
1
1
1
0
0
0
0
0
0
–
4
WR
0
1
0
0
1
0
0
0
0
F
0
00110011
5
D
1
0
0
0
1
0
0
0
0
F
0
–
6
D#
1
1
1
1
1
0
0
0
0
F
0
–
7
D#
1
1
1
1
1
0
0
0
0
F
0
–
1
8–15
Repeat sub-loop 0, use BA[2:0] = 1
2
16–23
Repeat sub-loop 0, use BA[2:0] = 2
3
24–31
Repeat sub-loop 0, use BA[2:0] = 3
4
32–39
Repeat sub-loop 0, use BA[2:0] = 4
5
40–47
Repeat sub-loop 0, use BA[2:0] = 5
6
48–55
Repeat sub-loop 0, use BA[2:0] = 6
7
56–63
Repeat sub-loop 0, use BA[2:0] = 7
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1.
2.
3.
4.
A[6:3]
0
0
A[9:7]
0
0
A[10]
1
1
A[15:11]
CAS#
0
D
BA[2:0]
RAS#
WR
1
ODT
CS#
0
WE#
Command
Static HIGH
Toggling
0
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 15: DDR3L IDD4W Measurement Loop
DQ, DQS, DQS# are midlevel when not driving in burst sequence.
DM is LOW.
Burst sequence is driven on each DQ signal by the WR command.
All banks open.
33
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
0
0
0
–
0
0
0
0
–
2
D
1
0
0
0
0
0
0
0
0
0
0
–
3
D#
1
1
1
1
0
0
0
0
0
F
0
–
4
D#
1
1
1
1
0
0
0
0
0
F
0
–
Static HIGH
Toggling
1a
1b
5–8
Repeat sub-loop 1a, use BA[2:0] = 1
1c
9–12
Repeat sub-loop 1a, use BA[2:0] = 2
1d
13–16
Repeat sub-loop 1a, use BA[2:0] = 3
1e
17–20
Repeat sub-loop 1a, use BA[2:0] = 4
1f
21–24
Repeat sub-loop 1a, use BA[2:0] = 5
1g
25–28
Repeat sub-loop 1a, use BA[2:0] = 6
1h
29–32
Repeat sub-loop 1a, use BA[2:0] = 7
2
33–nRFC - 1
Repeat sub-loop 1a through 1h until nRFC - 1; truncate if needed
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
Data
0
0
A[2:0]
0
0
A[6:3]
0
0
A[9:7]
0
0
A[10]
1
0
A[15:11]
0
0
BA[2:0]
0
1
ODT
0
D
WE#
REF
1
CAS#
Command
0
RAS#
Cycle
Number
0
CS#
Sub-Loop
CKE
CK, CK#
Table 16: DDR3L IDD5B Measurement Loop
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
34
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
Table 17: DDR3L IDD Measurement Conditions for IDD6, IDD6ET, and IDD8
IDD Test
CKE
External clock
IDD6: Self Refresh Current
Normal Temperature Range
TC = 0°C to +85°C
IDD6ET: Self Refresh Current
Extended Temperature Range
TC = 0°C to +95°C
IDD8: Reset2
LOW
LOW
Midlevel
Off, CK and CK# = LOW
Off, CK and CK# = LOW
Midlevel
tCK
N/A
N/A
N/A
tRC
N/A
N/A
N/A
tRAS
N/A
N/A
N/A
tRCD
N/A
N/A
N/A
tRRD
N/A
N/A
N/A
tRC
N/A
N/A
N/A
CL
N/A
N/A
N/A
AL
N/A
N/A
N/A
CS#
Midlevel
Midlevel
Midlevel
Command inputs
Midlevel
Midlevel
Midlevel
Row/column addresses
Midlevel
Midlevel
Midlevel
Bank addresses
Midlevel
Midlevel
Midlevel
Data I/O
Midlevel
Midlevel
Midlevel
Output buffer DQ, DQS
Enabled
Enabled
Midlevel
Enabled, midlevel
Enabled, midlevel
Midlevel
Burst length
N/A
N/A
N/A
Active banks
N/A
N/A
None
Idle banks
N/A
N/A
All
SRT
Disabled (normal)
Enabled (extended)
N/A
ASR
Disabled
Disabled
N/A
ODT1
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable
and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns + tRFC.
35
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Data3
0
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 18: DDR3L IDD7 Measurement Loop
0
ACT
0
0
1
1
0
0
0
0
0
0
0
–
1
RDA
0
1
0
1
0
0
0
1
0
0
0
00000000
2
D
1
0
0
0
0
0
0
0
0
0
0
–
3
1
Static HIGH
nRRD
ACT
0
0
1
1
0
1
0
0
0
F
0
–
nRRD + 1
RDA
0
1
0
1
0
1
0
1
0
F
0
00110011
nRRD + 2
D
1
0
0
0
0
1
0
0
0
F
0
–
0
–
nRRD + 3
Repeat cycle nRRD + 2 until 2 × nRRD - 1
2
2 × nRRD
Repeat sub-loop 0, use BA[2:0] = 2
3
3 × nRRD
Repeat sub-loop 1, use BA[2:0] = 3
4 × nRRD
4
Toggling
Repeat cycle 2 until nRRD - 1
D
1
0
0
0
0
3
0
0
0
F
4 × nRRD + 1
Repeat cycle 4 × nRRD until nFAW - 1, if needed
5
nFAW
Repeat sub-loop 0, use BA[2:0] = 4
6
nFAW + nRRD
Repeat sub-loop 1, use BA[2:0] = 5
7
nFAW + 2 × nRRD
Repeat sub-loop 0, use BA[2:0] = 6
8
nFAW + 3 × nRRD
Repeat sub-loop 1, use BA[2:0] = 7
9
nFAW + 4 × nRRD
D
1
nFAW + 4 × nRRD + 1
10
0
0
0
7
0
0
0
F
0
–
Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed
2 × nFAW
ACT
0
0
1
1
0
0
0
0
0
F
0
–
2 × nFAW + 1
RDA
0
1
0
1
0
0
0
1
0
F
0
00110011
2 × nFAW + 2
D
1
0
0
0
0
0
0
0
0
F
0
–
2 × nFAW + 3
11
0
Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1
2 × nFAW + nRRD
ACT
0
0
1
1
0
1
0
0
0
0
0
–
2 × nFAW + nRRD + 1
RDA
0
1
0
1
0
1
0
1
0
0
0
00000000
2 × nFAW + nRRD + 2
D
1
0
0
0
0
1
0
0
0
0
0
–
2 × nFAW + nRRD + 3
Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1
12
2 × nFAW + 2 × nRRD
Repeat sub-loop 10, use BA[2:0] = 2
13
2 × nFAW + 3 × nRRD
Repeat sub-loop 11, use BA[2:0] = 3
14
2 × nFAW + 4 × nRRD
D
1
0
0
0
0
3
0
0
0
0
0
2 × nFAW + 4 × nRRD + 1
Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed
3 × nFAW
Repeat sub-loop 10, use BA[2:0] = 4
15
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
36
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – IDD Specifications and Conditions
3 × nFAW + 4 × nRRD + 1
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1.
2.
3.
4.
A[6:3]
A[9:7]
A[10]
Data3
19
3 × nFAW + 3 × nRRD
3 × nFAW + 4 × nRRD
A[2:0]
18
A[15:11]
Repeat sub-loop 10, use BA[2:0] = 6
BA[2:0]
3 × nFAW + 2 × nRRD
ODT
17
WE#
Repeat sub-loop 11, use BA[2:0] = 5
CAS#
3 × nFAW + nRRD
RAS#
16
CS#
Cycle
Number
Command
Sub-Loop
CKE
Static HIGH
Toggling
CK, CK#
Table 18: DDR3L IDD7 Measurement Loop (Continued)
0
–
Repeat sub-loop 11, use BA[2:0] = 7
D
1
0
0
0
0
7
0
0
0
0
Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed
DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
DM is LOW.
Burst sequence is driven on each DQ signal by the RD command.
AL = CL-1.
37
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications
Table 19: IDD Maximum Limits - Die Rev F
Speed Bin
Parameter
Symbol
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
Symbol
IDD1
DDR3L-1333
DDR3L-1600
Units
x4, x8
40
45
mA
1, 2
IDD0
50
55
mA
1, 2
x4
55
60
mA
1, 2
x8
55
60
mA
1, 2
x16
70
75
mA
1, 2
Width
Notes
Precharge power-down current: Slow exit
IDD2P0
All
12
12
mA
1, 2
Precharge power-down current: Fast exit
IDD2P1
All
17
18
mA
1, 2
Precharge quiet standby current
IDD2Q
All
25
25
mA
1, 2
Precharge standby current
IDD2N
All
25
25
mA
1, 2
Precharge standby ODT current
IDD2NT
x4, x8
30
30
mA
1, 2
x16
30
30
mA
1, 2
x4, x8
20
20
mA
1, 2
x16
22
32
x4, x8
30
30
mA
1, 2
x16
30
32
mA
1, 2
x4
80
90
mA
1, 2
x8
90
100
mA
1, 2
x16
120
135
mA
1, 2
x4
85
95
mA
1, 2
x8
95
105
mA
1, 2
x16
135
150
mA
1, 2
Active power-down current
IDD3P
Active standby current
IDD3N
Burst read operating current
IDD4R
Burst write operating current
IDD4W
Burst refresh current
IDD5B
All
160
160
mA
1, 2
Room temperature self refresh
IDD6
All
12
12
mA
1, 2, 3
Extended temperature self refresh
IDD6ET
All
17
17
mA
2, 4
All banks interleaved read current
IDD7
x4, x8
145
150
mA
1, 2
Reset current
IDD8
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
1.
2.
3.
4.
x16
175
195
mA
1, 2
All
IDD2P + 2mA
IDD2P + 2mA
mA
1, 2
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC (MAX) = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
38
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
DC Operating Conditions
Table 20: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Unit
Notes
Supply voltage
VDD
1.283
1.35
1.45
V
1–7
I/O supply voltage
VDDQ
1.283
1.35
1.45
V
1–7
II
–2
–
2
μA
IVREF
–1
–
1
μA
Input leakage current
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Notes:
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
8, 9
1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the
DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC
timing parameters.
3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average
of VDD/VDDQ(t) over a very long period of time (for example, 1 second).
4. Under these supply voltages, the device operates to this DDR3L specification.
5. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
6. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device.
7. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3 operation (see VDD Voltage Switching (page 127)).
8. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
9. VREF (see Table 21).
39
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Input Operating Conditions
Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Unit
VIN low; DC/commands/address busses
VIL
VSS
N/A
See Table 22
V
VIN high; DC/commands/address busses
VIH
See Table 22
N/A
VDD
V
Notes
Input reference voltage command/address bus
VREFCA(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
1, 2
I/O reference voltage DQ bus
VREFDQ(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
2, 3
I/O reference voltage DQ bus in SELF REFRESH
VREFDQ(SR)
VSS
0.5 × VDD
VDD
V
4
VTT
–
0.5 × VDDQ
–
V
5
Command/address termination voltage
(system level, not direct DRAM input)
Notes:
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1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (non-common mode) on VREFCA may not exceed
±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (non-common mode) on VREFDQ may not exceed
±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC).
4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH,
within restrictions outlined in the SELF REFRESH section.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. Minimum and maximum values are system-dependent.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Table 22: DDR3L 1.35V Input Switching Conditions - Command and Address
Parameter/Condition
Symbol
DDR3L-800/1066
DDR3L-1333/1600
DDR3L-1866
Units
Command and Address
5
160
160
–
mV
VIH(AC135),min5
135
135
135
mV
–
–
125
mV
VIH(DC90),min
90
90
90
mV
Input low DC voltage: Logic 0
VIL(DC90),min
–90
–90
–90
mV
Input low AC voltage: Logic 0
VIL(AC125),min5
–
–
–125
mV
VIL(AC135),min
5
–135
–135
–135
mV
VIL(AC160),min
5
–160
–160
–
mV
Input high AC voltage: Logic 1
VIH(AC160),min
VIH(AC125,)min
Input high DC voltage: Logic 1
5
DQ and DM
Input high AC voltage: Logic 1
VIH(AC160),min5
160
160
–
mV
5
135
135
135
mV
5
–
–
130
mV
VIH(AC135),min
VIH(AC125),min
Input high DC voltage: Logic 1
VIH(DC90),min
90
90
90
mV
Input low DC voltage: Logic 0
VIL(DC90),min
–90
–90
–90
mV
Input low AC voltage: Logic 0
VIL(AC125),min5
Notes:
–
–
–130
mV
VIL(AC135),min
5
–135
–135
–135
mV
VIL(AC160),min
5
–160
–160
–
mV
1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ
and DM inputs.
2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and
VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/
command inputs must use either VIH(AC160),min with tIS(AC160) of 210ps or VIH(AC150),min
with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min
with tDS(AC160) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Table 23: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Differential input logic high – slew
VIH,diff(AC)slew
180
N/A
mV
4
Differential input logic low – slew
VIL,diff(AC)slew
N/A
–180
mV
4
Differential input logic high
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDD/VDDQ
mV
5
Differential input logic low
VIL,diff(AC)
VSS/VSSQ
2 × (VIL(AC) - VREF)
mV
6
Differential input crossing voltage
relative to VDD/2 for DQS, DQS#;
CK, CK#
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
5, 7, 9
Differential input crossing voltage
relative to VDD/2 for CK, CK#
VIX (175)
VREF(DC) - 175
VREF(DC) + 175
mV
5, 7–9
VDDQ/2 + 160
VDDQ
mV
5
VDD/2 + 160
VDD
mV
5
VSSQ
VDDQ/2 - 160
mV
6
VSS
VDD/2 - 160
mV
6
Single-ended high level for strobes
VSEH
Single-ended high level for CK,
CK#
Single-ended low level for strobes
Single-ended low level for CK, CK#
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
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VSEL
Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.
Differential input slew rate = 2 V/ns.
Defines slew rate reference points, relative to input crossing voltages.
Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable.
Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable.
The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range
is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and
the differential slew rate of CK, CK# is greater than 3 V/ns.
VIX must provide 25mV (single-ended) of the voltages separation.
42
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Figure 11: DDR3L 1.35V Input Signal
VIL and VIH levels with ringback
VDDQ + 0.4V
Overshoot
VDD + 0.4V
Narrow pulse width
Minimum VIL and VIH levels
VIH MIN(AC)
VIH MIN(DC)
VIH(AC)
VIH(DC)
VIL MIN(AC)
VDDQ
VREF + 125/135/160mV
VIH(AC)
VREF + 90mV
VIH(DC)
VREF DC MAX + 1% VDD
VREF + 1% VDD
VREF = VDD/2
VREF - 1% VDD
VREF DC MIN - 1% VDD
MAX 2% Total
VREF DC MAX
VREF
DC MIN
MAX 2% Total
VIL MIN(DC)
VDD
VIL(DC)
VREFDQ + AC noise
VREFDQ + DC error
VREFDQ - DC error
VREFDQ - AC noise
VREF - 90mV
VIL(DC)
VREF - 125/135/160mV
VIL(AC)
VIL(AC)
0.0V
VSS
VSS - 0.40V
Undershoot
VSS - 0.40V
Narrow pulse width
Note:
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1. Numbers in diagrams reflect nominal values.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
DDR3L 1.35V AC Overshoot/Undershoot Specification
Table 24: DDR3L Control and Address Pins
Parameter
DDR3L-800
DRR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Maximum peak amplitude allowed
for overshoot area
(see Figure 12)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed
for undershoot area
(see Figure 13)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above VDD
(see Figure 12)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
Maximum undershoot area below VSS
(see Figure 13)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
Table 25: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins
Parameter
DDR3L-800
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Maximum peak amplitude allowed
for overshoot area
(see Figure 12)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed
for undershoot area
(see Figure 13)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above
VDD/VDDQ (see Figure 12)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
Maximum undershoot area below
VSS/VSSQ (see Figure 13)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
Figure 12: Overshoot
Maximum amplitude
Overshoot area
Volts (V)
VDD/VDDQ
Time (ns)
Figure 13: Undershoot
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
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Electrical Specifications – DC and AC
Figure 14: VIX for Differential Signals
VDD, VDDQ
VDD, VDDQ
CK#, DQS#
CK#, DQS#
X
VIX
VIX
VDD/2, VDDQ/2
X
X
VDD/2, VDDQ/2
VIX
X
VIX
CK, DQS
CK, DQS
VSS, VSSQ
VSS, VSSQ
Figure 15: Single-Ended Requirements for Differential Signals
VDD or VDDQ
VSEH,min
VDD/2 or VDDQ/2
VSEH
CK or DQS
VSEL,max
VSEL
VSS or VSSQ
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Electrical Specifications – DC and AC
Figure 16: Definition of Differential AC-Swing and tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff,min
CK - CK#
DQS - DQS#
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Table 26: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC
Ringback
DDR3L-800/1066/1333/1600
tDVAC
tDVAC
DDR3L-1866
tDVAC
tDVAC
tDVAC
Slew Rate (V/ns)
at
320mV (ps)
at
270mV (ps)
at
270mV (ps)
at
250mV (ps)
at
260mV (ps)
>4.0
189
201
163
168
176
4.0
189
201
163
168
176
3.0
162
179
140
147
154
2.0
109
134
95
105
111
1.8
91
119
80
91
97
1.6
69
100
62
74
78
1.4
40
76
37
52
55
1.2
Note1
44
5
22
24
1.0
Note1
<1.0
Note1
Note:
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1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input
signal shall become equal to or less than VIL(AC) level.
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Electrical Specifications – DC and AC
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V REF and the first crossing of V IH(AC)min. Setup (tIS and tDS)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V REF and the first crossing of V IL(AC)max.
Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF. Hold (tIH and tDH)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V IH(DC)min and the first crossing of V REF (see Figure 17 (page 48)).
Table 27: Single-Ended Input Slew Rate Definition
Input Slew Rates
(Linear Signals)
Input
Measured
Edge
From
To
Rising
VREF
VIH(AC),min
Falling
VREF
VIL(AC),max
Rising
VIL(DC),max
VREF
Falling
VIH(DC),min
VREF
Calculation
VIH(AC),min - VREF
ΔTRSse
Setup
VREF - VIL(AC),max
ΔTFSse
VREF - VIL(DC),max
ΔTFHse
Hold
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47
VIH(DC),min - VREF
ΔTRSHse
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Figure 17: Nominal Slew Rate Definition for Single-Ended Input Signals
ΔTRSse
Setup
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC)min
VIH(DC)min
VREFDQ or
VREFCA
VIL(DC)max
VIL(AC)max
ΔTFSse
ΔTRHse
Hold
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC)min
VIH(DC)min
VREFDQ or
VREFCA
VIL(DC)max
VIL(AC)max
ΔTFHse
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured, as shown in Table 28 and Figure 18. The nominal slew rate for a rising signal is
defined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for a
falling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max.
Table 28: DDR3L 1.35V Differential Input Slew Rate Definition
Differential Input
Slew Rates
(Linear Signals)
Input
CK and
DQS
reference
Measured
Edge
From
To
Calculation
Rising
VIL,diff,max
VIH,diff,min
Falling
VIH,diff,min
VIL,diff,max
VIH,diff,min - VIL,diff,max
ΔTRdiff
VIH,diff,min - VIL,diff,max
ΔTFdiff
Figure 18: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
Differential input voltage (DQS, DQS#; CK, CK#)
ΔTRdiff
VIH,diff,min
0
VIL,diff,max
ΔTFdiff
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4Gb: x4, x8, x16 DDR3L SDRAM
ODT Characteristics
ODT Characteristics
The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the
DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values
and a functional representation are listed in Table 29 and Table 30 (page 51). The individual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows:
• RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off
• RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off
Figure 19: ODT Levels and I-V Characteristics
Chip in termination mode
ODT
VDDQ
IPU
IOUT = IPD - IPU
RTT(PU)
To
other
circuitry
such as
RCV, . . .
DQ
IOUT
RTT(PD)
VOUT
IPD
VSSQ
Table 29: On-Die Termination DC Electrical Characteristics
Parameter/Condition
Symbol
RTT effective impedance
RTT(EFF)
ΔVM
Deviation of VM with respect to
VDDQ/2
Notes:
Min
Nom
Max
Unit
See Table 30 (page 51)
–5
5
Notes
1, 2
%
1, 2, 3
1. Tolerance limits are applicable after proper ZQ calibration has been performed at a
stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity
(page 52) if either the temperature or voltage changes after calibration.
2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current
I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]:
VIH(AC) - VIL(AC)
RTT =
I(VIH(AC)) - I(VIL(AC))
3. Measure voltage (VM) at the tested pin with no load:
ΔVM =
2 × VM
– 1 × 100
VDDQ
4. For IT and AT devices, the minimum values are derated by 6% when the device operates
between –40°C and 0°C (TC).
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4Gb: x4, x8, x16 DDR3L SDRAM
ODT Characteristics
1.35V ODT Resistors
Table 30 provides an overview of the ODT DC electrical characteristics. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what RTT is targeted to provide:
•
•
•
•
•
RTT Ω is made up of RTT120(PD240) and RTT120(PU240)
RTT Ω is made up of RTT60(PD120) and RTT60(PU120)
RTT Ω is made up of RTT40(PD80) and RTT40(PU80)
RTT Ω is made up of RTT30(PD60) and RTT30(PU60)
RTT Ω is made up of RTT20(PD40) and RTT20(PU40)
Table 30: 1.35V RTT Effective Impedance
Gray-shaded cells are DDR3L unique values; All other values are the same for both DDR3L and DDR3
MR1
[9, 6, 2]
RTT
Resistor
VOUT
Min
Nom
Max
0, 1, 0
Ω
RTT,120PD240
RTT,120PU240
Ω
0, 0, 1
Ω
RTT,60PD120
RTT,60PU120
Ω
0, 1, 1
Ω
RTT,40PD80
RTT,40PU80
Ω
1, 0, 1
Ω
RTT,30PD60
RTT,30PU60
Ω
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Units
0.2 × VDDQ
0.6
1.0
1.15
RZQ/1
0.5 × VDDQ
0.9
1.0
1.15
RZQ/1
0.8 × VDDQ
0.9
1.0
1.45
RZQ/1
0.2 × VDDQ
0.9
1.0
1.45
RZQ/1
0.5 × VDDQ
0.9
1.0
1.15
RZQ/1
0.8 × VDDQ
0.6
1.0
1.15
RZQ/1
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/2
0.2 × VDDQ
0.6
1.0
1.15
RZQ/2
0.5 × VDDQ
0.9
1.0
1.15
RZQ/2
0.8 × VDDQ
0.9
1.0
1.45
RZQ/2
0.2 × VDDQ
0.9
1.0
1.45
RZQ/2
0.5 × VDDQ
0.9
1.0
1.15
RZQ/2
0.8 × VDDQ
0.6
1.0
1.15
RZQ/2
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/4
0.2 × VDDQ
0.6
1.0
1.15
RZQ/3
0.5 × VDDQ
0.9
1.0
1.15
RZQ/3
0.8 × VDDQ
0.9
1.0
1.45
RZQ/3
0.2 × VDDQ
0.9
1.0
1.45
RZQ/3
0.5 × VDDQ
0.9
1.0
1.15
RZQ/3
0.8 × VDDQ
0.6
1.0
1.15
RZQ/3
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/6
0.2 × VDDQ
0.6
1.0
1.15
RZQ/4
0.5 × VDDQ
0.9
1.0
1.15
RZQ/4
0.8 × VDDQ
0.9
1.0
1.45
RZQ/4
0.2 × VDDQ
0.9
1.0
1.45
RZQ/4
0.5 × VDDQ
0.9
1.0
1.15
RZQ/4
0.8 × VDDQ
0.6
1.0
1.15
RZQ/4
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/8
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ODT Characteristics
Table 30: 1.35V RTT Effective Impedance (Continued)
Gray-shaded cells are DDR3L unique values; All other values are the same for both DDR3L and DDR3
MR1
[9, 6, 2]
RTT
Resistor
VOUT
Min
Nom
Max
1, 0, 0
Ω
RTT,20PD40
0.2 × VDDQ
0.6
1.0
1.15
RZQ/6
0.5 × VDDQ
0.9
1.0
1.15
RZQ/6
0.8 × VDDQ
0.9
1.0
1.45
RZQ/6
0.2 × VDDQ
0.9
1.0
1.45
RZQ/6
0.5 × VDDQ
0.9
1.0
1.15
RZQ/6
0.8 × VDDQ
0.6
1.0
1.15
RZQ/6
VIL(AC) to VIH(AC)
0.9
1.0
1.65
RZQ/12
RTT,20PU40
Ω
Units
ODT Sensitivity
If either the temperature or voltage changes after I/O calibration, then the tolerance
limits listed in Table 29 and Table 30 can be expected to widen according to Table 31
and Table 32.
Table 31: ODT Sensitivity Definition
Symbol
Min
Max
Unit
RTT
0.9 - dRTTdT × |DT| - dRTTdV × |DV|
1.6 + dRTTdT × |DT| + dRTTdV × |DV|
RZQ/(2, 4, 6, 8, 12)
Note:
1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ.
Table 32: ODT Temperature and Voltage Sensitivity
Note:
Change
Min
Max
Unit
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ.
ODT Timing Definitions
ODT loading differs from that used in AC timing measurements. The reference load for
ODT timings is shown in Figure 20. Two parameters define when ODT turns on or off
synchronously, two define when ODT turns on or off asynchronously, and another defines when ODT turns on or off dynamically. Table 33 and Table 34 (page 53) outline
and provide definition and measurement references settings for each parameter.
ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to
turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance
begins to turn off.
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ODT Characteristics
Figure 20: ODT Timing Reference Load
DUT
CK, CK#
VREF
VDDQ/2
RTT = 25Ω
DQ, DM
DQS, DQS#
TDQS, TDQS#
ZQ
VTT = VSSQ
Timing reference point
RZQ = 240Ω
VSSQ
Table 33: ODT Timing Definitions
Symbol
Begin Point Definition
End Point Definition
Figure
tAON
Rising edge of CK – CK# defined by the end
point of ODTLon
Extrapolated point at VSSQ
Figure 21 (page 54)
tAOF
Rising edge of CK – CK# defined by the end
point of ODTLoff
Extrapolated point at VRTT,nom
Figure 21 (page 54)
tAONPD
Rising edge of CK – CK# with ODT first being Extrapolated point at VSSQ
registered HIGH
Figure 22 (page 54)
tAOFPD
Rising edge of CK – CK# with ODT first being Extrapolated point at VRTT,nom
registered LOW
Figure 22 (page 54)
Rising edge of CK – CK# defined by the end Extrapolated points at VRTT(WR) and
point of ODTLcnw, ODTLcwn4, or ODTLcwn8 VRTT,nom
Figure 23 (page 55)
tADC
Table 34: DDR3L(1.35V) Reference Settings for ODT Timing Measurements
Gray-shaded cells are DDR3L unique values; All other values are the same for both DDR3L and DDR3
Measured
Parameter
RTT,nom Setting
RTT(WR) Setting
VSW1
tAON
tAOF
tAONPD
tAOFPD
tADC
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VSW2
RZQ/4 (60Ω
N/A
50mV
100mV
RZQ/12 (20Ω
N/A
100mV
200mV
RZQ/4 (60Ω
N/A
50mV
100mV
RZQ/12 (20Ω
N/A
100mV
200mV
RZQ/4 (60Ω
N/A
50mV
100mV
RZQ/12 (20Ω
N/A
100mV
200mV
RZQ/4 (60Ω
N/A
50mV
100mV
RZQ/12 (20Ω
N/A
100mV
200mV
RZQ/12 (20Ω
RZQ/2 (20Ω
200mV
250mV
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ODT Characteristics
Figure 21: tAON and tAOF Definitions
tAON
tAOF
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLoff
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLon
CK
CK
VDDQ/2
CK#
CK#
tAON
tAOF
End point: Extrapolated point at VRTT,nom
TSW2
TSW1
TSW1
DQ, DM
DQS, DQS#
TDQS, TDQS#
VSW2
TSW1
VSW2
VSW1
VSW1
VSSQ
VRTT,nom
VSSQ
End point: Extrapolated point at VSSQ
Figure 22: tAONPD and tAOFPD Definitions
tAONPD
tAOFPD
Begin point: Rising edge of CK - CK#
with ODT first registered low
Begin point: Rising edge of CK - CK#
with ODT first registered high
CK
CK
VDDQ/2
CK#
CK#
tAONPD
tAOFPD
End point: Extrapolated point at VRTT,nom
TSW2
TSW2
TSW1
DQ, DM
DQS, DQS#
TDQS, TDQS#
TSW1
VSW2
VSSQ
VRTT,nom
VSW2
VSW1
VSW1
VSSQ
End point: Extrapolated point at VSSQ
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ODT Characteristics
Figure 23: tADC Definition
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLcnw
Begin point: Rising edge of CK - CK# defined by
the end point of ODTLcwn4 or ODTLcwn8
CK
VDDQ/2
CK#
tADC
VRTT,nom
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point:
Extrapolated
point at VRTT,nom
tADC
VRTT,nom
TSW21
TSW11
VSW2
VSW1
TSW22
TSW12
VRTT(WR)
End point: Extrapolated point at VRTT(WR)
VSSQ
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Output Driver Impedance
Output Driver Impedance
The output driver impedance is selected by MR1[5,1] during initialization. The selected
value is able to maintain the tight tolerances specified if proper ZQ calibration is performed. Output specifications refer to the default output driver unless specifically stated otherwise. A functional representation of the output buffer is shown below. The output driver impedance RON is defined by the value of the external reference resistor RZQ
as follows:
• RON,x = RZQ/y (with RZQ = 240Ω x Ω or 40Ω with y = 7 or 6, respectively)
The individual pull-up and pull-down resistors RON(PU) and RON(PD) are defined as follows:
• RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off
• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off
Figure 24: Output Driver
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
RON(PU)
DQ
IOUT
RON(PD)
VOUT
IPD
VSSQ
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Output Driver Impedance
34 Ohm Output Driver Impedance
The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings
and specifications listed herein apply to the 34Ω driver only. Its impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ/7 (with
nominal RZQ = 240Ω ±1%) and is actually 34.3Ω 
Table 35: DDR3L 34 Ohm Driver Impedance Characteristics
Gray-shaded cells are DDR3L unique values; All other values are the same for both DDR3L and DDR3
MR1
[5, 1]
RON
Resistor
VOUT
Min
Nom
Max
0, 1
Ω
RON,34PD
RON,34PU
Pull-up/pull-down mismatch (MMPUPD)
Notes:
Units
0.2 × VDDQ
0.6
1.0
1.15
RZQ/7
0.5 × VDDQ
0.9
1.0
1.15
RZQ/7
0.8 × VDDQ
0.9
1.0
1.45
RZQ/7
0.2 × VDDQ
0.9
1.0
1.45
RZQ/7
0.5 × VDDQ
0.9
1.0
1.15
RZQ/7
0.8 × VDDQ
0.6
1.0
1.15
RZQ/7
VIL(AC) to VIH(AC)
–10
N/A
10
%
1. Tolerance limits assume RZQ of 240Ω ±1% and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage: VDDQ = VDD; VSSQ = VSS).
Refer to DDR3L 34 Ohm Output Driver Sensitivity (page 59) if either the temperature
or the voltage changes after calibration.
2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 × VDDQ:
RON(PU) - RON(PD)
MMPUPD =
× 100
RON,nom
3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (TC).
A larger maximum limit will result in slightly lower minimum currents.
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Output Driver Impedance
DDR3L 34 Ohm Driver
Using Table 36, the 34Ω driver’s current range has been calculated and summarized in
Table 37 (page 58) V DD = 1.35V, Table 38 for V DD = 1.45V, and Table 39 (page 59) for
VDD = 1.283V. The individual pull-up and pull-down resistors R ON34(PD) and RON34(PU)
are defined as follows:
• RON34(PD) = (VOUT)/|IOUT|; RON34(PU) is turned off
• RON34(PU) = (VDDQ - VOUT)/|IOUT|; RON34(PD) is turned off
Table 36: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations
RON
Min
Nom
Max
Unit
RZQ = 240Ω 
237.6
240
242.4
Ω
33.9
34.3
34.6
Ω
MR1[5,1]
RON
Resistor
VOUT
Min
Nom
Max
Unit
0, 1
Ω
RON34(PD)
0.2 × VDDQ
20.4
34.3
38.1
Ω
0.5 × VDDQ
30.5
34.3
38.1
Ω
0.8 × VDDQ
30.5
34.3
48.5
Ω
0.2 × VDDQ
30.5
34.3
48.5
Ω
0.5 × VDDQ
30.5
34.3
38.1
Ω
0.8 × VDDQ
20.4
34.3
38.1
Ω
RZQ/7 = (240Ω 
RON34(PU)
Table 37: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.35V
MR1[5,1]
RON
Resistor
VOUT
Max
Nom
Min
Unit
0, 1
Ω
RON34(PD)
IOL @ 0.2 × VDDQ
13.3
7.9
7.1
mA
IOL @ 0.5 × VDDQ
22.1
19.7
17.7
mA
IOL @ 0.8 × VDDQ
35.4
31.5
22.3
mA
IOH @ 0.2 × VDDQ
35.4
31.5
22.3
mA
IOH @ 0.5 × VDDQ
22.1
19.7
17.7
mA
IOH @ 0.8 × VDDQ
13.3
7.9
7.1
mA
Min
Unit
RON34(PU)
Table 38: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.45V
MR1[5,1]
RON
Resistor
VOUT
Max
0, 1
Ω
RON34(PD)
IOL @ 0.2 × VDDQ
14.2
8.5
7.6
mA
IOL @ 0.5 × VDDQ
23.7
21.1
19.0
mA
IOL @ 0.8 × VDDQ
38.0
33.8
23.9
mA
IOH @ 0.2 × VDDQ
38.0
33.8
23.9
mA
IOH @ 0.5 × VDDQ
23.7
21.1
19.0
mA
IOH @ 0.8 × VDDQ
14.2
8.5
7.6
mA
RON34(PU)
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Output Driver Impedance
Table 39: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.283
MR1[5,1]
RON
Resistor
VOUT
Max
Nom
Min
Unit
0, 1
Ω
RON34(PD)
IOL @ 0.2 × VDDQ
12.6
7.5
6.7
mA
IOL @ 0.5 × VDDQ
21.0
18.7
16.8
mA
IOL @ 0.8 × VDDQ
33.6
29.9
21.2
mA
RON34(PU)
IOH @ 0.2 × VDDQ
33.6
29.9
21.2
mA
IOH @ 0.5 × VDDQ
21.0
18.7
16.8
mA
IOH @ 0.8 × VDDQ
12.6
7.5
6.7
mA
DDR3L 34 Ohm Output Driver Sensitivity
If either the temperature or the voltage changes after ZQ calibration, then the tolerance
limits listed in Table 35 (page 57) can be expected to widen according to Table 40 and
Table 41.
Table 40: DDR3L 34 Ohm Output Driver Sensitivity Definition
Symbol
Min
Max
Unit
RON(PD) @ 0.2 × VDDQ
0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/7
RON(PD) @ 0.5 × VDDQ
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
RZQ/7
RON(PD) @ 0.8 × VDDQ
0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
1.4 + dRONdTH × |ΔT| + dRONdVH × |ΔV|
RZQ/7
RON(PU) @ 0.2 × VDDQ
0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.4 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/7
RON(PU) @ 0.5 × VDDQ
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
RZQ/7
RON(PU) @ 0.8 × VDDQ
0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
1.1 + dRONdTH × |ΔT| + dRONdVH × |ΔV|
RZQ/7
Note:
1. ΔT = T - T(@CALIBRATION)ΔV = VDDQ - VDDQ(@CALIBRATION); and VDD = VDDQ.
Table 41: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity
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Change
Min
Max
Unit
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.13
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.13
%/mV
dRONdTH
0
1.5
%/°C
dRONdVH
0
0.13
%/mV
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Output Driver Impedance
DDR3L Alternative 40 Ohm Driver
Table 42: DDR3L 40 Ohm Driver Impedance Characteristics
Gray-shaded cells are DDR3L unique values; All other values are the same for both DDR3L and DDR3
MR1
[5, 1]
RON
Resistor
VOUT
Min
Nom
Max
0, 0
Ω
RON,40PD
0.2 × VDDQ
0.6
1.0
1.15
RZQ/6
0.5 × VDDQ
0.9
1.0
1.15
RZQ/6
0.8 × VDDQ
0.9
1.0
1.45
RZQ/6
0.2 × VDDQ
0.9
1.0
1.45
RZQ/6
0.5 × VDDQ
0.9
1.0
1.15
RZQ/6
0.8 × VDDQ
0.6
1.0
1.15
RZQ/6
VIL(AC) to VIH(AC)
–10
N/A
10
%
RON,40PU
Pull-up/pull-down mismatch (MMPUPD)
Units
1. Tolerance limits assume RZQ of 240Ω ±1% and are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD; VSSQ = VSS).
Refer to DDR3L 40 Ohm Output Driver Sensitivity (page 60) if either the temperature
or the voltage changes after calibration.
2. Measurement definition for mismatch between pull-up and pull-down (MMPUPD). Measure both RON(PU) and RON(PD) at 0.5 × VDDQ:
RON(PU) - RON(PD)
MMPUPD =
× 100
RON,nom
Notes:
3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (TC).
A larger maximum limit will result in slightly lower minimum currents.
DDR3L 40 Ohm Output Driver Sensitivity
If either the temperature or the voltage changes after I/O calibration, then the tolerance
limits listed in Table 42 can be expected to widen according to Table 43 and Table 44
(page 61).
Table 43: DDR3L 40 Ohm Output Driver Sensitivity Definition
Symbol
Min
Max
Unit
RON(PD) @ 0.2 × VDDQ
0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/6
RON(PD) @ 0.5 × VDDQ
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
RZQ/6
RON(PD) @ 0.8 × VDDQ
0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
1.4 + dRONdTH × |ΔT| + dRONdVH × |ΔV|
RZQ/6
RON(PU) @ 0.2 × VDDQ
0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.4 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/6
RON(PU) @ 0.5 × VDDQ
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
RZQ/6
RON(PU) @ 0.8 × VDDQ
0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
1.1 + dRONdTH × |ΔT| + dRONdVH × |ΔV|
RZQ/6
Note:
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1. ΔT = T - T(@CALIBRATION)ΔV = VDDQ - VDDQ(@CALIBRATION); and VDD = VDDQ.
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Output Driver Impedance
Table 44: 40 Ohm Output Driver Voltage and Temperature Sensitivity
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Change
Min
Max
Unit
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.15
%/mV
dRONdTH
0
1.5
%/°C
dRONdVH
0
0.15
%/mV
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Output Characteristics and Operating Conditions
Output Characteristics and Operating Conditions
Table 45: DDR3L Single-Ended Output Driver Characteristics
All voltages are referenced to VSS
Parameter/Condition
Output leakage current: DQ are disabled;
0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH
Output slew rate: Single-ended; For rising and falling edges,
measure between VOL(AC) = VREF - 0.09 × VDDQ and VOH(AC) =
VREF + 0.09 × VDDQ
Symbol
Min
Max
Unit
Notes
IOZ
–5
5
μA
1
SRQse
1.75
6
V/ns
1, 2, 3, 4
Single-ended DC high-level output voltage
VOH(DC)
0.8 × VDDQ
V
1, 2, 5
Single-ended DC mid-point level output voltage
VOM(DC)
0.5 × VDDQ
V
1, 2, 5
Single-ended DC low-level output voltage
VOL(DC)
0.2 × VDDQ
V
1, 2, 5
Single-ended AC high-level output voltage
VOH(AC)
VTT + 0.1 × VDDQ
V
1, 2, 3, 6
Single-ended AC low-level output voltage
VOL(AC)
VTT - 0.1 × VDDQ
V
1, 2, 3, 6
%
1, 7
Delta RON between pull-up and pull-down for DQ/DQS
MMPUPD
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10
Output to VTT (VDDQ/2) via 25Ω resistor
Test load for AC timing and output slew rates
Notes:
–10
3
1. RZQ of 240Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD;
VSSQ = VSS).
2. VTT = VDDQ/2.
3. See (page 0 ) for the test load configuration.
4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from
HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are
either all static or all switching in the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
5. See Figure 24 (page 56) for IV curve linearity. Do not use AC test load.
6. See Table 47 (page 64) for output slew rate.
7. See Figure 24 (page 56) for additional information.
8. See Figure 25 (page 63) for an example of a single-ended output signal.
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Output Characteristics and Operating Conditions
Figure 25: DQ Output Signal
MAX output
VOH(AC)
VOL(AC)
MIN output
Table 46: DDR3L Differential Output Driver Characteristics
All voltages are referenced to VSS
Parameter/Condition
Output leakage current: DQ are disabled;
0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH
DDR3L Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = –0.18 × VDDQ
and VOH,diff(AC) = 0.18 × VDDQ
Symbol
Min
Max
Unit
Notes
IOZ
–5
5
μA
1
SRQdiff
3.5
12
V/ns
1
Differential high-level output voltage
VOH,diff(AC)
+0.2 × VDDQ
V
1, 4
Differential low-level output voltage
VOL,diff(AC)
–0.2 × VDDQ
V
1, 4
%
1, 5
Delta Ron between pull-up and pull-down for DQ/DQS
MMPUPD
Notes:
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–10
10
Output to VTT (VDDQ/2) via 25Ω resistor
Test load for AC timing and output slew rates
3
1. RZQ of 240Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD;
VSSQ = VSS).
2. VREF = VDDQ/2; slew rate @ 5 V/ns, interpolate for faster slew rate.
3. See Figure 26 (page 64) for the test load configuration.
4. See Table 48 (page 66) for the output slew rate.
5. See Table 35 (page 57) for additional information.
6. See on page for an example of a differential output signal.
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Output Characteristics and Operating Conditions
Reference Output Load
Figure 26 represents the effective reference load of 25Ω used in defining the relevant device AC timing parameters (except ODT reference timing) as well as the output slew rate
measurements. It is not intended to be a precise representation of a particular system
environment or a depiction of the actual load presented by a production tester. System
designers should use IBIS or other simulation tools to correlate the timing reference
load to a system environment.
Figure 26: Reference Output Load for AC Timing and Output Slew Rate
VDDQ/2
DUT
VREF
RTT = 25ȍ
DQ
DQS
DQS#
VTT = VDDQ/2
Timing reference point
ZQ
RZQ = 240ȍ
VSS
Slew Rate Definitions for Single-Ended Output Signals
The single-ended output driver is summarized in Table 45 (page 62). With the reference
load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-ended signals.
Table 47: Single-Ended Output Slew Rate Definition
Single-Ended Output Slew
Rates (Linear Signals)
Measured
Output
Edge
From
To
Calculation
DQ
Rising
VOL(AC)
VOH(AC)
VOH(AC) - VOL(AC)
ΔTRse
Falling
VOH(AC)
VOL(AC)
VOH(AC) - VOL(AC)
ΔTFse
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Output Characteristics and Operating Conditions
Figure 27: Nominal Slew Rate Definition for Single-Ended Output Signals
ΔTRse
VOH(AC)
VTT
VOL(AC)
ΔTFse
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4Gb: x4, x8, x16 DDR3L SDRAM
Output Characteristics and Operating Conditions
Slew Rate Definitions for Differential Output Signals
The differential output driver is summarized in Table 46 (page 63). With the reference
load for timing measurements, the output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for differential signals.
Table 48: Differential Output Slew Rate Definition
Differential Output Slew
Rates (Linear Signals)
Measured
Output
Edge
From
To
Calculation
DQS, DQS#
Rising
VOL,diff(AC)
VOH,diff(AC)
VOH,diff(AC) - VOL,diff(AC)
ΔTRdiff
Falling
VOH,diff(AC)
VOL,diff(AC)
VOH,diff(AC) - VOL,diff(AC)
ΔTFdiff
Figure 28: Nominal Differential Output Slew Rate Definition for DQS, DQS#
ΔTRdiff
VOH,diff(AC)
0
VOL,diff(AC)
ΔTFdiff
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4Gb: x4, x8, x16 DDR3L SDRAM
Speed Bin Tables
Speed Bin Tables
Table 49: DDR3L-1066 Speed Bins
DDR3L-1066 Speed Bin
-187E
-187
CL-tRCD-tRP
7-7-7
8-8-8
Parameter
Symbol
Min
Max
Min
Max
Unit
tAA
13.125
–
15
–
ns
tRCD
13.125
–
15
–
ns
PRECHARGE command period
tRP
13.125
–
15
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command
period
tRC
50.625
–
52.5
–
ns
tRAS
37.5
9 x tREFI
37.5
9 x tREFI
ns
1
3.0
3.3
3.0
3.3
ns
2
ns
3
Internal READ command to first data
ACTIVATE to internal READ or WRITE delay
time
ACTIVATE-to-PRECHARGE command period
CL = 5
CL = 6
CL = 7
CL = 8
CWL = 5
tCK
(AVG)
CWL = 6
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
2
CWL = 6
tCK
(AVG)
Reserved
Reserved
ns
3
CWL = 5
tCK
(AVG)
Reserved
Reserved
ns
3
CWL = 6
tCK
(AVG)
Reserved
ns
2, 3
CWL = 5
tCK
(AVG)
Reserved
ns
3
CWL = 6
tCK
(AVG)
ns
2
Reserved
2.5
<2.5
Reserved
1.875
Supported CWL settings
Notes:
3.3
1.875
Supported CL settings
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Notes
<2.5
Reserved
2.5
3.3
1.875
<2.5
5, 6, 7, 8
5, 6, 8
CK
5, 6
5, 6
CK
1. tREFI depends on TOPER.
2. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
3. Reserved settings are not allowed.
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4Gb: x4, x8, x16 DDR3L SDRAM
Speed Bin Tables
Table 50: DDR3L-1333 Speed Bins
DDR3L-1333 Speed Bin
-DJ1
-N/A2
CL-tRCD-tRP
9-9-9
10-10-10
Parameter
Symbol
Min
Max
Min
Max
Unit
tAA
13.5
20
15
20
ns
tRCD
13.5
–
15
–
ns
PRECHARGE command period
tRP
13.5
–
15
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command
period
tRC
49.5
–
51
–
ns
tRAS
36
9 x tREFI
36
9 x tREFI
ns
3
3.0
3.3
3.0
3.3
ns
4
ns
5
Internal READ command to first data
ACTIVATE to internal READ or WRITE delay
time
ACTIVATE-to-PRECHARGE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CWL = 5
tCK
(AVG)
CWL = 6, 7
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
4
CWL = 6
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 7
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 5
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 6
tCK
(AVG)
Reserved
ns
4, 5
CWL = 7
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 5
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 6
tCK
(AVG)
ns
4
CWL = 7
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 5, 6
tCK
(AVG)
Reserved
Reserved
ns
5
CWL = 7
tCK
(AVG)
Reserved
ns
4, 5
CWL = 5, 6
tCK
(AVG)
Reserved
ns
5
CWL = 7
tCK
(AVG)
ns
4
Reserved
2.5
<2.5
1.875
1.5
<2.5
<1.875
Reserved
1.5
Supported CWL settings
Notes:
3.3
1.875
Supported CL settings
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Notes
<1.875
Reserved
2.5
3.3
1.875
1.5
<2.5
<1.875
5, 6, 7, 8, 9, 10
5, 6, 8, 10
CK
5, 6, 7
5, 6, 7
CK
1.
2.
3.
4.
The -DJ speed grade is backward compatible with 1066, CL = 7.
The 1333 10-10-10 is not guaranteed).
tREFI depends on T
OPER.
The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
5. Reserved settings are not allowed.
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4Gb: x4, x8, x16 DDR3L SDRAM
Speed Bin Tables
Table 51: DDR3L-1600 Speed Bins
-GN1
DDR3L-1600 Speed Bin
CL-tRCD-tRP
11-11-11
Parameter
Symbol
Min
Max
Unit
tAA
13.75
20
ns
tRCD
13.75
–
ns
PRECHARGE command period
tRP
13.75
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
48.75
–
ns
tRAS
35
9 x tREFI
ns
2
3.0
3.3
ns
3
ns
4
Internal READ command to first data
ACTIVATE to internal READ or WRITE delay time
ACTIVATE-to-PRECHARGE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CWL = 5
tCK
(AVG)
CWL = 6, 7, 8
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
3
CWL = 6
tCK
(AVG)
Reserved
ns
4
CWL = 7, 8
tCK
(AVG)
Reserved
ns
4
CWL = 5
tCK
(AVG)
Reserved
ns
4
CWL = 6
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
Reserved
ns
4
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5
tCK
(AVG)
Reserved
ns
4
CWL = 6
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
Reserved
ns
4
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6
tCK
(AVG)
Reserved
ns
4
CWL = 7
tCK
(AVG)
ns
3
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6
tCK
(AVG)
Reserved
ns
4
CWL = 7
tCK
(AVG)
ns
3
CWL = 8
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6, 7
tCK
(AVG)
Reserved
ns
4
CWL = 8
tCK
(AVG)
ns
3
Supported CL settings
Supported CWL settings
Notes:
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Notes
Reserved
2.5
3.3
1.875
<2.5
1.875
1.5
1.5
<2.5
<1.875
<1.875
1.25
<1.5
5, 6, 7, 8, 9, 10, 11
CK
5, 6, 7, 8
CK
1. The -GN speed grade is backward compatible with 1333, CL = 9 and 1066, CL = 7.
2. tREFI depends on TOPER.
3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
4. Reserved settings are not allowed.
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4Gb: x4, x8, x16 DDR3L SDRAM
Speed Bin Tables
Table 52: DDR3L-1866 Speed Bins
-1071
DDR3L-1866 Speed Bin
CL-tRCD-tRP
13-13-13
Parameter
Symbol
Min
Max
tAA
13.91
20
tRCD
13.91
–
ns
PRECHARGE command period
tRP
13.91
–
ns
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC
47.91
–
ns
tRAS
34
9 x tREFI
ns
2
3.0
3.3
ns
3
ns
4
Internal READ command to first data
ACTIVATE to internal READ or WRITE delay time
ACTIVATE-to-PRECHARGE command period
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
CL = 12
CL = 13
CWL = 5
(AVG)
CWL = 6, 7, 8, 9
tCK
(AVG)
CWL = 5
tCK
(AVG)
ns
3
CWL = 6, 7, 8, 9
tCK
(AVG)
Reserved
ns
4
CWL = 5, 7, 8, 9
tCK
(AVG)
Reserved
ns
4
CWL = 6
tCK
(AVG)
ns
3
CWL = 5, 8, 9
tCK
(AVG)
ns
4
CWL = 6
tCK
(AVG)
ns
3
CWL = 7
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6, 8, 9
tCK
(AVG)
Reserved
ns
4
CWL = 7
tCK
(AVG)
ns
3
CWL = 5, 6, 9
tCK
(AVG)
ns
4
CWL = 7
tCK
(AVG)
ns
3
CWL = 8
tCK
(AVG)
ns
4
CWL = 5, 6, 7
tCK
(AVG)
ns
4
CWL = 8
tCK
(AVG)
ns
3
CWL = 9
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6, 7, 8
tCK
(AVG)
Reserved
ns
4
CWL = 9
tCK
(AVG)
Reserved
ns
4
CWL = 5, 6, 7, 8
tCK
(AVG)
Reserved
ns
4
CWL = 9
tCK
(AVG)
ns
3
Supported CWL settings
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Notes
tCK
Supported CL settings
Notes:
Unit
Reserved
2.5
3.3
1.875
<2.5
Reserved
1.875
1.5
<2.5
<1.875
Reserved
1.5
<1.875
Reserved
Reserved
1.25
<1.5
1.071
<1.25
5, 6, 7, 8, 9, 10, 11, 13
CK
5, 6, 7, 8, 9
CK
1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9
(-15E) and 1066, CL = 7 (-187E).
2. tREFI depends on TOPER.
3. The CL and CWL settings result in tCK requirements. When making a selection of tCK,
both CL and CWL requirement settings need to be fulfilled.
4. Reserved settings are not allowed.
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Electrical Characteristics and AC Operating Conditions
Electrical Characteristics and AC Operating Conditions
Table 53: Electrical Characteristics and AC Operating Conditions
Note 1 below applies to base timing specifications; For additional specifications, see the DDR3 Electrical Characteristics and
AC Operating Condition tables and notes
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max Units
tDS
90
–
40
–
N/A
–
N/A
–
N/A
–
ps
250
–
200
–
N/A
–
N/A
–
N/A
–
ps
140
–
90
–
45
–
25
–
N/A
–
ps
275
–
225
–
180
–
160
–
N/A
–
ps
160
–
110
–
75
–
55
–
N/A
–
ps
DQ Input Timing
Data setup
time to DQS,
DQS#
Data setup
time to DQS,
DQS#
Data hold
time from
DQS, DQS#
Data setup
time to DQS,
DQS#
Data hold
time from
DQS, DQS#
Base
(specification)
(AC160)
VREF @ 1 V/ns
Base
(specification)
tDS
(AC135)
VREF @ 1 V/ns
Base
(specification)
tDH
(DC90)
VREF @ 1 V/ns
Base
(specification)
tDS
–
200
–
165
–
145
–
N/A
–
ps
–
N/A
–
N/A
–
N/A
–
70
–
ps
N/A
–
N/A
–
N/A
–
N/A
–
135
–
ps
N/A
–
N/A
–
N/A
–
N/A
–
75
–
ps
N/A
–
N/A
–
N/A
–
N/A
–
110
–
ps
215
–
140
–
80
–
60
–
N/A
–
ps
375
–
300
–
240
–
220
–
N/A
–
ps
365
–
290
–
205
–
185
–
65
–
ps
500
–
425
–
340
–
320
–
200
–
ps
N/A
–
N/A
–
N/A
–
N/A
–
150
–
ps
N/A
–
N/A
–
N/A
–
N/A
–
275
–
ps
285
–
210
–
150
–
130
–
110
–
ps
375
–
300
–
240
–
220
–
200
–
ps
(AC130)
VREF @ 2 V/ns
Base
(specification)
250
N/A
tDH
(DC90)
VREF @ 2 V/ns
Command and Address Timing
CTRL, CMD,
ADDR setup
to CK, CK#
CTRL, CMD,
ADDR setup
to CK, CK#
CTRL, CMD,
ADDR setup
to CK, CK#
Base
(specification)
tIS
(AC160)
VREF @ 1 V/ns
Base
(specification)
tIS
(AC135)
VREF @ 1 V/ns
Base
(specification)
tIS
(AC125)
VREF @ 1 V/ns
Base
CTRL, CMD,
(specification)
ADDR hold
from CK, CK# V
REF @ 1 V/ns
Notes:
tIH
(DC90)
1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and
VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/
command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min
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Electrical Characteristics and AC Operating Conditions
with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min
with tDS(AC160) of 90ps or VIH(AC135),min with tDS(AC135) of 140ps.
2. When DQ single-ended slew rate is 1V/ns, the DQS differential slew rate is 2V/ns; when
DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns.
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73
–194
–209
–222
–232
–241
–249
–257
–263
–269
tERR4per
tERR5per
tERR6per
tERR7per
tERR8per
tERR9per
tERR10per
tERR11per
tERR12per
tERRnper
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
n = 13, 14 . . . 49, 50
cycles
DQ Input Timing
–147
–175
tERR3per
Cumulative error across 2 cycles
180
DLL locking
tERR2per
200
tJITcc
tJITcc,lck
0.43
0.43
DLL locked
(ABS)
tCL
Clock absolute low pulse width
Cycle-to-cycle jitter
(ABS)
tCH
Clock absolute high pulse width
–90
(ABS)
tCK
DLL locking
Clock absolute period
tJITper,lck
0.47
–100
(AVG)
Low pulse width average
0.47
tJITper
tCL
8
8
Min
100
0.53
0.53
3900
7800
Max
8
8
Min
3900
7800
Max
DDR3L-1333
80
90
0.53
0.53
–70
–80
0.47
0.47
70
80
0.53
0.53
160
180
242
237
231
224
217
209
200
188
175
157
132
–
–
–215
–210
–205
–200
–193
–186
–177
–168
–155
–140
–118
0.43
0.43
140
160
215
210
205
200
193
186
177
168
155
140
118
–
–
–188
–184
–180
–175
–169
–163
–155
–147
–136
–122
–103
0.43
0.43
–60
–70
0.47
0.47
8
8
Min
120
140
188
184
180
175
169
163
155
147
136
122
103
–
–
60
70
0.53
0.53
3900
7800
Max
DDR3L-1600
MIN = (1 + 0.68ln[n]) × tJITper MIN
tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX
–242
–237
–231
–224
–217
–209
–200
–188
–175
–157
–132
0.43
0.43
MIN = tCK (AVG) MIN + tJITper MIN;
MAX = tCK (AVG) MAX + tJITper MAX
–80
–90
0.47
0.47
tERRnper
269
263
257
249
241
232
222
209
194
175
147
–
–
90
8
8
Min
DDR3L-1066
See Speed Bin Tables for tCK range allowed
3900
7800
Max
DDR3L-800
DLL locked
(AVG)
tCH
High pulse width average
Clock period jitter
(AVG)
(DLL_DIS)
tCK
tCK
TC = >85°C to 95°C
TC ≤ 85°C
Symbol
Clock period average: DLL enable mode
Clock period average:
DLL disable mode
Clock Timing
Parameter
Notes 1–8 apply to the entire table
Table 54: Electrical Characteristics and AC Operating Conditions
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
(AVG)
tCK
(AVG)
tCK
ps
ps
ps
CK
CK
ns
ns
ns
Unit
17
17
17
17
17
17
17
17
17
17
17
17
16
16
15
14
13
13
12
12
10, 11
42
9, 42
Notes
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
Base (specification)
74
0.45
0.45
0.2
0.2
0.9
0.3
tDQSH
tDSS
tDSH
tWPRE
tWPST
DQS, DQS# differential input high pulse
width
DQS, DQS# falling setup to CK, CK# rising
DQS, DQS# falling hold from CK, CK# rising
DQS, DQS# differential WRITE preamble
DQS, DQS# differential WRITE postamble
1
tDQSCK
(DLL_DIS)
tQSH
DQS, DQS# rising to/from rising CK, CK#
when DLL is disabled
DQS, DQS# differential output high time
0.38
–400
tDQSCK
DQS, DQS# rising to/from rising CK, CK#
DQ Strobe Output Timing
–0.25
tDQSL
–
tHZDQ
DQS, DQS# differential input low pulse width
–800
tLZDQ
tDQSS
0.38
–
600
250
150
–
–
275
125
tQH
tDQSQ
tDIPW
(DC100)
tDH
(AC135)
tDS
(AC150)
tDS
250
75
tDS
(AC175)
Min
Symbol
–
10
400
–
–
–
–
0.55
0.55
0.25
400
400
–
200
–
–
–
–
–
–
–
–
–
Max
DDR3L-800
DQS, DQS# rising to CK, CK# rising
DQ Strobe Input Timing
DQ High-Z time from CK, CK#
DQ Low-Z time from CK, CK#
DQ output hold time from DQS, DQS#
DQS, DQS# to DQ skew, per access
DQ Output Timing
Minimum data pulse width
Data hold time from
DQS, DQS#
Data setup time to
DQS, DQS#
Data setup time to
DQS, DQS#
Data setup time to
DQS, DQS#
Parameter
Notes 1–8 apply to the entire table
0.38
1
–300
0.3
0.9
0.2
0.2
0.45
0.45
–0.25
–
–600
0.38
–
490
200
100
–
–
250
75
200
25
Min
–
10
300
–
–
–
–
0.55
0.55
0.25
300
300
–
150
–
–
–
–
–
–
–
–
–
Max
DDR3L-1066
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)
0.40
1
–255
0.3
0.9
0.2
0.2
0.45
0.45
–0.25
–
–500
0.38
–
400
165
65
–
–
180
30
–
–
Min
–
10
255
–
–
–
–
0.55
0.55
0.25
250
250
–
125
–
–
–
–
–
–
–
–
–
Max
DDR3L-1333
0.40
1
–225
0.3
0.9
0.18
0.18
0.45
0.45
–0.27
–
–450
0.38
–
360
145
45
–
–
160
10
–
–
Min
–
10
225
–
–
–
–
0.55
0.55
0.27
225
225
–
100
–
–
–
–
–
–
–
–
–
Max
DDR3L-1600
CK
ns
ps
CK
CK
CK
CK
CK
CK
CK
ps
ps
(AVG)
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Unit
Notes
21
26
23
25
25
25
22, 23
22, 23
21
41
19, 20
18, 19
19, 20
18, 19
19, 20
18, 19,
44
19, 20
18, 19,
44
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Min
0.38
–800
tQSL
tLZDQS
DQS, DQS# Low-Z time (RL - 1)
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DQS, DQS# High-Z time (RL + BL/2)
0.3
tRPRE
tRPST
DQS, DQS# differential READ preamble
DQS, DQS# differential READ postamble
VREF @ 1 V/ns
Base (specification)
75
–
–
–
–
–
620
240
140
340
190
240
–
–
–
–
–
–
–
–
Note 27
Note 24
250
250
Four ACTIVATE
windows
MIN = greater of 4CK or 7.5ns; MAX = N/A
tRTP
READ-to-PRECHARGE time
–
–
MIN = greater of 4CK or 7.5ns; MAX = N/A
45
30
tWTR
–
–
Delay from start of internal WRITE
transaction to internal READ command
50
37.5
MIN = 15ns; MAX = N/A
–
–
tWR
50
40
Write recovery time
x16 (2KB page size)
x4/x8 (1KB page
size)
tFAW
ACTIVATE-to-ACTIVATE x4/x8 (1KB page
size)
minimum command
period
x16 (2KB page size)
40
30
–
–
MIN = greater of 4CK or 7.5ns
MIN = greater of MIN = greater of MIN = greater of MIN = greater of
4CK or 10ns
4CK or 7.5ns
4CK or 6ns
4CK or 6ns
tRRD
MIN = greater of 4CK or 10ns
See Speed Bin Tables for tRC
tRC
ACTIVATE-to-ACTIVATE command period
–
–
–
–
–
–
–
–
Note 27
Note 24
225
225
–
Max
See Speed Bin Tables for
560
220
120
320
170
220
45
512
0.3
0.9
–
–450
0.40
Min
See Speed Bin Tables for tRAS
tRP
See Speed Bin Tables for tRCD
780
300
200
425
275
–
65
512
0.3
0.9
–
–500
–
Max
tRAS
–
–
–
–
–
300
–
–
Note 27
Note 24
300
300
0.40
Min
DDR3L-1600
ACTIVATE-to-PRECHARGE command period
900
375
275
500
350
–
125
512
0.3
0.9
–
–600
–
Max
DDR3L-1333
PRECHARGE command period
tRCD
tIPW
(DC100)
tIH
(AC150)
tIS
–
–
Note 27
Note 24
400
400
0.38
Min
DDR3L-1066
tRP
ACTIVATE to internal READ or WRITE delay
Minimum CTRL, CMD, ADDR pulse width
CTRL, CMD, ADDR hold Base (specification)
from CK,CK#
VREF @ 1 V/ns
CTRL, CMD, ADDR
setup to CK,CK#
VREF @ 1 V/ns
375
200
CTRL, CMD, ADDR
setup to CK,CK#
(AC175)
tIS
Base (specification)
512
tDLLK
DLL locking time
Command and Address Timing
–
0.9
tHZDQS
–
Max
DDR3L-800
Symbol
DQS, DQS# differential output low time
Parameter
Notes 1–8 apply to the entire table
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)
CK
CK
ns
ns
ns
CK
CK
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
CK
CK
CK
ps
ps
CK
Unit
31, 32
31, 34
31, 32,
33,34
31
31
31
31
31, 43
31, 32
31
31
41
20, 30
29, 30
20, 30
29, 30,
44
20, 30
29, 30,
44
28
23, 27
23, 24
22, 23
22, 23
21
Notes
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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512
256
64
tZQinit
tZQoper
tZQCS
Normal operation
76
64
256
512
TC > 85°C
TC ≤ 85°C
TC > 85°C
TC ≤ 85°C
Exit self refresh to commands not requiring a
locked DLL
Self Refresh Timing
Maximum average
periodic refresh
Maximum refresh
period
REFRESH-to-ACTIVATE or REFRESH
command period
– 2Gb
– 4Gb
– 8Gb
tRFC
tRFC
tXS
tREFI
–
– 1Gb
tRFC
MIN = greater of 5CK or tRFC + 10ns; MAX = N/A
3.9 (32ms/8192)
7.8 (64ms/8192)
32 (2X)
64 (1X)
MIN = 350; MAX = 70,200
MIN = 260; MAX = 70,200
MIN = 160; MAX = 70,200
MIN = 110; MAX = 70,200
RESET# LOW to I/O and RTT High-Z
tRFC
MIN = N/A; MAX = 20
tIOZ
Refresh Timing
MIN = 0; MAX = 200
tRPS
RESET# LOW to power supplies stable
MIN = N/A; MAX = 200
–
–
–
tVDDPR
64
256
512
Begin power supply ramp to power supplies
stable
–
–
–
MIN = greater of 5CK or tRFC + 10ns; MAX = N/A
64
256
512
tXPR
–
–
–
Exit reset from CKE HIGH to a valid command
Initialization and Reset Timing
ZQCS command: Short calibration time
ZQCL command: Long
calibration time
POWER-UP and RESET operation
MIN = 1CK; MAX = N/A
tMPRR
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit
Calibration Timing
MIN = 4CK; MAX = N/A
MIN = greater of 12CK or 15ns; MAX = N/A
tMOD
MODE REGISTER SET command update delay
Min
tMRD
Max
MODE REGISTER SET command cycle time
Min
MIN = WR + tRP/tCK (AVG); MAX = N/A
Max
tDAL
Min
–
–
–
Max
DDR3L-1600
Auto precharge write recovery + precharge
time
Max
DDR3L-1333
MIN = 4CK; MAX = N/A
Min
DDR3L-1066
tCCD
Symbol
DDR3L-800
CAS#-to-CAS# command delay
Parameter
Notes 1–8 apply to the entire table
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)
CK
μs
μs
ms
ms
ns
ns
ns
ns
ns
ms
ms
CK
CK
CK
CK
CK
CK
CK
CK
CK
Unit
36
36
36
36
35
Notes
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
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77
MIN = 1
tMOD
MIN = RL + 4 + 1
MIN = WL + 4 + tWR/tCK (AVG)
MIN = WL + 2 + tWR/tCK (AVG)
tREFPDEN
tMRSPDEN
tRDPDEN
tWRPDEN
tWRPDEN
REFRESH command to power-down entry
MRS command to power-down entry
READ/READ with auto precharge command
to power-down entry
BL8 (OTF, MRS)
BC4OTF
BC4MRS
WRITE command to
power-down entry
(MIN)
MIN = 1
PRECHARGE/PRECHARGE ALL command to
power-down entry
MIN =
MIN = 1
tPRPDEN
+ tXPDLL
tACTPDEN
tANPD
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Greater of tANPD or tRFC - REFRESH command to CKE LOW time
(MIN); MAX = 9 ×
Greater of 3CK
or 5ns
CK
MIN =
tCKE
tREFI
Greater of 3CK
or 5.625ns
MIN = 1; MAX = N/A
Greater of 3CK
or 5.625ns
CK
CK
CK
CK
Unit
WL - 1CK
Greater of 3CK
or 7.5ns
ACTIVATE command to power-down entry
Power-Down Entry Minimum Timing
PDX
PDE
Power-down entry period: ODT either
synchronous or asynchronous
Power-down exit period: ODT either
synchronous or asynchronous
tANPD
tPD
tCPDED
(MIN)
Begin power-down period prior to CKE
registered HIGH
Power-down entry to power-down exit timing
Command pass disable delay
CKE MIN pulse width
tCKE
MIN = greater of 5CK or 10ns; MAX = N/A
tCKSRX
Valid clocks before self refresh exit,
power-down exit, or reset exit
Power-Down Timing
MIN = greater of 5CK or 10ns; MAX = N/A
Max
DDR3L-1600
Min
tCKSRE
Max
Valid clocks after self refresh entry or powerdown entry
Min
MIN = tCKE (MIN) + CK; MAX = N/A
Max
tCKESR
Min
Minimum CKE low pulse width for self refresh entry to self refresh exit timing
Max
MIN = tDLLK (MIN); MAX = N/A
Min
tXSDLL
DDR3L-1333
Symbol
DDR3L-1066
Exit self refresh to commands requiring a
locked DLL
DDR3L-800
Parameter
Notes 1–8 apply to the entire table
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)
37
28
Notes
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
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© 2013 Micron Technology, Inc. All rights reserved.
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78
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
DQS, DQS# delay
First DQS, DQS# rising edge
Write Leveling Timing
RTT dynamic change skew
ODTLcwn8
RTT(WR)-to-RTT,nom change skew - BL8
40
25
325
tWLMRD
tWLDQSEN
tWLS
tADC
ODTLcnw
ODTLcwn4
RTT,nom-to-RTT(WR) change skew
RTT(WR)-to-RTT,nom change skew - BC4
0.3
–
–
–
0.7
245
25
40
0.3
ODTH4
ODT HIGH time without WRITE command or
with WRITE command and BC4
Dynamic ODT Timing
ODTH8
ODT HIGH time with WRITE command and
BL8
–
–
–
0.7
195
25
40
0.3
6CK + ODTLoff
4CK + ODTLoff
WL - 2CK
MIN = 4; MAX = N/A
MIN = 6; MAX = N/A
MIN = 2; MAX = 8.5
0.3
tAOFPD
0.7
–250
Asynchronous RTT turn-off delay
(power-down with DLL off)
0.3
300
CWL + AL - 2CK
MIN = 2; MAX = 8.5
0.7
–300
Asynchronous RTT turn-on delay
(power-down with DLL off)
0.3
tAOF
RTT turn-off from ODTL off reference
400
CWL + AL - 2CK
tAONPD
–400
tAON
ODTLoff
RTT synchronous turn-off delay
Max
Min
Max
–
–
–
0.7
0.7
250
165
25
40
0.3
0.3
–225
–
–
–
0.7
0.7
225
MIN = greater of 3CK or 6ns;
MAX = N/A
Min
DDR3L-1600
MIN = greater of 10CK or 24ns; MAX = N/A
MIN = greater of 3CK or 7.5ns;
MAX = N/A
RTT turn-on from ODTL on reference
ODTLon
tXPDLL
tXP
RTT synchronous turn-on delay
ODT Timing
Precharge power-down with DLL off to
commands requiring a locked DLL
DLL on, any valid command, or DLL off to
commands not requiring locked DLL
Power-Down Exit Timing
Max
MIN = WL + 2 + WR + 1
DEN
DEN
Min
tWRAP-
Max
MIN = WL + 4 + WR + 1
Min
tWRAP-
DDR3L-1333
Symbol
DDR3L-1066
BL8 (OTF, MRS)
WRITE with auto
precharge command to BC4OTF
power-down entry
BC4MRS
DDR3L-800
Parameter
Notes 1–8 apply to the entire table
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)
ps
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
CK
ps
CK
CK
CK
CK
CK
CK
Unit
39
40
38
39, 40
23, 38
40
38
28
Notes
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Min
325
0
0
Symbol
tWLH
tWLO
tWLOE
Write leveling output delay
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4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
Write leveling output error
2
9
–
Max
DDR3L-800
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
Parameter
Notes 1–8 apply to the entire table
0
0
245
Min
2
9
–
Max
DDR3L-1066
Table 54: Electrical Characteristics and AC Operating Conditions (Continued)
0
0
195
Min
2
9
–
Max
DDR3L-1333
0
0
165
Min
2
7.5
–
Max
DDR3L-1600
ns
ns
ps
Unit
Notes
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
79
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
AC timing parameters are valid from specified TC MIN to TC MAX values.
All voltages are referenced to VSS.
Output timings are only valid for RON34 output buffer selection.
The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC).
All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the
correct number of clocks (Table 54 (page 73) uses CK or tCK [AVG] interchangeably). In
the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.
Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ/2 for single-ended signals and the crossing point for differential signals (see
(page 0 )).
When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
The period jitter (tJITper) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge.
The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs and 2 V/ns
slew rate differential DQS, DQS#.
These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing.
80
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© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK
(MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are required to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS
(MAX), tLZDQ MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN).
24. The maximum preamble is bound by tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met.
29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM
[ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will
support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR.
34. The start of the write recovery time is defined as follows:
• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity.
36. The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an average refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at
least once every 70.3μs. When TC is greater than 85°C, the refresh period is 32ms.
37. Although CKE is allowed to be registered LOW after a REFRESH command when
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
tREFPDEN
38.
39.
40.
41.
42.
43.
44.
(MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)
is required.
ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 20 (page 53). Designs that were created prior to JEDEC
tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.
Half-clock output parameters must be derated by the actual tERR10per and tJITdty when
input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are
required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX).
ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 20 (page 53). This output load is used for ODT timings (see (page 0 )).
Pulse width of a input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.
DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.
When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
Min
Max
Unit
Notes
8
7800
ns
9, 42
8
3900
ns
42
ns
10, 11
Clock Timing
Clock period average: DLL
disable mode
TC = 0°C to 85°C
tCK
(DLL_DIS)
TC = >85°C to 95°C
Clock period average: DLL enable mode
tCK
(AVG)
High pulse width average
tCH
(AVG)
0.47
0.53
CK
12
Low pulse width average
tCL
(AVG)
0.47
0.53
CK
12
–60
60
ps
13
–50
50
ps
13
Clock period jitter
DLL locked
tJITper
DLL locking
tJITper,lck
Clock absolute period
tCK
(ABS)
Clock absolute high pulse width
tCH
(ABS)
Clock absolute low pulse width
tCL
Cycle-to-cycle jitter
Cumulative error across
(ABS)
See Speed Bin Tables for
range allowed
tCK
MIN = tCK (AVG) MIN +tJITper MIN;
MAX = tCK (AVG) MAX +
tJITper MAX
0.43
0.43
ps
–
tCK
(AVG)
14
–
tCK
(AVG)
15
DLL locked
tJITcc
120
ps
16
DLL locking
tJITcc,lck
100
ps
16
2 cycles
tERR2per
–88
88
ps
17
3 cycles
tERR3per
–105
105
ps
17
4 cycles
tERR4per
–117
117
ps
17
5 cycles
tERR5per
–126
126
ps
17
6 cycles
tERR6per
–133
133
ps
17
7 cycles
tERR7per
–139
139
ps
17
8 cycles
tERR8per
–145
145
ps
17
9 cycles
tERR9per
–150
150
ps
17
10 cycles
tERR10per
–154
154
ps
17
11 cycles
tERR11per
–158
158
ps
17
12 cycles
tERR12per
–161
161
n = 13, 14 . . . 49, 50
cycles
tERRnper
tERRnper
MIN = (1 +
0.68ln[n]) × tJITper MIN
tERRnper MAX = (1 +
0.68ln[n]) × tJITper MAX
ps
17
ps
17
DQ Input Timing
Data setup time to DQS,
DQS#
Base (specification) @
2 V/ns
tDS
VREF @ 2 V/ns
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–
ps
18, 19
135
–
ps
19, 20
(AC135)
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Data hold time from DQS,
DQS#
Base (specification) @
2 V/ns
Symbol
Min
Max
Unit
Notes
tDH
70
–
ps
18, 19
(DC100)
VREF @ 2 V/ns
Minimum data pulse width
120
–
ps
19, 20
tDIPW
320
–
ps
41
tDQSQ
–
85
DQ Output Timing
DQS, DQS# to DQ skew, per access
ps
tQH
0.38
–
DQ Low-Z time from CK, CK#
tLZDQ
–390
195
ps
22, 23
DQ High-Z time from CK, CK#
tHZDQ
–
195
ps
22, 23
DQS, DQS# rising to CK, CK# rising
tDQSS
–0.27
0.27
CK
25
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
CK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
CK
DQS, DQS# falling setup to CK, CK# rising
tDSS
0.18
–
CK
25
DQS, DQS# falling hold from CK, CK# rising
tDSH
0.18
–
CK
25
DQS, DQS# differential WRITE preamble
tWPRE
0.9
–
CK
DQS, DQS# differential WRITE postamble
tWPST
0.3
–
CK
DQS, DQS# rising to/from rising CK, CK#
tDQSCK
–195
195
ps
23
DQS, DQS# rising to/from rising CK, CK# when DLL is
disabled
tDQSCK
1
10
ns
26
DQ output hold time from DQS, DQS#
tCK
(AVG)
21
DQ Strobe Input Timing
DQ Strobe Output Timing
(DLL_DIS)
DQS, DQS# differential output high time
tQSH
0.40
–
CK
21
DQS, DQS# differential output low time
tQSL
0.40
–
CK
21
DQS, DQS# Low-Z time (RL - 1)
tLZDQS
–390
195
ps
22, 23
DQS, DQS# High-Z time (RL + BL/2)
tHZDQS
–
195
ps
22, 23
DQS, DQS# differential READ preamble
tRPRE
0.9
Note 24
CK
23, 24
DQS, DQS# differential READ postamble
tRPST
0.3
Note 27
CK
23, 27
tDLLK
512
–
CK
28
tIS
65
–
ps
29, 30, 44
(AC135)
200
–
ps
20, 30
tIS
150
–
ps
29, 30, 44
(AC125)
275
–
ps
20, 30
tIH
100
–
ps
29, 30
(DC100)
200
–
ps
20, 30
tIPW
535
–
ps
41
Command and Address Timing
DLL locking time
CTRL, CMD, ADDR
setup to CK,CK#
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
VREF @ 1 V/ns
Base (specification)
VREF @ 1 V/ns
CTRL, CMD, ADDR hold from Base (specification)
CK,CK#
VREF @ 1 V/ns
Minimum CTRL, CMD, ADDR pulse width
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
ACTIVATE to internal READ or WRITE delay
PRECHARGE command period
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
ACTIVATE-to-ACTIVATE
minimum command period
Four ACTIVATE
windows
1KB page size
Unit
Notes
See Speed Bin Tables for
tRCD
ns
31
tRP
See Speed Bin Tables for tRP
ns
31
tRAS
See Speed Bin Tables for
tRAS
ns
31, 32
tRC
See Speed Bin Tables for tRC
ns
31, 43
tRRD
MIN = greater of 4CK or 5ns
CK
31
MIN = greater of 4CK or 6ns
tRCD
2KB page size
1KB page size
tFAW
2KB page size
Min
Max
CK
31
27
–
ns
31
35
–
ns
31
tWR
MIN = 15ns; MAX = N/A
ns
31, 32, 33
tWTR
MIN = greater of 4CK or
7.5ns; MAX = N/A
CK
31, 34
READ-to-PRECHARGE time
tRTP
MIN = greater of 4CK or
7.5ns; MAX = N/A
CK
31, 32
CAS#-to-CAS# command delay
tCCD
MIN = 4CK; MAX = N/A
CK
Auto precharge write recovery + precharge time
tDAL
MODE REGISTER SET command cycle time
tMRD
MIN = 4CK; MAX = N/A
CK
MODE REGISTER SET command update delay
tMOD
MIN = greater of 12CK or
15ns; MAX = N/A
CK
MULTIPURPOSE REGISTER READ burst end to mode
register set for multipurpose register exit
tMPRR
MIN = 1CK; MAX = N/A
CK
tZQinit
MIN = N/A
MAX = MAX(512nCK, 640ns)
CK
tZQoper
MIN = N/A
MAX = MAX(256nCK, 320ns)
CK
Write recovery time
Delay from start of internal WRITE transaction to internal READ command
tRP/tCK
MIN = WR +
(AVG);
MAX = N/A
CK
Calibration Timing
ZQCL command: Long calibration time
POWER-UP and RESET
operation
Normal operation
ZQCS command: Short calibration time
MIN = N/A
MAX = MAX(64nCK, 80ns) tZQCS
CK
Initialization and Reset Timing
tXPR
MIN = greater of 5CK or
tRFC + 10ns; MAX = N/A
CK
tVDDPR
MIN = N/A; MAX = 200
ms
RESET# LOW to power supplies stable
tRPS
MIN = 0; MAX = 200
ms
RESET# LOW to I/O and RTT High-Z
tIOZ
MIN = N/A; MAX = 20
ns
Exit reset from CKE HIGH to a valid command
Begin power supply ramp to power supplies stable
35
Refresh Timing
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
tRFC
– 1Gb
tRFC
tRFC
tRFC
Min
Max
Unit
Notes
MIN = 110; MAX = 70,200
ns
– 2Gb
MIN = 160; MAX = 70,200
ns
– 4Gb
MIN = 260; MAX = 70,200
ns
– 8Gb
MIN = 350; MAX = 70,200
ns
–
64 (1X)
ms
36
32 (2X)
ms
36
tREFI
7.8 (64ms/8192)
μs
36
3.9 (32ms/8192)
μs
36
tXS
MIN = greater of 5CK or
tRFC + 10ns; MAX = N/A
CK
Exit self refresh to commands requiring a
locked DLL
tXSDLL
MIN = tDLLK (MIN);
MAX = N/A
CK
Minimum CKE low pulse width for self refresh entry
to self refresh exit timing
tCKESR
MIN = tCKE (MIN) + CK; MAX
= N/A
CK
Valid clocks after self refresh entry or power-down
entry
tCKSRE
MIN = greater of 5CK or
10ns; MAX = N/A
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
tCKSRX
MIN = greater of 5CK or
10ns; MAX = N/A
CK
REFRESH-to-ACTIVATE or REFRESH
command period
Maximum refresh
period
TC ≤ 85°C
Maximum average
periodic refresh
TC ≤ 85°C
TC > 85°C
TC > 85°C
Self Refresh Timing
Exit self refresh to commands not requiring a locked
DLL
28
Power-Down Timing
tCKE
Greater of 3CK or 5ns
CK
tCPDED
MIN = 2;
MAX = N/A
CK
tPD
MIN = tCKE (MIN);
MAX = 9 × tREFI
CK
tANPD
WL - 1CK
CK
Power-down entry period: ODT either
synchronous or asynchronous
PDE
Greater of tANPD or tRFC REFRESH command to CKE
LOW time
CK
Power-down exit period: ODT either
synchronous or asynchronous
PDX
CKE MIN pulse width
Command pass disable delay
Power-down entry to power-down exit timing
Begin power-down period prior to CKE
registered HIGH
(MIN)
tANPD
+ tXPDLL
CK
Power-Down Entry Minimum Timing
ACTIVATE command to power-down entry
tACTPDEN
MIN = 2
CK
PRECHARGE/PRECHARGE ALL command to
power-down entry
tPRPDEN
MIN = 2
CK
REFRESH command to power-down entry
tREFPDEN
MIN = 2
CK
MRS command to power-down entry
tMRSPDEN
tMOD
CK
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86
MIN =
(MIN)
37
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Symbol
READ/READ with auto precharge command to power-down entry
tRDPDEN
MIN = RL + 4 + 1
CK
WRITE command to powerdown entry
BL8 (OTF, MRS)
BC4OTF
tWRPDEN
MIN = WL + 4 +
tWR/tCK (AVG)
CK
BC4MRS
tWRPDEN
MIN = WL + 2 +
tWR/tCK (AVG)
CK
BL8 (OTF, MRS)
BC4OTF
tWRAPDEN
MIN = WL + 4 + WR + 1
CK
BC4MRS
tWRAPDEN
MIN = WL + 2 + WR + 1
CK
tXP
MIN = greater of 3CK or 6ns;
MAX = N/A
CK
tXPDLL
MIN = greater of 10CK or
24ns; MAX = N/A
CK
28
WRITE with auto precharge
command to power-down
entry
Min
Max
Unit
Notes
Power-Down Exit Timing
DLL on, any valid command, or DLL off to
commands not requiring locked DLL
Precharge power-down with DLL off to
commands requiring a locked DLL
ODT Timing
RTT synchronous turn-on delay
ODTL on
CWL + AL - 2CK
CK
38
RTT synchronous turn-off delay
ODTL off
CWL + AL - 2CK
CK
40
RTT turn-on from ODTL on reference
tAON
–195
195
ps
23, 38
RTT turn-off from ODTL off reference
tAOF
0.3
0.7
CK
39, 40
Asynchronous RTT turn-on delay
(power-down with DLL off)
tAONPD
MIN = 2; MAX = 8.5
ns
38
Asynchronous RTT turn-off delay
(power-down with DLL off)
tAOFPD
MIN = 2; MAX = 8.5
ns
40
ODT HIGH time with WRITE command and BL8
ODTH8
MIN = 6; MAX = N/A
CK
ODT HIGH time without WRITE command or with
WRITE command and BC4
ODTH4
MIN = 4; MAX = N/A
CK
RTT,nom-to-RTT(WR) change skew
ODTLcnw
WL - 2CK
CK
RTT(WR)-to-RTT,nom change skew - BC4
ODTLcwn4
4CK + ODTLoff
CK
RTT(WR)-to-RTT,nom change skew - BL8
ODTLcwn8
6CK + ODTLoff
CK
Dynamic ODT Timing
tADC
0.3
0.7
CK
tWLMRD
40
–
CK
tWLDQSEN
25
–
CK
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
tWLS
140
–
ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
tWLH
140
–
ps
Write leveling output delay
tWLO
0
7.5
ns
RTT dynamic change skew
39
Write Leveling Timing
First DQS, DQS# rising edge
DQS, DQS# delay
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 55: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
DDR3L-1866
Parameter
Write leveling output error
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
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Symbol
Min
Max
Unit
tWLOE
0
2
ns
Notes
AC timing parameters are valid from specified TC MIN to TC MAX values.
All voltages are referenced to VSS.
Output timings are only valid for RON34 output buffer selection.
The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the
AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
(DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in
the range between VIL(AC) and VIH(AC).
All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the
correct number of clocks (Table 55 (page 83) uses CK or tCK [AVG] interchangeably). In
the case of noninteger results, all minimum limits are to be rounded up to the nearest
whole integer, and all maximum limits are to be rounded down to the nearest whole
integer.
Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is
VDDQ/2 for single-ended signals and the crossing point for differential signals (see
(page 0 )).
When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below tCK (AVG) MIN.
The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
The period jitter (tJITper) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge.
88
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Electrical Characteristics and AC Operating Conditions
16. The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at
2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to VREF when the slew rate is 1 V/ns (DQs are at 2V/ns for
DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns
for DDR3-1866 and DDR3-2133), are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK
(MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are required to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS
(MAX), tLZDQ (MAX), and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN).
24. The maximum preamble is bound by tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by tHZDQS (MAX).
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met.
29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM
[ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will
support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR.
34. The start of the write recovery time is defined as follows:
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity.
The refresh period is 64ms when TC is less than or equal to 85°C. This equates to an average refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at
least once every 70.3μs. When TC is greater than 85°C, the refresh period is 32ms.
Although CKE is allowed to be registered LOW after a REFRESH command when
tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN)
is required.
ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT
reference load is shown in Figure 20 (page 53). Designs that were created prior to JEDEC
tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maximum.
Half-clock output parameters must be derated by the actual tERR10per and tJITdty when
input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both
tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are
required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX).
ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is
shown in Figure 20 (page 53). This output load is used for ODT timings (see (page 0 )).
Pulse width of a input signal is defined as the width between the first crossing of
VREF(DC) and the consecutive crossing of VREF(DC).
Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by a PRECHARGE ALL command.
DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in a reduction of REFRESH characteristics or
product lifetime.
When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
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Command and Address Setup, Hold, and Derating
Command and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated by adding the data
sheet tIS (base) and tIH (base) values (see Table 56; values come from Table 54
(page 73)) to the ΔtIS and ΔtIH derating values (see Table 57 (page 92), Table 58
(page 92) or Table 59 (page 93)) respectively. Example: tIS (total setup time) = tIS
(base) + ΔtIS. For a valid transition, the input signal has to remain above/below
VIH(AC)/VIL(AC) for some time tVAC (see Table 60 (page 93)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH(AC)/VIL(AC) (see Figure 11 (page 43) for input signal requirements). For slew rates that
fall between the values listed in Table 57 (page 92) and Table 59 (page 93), the derating values may be obtained by linear interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tIS) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and
the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal slew
rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for derating value (see Figure 29 (page 94)). If the actual signal is later than the nominal slew
rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent
line to the actual signal from the AC level to the DC level is used for derating value (see
Figure 31 (page 96)).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and
the first crossing of V REF(DC). If the actual signal is always later than the nominal slew
rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Figure 30 (page 95)). If the actual signal is earlier than the nominal slew
rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a tangent
line to the actual signal from the DC level to the V REF(DC) level is used for derating value
(see Figure 32 (page 97)).
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4Gb: x4, x8, x16 DDR3L SDRAM
Command and Address Setup, Hold, and Derating
Table 56: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based
Symbol
tIS(base,
tIS(base,
tIS(base,
800
1066
1333
1600
1866
Unit
Reference
AC160)
215
140
80
60
–
ps
VIH(AC)/VIL(AC)
AC135)
365
290
205
185
65
ps
VIH(AC)/VIL(AC)
AC125)
–
–
–
–
150
ps
VIH(AC)/VIL(AC)
285
210
150
130
110
ps
VIH(DC)/VIL(DC)
tIH(base,
DC90)
Table 57: DDR3L-800/1066/1333/1600 Derating Values tIS/tIH – AC160/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
CMD/ADDR
4.0 V/ns
Slew Rate
V/ns
ΔtIS ΔtIH
CK, CK# Differential Slew Rate
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
80
45
80
45
80
45
88
53
96
61
104
69
112
79
120
95
1.5
53
30
53
30
53
30
61
38
69
46
77
54
85
64
93
80
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
–1
–3
–1
–3
–1
–3
7
5
15
13
23
21
31
31
39
47
0.8
–3
–8
–3
–8
–3
–8
5
1
13
9
21
17
29
27
37
43
0.7
–5
–13
–5
–13
–5
–13
3
–5
11
3
19
11
27
21
35
37
0.6
–8
–20
–8
–20
–8
–20
0
–12
8
–4
16
4
24
14
32
30
0.5
–20
–30
–20
–30
–20
–30
–12
–22
–4
–14
4
–6
12
4
20
20
0.4
–40
–45
–40
–45
–40
–45
–32
–37
–24
–29
–16
–21
–8
–11
0
5
Table 58: DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC135/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
CMD/ADDR
4.0 V/ns
Slew Rate
V/ns
ΔtIS ΔtIH
CK, CK# Differential Slew Rate
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
68
45
68
45
68
45
76
53
84
61
92
69
100
79
108
95
1.5
45
30
45
30
45
30
53
38
61
46
69
54
77
64
85
80
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
2
–3
2
–3
2
–3
10
5
18
13
26
21
34
31
42
47
0.8
3
–8
3
–8
3
–8
11
1
19
9
27
17
35
27
43
43
0.7
6
–13
6
–13
6
–13
14
–5
22
3
30
11
38
21
46
37
0.6
9
–20
9
–20
9
–20
17
–12
25
–4
33
4
41
14
49
30
0.5
5
–30
5
–30
5
–30
13
–22
21
–14
29
–6
37
4
45
20
0.4
–3
–45
–3
–45
–3
–45
6
–37
14
–29
22
–21
30
–11
38
5
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Command and Address Setup, Hold, and Derating
Table 59: DDR3L-1866 Derating Values for tIS/tIH – AC125/DC90-Based
ΔtIS, ΔtIH Derating (ps) – AC/DC-Based
CMD/ADDR
4.0 V/ns
Slew Rate
V/ns
ΔtIS ΔtIH
CK, CK# Differential Slew Rate
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
2.0
63
45
63
45
63
45
71
53
79
61
87
69
95
79
103
95
1.5
42
30
42
30
42
30
50
38
58
46
66
54
74
64
82
80
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
3
–3
3
–3
3
–3
11
5
19
13
27
21
35
31
43
47
0.8
6
–8
6
–8
6
–8
14
1
22
9
30
17
38
27
46
43
0.7
10
–13
10
–13
10
–13
18
–5
26
3
34
11
42
21
50
37
0.6
16
–20
16
–20
16
–20
24
–12
32
–4
40
4
48
14
56
30
0.5
15
–30
15
–30
15
–30
23
–22
31
–14
39
–6
47
4
55
20
0.4
13
–45
13
–45
13
–45
21
–37
29
–29
37
–21
45
–11
53
5
Table 60: DDR3L Minimum Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD
Transition
DDR3L-800/1066/1333/1600
Slew Rate (V/ns)
tVAC
DDR3L-1866
at 160mV (ps) tVAC at 135mV (ps) tVAC at 135mV (ps) tVAC at 125mV (ps)
>2.0
70
209
200
205
2.0
53
198
200
205
1.5
47
194
178
184
1.0
35
186
133
143
0.9
31
184
118
129
0.8
26
181
99
111
0.7
20
177
75
89
0.6
12
171
43
59
0.5
Note 1
164
Note 1
18
<0.5
Note 1
164
Note 1
18
Note:
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1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input
signal shall become equal to or less than VIL(AC) level.
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Command and Address Setup, Hold, and Derating
Figure 29: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock)
tIS
tIS
tIH
tIH
CK
CK#
DQS#
DQS
VDDQ
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(DC)max
tVAC
VSS
ΔTF
Setup slew rate
falling signal =
Note:
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ΔTR
VREF(DC) - VIL(AC)max
Setup slew rate
rising signal =
ΔTF
VIH(AC)min - VREF(DC)
ΔTR
1. The clock and the strobe are drawn on different time scales.
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Command and Address Setup, Hold, and Derating
Figure 30: Nominal Slew Rate for tIH (Command and Address – Clock)
tIS
tIS
tIH
tIH
CK
CK#
DQS#
DQS
VDDQ
VIH(AC)min
VIH(DC)min
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSS
ΔTF
ΔTR
VREF(DC) - VIL(DC)max
Hold slew rate
rising signal =
ΔTR
Note:
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VIH(DC)min - VREF(DC)
Hold slew rate
falling signal =
ΔTF
1. The clock and the strobe are drawn on different time scales.
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Command and Address Setup, Hold, and Derating
Figure 31: Tangent Line for tIS (Command and Address – Clock)
tIS
tIS
tIH
tIH
CK
CK#
DQS#
DQS
VDDQ
Nominal
line
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
VREF to AC
region
VIL(DC)max
Nominal
line
tVAC
ΔTR
VSS
Tangent line (VIH(DC)min - VREF(DC))
Setup slew rate
rising signal =
ΔTR
ΔTF
Note:
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Tangent line (VREF(DC) - VIL(AC)max)
Setup slew rate
falling signal =
ΔTF
1. The clock and the strobe are drawn on different time scales.
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Command and Address Setup, Hold, and Derating
Figure 32: Tangent Line for tIH (Command and Address – Clock)
tIS
tIH
tIS
tIH
CK
CK#
DQS#
DQS
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangen t
line
VREF(DC)
DC to VREF
region
Tangen t
line
Nominal
line
VIL( DC)max
VIL( AC)max
VSS
ΔTR
ΔTR
Tangent line (VREF(DC) - VIL(DC)max)
Hold slew rate
rising signal =
ΔTR
Tangent line (VIH(DC)min - VREF(DC))
Hold slew rate
falling signal =
ΔTF
Note:
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1. The clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Data Setup, Hold, and Derating
The total tDS (setup time) and tDH (hold time) required is calculated by adding the data
sheet tDS (base) and tDH (base) values (see Table 61 (page 99); values come from Table 54 (page 73)) to the ΔtDS and ΔtDH derating values (see Table 62 (page 99)), Table 63 (page 99)) or Table 63 (page 99)) respectively. Example: tDS (total setup time)
= tDS (base) + ΔtDS. For a valid transition, the input signal has to remain above/below
VIH(AC)/VIL(AC) for some time tVAC (see Table 65 (page 101)).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC)) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH/VIL(AC). For slew rates that fall between the values listed in Table 62 (page 99)), Table 63 (page 99)) or Table 63 (page 99), the derating values may obtained by linear
interpolation.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC)
and the first crossing of V IL(AC)max. If the actual signal is always earlier than the nominal
slew rate line between the shaded V REF(DC)-to-AC region, use the nominal slew rate for
derating value (see Figure 33 (page 102)). If the actual signal is later than the nominal
slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a
tangent line to the actual signal from the AC level to the DC level is used for derating
value (see Figure 35 (page 104)).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min
and the first crossing of V REF(DC). If the actual signal is always later than the nominal
slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for
derating value (see Figure 34 (page 103)). If the actual signal is earlier than the nominal
slew rate line anywhere between the shaded DC-to-VREF(DC) region, the slew rate of a
tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating value (see Figure 36 (page 105)).
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Data Setup, Hold, and Derating
Table 61: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based
Symbol
800
1066
1333
1600
1866
Unit
Reference
(base) AC160
90
40
–
–
–
ps
VIH(AC)/VIL(AC)
(base) AC135
140
90
45
45
–
ps
(base) AC130
-
-
-
-
70
ps
tDH
(base) DC100
160
110
75
55
-
ps
tDH
(base) DC100
-
-
-
-
75
ps
1
1
1
1
2
V/ns
tDS
tDS
tDS
Slew Rate Referenced
Table 62: DDR3L Derating Values for tDS/tDH – AC160/DC90-Based
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQS, DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
DQ Slew
Rate V/ns
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
2.0
80
45
80
45
80
45
1.5
53
30
53
30
53
1.0
0
0
0
0
–1
–3
0.9
0.8
1.8 V/ns
ΔtDS
ΔtDH
30
61
38
0
0
8
–1
–3
7
–3
–8
0.7
1.6 V/ns
ΔtDS
ΔtDH
8
16
16
5
15
5
1
–3
–5
0.6
1.4 V/ns
ΔtDS
ΔtDH
13
23
21
13
9
21
11
3
19
8
–4
0.5
1.2 V/ns
ΔtDS
ΔtDH
17
29
27
11
27
16
4
4
6
0.4
1.0 V/ns
ΔtDS
ΔtDH
21
35
37
24
14
32
30
12
4
20
20
–8
–11
0
5
Table 63: DDR3L Derating Values for tDS/tDH – AC135/DC100-Based
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
DQS, DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
DQ Slew
Rate V/ns
ΔtDS
ΔtDH
ΔtDS
ΔtDH
ΔtDS
ΔtDH
2.0
68
45
68
45
68
45
1.5
45
30
45
30
45
1.0
0
0
0
0
2
–3
0.9
0.8
0.7
1.8 V/ns
ΔtDS
ΔtDH
30
53
38
0
0
8
2
–3
10
3
–8
ΔtDH
8
16
16
5
18
11
1
14
–5
0.6
0.5
0.4
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1.6 V/ns
ΔtDS
99
1.4 V/ns
ΔtDS
ΔtDH
13
26
21
19
9
27
22
3
30
25
–4
1.2 V/ns
ΔtDS
ΔtDH
17
35
27
11
38
33
4
39
–6
1.0 V/ns
ΔtDS
ΔtDH
21
46
37
41
14
49
30
37
4
45
20
30
–11
38
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28
22
3.5
3.0
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.5
2.0
2.5
33
4.0
15
19
23
Δ
tDH
Δ
tDS
8.0 V/ns
DQ Slew Rate V/ns
13
22
28
33
tDS
Δ
9
15
19
23
tDH
Δ
7.0 V/ns
0
13
22
28
33
tDS
Δ
0
9
15
19
23
tDH
Δ
6.0 V/ns
–22
0
13
22
28
tDS
Δ
–15
0
9
15
19
tDH
Δ
5.0 V/ns
–65
–22
0
13
22
tDS
Δ
–45
–15
0
9
15
tDH
Δ
4.0 V/ns
–62
–65
–22
0
13
tDS
Δ
–48
–45
–15
0
9
tDH
Δ
3.0 V/ns
–61
–62
–65
–22
0
tDS
Δ
–53
–48
–45
–15
0
tDH
Δ
2.0 V/ns
–49
–53
–54
–57
–14
tDS
Δ
–50
–45
–40
–37
–7
tDH
Δ
1.8 V/ns
DQS, DQS# Differential Slew Rate
Shaded cells indicate slew rate combinations not supported
ΔtDS, ΔtDH Derating (ps) – AC/DC-Based
Table 64: DDR3L Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns
–37
–41
–45
–46
–49
tDS
Δ
-49
-42
–37
–32
–29
tDH
Δ
1.6 V/ns
–31
–29
–33
–37
–38
tDS
Δ
–51
–41
–34
–29
–24
tDH
Δ
1.4 V/ns
–28
–23
–21
–25
–29
tDS
Δ
–56
–41
–31
–24
–19
tDH
Δ
1.2 V/ns
–20
–15
–13
–17
tDS
Δ
–40
–25
–15
–8
tDH
Δ
1.0 V/ns
4Gb: x4, x8, x16 DDR3L SDRAM
Data Setup, Hold, and Derating
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Data Setup, Hold, and Derating
Table 65: DDR3L Minimum Required Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition
Slew Rate (V/ns)
DDR3L-800/1066 160mV
(ps) min
DDR3L-800/1066/1333
135mV (ps) min
DDR3L-1866 130mV
(ps) min
>2.0
165
113
95
2.0
165
113
95
1.5
138
90
73
1.0
85
45
30
0.9
67
30
16
0.8
45
11
Note1
0.7
16
Note1
–
0.6
Note1
Note1
–
0.5
Note1
Note1
–
<0.5
Note1
Note1
–
Note:
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1. Rising input signal shall become equal to or greater than VIH(AC) level and Falling input
signal shall become equal to or less than VIL(AC) level.
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Data Setup, Hold, and Derating
Figure 33: Nominal Slew Rate and tVAC for tDS (DQ – Strobe)
CK
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSS
ΔTF
Setup slew rate
=
falling signal
Note:
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ΔTR
VIH(AC)min - VREF(DC)
Setup slew rate
=
rising signal
ΔTR
VREF(DC) - VIL(AC)max
ΔTF
1. The clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Figure 34: Nominal Slew Rate for tDH (DQ – Strobe)
CK
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
VIH(DC)min
Nominal
slew rate
DC to VREF
region
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSS
ΔTR
VIL(DC)min - VREF(DC)
Hold slew rate
falling signal =
ΔTF
VREF(DC) - VIL(DC)max
Hold slew rate
rising signal =
ΔTR
Note:
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ΔTF
1. The clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Figure 35: Tangent Line for tDS (DQ – Strobe)
CK
CK#
DQS#
DQS
tDS
tDS
tDH
tDH
VDDQ
Nominal
line
tVAC
VIH(AC)min
VREF to AC
region
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
VREF to AC
region
VIL(AC)max
Nominal
line
ΔTR
tVAC
VSS
Setup slew rate
Tangent line (VIH(AC)min - VREF(DC))
rising signal =
ΔTR
ΔTF
Note:
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Setup slew rate
Tangent line (VREF(DC) - VIL(AC)max)
falling signal =
ΔTF
1. The clock and the strobe are drawn on different time scales.
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Data Setup, Hold, and Derating
Figure 36: Tangent Line for tDH (DQ – Strobe)
CK
CK#
DQS#
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
DC to VREF
region
Tangent
line
Nominal
line
VIL(DC)max
VIL(AC)max
VSS
ΔTR
Note:
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ΔTF
Hold slew rate
rising signal =
Tangent line (VREF(DC) - VIL(DC)max)
Hold slew rate
falling signal =
Tangent line (VIH(DC)min - VREF(DC))
ΔTR
ΔTF
1. The clock and the strobe are drawn on different time scales.
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands – Truth Tables
Commands – Truth Tables
Table 66: Truth Table – Command
Notes 1–5 apply to the entire table
CKE
Symbol
Prev.
Cycle
MODE REGISTER SET
MRS
H
H
L
L
L
L
BA
REFRESH
REF
H
H
L
L
L
H
V
V
V
V
V
Self refresh entry
SRE
H
L
L
L
L
H
V
V
V
V
V
6
Self refresh exit
SRX
L
H
H
V
V
V
V
V
V
V
V
6, 7
L
H
H
H
V
V
L
V
V
H
V
Function
Single-bank PRECHARGE
Next
BA
Cycle CS# RAS# CAS# WE# [2:0]
An
A12
A10
A[11,
9:0] Notes
OP code
PRE
H
H
L
L
H
L
BA
PRECHARGE all banks
PREA
H
H
L
L
H
L
V
Bank ACTIVATE
ACT
H
H
L
L
H
H
BA
WRITE
BL8MRS,
BC4MRS
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
8
BC4OTF
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
8
BL8OTF
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
8
BL8MRS,
BC4MRS
WRAP
H
H
L
H
L
L
BA
RFU
V
H
CA
8
BC4OTF
WRAPS4
H
H
L
H
L
L
BA
RFU
L
H
CA
8
BL8OTF
WRAPS8
H
H
L
H
L
L
BA
RFU
H
H
CA
8
BL8MRS,
BC4MRS
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
8
BC4OTF
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
8
BL8OTF
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
8
BL8MRS,
BC4MRS
RDAP
H
H
L
H
L
H
BA
RFU
V
H
CA
8
BC4OTF
RDAPS4
H
H
L
H
L
H
BA
RFU
L
H
CA
8
BL8OTF
L
H
L
H
BA
RFU
H
H
CA
8
H
H
H
V
V
V
V
V
9
WRITE
with auto
precharge
READ
READ
with auto
precharge
Row address (RA)
RDAPS8
H
H
NO OPERATION
NOP
H
H
Device DESELECTED
DES
H
H
H
X
X
X
X
X
X
X
X
10
Power-down entry
PDE
H
L
L
H
H
H
V
V
V
V
V
6
Power-down exit
PDX
L
H
V
V
V
V
V
6, 11
12
H
V
V
V
L
H
H
H
H
V
V
V
ZQ CALIBRATION LONG
ZQCL
H
H
L
H
H
L
X
X
X
H
X
ZQ CALIBRATION SHORT
ZQCS
H
H
L
H
H
L
X
X
X
L
X
Notes:
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1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising
edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configurationdependent.
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Commands – Truth Tables
2. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be
held HIGH during any normal operation.
3. The state of ODT does not affect the states described in this table.
4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of
four mode registers.
5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.”
6. See Table 67 (page 108) for additional information on CKE transition.
7. Self refresh exit is asynchronous.
8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC
are defined in MR0.
9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing.
10. The DES and NOP commands perform similarly.
11. The power-down mode does not perform any REFRESH operations.
12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initialization) or ZQoper (ZQCL command after initialization).
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands – Truth Tables
Table 67: Truth Table – CKE
Notes 1–2 apply to the entire table; see Table 66 (page 106) for additional command details
CKE
Current
State3
Previous Cycle4 Present Cycle4
Command5
(n - 1)
(n)
(RAS#, CAS#, WE#, CS#)
Power-down
Action5
L
L
“Don’t Care”
Maintain power-down
L
H
DES or NOP
Power-down exit
Self refresh
L
L
“Don’t Care”
Maintain self refresh
L
H
DES or NOP
Self refresh exit
Bank(s) active
H
L
DES or NOP
Active power-down entry
Reading
H
L
DES or NOP
Power-down entry
Writing
H
L
DES or NOP
Power-down entry
Precharging
H
L
DES or NOP
Power-down entry
Refreshing
H
L
DES or NOP
Precharge power-down entry
All banks idle
H
L
DES or NOP
Precharge power-down entry
H
L
REFRESH
Self refresh
Notes:
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Notes
6
1. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges.
CKE must remain at the valid input level the entire time it takes to achieve the required
number of registration clocks. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + tCKE (MIN) + tIH.
3. Current state = The state of the DRAM immediately prior to clock edge n.
4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the
previous clock edge.
5. COMMAND is the command registered at the clock edge (must be a legal command as
defined in Table 66 (page 106)). Action is a result of COMMAND. ODT does not affect
the states described in this table and is not listed.
6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied. All self refresh exit and power-down exit parameters are also satisfied.
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Commands
Commands
DESELECT
The DESELT (DES) command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected.
NO OPERATION
The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from
being registered during idle or wait states. Operations already in progress are not affected.
ZQ CALIBRATION LONG
The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibration during a power-up initialization and reset sequence (see Figure 45 (page 125)).
This command may be issued at any time by the controller, depending on the system
environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values.
The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform
a full calibration and transfer of values. When ZQCL is issued during the initialization
sequence, the timing parameter tZQinit must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQoper to be satisfied.
ZQ CALIBRATION SHORT
The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibrations to account for small voltage and temperature variations. A shorter timing window
is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON
and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities
specified in DDR3L 34 Ohm Output Driver Sensitivity (page 59).
ACTIVATE
The ACTIVATE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA[2:0] inputs selects the bank, and the address
provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses
until a PRECHARGE command is issued to that bank.
A PRECHARGE command must be issued before opening a different row in the same
bank.
READ
The READ command is used to initiate a burst read access to an active row. The address
provided on inputs A[2:0] selects the starting column address, depending on the burst
length and burst type selected (see Burst Order table for additional information). The
value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto
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Commands
precharge is not selected, the row will remain open for subsequent accesses. The value
on input A12 (if enabled in the mode register) when the READ command is issued determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the
READ burst may not be interrupted.
Table 68: READ Command Summary
CKE
Function
READ
READ with
auto
precharge
Symbol
Prev.
Cycle
Next
BA
Cycle CS# RAS# CAS# WE# [2:0]
An
A12
A10
A[11,
9:0]
BL8MRS,
BC4MRS
RD
H
L
H
L
H
BA
RFU
V
L
CA
BC4OTF
RDS4
H
L
H
L
H
BA
RFU
L
L
CA
BL8OTF
RDS8
H
L
H
L
H
BA
RFU
H
L
CA
BL8MRS,
BC4MRS
RDAP
H
L
H
L
H
BA
RFU
V
H
CA
BC4OTF
RDAPS4
H
L
H
L
H
BA
RFU
L
H
CA
BL8OTF
RDAPS8
H
L
H
L
H
BA
RFU
H
H
CA
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA[2:0] inputs selects the bank. The value on input A10 determines whether auto
precharge is used. The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW,
the corresponding data will be written to memory. If the DM signal is registered HIGH,
the corresponding data inputs will be ignored and a WRITE will not be executed to that
byte/column location.
Table 69: WRITE Command Summary
CKE
Function
WRITE
WRITE with
auto
precharge
Symbol
Prev.
Cycle
Next
BA
Cycle CS# RAS# CAS# WE# [2:0]
An
A12
A10
A[11,
9:0]
BL8MRS,
BC4MRS
WR
H
L
H
L
L
BA
RFU
V
L
CA
BC4OTF
WRS4
H
L
H
L
L
BA
RFU
L
L
CA
BL8OTF
WRS8
H
L
H
L
L
BA
RFU
H
L
CA
BL8MRS,
BC4MRS
WRAP
H
L
H
L
L
BA
RFU
V
H
CA
BC4OTF
WRAPS4
H
L
H
L
L
BA
RFU
L
H
CA
BL8OTF
WRAPS8
H
L
H
L
L
BA
RFU
H
H
CA
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands
PRECHARGE
The PRECHARGE command is used to de-activate the open row in a particular bank or
in all banks. The bank(s) are available for a subsequent row access a specified time ( tRP)
after the PRECHARGE command is issued, except in the case of concurrent auto precharge. A READ or WRITE command to a different bank is allowed during a concurrent
auto precharge as long as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Input A10 determines whether one or all
banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as “Don’t Care.”
After a bank is precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. A PRECHARGE command is treated as
a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging. However, the precharge period is determined by
the last PRECHARGE command issued to the bank.
REFRESH
The REFRESH command is used during normal operation of the DRAM and is analogous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by
the internal refresh controller. This makes the address bits a “Don’t Care” during a REFRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs
(maximum when T C ≤ 85°C or 3.9μs maximum when T C ≤ 95°C). The REFRESH period
begins when the REFRESH command is registered and ends tRFC (MIN) later.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval
between any REFRESH command and the next REFRESH command is nine times the
maximum average interval refresh rate. Self refresh may be entered with up to eight REFRESH commands being posted. After exiting self refresh (when entered with posted
REFRESH commands), additional posting of REFRESH commands is allowed to the extent that the maximum number of cumulative posted REFRESH commands (both preand post-self refresh) does not exceed eight REFRESH commands.
At any given time, a maximum of 16 REFRESH commands can be issued within
2 x tREFI.
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands
Figure 37: Refresh Mode
T0
T2
T1
CK#
CK
tCK
T3
tCH
T4
Ta1
Valid 5
NOP1
PRE
Tb0
Tb1
Valid 5
Valid 5
NOP5
NOP5
Tb2
tCL
CKE
Command
Ta0
NOP1
NOP1
REF
NOP5
REF2
Address
ACT
RA
All banks
A10
RA
One bank
BA[2:0]
Bank(s)3
BA
DQS, DQS#4
DQ4
DM4
tRP
tRFC
(MIN)
tRFC2
Indicates break
in time scale
Notes:
Don’t Care
1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH
commands, but may be inactive at other times (see Power-Down Mode (page 174)).
2. The second REFRESH is not required, but two back-to-back REFRESH commands are
shown.
3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one
bank is active (must precharge all active banks).
4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z.
5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC
(MIN) is satisfied.
SELF REFRESH
The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the
system is powered down. When in self refresh mode, the DRAM retains data without external clocking. Self refresh mode is also a convenient method used to enable/disable
the DLL as well as to change the clock frequency within the allowed synchronous operating range (see Input Clock Frequency Change (page 117)). All power supply inputs
(including V REFCA and V REFDQ) must be maintained at valid levels upon entry/exit and
during self refresh mode operation. V REFDQ may float or not drive V DDQ/2 while in self
refresh mode under the following conditions:
•
•
•
•
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VSS < V REFDQ < V DD is maintained
VREFDQ is valid and stable prior to CKE going back HIGH
The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid
All other self refresh mode exit timing requirements are met
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands
DLL Disable Mode
If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode, with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
WRITE latency (CWL = 6).
• DLL disable mode affects the read data clock-to-data strobe relationship (tDQSCK),
but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is
required to line up the read data with the controller time domain when the DLL is disabled.
• In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL
cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cycles after the READ command. Additionally, with the DLL disabled, the value of
tDQSCK could be larger than tCK.
The ODT feature (including dynamic ODT) is not supported during DLL disable mode.
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming RTT,nom MR1[9, 6, 2] and RTT(WR) MR2[10, 9] to 0 while in the DLL disable
mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (tCK [AVG] MAX
and tCK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross this
clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh:
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and RTT,nom and RTT(WR) are High-Z), set MR1[0] to 1 to disable the
DLL.
2. Enter self refresh mode after tMOD has been satisfied.
3. After tCKSRE is satisfied, change the frequency to the desired clock rate.
4. Self refresh may be exited when the clock is stable with the new frequency for
tCKSRX. After tXS is satisfied, update the mode registers with appropriate values.
5. The DRAM will be ready for its next command in the DLL disable mode after the
greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued
with appropriate timings met.
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands
Figure 38: DLL Enable Mode to DLL Disable Mode
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK#
CK
Valid1
CKE
MRS2
Command
6
SRE3
NOP
SRX4
NOP
7
tCKSRE
tMOD
tCKSRX8
NOP
tXS
MRS5
NOP
Valid1
tMOD
tCKESR
ODT9
Valid1
Indicates break
in time scale
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Don’t Care
Any valid command.
Disable DLL by setting MR1[0] to 1.
Enter SELF REFRESH.
Exit SELF REFRESH.
Update the mode registers with the DLL disable parameters setting.
Starting with the idle state, RTT is in the High-Z state.
Change frequency.
Clock must be stable tCKSRX.
Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 39 (page 115)).
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
is turned off, and RTT,nom and RTT(WR) are High-Z), enter self refresh mode.
2. After tCKSRE is satisfied, change the frequency to the new clock rate.
3. Self refresh may be exited when the clock is stable with the new frequency for
tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to 0 to enable the DLL. Wait tMRD, then set MR0[8]
to 1 to enable DLL RESET.
4. After another tMRD delay is satisfied, update the remaining mode registers with
the appropriate values.
5. The DRAM will be ready for its next command in the DLL enable mode after the
greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must
be satisfied. A ZQCL command should be issued with the appropriate timings met.
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands
Figure 39: DLL Disable Mode to DLL Enable Mode
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Tg0
Th0
CK#
CK
CKE
Valid
tDLLK
Command
SRE1
NOP
SRX2
NOP
tCKSRE
7
8
tCKSRX9
MRS3
tXS
MRS4
tMRD
MRS5
Valid 6
tMRD
ODTLoff + 1 × tCK
tCKESR
ODT10
Indicates break
in time scale
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Don’t Care
Enter SELF REFRESH.
Exit SELF REFRESH.
Wait tXS, then set MR1[0] to 0 to enable DLL.
Wait tMRD, then set MR0[8] to 1 to begin DLL RESET.
Wait tMRD, update registers (CL, CWL, and write recovery may be necessary).
Wait tMOD, any valid command.
Starting with the idle state.
Change frequency.
Clock must be stable at least tCKSRX.
Static LOW in the case that RTT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH.
The clock frequency range for the DLL disable mode is specified by the parameter tCK
(DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
supported.
DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK)
but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to
line up read data to the controller time domain.
Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL
cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles
after the READ command.
WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.
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4Gb: x4, x8, x16 DDR3L SDRAM
Commands
Figure 40: DLL Disable tDQSCK
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Valid
CK#
CK
RL = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQS, DQS# DLL on
DI
b
DQ BL8 DLL on
RL (DLL_DIS) = AL + (CL - 1) = 5
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
tDQSCK (DLL_DIS) MIN
DQS, DQS# DLL off
DI
b
DQ BL8 DLL disable
DI
b+1
tDQSCK
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
DI
b+3
DI
b+4
DI
b+5
DI
b+6
(DLL_DIS) MAX
DQS, DQS# DLL off
DI
b
DQ BL8 DLL disable
DI
b+1
DI
b+2
DI
b+7
Transitioning Data
Don’t Care
Table 70: READ Electrical Characteristics, DLL Disable Mode
Parameter
Access window of DQS from CK, CK#
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Symbol
tDQSCK
116
(DLL_DIS)
Min
Max
Unit
1
10
ns
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4Gb: x4, x8, x16 DDR3L SDRAM
Input Clock Frequency Change
Input Clock Frequency Change
When the DDR3 SDRAM is initialized, the clock must be stable during most normal
states of operation. This means that after the clock frequency has been set to the stable
state, the clock period is not allowed to deviate, except for what is allowed by the clock
jitter and spread spectrum clocking (SSC) specifications.
The input clock frequency can be changed from one stable clock rate to another under
two conditions: self refresh mode and precharge power-down mode. It is illegal to
change the clock frequency outside of those two modes. For the self refresh mode condition, when the DDR3 SDRAM has been successfully placed into self refresh mode and
tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the
clock becomes a “Don’t Care,” changing the clock frequency is permissible if the new
clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode
for the sole purpose of changing the clock frequency, the self refresh entry and exit
specifications must still be met.
The precharge power-down mode condition is when the DDR3 SDRAM is in precharge
power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a
logic LOW or RTT,nom and RTT(WR) must be disabled via MR1 and MR2. This ensures
RTT,nom and RTT(WR) are in an off state prior to entering precharge power-down mode,
and CKE must be at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW
before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade (tCK [AVG] MIN to tCK [AVG] MAX). During the input
clock frequency change, CKE must be held at a stable LOW level. When the input clock
frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge power-down may be exited. After precharge power-down is exited and tXP has
been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time,
RTT,nom and RTT(WR) must remain in an off state. After the DLL lock time, the DRAM is
ready to operate with a new clock frequency.
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4Gb: x4, x8, x16 DDR3L SDRAM
Input Clock Frequency Change
Figure 41: Change Frequency During Precharge Power-Down
Previous clock frequency
T0
T1
T2
New clock frequency
Ta0
Tb0
Tc1
Tc0
Td0
Td1
Te0
Te1
CK#
CK
tCH
tCH
b
tCL
tCKSRE
tIS
tCL
b
tCH
b
tCK
b
tCL
b
tCK
b
tCKSRX
tCKE
tIH
CKE
tIS
tCPDED
Command
tCH
b
tCK
b
tCK
tIH
tCL
b
NOP
NOP
NOP
NOP
NOP
Address
MRS
NOP
Valid
DLL RESET
tAOFPD/tAOF
tXP
Valid
tIH
tIS
ODT
DQS, DQS#
High-Z
DQ
High-Z
DM
tDLLK
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
Indicates break
in time scale
Notes:
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Don’t Care
1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes.
2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termination (ODT) for exact requirements).
3. If the RTT,nom feature was enabled in the mode register prior to entering precharge
power-down mode, the ODT signal must be continuously registered LOW, ensuring RTT
is in an off state. If the RTT,nom feature was disabled in the mode register prior to entering precharge power-down mode, RTT will remain in the off state. The ODT signal can
be registered LOW or HIGH in this case.
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4Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
Write Leveling
For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme
for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal
DRAM operation, this feature must be disabled. This is the only DRAM operation where
the DQS functions as an input (to capture the incoming clock) and the DQ function as
outputs (to report the state of the clock). Note that nonstandard ODT schemes are required.
The memory controller using the write leveling procedure must have adjustable delay
settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins.
This is accomplished when the DRAM asynchronously feeds back the CK status via the
DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the
DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established by
this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use
fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this
procedure is shown in Figure 42.
Figure 42: Write Leveling Concept
T0
T1
T2
T3
T5
T4
T6
T7
CK#
CK
Source
Differential DQS
Tn
T0
T1
T2
T3
T4
T5
T6
T4
T5
T6
CK#
CK
Destination
Differential DQS
0
DQ
Destination
Tn
T0
T1
0
T2
T3
CK#
CK
Push DQS to capture
0–1 transition
Differential DQS
DQ
1
1
Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with
all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the
lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS
and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a
x16 enable each byte lane to be leveled independently.
The write leveling mode register interacts with other mode registers to correctly configure the write leveling functionality. Besides using MR1[7] to disable/enable write leveling, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst
length, and so forth need to be selected as well. This interaction is shown in Table 71. It
should also be noted that when the outputs are enabled during write leveling mode, the
DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write
leveling mode, only the DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the ODT ball.
Table 71: Write Leveling Matrix
Note 1 applies to the entire table
MR1[7]
MR1[12]
MR1[2, 6, 9]
Write
Leveling
Output
Buffers
RTT,nom
Value
Disabled
Enabled
(1)
DRAM
RTT,nom
DRAM
ODT Ball DQS
DQ
See normal operations
Disabled
(1)
Write leveling not enabled
0
DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
1
Low
Off
ΩΩ
ΩΩ, or
120Ω
High
On
DQS not receiving: terminated by RTT
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
2
n/a
Low
Off
DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
3
ΩΩ, or
120Ω
High
On
DQS receiving: terminated by RTT
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
4
Notes:
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Case Notes
n/a
Enabled
(0)
Off
DRAM State
2
3
1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a
dual-rank module and on the rank not being leveled or on any rank of a module not
being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of
a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is
generally used when DRAM are on the rank that is being leveled.
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,
and all RTT,nom values are allowed. This simulates a normal standby state to DQS.
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and
only some RTT,nom values are allowed. This simulates a normal write state to DQS.
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4Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
Write Leveling Procedure
A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the
DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a
High-Z state to an undefined driving state, so the DQ bus should not be driven. During
write leveling mode, only the NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks
should be disabled by setting MR1[12] to 1 in the other ranks. The memory controller
may assert ODT after a tMOD delay, as the DRAM will be ready to process the ODT transition. ODT should be turned on prior to DQS being driven LOW by at least ODTLon
delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay requirement.
The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has
been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle
is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a
HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTLon and tAON must be satisfied at least one clock prior to DQS toggling.
After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory
controller may provide either a single DQS toggle or multiple DQS toggles to sample CK
for a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH
(MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable
during write leveling mode. The DQS must be able to distinguish the CK’s rising edge
within tWLS and tWLH. The prime DQ will output the CK’s status asynchronously from
the associated DQS rising edge CK capture within tWLO. The remaining DQ that always
drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQ going LOW). As previously noted, DQS is an input and not an output during this process. Figure 43 (page 122) depicts the basic timing parameters for
the overall write leveling procedure.
The memory controller will most likely sample each applicable prime DQ state and determine whether to increment or decrement its DQS delay setting. After the memory
controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memory controller should lock the DQS delay setting for that DRAM. After locking the DQS
setting is locked, leveling for the rank will have been achieved, and the write leveling
mode for the rank should be disabled or reprogrammed (if write leveling of another
rank follows).
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4Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
Figure 43: Write Leveling Sequence
T1
T2
tWLS
tWLH
CK#
CK
Command
MRS1
NOP2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
ODT
tWLDQSEN
tDQSL3
tDQSH3
tDQSL3
tDQSH3
Differential DQS4
tWLMRD
tWLO
tWLO
Prime DQ5
tWLO
tWLOE
Early remaining DQ
tWLO
Late remaining DQ
Indicates break
in time scale
Notes:
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Undefined Driving Mode
Don’t Care
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or DES.
3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL
(MIN) as defined for regular writes. The maximum pulse width is system-dependent.
4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are
the zero crossings. The solid line represents DQS; the dotted line represents DQS#.
5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ
are driven LOW and remain in this state throughout the leveling procedure.
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4Gb: x4, x8, x16 DDR3L SDRAM
Write Leveling
Write Leveling Mode Exit Procedure
After the DRAM are leveled, they must exit from write leveling mode before the normal
mode can be used. Figure 44 depicts a general procedure for exiting write leveling
mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop
driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become
undefined when DQS no longer remains LOW, and they remain undefined until tMOD
after the MRS command (at Te1).
The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the
DQS is no longer driving LOW. When ODT LOW satisfies tIS, ODT must be kept LOW (at
~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal
mode can be used. After DQS termination is switched off, write level mode should be
disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the DRAM. Some MRS commands may be issued after tMRD
(at Td1).
Figure 44: Write Leveling Exit Procedure
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
Td0
Td1
Te0
Te1
NOP
Valid
NOP
Valid
CK#
CK
Command
tMRD
Address
MR1
tIS
Valid
Valid
tMOD
ODT
t
ODTLoff AOF (MIN)
RTT,nom
RTT DQS, RTT DQS#
t
AOF (MAX)
DQS, DQS#
RTT(DQ)
tWLO
DQ
+ tWLOE
CK = 1
Indicates break
in time scale
Note:
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Undefined Driving Mode
Transitioning
Don’t Care
1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
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4Gb: x4, x8, x16 DDR3L SDRAM
Initialization
Initialization
The following sequence is required for power-up and initialization, as shown in Figure 45 (page 125):
1. Apply power. RESET# is recommended to be below 0.2 × V DDQ during power ramp
to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z).
All other inputs, including ODT, may be undefined.
During power-up, either of the following conditions may exist and must be met:
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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• Condition A:
– VDD and V DDQ are driven from a single-power converter output and are
ramped with a maximum delta voltage between them of ΔV ≤ 300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than V DD, V DDQ, V SS, V SSQ must be less than or equal to V DDQ and V DD on
one side, and must be greater than or equal to V SSQ and V SS on the other side.
– Both V DD and V DDQ power supplies ramp to V DD,min and V DDQ,min within
tV
DDPR = 200ms.
– VREFDQ tracks V DD × 0.5, V REFCA tracks V DD × 0.5.
– VTT is limited to 0.95V when the power ramp is complete and is not applied
directly to the device; however, tVTD should be greater than or equal to 0 to
avoid device latchup.
• Condition B:
– VDD may be applied before or at the same time as V DDQ.
– VDDQ may be applied before or at the same time as V TT, V REFDQ, and V REFCA.
– No slope reversals are allowed in the power supply ramp for this condition.
Until stable power, maintain RESET# LOW to ensure the outputs remain disabled
(High-Z). After the power is stable, RESET# must be LOW for at least 200μs to begin the initialization process. ODT will remain in the High-Z state while RESET# is
LOW and until CKE is registered HIGH.
CKE must be LOW 10ns prior to RESET# transitioning HIGH.
After RESET# transitions HIGH, wait 500μs (minus one clock) with CKE LOW.
After the CKE LOW time, CKE may be brought HIGH (synchronously) and only
NOP or DES commands may be issued. The clock must be present and valid for at
least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least
tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be
continuously registered HIGH until the full initialization process is complete.
After CKE is registered HIGH and after tXPR has been satisfied, MRS commands
may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable
settings (provide LOW to BA2 and BA0 and HIGH to BA1).
Issue an MRS command to MR3 with the applicable settings.
Issue an MRS command to MR1 with the applicable settings, including enabling
the DLL and configuring ODT.
Issue an MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL.
Issue a ZQCL command to calibrate RTT and RON values for the process voltage
temperature (PVT). Prior to normal operation, tZQinit must be satisfied.
When tDLLK and tZQinit have been satisfied, the DDR3 SDRAM will be ready for
normal operation.
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4Gb: x4, x8, x16 DDR3L SDRAM
Initialization
Figure 45: Initialization Sequence
T (MAX) = 200ms
VDD
VDDQ
VTT
See power-up
conditions
in the
initialization
sequence text,
set up 1
VREF
Power-up
ramp
tVTD
Stable and
valid clock
T0
T1
tCK
Tc0
Tb0
Ta0
Td0
CK#
CK
tCKSRX
tIOZ
tCL
tCL
= 20ns
RESET#
tIS
T (MIN) = 10ns
CKE
Valid
ODT
Valid
tIS
NOP
Command
MRS
MRS
MRS
MRS
Address
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
ZQCL
Valid
DM
BA[2:0]
Valid
Valid
A10 = H
Valid
DQS
DQ
RTT
T = 200μs (MIN)
T = 500μs (MIN)
tXPR
MR2
All voltage
supplies valid
and stable
tMRD
tMRD
MR3
tMRD
MR1 with
DLL enable
tMOD
MR0 with
DLL reset
tZQinit
ZQ calibration
tDLLK
DRAM ready for
external commands
Normal
operation
Indicates break
in time scale
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125
Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
Voltage Initialization / Change
Voltage Initialization / Change
If the SDRAM is powered up and initialized for the 1.35V operating voltage range, voltage can be increased to the 1.5V operating range provided the following conditions are
met (See Figure 46 (page 127)):
• Just prior to increasing the 1.35V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
• The 1.5V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
• The DLL is reset and relocked after the 1.5V operating voltages are stable and prior to
any READ command.
• The ZQ calibration is performed. tZQinit must be satisfied after the 1.5V operating
voltages are stable and prior to any READ command.
If the SDRAM is powered up and initialized for the 1.5V operating voltage range, voltage
can be reduced to the 1.35V operation range provided the following conditions are met
(See Figure 46 (page 127)) :
• Just prior to reducing the 1.5V operating voltages, no further commands are issued,
other than NOPs or COMMAND INHIBITs, and all banks are in the precharge state.
• The 1.35V operating voltages are stable prior to issuing new commands, other than
NOPs or COMMAND INHIBITs.
• The DLL is reset and relocked after the 1.35V operating voltages are stable and prior to
any READ command.
• The ZQ calibration is performed. tZQinit must be satisfied after the 1.35V operating
voltages are stable and prior to any READ command.
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4Gb: x4, x8, x16 DDR3L SDRAM
Voltage Initialization / Change
VDD Voltage Switching
After the DDR3L DRAM is powered up and initialized, the power supply can be altered
between the DDR3L and DDR3 levels, provided the sequence in Figure 46 is maintained.
Figure 46: VDD Voltage Switching
Tb
Ta
CK, CK#
Tc
Te
Td
((
))
((
))
((
))
((
))
((
))
((
))
Tf
Ti
Th
Tg
Tj
Tk
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Valid
tXPR
tMRD
tMRD
((
))
((
))
Valid
((
))
((
))
((
))
((
))
Valid
((
))
((
))
((
))
((
))
((
))
((
))
tCKSRX
TMIN = 10ns
VDD, VDDQ (DDR3)
((
))
((
))
((
))
((
))
VDD, VDDQ (DDR3L)
TMIN = 10ns
TMIN = 200μs
T = 500μs
RESET#
CKE
((
))
((
))
((
))
((
))
tIS
TMIN = 10ns
((
))
tDLLK
tIS
((
))
((
))
MRS
((
))
((
))
MRS
((
))
((
))
((
))
((
))
MR2
((
))
((
))
MR3
((
))
((
))
Command
((
))
((
))
((
))
((
))
BA
((
))
((
))
((
))
((
))
ODT
((
))
((
))
((
))
((
))
((
))
((
))
RTT
((
))
((
))
((
))
Note 1
tMRD
MRS
MR1
tMOD
((
))
((
))
MRS
((
))
((
))
((
))
((
))
MR0
((
))
((
))
tZQinit
ZQCL
((
))
((
))
Note 1
tIS
tIS
((
((
((
((
))
))
))
))
Static LOW in case RTT,nom is enabled at time Tg, otherwise static HIGH or LOW
((
((
((
((
))
))
))
))
((
))
((
))
((
))
((
))
((
))
Time break
((
))
Note:
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4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
Valid
Don’t Care
1. From time point Td until Tk, NOP or DES commands must be applied between MRS and
ZQCL commands.
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Registers
Mode Registers
Mode registers (MR0–MR3) are used to define various modes of programmable operations of the DDR3 SDRAM. A mode register is programmed via the mode register set
(MRS) command during initialization, and it retains the stored information (except for
MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device
loses power.
Contents of a mode register can be altered by re-executing the MRS command. Even if
the user wants to modify only a subset of the mode register’s variables, all variables
must be programmed when the MRS command is issued. Reprogramming the mode
register will not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands.
Figure 47: MRS to MRS Command Timing (tMRD)
T0
T1
T2
Ta0
Ta1
Ta2
MRS1
NOP
NOP
NOP
NOP
MRS2
CK#
CK
Command
tMRD
Address
Valid
Valid
CKE3
Indicates break
in time scale
Notes:
Don’t Care
1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN)
must be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS to MRS command minimum cycle time.
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Power-Down Mode (page 174)).
4. For a CAS latency change, tXPDLL timing must be met before any non-MRS command.
The controller must also wait tMOD before initiating any non-MRS commands (excluding NOP and DES). The DRAM requires tMOD in order to update the requested features,
with the exception of DLL RESET, which requires additional time. Until tMOD has been
satisfied, the updated features are to be assumed unavailable.
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 0 (MR0)
Figure 48: MRS to nonMRS Command Timing (tMOD)
T0
T1
T2
Ta0
Ta1
Ta2
MRS
NOP
NOP
NOP
NOP
non
MRS
CK#
CK
Command
tMOD
Valid
Valid
Address
Valid
CKE
Old
setting
New
setting
Updating setting
Indicates break
in time scale
Notes:
Don’t Care
1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP
must be satisfied, and no data bursts can be in progress).
2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be
issued.
3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until
tMODmin is satisfied at Ta2.
4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which
time power-down may occur (see Power-Down Mode (page 174)).
Mode Register 0 (MR0)
The base register, mode register 0 (MR0), is used to define various DDR3 SDRAM modes
of operation. These definitions include the selection of a burst length, burst type, CAS
latency, operating mode, DLL RESET, write recovery, and precharge power-down mode
(see Figure 49 (page 130)).
Burst Length
Burst length is defined by MR0[1:0]. Read and write accesses to the DDR3 SDRAM are
burst-oriented, with the burst length being programmable to 4 (chop) mode, 8 (fixed)
mode, or selectable using A12 during a READ/WRITE command (on-the-fly). The burst
length determines the maximum number of column locations that can be accessed for
a given READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE
command, if A12 = 0, then BC4 mode is selected. If A12 = 1, then BL8 mode is selected.
Specific timing diagrams, and turnaround between READ/WRITE, are shown in the
READ/WRITE sections of this document.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst
length is set to 8, where Ai is the most significant column address bit for a given configuration. The remaining (least significant) address bit(s) is (are) used to select the start-
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 0 (MR0)
ing location within the block. The programmed burst length applies to both READ and
WRITE bursts.
Figure 49: Mode Register 0 (MR0) Definitions
BA2 BA1 BA0 A[15:13] A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
18 17 16 15–13 12 11 10
WR
PD
01 0 0
01
Mode register 0 (MR0)
9
8 7 6 5 4 3 2
DLL 0 CAS# latency BT CL
1 0
BL
M1 M0
Mode Register Select
M17 M16
0
0
Mode register select 0 (MR0)
0
1
Mode register select 1 (MR1)
M12
Precharge PD
1
0
Mode register select 2 (MR2)
0
DLL off (slow exit)
0
1
1
Mode register select 3 (MR3)
1
DLL on (fast exit)
1
Note:
0
Fixed BL8
M7
Mode
0
1
4 or 8 (on-the-fly via A12)
No
0
Normal
1
0
Fixed BC4 (chop)
Yes
1
Test
1
1
Reserved
M8 DLL Reset
M11 M10 M9 Write Recovery
Burst Length
0
M6 M5 M4 M2
CAS Latency
M3
0
0
0
16
0
0
0
0
Reserved
0
Sequential (nibble)
READ Burst Type
0
0
1
5
0
0
1
0
5
1
Interleaved
0
1
0
6
0
1
0
0
6
0
1
1
7
0
1
1
0
7
1
0
0
8
1
0
0
0
8
1
0
1
10
1
0
1
0
9
1
1
0
12
1
1
0
0
10
1
1
1
14
1
1
1
0
11
0
0
0
1
12
0
0
1
1
13
0
1
0
1
14
1. MR0[18, 15:13] are reserved for future use and must be programmed to 0.
Burst Type
Accesses within a given burst can be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3] (see Figure 49 (page 130)). The ordering of accesses within a burst is determined by the burst length, the burst type, and the
starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access
modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries.
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 0 (MR0)
Table 72: Burst Order
Burst
Length
READ/
WRITE
Starting
Column Address
(A[2, 1, 0])
Burst Type = Sequential
(Decimal)
Burst Type = Interleaved
(Decimal)
Notes
4 (chop)
READ
000
0, 1, 2, 3, Z, Z, Z, Z
0, 1, 2, 3, Z, Z, Z, Z
1, 2
001
1, 2, 3, 0, Z, Z, Z, Z
1, 0, 3, 2, Z, Z, Z, Z
1, 2
010
2, 3, 0, 1, Z, Z, Z, Z
2, 3, 0, 1, Z, Z, Z, Z
1, 2
011
3, 0, 1, 2, Z, Z, Z, Z
3, 2, 1, 0, Z, Z, Z, Z
1, 2
100
4, 5, 6, 7, Z, Z, Z, Z
4, 5, 6, 7, Z, Z, Z, Z
1, 2
101
5, 6, 7, 4, Z, Z, Z, Z
5, 4, 7, 6, Z, Z, Z, Z
1, 2
110
6, 7, 4, 5, Z, Z, Z, Z
6, 7, 4, 5, Z, Z, Z, Z
1, 2
WRITE
8 (fixed)
READ
WRITE
Notes:
111
7, 4, 5, 6, Z, Z, Z, Z
7, 6, 5, 4, Z, Z, Z, Z
1, 2
0VV
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1, 3, 4
1VV
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
1, 3, 4
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
1
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
1
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
1
VVV
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
1, 3
1. Internal READ and WRITE operations start at the same point in time for BC4 as they do
for BL8.
2. Z = Data and strobe output drivers are in tri-state.
3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input
pins.
4. X = “Don’t Care.”
DLL RESET
DLL RESET is defined by MR0[8] (see Figure 49 (page 130)). Programming MR0[8] to 1
activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value
of 0 after the DLL RESET function has been initiated.
Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held
stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to
allow time for the internal clock to be synchronized with the external clock. Failing to
wait for synchronization can result in invalid output timing specifications, such as
tDQSCK timings.
Write Recovery
WRITE recovery time is defined by MR0[11:9] (see Figure 49 (page 130)). Write recovery
values of 5, 6, 7, 8, 10, or 12 can be used by programming MR0[11:9]. The user is rePDF: 09005aef8591e091
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 0 (MR0)
quired to program the correct value of write recovery, which is calculated by dividing
(ns) by tCK (ns) and rounding up a noninteger value to the next integer:
WR (cycles) = roundup (tWR (ns)/tCK (ns)).
tWR
Precharge Power-Down (Precharge PD)
The precharge power-down (precharge PD) bit applies only when precharge powerdown mode is being used. When MR0[12] is set to 0, the DLL is off during precharge
power-down, providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge
power-down mode to enable a faster exit of precharge power-down mode; however, tXP
must be satisfied when exiting (see Power-Down Mode (page 174)).
CAS Latency (CL)
CAS latency (CL) is defined by MR0[6:4], as shown in Figure 49 (page 130). CAS latency
is the delay, in clock cycles, between the internal READ command and the availability of
the first bit of output data. CL can be set to 5 through 14. DDR3 SDRAM do not support
half-clock latencies.
Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. See Speed Bin Tables for the CLs supported at
various operating frequencies.
Figure 50: READ Latency
T0
T1
T2
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
AL = 0, CL = 6
DQS, DQS#
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
T0
T1
T2
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
AL = 0, CL = 8
DQS, DQS#
DI
n
DQ
Transitioning Data
Notes:
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Don’t Care
1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.
2. Shown with nominal tDQSCK and nominal tDSDQ.
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 1 (MR1)
Mode Register 1 (MR1)
The mode register 1 (MR1) controls additional functions and features not available in
the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration
only), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTED
CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 51 (page 133). The MR1 register is programmed via the
MRS command and retains the stored information until it is reprogrammed, until RESET# goes LOW, or until the device loses power. Reprogramming the MR1 register will
not alter the contents of the memory array, provided it is performed correctly.
The MR1 register must be loaded when all banks are idle and no bursts are in progress.
The controller must satisfy the specified timing parameters tMRD and tMOD before initiating a subsequent operation.
Figure 51: Mode Register 1 (MR1) Definition
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
A1 A0
Address bus
18 17 16 15 14 13 12 11 10 9 8 7 6 5
01 0 1 01 01 01 Q Off TDQS 01 RTT 01 WL RTT ODS
M17 M16
4
3
AL
2
1 0
RTT ODS DLL
Mode register 1 (MR1)
Mode Register
0
0
Mode register set 0 (MR0)
M12
Q Off
M11
TDQS
0
1
Mode register set 1 (MR1)
0
Enabled
0
Disabled
1
0
Mode register set 2 (MR2)
1
Disabled
1
Enabled
1
1
Mode register set 3 (MR3)
R TT,nom
(ODT) 2
M0
DLL Enable
0
Enable (normal)
1
Disable
M5 M1 Output Drive St rength
R TT,nom
(ODT) 3
M7 Write Levelization
M9 M6 M2
Non- Writes
Writes
0
0 0 0
R TT,nom disabled
R TT,nom disabled
1
0 0 1
RZQ/4 (60Ω [NOM])
RZQ/4 (60Ω [NOM])
Disable (normal)
Enable
0
0
RZQ/6 (40Ω [NOM])
0
1
RZQ/7 (34Ω [NOM])
1
0
Reserved
1
1
Reserved
0 1 0 RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM])
0 1 1
Notes:
RZQ/6 (40Ω [NOM])
RZQ/6 (40Ω [NOM])
M4 M3 Additive Latency (AL)
1 0 0 RZQ/12 (20Ω [NOM])
n/a
0
0
Disabled (AL = 0)
1 0 1
RZQ/8 (30Ω [NOM])
n/a
0
1
AL = CL - 1
1 1 0
Reserved
Reserved
1
0
AL = CL - 2
1 1 1
Reserved
Reserved
1
1
Reserved
1. MR1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.
2. During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available
for use.
3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values
are available for use.
DLL Enable/DLL Disable
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE
command, as shown in Figure 51 (page 133). The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command.
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 1 (MR1)
upon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until
it is re-enabled and reset.
The DRAM is not tested to check—nor does Micron warrant compliance with—normal
mode timings or functionality when the DLL is disabled. An attempt has been made to
have the DRAM operate in the normal mode where reasonably possible when the DLL
has been disabled; however, by industry standard, a few known exceptions are defined:
• ODT is not allowed to be used
• The output data is no longer edge-aligned to the clock
• CL and CWL can only be six clocks
When the DLL is disabled, timing and functionality can vary from the normal operation
specifications when the DLL is enabled (see DLL Disable Mode (page 113)). Disabling
the DLL also implies the need to change the clock frequency (see Input Clock Frequency Change (page 117)).
Output Drive Strength
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength
mode register setting is defined by MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output
driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver impedance, an external precision resistor (RZQ) is connected between the ZQ ball and
VSSQ. The value of the resistor must be 240Ω 
The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation, and all data sheet timings and current specifications are met during an update.
To meet the 34Ω specification, the output drive strength must be set to 34Ω during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset procedure.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 51
(page 133). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in
the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs
(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be used
during IDD characterization of the READ current and during tDQSS margining (write
leveling) only.
TDQS Enable
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration that
provides termination resistance (RTT) and may be useful in some system configurations.
TDQS is not supported in x4 or x16 configurations. When enabled via the mode register
(MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#.
In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termination resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not provided
by TDQS; thus, R ON does not apply to TDQS and TDQS#. The TDQS and DM functions
share the same ball. When the TDQS function is enabled via the mode register, the DM
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 1 (MR1)
vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3
SDRAM configuration only and must be disabled via the mode register for the x4 and
x16 configurations.
On-Die Termination
ODT resistance RTT,nom is defined by MR1[9, 6, 2] (see Figure 51 (page 133)). The R TT
termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3
supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or
12 and RZQ is 240Ω
Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain
off during a READ burst. RTT,nom termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh
mode. Additionally, write accesses with dynamic ODT (RTT(WR)) enabled temporarily replaces RTT,nom with RTT(WR).
The actual effective termination, RTT(EFF), may be different from the RTT targeted due to
nonlinearity of the termination. For RTT(EFF) values and calculations (see On-Die Termination (ODT) (page 184)).
The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when R TT is turned on (ODTL on)
and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2].
Timings for ODT are detailed in On-Die Termination (ODT) (page 184).
WRITE LEVELING
The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 51 (page 133).
Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as
a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory
modules adopted fly-by topology for the commands, addresses, control signals, and
clocks.
The fly-by topology benefits from a reduced number of stubs and their lengths. However, fly-by topology induces flight time skews between the clock and DQS strobe (and
DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining
tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems
which use fly-by topology-based modules. Write leveling timing and detailed operation
information is provided in Write Leveling (page 119).
POSTED CAS ADDITIVE Latency
POSTED CAS ADDITIVE latency (AL) is supported to make the command and data bus
efficient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL,
as shown in Figure 52 (page 136). MR1[4, 3] enable the user to program the DDR3
SDRAM with AL = 0, CL - 1, or CL - 2.
With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is
ACTIVATE to READ or WRITE + AL ≥ tRCD (MIN) must be satisfied. Assuming tRCD
(MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1
tCK. The READ or WRITE command is held for the time of the AL before it is released
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 2 (MR2)
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see (page 0 )). Examples of READ and WRITE
latencies are shown in Figure 52 (page 136) and (page 0 ).
Figure 52: READ Latency (AL = 5, CL = 6)
BC4
T0
T1
T2
T6
T11
T12
T13
T14
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
tRCD
(MIN)
DQS, DQS#
AL = 5
CL = 6
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
RL = AL + CL = 11
Indicates break
in time scale
Transitioning Data
Don’t Care
Mode Register 2 (MR2)
The mode register 2 (MR2) controls additional functions and features not available in
the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT
(RTT(WR)). These functions are controlled via the bits shown in Figure 53. The MR2 is
programmed via the MRS command and will retain the stored information until it is
programmed again or until the device loses power. Reprogramming the MR2 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR2 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation.
Figure 53: Mode Register 2 (MR2) Definition
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 2 (MR2)
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
18 17 16 15 14 13 12 11 10 9 8 7 6
0 01 01 01 01 01 RTT(WR) 01 SRT ASR
Mode register 2 (MR2)
5
01 1
M17 M16
Mode Register
M7 Self Refresh Temperature
4
3
CWL
M5 M4 M3
2 1 0
01 01 01
CAS Write Latency (CWL)
5 CK (tCK ≥ 2.5ns)
6 CK (2.5ns > tCK ≥ 1.875ns)
0
0
Mode register set 0 (MR0)
0 Normal (0°C to 85°C)
0
0
0
0
1
Mode register set 1 (MR1)
1 Extended (≥85°C to 95°C)
0
0
1
1
0
Mode register set 2 (MR2)
0
1
0
7 CK (1.875ns > tCK ≥ 1.5ns)
1
1
Mode register set 3 (MR3)
0
1
1
1
0
0
8 CK (1.5ns > tCK ≥ 1.25ns)
9 CK (1.25ns > tCK ≥ 1.071ns)
1
0
1 10 CK (1.071ns > t CK ≥ 0.938ns)
1
1
0
Reserved
1
1
1
Reserved
Dynamic ODT
(R TT(WR) )
M10 M9
RTT(WR) disabled
0
0
0
1
RZQ/4 (60 [NOM])
1
0
RZQ/2 (120 [NOM])
1
1
M6
Auto Self Refresh
(Optional)
0
Disabled: Manual
1 Enabled: Automatic
Reserved
1. MR2[18, 15:11, and 8] are reserved for future use and must all be programmed to 0.
Note:
CAS Write Latency (CWL)
CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the
internal write to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 53 (page 136)). The overall WRITE latency (WL) is equal to CWL + AL (Figure 51 (page 133)).
Figure 54: CAS Write Latency
T0
T1
ACTIVE n
WRITE n
T2
T6
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
tRCD
(MIN)
DQS, DQS#
AL = 5
CWL = 6
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL = AL + CWL = 11
Indicates break
in time scale
Transitioning Data
Don’t Care
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1x refresh rate). In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a T C of 85°C while in self refresh unless the user enables
the SRT feature listed below when the T C is between 85°C and 95°C.
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 2 (MR2)
Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to
2x when the case temperature exceeds 85°C. This enables the user to operate the DRAM
beyond the standard 85°C limit up to the optional extended temperature range of 95°C
while in self refresh mode.
The standard self refresh current test specifies test conditions to normal case temperature (85°C) only, meaning if ASR is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 173)).
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1x refresh rate). In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a T C of 85°C while in self refresh mode unless the user enables ASR.
When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regardless of the case temperature. This enables the user to operate the DRAM beyond the
standard 85°C limit up to the optional extended temperature range of 95°C while in self
refresh mode. The standard self refresh current test specifies test conditions to normal
case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 173)).
SRT vs. ASR
If the normal case temperature limit of 85°C is not exceeded, then neither SRT nor ASR
is required, and both can be disabled throughout operation. However, if the extended
temperature option of 95°C is needed, the user is required to provide a 2x refresh rate
during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is
performed at the 2x rate.
SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is
performed at the 2x refresh rate regardless of the case temperature.
ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between 1x to 2x over the supported temperature range. One other disadvantage with ASR
is the DRAM cannot always switch from a 1x to a 2x refresh rate at an exact case temperature of 85°C. Although the DRAM will support data integrity when it switches from a 1x
to a 2x refresh rate, it may switch at a lower temperature than 85°C.
Since only one mode is necessary, SRT and ASR cannot be enabled at the same time.
DYNAMIC ODT
The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled
when a value is selected. This new DDR3 SDRAM feature enables the ODT termination
value to change without issuing an MRS command, essentially changing the ODT termination on-the-fly.
With dynamic ODT (RTT(WR)) enabled, the DRAM switches from normal ODT (RTT,nom)
to dynamic ODT (RTT(WR)) when beginning a WRITE burst and subsequently switches
back to ODT (RTT,nom) at the completion of the WRITE burst. If R TT,nom is disabled, the
RTT,nom value will be High-Z. Special timing parameters must be adhered to when dy-
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
namic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,
and tADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (R TT,nom) is disabled, dynamic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent of
one other. Dynamic ODT is not available during write leveling mode, regardless of the
state of ODT (RTT,nom). For details on dynamic ODT operation, refer to Dynamic ODT
(page 186).
Mode Register 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 55 (page 139). The MR3 is programmed via the LOAD MODE command and retains the stored information until it is
programmed again or until the device loses power. Reprogramming the MR3 register
will not alter the contents of the memory array, provided it is performed correctly. The
MR3 register must be loaded when all banks are idle and no data bursts are in progress,
and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation.
Figure 55: Mode Register 3 (MR3) Definition
BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8
18 17 16
1 1
01
A4 A3
A2
A1 A0
15 14 13 12 11 10 9
8 7
6
5
4
3
2
1 0
01 01 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF
0
0
Mode register set (MR0)
0
MPR Enable
Normal DRAM operations2
0
1
Mode register set 1 (MR1)
1
Dataflow from MPR
1
0
Mode register set 2 (MR2)
1
1
Mode register set 3 (MR3)
M17 M16
Notes:
A7 A6 A5
M2
Mode Register
M1 M0
Address bus
Mode register 3 (MR3)
0
0
MPR READ Function
Predefined pattern3
0
1
Reserved
1
0
Reserved
1
1
Reserved
1. MR3[18 and 15:3] are reserved for future use and must all be programmed to 0.
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 56 (page 140).
If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a predefined read pattern for system calibration is selected.
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged,
and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands
are redirected to the multipurpose register. The resulting operation when either a READ
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see
Table 74 (page 141)). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
Power-down mode, self refresh, and any other nonREAD/RDAP commands are not allowed during MPR enable mode. The RESET function is supported during MPR enable
mode.
Figure 56: Multipurpose Register (MPR) Block Diagram
Memory core
MR3[2] = 0 (MPR off)
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
DQ, DM, DQS, DQS#
Notes:
1. A predefined data pattern can be read out of the MPR with an external READ command.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When
the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.
Table 73: MPR Functional Description of MR3 Bits
MR3[2]
MR3[1:0]
MPR
MPR READ Function
Function
0
“Don’t Care”
Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
1
A[1:0]
(see Table 74 (page 141))
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and
2
MPR Functional Description
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining
DQs driven LOW, or for all DQs to output the MPR data . The MPR readout supports
fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ
latencies and AC timings applicable, provided the DLL is locked as required.
MPR addressing for a valid MPR read is as follows:
• A[1:0] must be set to 00 as the burst order is fixed per nibble
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4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
• A2 selects the burst order:
– BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7
• For burst chop 4 cases, the burst order is switched on the nibble base along with the
following:
•
•
•
•
•
•
•
– A2 = 0; burst order = 0, 1, 2, 3
– A2 = 1; burst order = 4, 5, 6, 7
Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is
assigned to MSB
A[9:3] are a “Don’t Care”
A10 is a “Don’t Care”
A11 is a “Don’t Care”
A12: Selects burst chop mode on-the-fly, if enabled within MR0
A13 is a “Don’t Care”
BA[2:0] are a “Don’t Care”
MPR Register Address Definitions and Bursting Order
The MPR currently supports a single data format. This data format is a predefined read
pattern for system calibration. The predefined pattern is always a repeating 0–1 bit pattern.
Examples of the different types of predefined READ pattern bursts are shown in the following figures.
Table 74: MPR Readouts and Burst Order Bit Mapping
MR3[2]
MR3[1:0]
Function
1
00
READ predefined pattern
for system calibration
1
1
1
01
RFU
10
RFU
11
RFU
Note:
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Burst
Length
Read
A[2:0]
BL8
000
Burst order: 0, 1, 2, 3, 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1
BC4
000
Burst order: 0, 1, 2, 3
Predefined pattern: 0, 1, 0, 1
BC4
100
Burst order: 4, 5, 6, 7
Predefined pattern: 0, 1, 0, 1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Burst Order and Data Pattern
1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent.
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DQ
DQS, DQS#
tMOD
Notes:
0
0
A12/BC#
A[15:13]
0
A11
0
00
A[9:3]
1
1
A2
A10/AP
0
A[1:0]
tRP
MRS
Ta0
3
PREA
T0
Bank address
Command
CK#
CK
NOP
Tc4
NOP
Tc5
NOP
Tc6
tMPRR
MRS
Tc7
1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
0
0
Valid 1
Valid
0
0
00
Valid
Valid
Valid
0
NOP
Tc3
02
NOP
Tc2
Valid
NOP
Tc1
02
RL
NOP
Tc0
3
NOP
Tb1
Valid
READ1
Tb0
Figure 57: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout
tMOD
Indicates break
in time scale
NOP
Tc8
NOP
Tc9
Don’t Care
Valid
Tc10
4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
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DQ
tMOD
Notes:
0
A[15:13]
DQS, DQS#
0
A12/BC#
0
A10/AP
0
00
A[9:3]
A11
1
A2
1
0
MRS
A[1:0]
tRP
Ta
3
PREA
T0
Bank address
Command
CK#
CK
RL
NOP
Tc6
NOP
Tc7
NOP
Tc8
tMPRR
Indicates break
in time scale
NOP
Tc9
0
00
0
Valid
3
MRS
Tc10
RL
Valid
1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
Valid
0
0
NOP
Tc5
Valid 1
NOP
Tc4
Valid
NOP
Tc3
0
NOP
Tc2
Valid
Valid
NOP
Tc1
Valid
Valid
Valid
12
02
Valid
02
02
READ1
Valid
tCCD
Tc0
Valid
READ1
Tb
Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout
Valid
Don’t Care
tMOD
Td
4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
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DQ
tMOD
Notes:
0
A[15:13]
DQS, DQS#
0
A12/BC#
0
A10/AP
0
00
A[9:3]
A11
1
A2
1
0
A[1:0]
tRF
MRS
Ta
3
PREA
T0
Bank address
Command
CK#
CK
14
03
1.
2.
3.
4.
NOP
Tc1
NOP
Tc2
RL
NOP
Tc3
READ with BC4 either by MRS or OTF.
Memory controller must drive 0 on A[1:0].
A2 = 0 selects lower 4 nibble bits 0 . . . 3.
A2 = 1 selects upper 4 nibble bits 4 . . . 7.
RL
Valid
Valid 1
Valid 1
Valid
Valid
Valid
Valid
Valid
Valid
02
02
Valid
Valid
tCCD
READ1
Tc0
Valid
READ1
Tb
NOP
Tc4
NOP
Tc5
NOP
Tc6
Figure 59: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble
NOP
Tc7
tMPRR
0
0
0
0
00
0
Valid
3
MRS
Tc8
tMOD
NOP
Tc10
Indicates break
in time scale
NOP
Tc9
Don’t Care
Valid
Td
4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
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DQ
tMOD
Notes:
0
A[15:13]
DQS, DQS#
0
A12/BC#
0
A10/AP
0
00
A[9:3]
A11
1
A2
1
0
A[1:0]
tRF
MRS
Ta
3
PREA
T0
Bank address
Command
CK#
CK
04
13
1.
2.
3.
4.
NOP
Tc1
NOP
Tc2
RL
NOP
Tc3
READ with BC4 either by MRS or OTF.
Memory controller must drive 0 on A[1:0].
A2 = 1 selects upper 4 nibble bits 4 . . . 7.
A2 = 0 selects lower 4 nibble bits 0 . . . 3.
RL
Valid
Valid 1
Valid 1
Valid
Valid
Valid
Valid
Valid
Valid
02
02
Valid
Valid
tCCD
READ1
Tc0
Valid
READ1
Tb
NOP
Tc4
NOP
Tc5
NOP
Tc6
Figure 60: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble
NOP
Tc7
tMPRR
0
0
0
0
00
0
Valid
3
MRS
Tc8
tMOD
Indicates break
in time scale
NOP
Tc9
NOP
Tc10
Don’t Care
Valid
Td
4Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
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4Gb: x4, x8, x16 DDR3L SDRAM
MODE REGISTER SET (MRS) Command
MPR Read Predefined Pattern
The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The
following is an example of using the read out predetermined read calibration pattern.
The example is to perform multiple reads from the multipurpose register to do system
level read timing calibration based on the predetermined and standardized pattern.
The following protocol outlines the steps used to perform the read calibration:
1. Precharge all banks
2. After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subsequent reads and loads the predefined pattern into the MPR. As soon as tMRD
and tMOD are satisfied, the MPR is available
3. Data WRITE operations are not allowed until the MPR returns to the normal
DRAM state
4. Issue a read with burst order information (all other address pins are “Don’t Care”):
5.
6.
7.
8.
• A[1:0] = 00 (data burst order is fixed starting at nibble)
• A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
• A12 = 1 (use BL8)
After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern
(0, 1, 0, 1, 0, 1, 0, 1)
The memory controller repeats the calibration reads until read data capture at
memory controller is optimized
After the last MPR READ burst and after tMPRR has been satisfied, issue MRS,
MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subsequent read and write accesses will be regular reads and writes from/to the DRAM
array
When tMRD and tMOD are satisfied from the last MRS, the regular DRAM commands (such as activate a memory bank for regular read or write access) are permitted
MODE REGISTER SET (MRS) Command
The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which
mode register is programmed:
•
•
•
•
BA2 = 0, BA1 = 0, BA0 = 0 for MR0
BA2 = 0, BA1 = 0, BA0 = 1 for MR1
BA2 = 0, BA1 = 1, BA0 = 0 for MR2
BA2 = 0, BA1 = 1, BA0 = 1 for MR3
The MRS command can only be issued (or re-issued) when all banks are idle and in the
precharged state (tRP is satisfied and no data bursts are in progress). The controller
must wait the specified time tMRD before initiating a subsequent operation such as an
ACTIVATE command (see Figure 47 (page 128)). There is also a restriction after issuing
an MRS command with regard to when the updated functions become available. This
parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Figure 47 (page 128) and Figure 48 (page 129). Violating either of these requirements will
result in unspecified operation.
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4Gb: x4, x8, x16 DDR3L SDRAM
ZQ CALIBRATION Operation
ZQ CALIBRATION Operation
The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)
and ODT values (RTT) over process, voltage, and temperature, provided a dedicated
240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to V SSQ.
DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initialization
and self refresh exit, and a relatively shorter time to perform periodic calibrations.
DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example
of ZQ calibration timing is shown below.
All banks must be precharged and tRP must be met before ZQCL or ZQCS commands
can be issued to the DRAM. No other activities (other than issuing another ZQCL or
ZQCS command) can be performed on the DRAM channel by the controller for the duration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM should disable the
ZQ ball’s current consumption path to reduce power.
ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.
Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.
In dual-rank systems that share the ZQ resistor between devices, the controller must not
enable overlap of tZQinit, tZQoper, or tZQCS between ranks.
Figure 61: ZQ CALIBRATION Timing (ZQCL and ZQCS)
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
NOP
NOP
NOP
Valid
Valid
ZQCS
NOP
NOP
NOP
Valid
Address
Valid
Valid
Valid
A10
Valid
Valid
Valid
CK#
CK
Command
CKE
1
Valid
Valid
1
Valid
ODT
2
Valid
Valid
2
Valid
DQ
3
Activities
3
High-Z
tZQinit
or tZQoper
High-Z
tZQCS
Indicates break
in time scale
Notes:
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Activities
Don’t Care
1. CKE must be continuously registered HIGH during the calibration procedure.
2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure.
3. All devices connected to the DQ bus should be High-Z during calibration.
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4Gb: x4, x8, x16 DDR3L SDRAM
ACTIVATE Operation
ACTIVATE Operation
Before any READ or WRITE commands can be issued to a bank within the DRAM, a row
in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row, subject to the tRCD specification. However, if the additive latency
is programmed correctly, a READ or WRITE command may be issued prior to tRCD
(MIN). In this operation, the DRAM enables a READ or WRITE command to be issued
after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the requirement that (ACTIVATE-to-READ/WRITE) + AL ≥ tRCD (MIN) (see Posted CAS Additive
Latency). tRCD (MIN) should be divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after the ACTIVATE command on
which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles.
When at least one bank is open, any READ-to-READ command delay or WRITE-toWRITE command delay is restricted to tCCD (MIN).
A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands to the same bank is defined by tRC.
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVATE commands to different banks is defined by tRRD. No more than four bank ACTIVATE commands may be issued in a given
tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of banks already opened or closed.
Figure 62: Example: Meeting tRRD (MIN) and tRCD (MIN)
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
Command
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Address
Row
Row
Col
BA[2:0]
Bank x
Bank y
Bank y
CK#
CK
tRRD
tRCD
Indicates break
in time scale
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Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
ACTIVATE Operation
Figure 63: Example: tFAW
CK#
T0
T1
T4
T5
T8
T9
T10
T11
T19
T20
ACT
NOP
ACT
NOP
ACT
NOP
ACT
NOP
NOP
ACT
CK
Command
Address
BA[2:0]
Row
Row
Row
Row
Row
Bank a
Bank b
Bank c
Bank d
Bank ey
tRRD
tFAW
Indicates break
in time scale
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Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
READ Operation
READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is disabled,
the row will be left open after the completion of the burst.
During READ bursts, the valid data-out element from the starting column address is
available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element is
valid nominally at the next positive or negative clock edge (that is, at the next crossing
of CK and CK#). Figure 64 shows an example of RL based on a CL setting of 8 and an AL
setting of 0.
Figure 64: READ Latency
T0
T7
T8
T9
T10
T11
T12
T12
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
Address
Bank a,
Col n
CL = 8, AL = 0
DQS, DQS#
DO
n
DQ
Indicates break
in time scale
Notes:
Transitioning Data
Don’t Care
1. DO n = data-out from column n.
2. Subsequent elements of data-out appear in the programmed order following DO n.
DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on
DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW state
on DQS and the HIGH state on DQS#, coincident with the last data-out element, is
known as the READ postamble (tRPST). Upon completion of a burst, assuming no other
commands have been initiated, the DQ goes High-Z. A detailed explanation of tDQSQ
(valid data-out skew), tQH (data-out window hold), and the valid data window are depicted in Figure 75 (page 158). A detailed explanation of tDQSCK (DQS transition skew
to CK) is also depicted in Figure 75 (page 158).
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 65
(page 152). If BC4 is enabled, tCCD must still be met, which will cause a gap in the data
output, as shown in Figure 66 (page 152). Nonconsecutive READ data is reflected in
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READ Operation
Figure 67 (page 153). DDR3 SDRAM does not allow interrupting or truncating any
READ burst.
Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst for BL8 is shown in Figure 68 (page 153) (BC4 is shown in Figure 69 (page 154)). To ensure the READ data is
completed before the WRITE data is on the bus, the minimum READ-to-WRITE timing
is RL + tCCD - WL + 2 tCK.
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spacing to the same bank is four clocks and must also satisfy a minimum analog time from
the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL
cycles later than the READ command. Examples for BL8 are shown in Figure 70
(page 154) and BC4 in Figure 71 (page 155). Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be determined by the last PRECHARGE command issued to the bank.
If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DRAM starts an auto precharge operation on the rising edge, which
is AL + tRTP cycles after the READ command. DRAM support a tRAS lockout feature (see
Figure 73 (page 155)). If tRAS (MIN) is not satisfied at the edge, the starting point of the
auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is
not satisfied at the edge, the starting point of the auto precharge operation is delayed
until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP, tRP
starts at the point at which the internal precharge happens (not at the next rising clock
edge after this event). The time from READ with auto precharge to the next ACTIVATE
command to the same bank is AL + (tRTP + tRP)*, where * means rounded up to the next
integer. In any event, internal precharge does not start earlier than four clocks after the
last 8n-bit prefetch.
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Bank,
Col n
Address2
NOP
T1
Notes:
RL = 5
NOP
T3
Bank,
Col b
READ
T4
152
Bank,
Col n
Address2
DQ3
DQS, DQS#
READ
T0
Command1
CK
CK#
NOP
T1
Notes:
tCCD
NOP
T2
tRPRE
NOP
T5
DO
n
DO
n+1
NOP
T6
DO
n+3
RL = 5
DO
n+2
DO
n+4
NOP
T7
DO
n+5
NOP
T8
DO
n+6
DO
n+7
NOP
T9
DO
b
DO
b+1
NOP
T10
DO
b+2
DO
b+3
NOP
T11
DO
b+4
DO
b+5
NOP
T12
DO
b+7
Transitioning Data
DO
b+6
tRPST
NOP
T13
Don’t Care
NOP
T14
Bank,
Col b
READ
T4
tRPRE
NOP
DO
n
DO
n+1
NOP
T6
RL = 5
DO
n+2
DO
n+3
tRPST
NOP
T7
NOP
T8
tRPRE
NOP
T9
DO
b
DO
b+1
NOP
T10
DO
b+2
DO
b+3
tRPST
NOP
T11
NOP
T13
Transitioning Data
NOP
T12
Don’t Care
NOP
T14
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BC4, RL = 5 (CL = 5, AL = 0).
RL = 5
NOP
T3
T5
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0
and T4.
3. DO n (or b) = data-out from column n (or column b).
4. BL8, RL = 5 (CL = 5, AL = 0).
tCCD
NOP
T2
Figure 66: Consecutive READ Bursts (BC4)
DQ3
DQS, DQS#
READ
T0
Command1
CK
CK#
Figure 65: Consecutive READ Bursts (BL8)
4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
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NOP
T1
Notes:
NOP
T2
1.
2.
3.
4.
CL = 8
NOP
T4
153
DQ3
DQS, DQS#
Address2
Command1
CK
CK#
Bank,
Col n
READ
T0
NOP
T2
NOP
T3
NOP
T4
NOP
T5
Notes:
NOP
T6
NOP
T7
NOP
T8
DO
n
CL = 8
NOP
T9
NOP
T10
NOP
T11
NOP
T12
NOP
T13
DO
b
NOP
T14
DO
n
DO
n+1
DO
n+2
Bank,
Col b
WRITE
T6
DO
n+3
DO
n+4
NOP
T7
DO
n+5
NOP
T9
DO
n+7
tRPST
WL = 5
DO
n+6
NOP
T8
NOP
T10
tWPRE
DI
n
NOP
T11
DI
n+1
tBL
DI
DI
n+2 n+3
NOP
T12
DI
n+5
NOP
T16
DI
n+6
NOP
Don’t Care
DI
n+7
tWPST
tWR
tWR
NOP
T15
Transitioning Data
T14
Transitioning Data
DI
n+4
= 4 clocks
NOP
T13
NOP
T15
Don’t Care
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at
T0, and the WRITE command at T6.
3. DO n = data-out from column, DI b = data-in for column b.
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
RL = 5
tRPRE
READ-to-WRITE command delay = RL + tCCD + 2tCK - WL
NOP
T1
Bank a,
Col b
READ
T5
AL = 0, RL = 8.
DO n (or b) = data-out from column n (or column b).
Seven subsequent elements of data-out appear in the programmed order following DO n.
Seven subsequent elements of data-out appear in the programmed order following DO b.
NOP
T3
Figure 68: READ (BL8) to WRITE (BL8)
DQ
DQS, DQS#
READ
Bank a,
Col n
Address
T0
Command
CK
CK#
Figure 67: Nonconsecutive READ Bursts
4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
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154
NOP
T1
NOP
T2
NOP
T3
WRITE
Bank,
Col n
DQ
DQS, DQS#
READ
Bank a,
Col n
Address
T0
Command
CK
CK#
T4
Notes:
NOP
T1
tRTP
tRAS
NOP
T2
NOP
T5
DO
n
DO
n+ 1
NOP
T7
DO
n+3
tRPST
WL = 5
DO
n+ 2
NOP
T6
NOP
T8
tWPRE
DI
n
NOP
T9
DI
n+ 1
DI
n+2
NOP
T10
= 4 clocks
DI
n+ 3
tWPST
tBL
NOP
T11
NOP
T12
tWR
tWTR
NOP
T14
Transitioning Data
NOP
T13
Don’t Care
NOP
T15
NOP
T3
NOP
T4
Bank a,
(or all)
PRE
T5
NOP
T6
NOP
T7
NOP
T8
DO
n
DO
n+1
tRP
DO
n+2
NOP
T9
DO
n+3
DO
n+4
NOP
T10
DO
n+5
DO
n+6
NOP
T11
DO
n+7
NOP
T12
Bank a,
Row b
ACT
T13
NOP
T14
NOP
T15
Transitioning Data
NOP
T16
Don’t Care
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at
T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
RL = 5
tRPRE
Bank,
Col b
READ-to-WRITE command delay = RL + tCCD/2 + 2tCK - WL
READ
T0
Figure 70: READ to PRECHARGE (BL8)
DQ3
DQS, DQS#
Address2
Command1
CK
CK#
Figure 69: READ (BC4) to WRITE (BC4) OTF
4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
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Address
NOP
T1
tRTP
tRAS
NOP
T2
NOP
T3
NOP
T4
Bank a,
(or all)
PRE
T5
NOP
T6
Address
155
NOP
T1
NOP
T2
AL = 5
NOP
T3
NOP
T4
tRAS
NOP
T5
NOP
T6
Address
DQ
DQS, DQS#
READ
Bank a,
Col n
T0
Command
CK
CK#
NOP
T1
AL = 4
NOP
T2
NOP
T3
NOP
T4
NOP
T5
tRTP
tRAS
(MIN)
NOP
T6
T7
NOP
Figure 73: READ with Auto Precharge (AL = 4, CL = 6)
DQ
DQS, DQS#
READ
Bank a,
Col n
T0
Command
CK
CK#
Figure 72: READ to PRECHARGE (AL = 5, CL = 6)
DQ
DQS, DQS#
READ
Bank a,
Col n
T0
Command
CK
CK#
Figure 71: READ to PRECHARGE (BC4)
(MIN)
DO
n
CL = 6
NOP
T7
tRTP
NOP
T7
NOP
T8
T8
T10
NOP
T9
Bank a,
(or all)
PRE
T9
NOP
DO
n+3
CL = 6
DO
n+2
NOP
T8
NOP
DO
n+1
tRP
NOP
T9
NOP
T10
NOP
T10
NOP
T11
DO
n
T11
NOP
DO
n
DO
n+2
T11
NOP
DO
n+1
NOP
T12
DO
n+3
DO
n+1
Bank a,
Row b
ACT
T13
DO
n+2
DO
n+3
NOP
T13
NOP
T13
Indicates break
in time scale
NOP
T12
tRP
NOP
T12
NOP
T14
tRP
NOP
Transitioning Data
NOP
T14
Transitioning Data
NOP
T16
Transitioning Data
NOP
T15
Don’t Care
Bank a,
Row b
ACT
Ta0
Don’t Care
Bank a,
Row b
ACT
T15
Don’t Care
NOP
T17
4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
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4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
DQS to DQ output timing is shown in Figure 74 (page 157). The DQ transitions between
valid data outputs must be within tDQSQ of the crossing point of DQS, DQS#. DQS must
also maintain a minimum HIGH and LOW time of tQSH and tQSL. Prior to the READ
preamble, the DQ balls will either be floating or terminated, depending on the status of
the ODT signal.
Figure 75 (page 158) shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±tDQSCK of the clock crossing point. The data
out has no timing relationship to CK, only to DQS, as shown in Figure 75 (page 158).
Figure 75 (page 158) also shows the READ preamble and postamble. Typically, both
DQS and DQS# are High-Z to save power (VDDQ). Prior to data output from the DRAM,
DQS is driven LOW and DQS# is HIGH for tRPRE. This is known as the READ preamble.
The READ postamble, tRPST, is one half clock from the last DQS, DQS# transition. During the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the
DQ is disabled or continues terminating, depending on the state of the ODT signal. Figure 78 (page 160) demonstrates how to measure tRPST.
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All DQ collectively
DQ3 (first data no longer valid)
DQ3 (last data valid)
Notes:
Bank,
Col n
Address2
DQS, DQS#
READ
T0
Command1
CK
CK#
NOP
T2
RL = AL + CL
NOP
T3
tRPRE
(MAX)
tLZDQ (MIN)
tDQSQ
NOP
T4
NOP
T6
tDQSQ
(MAX)
NOP
T7
NOP
T8
tRPST
NOP
T9
DO
n+1
DO
n+2
Data valid
DO
n+3
DO
n+4
DO
n+5
DO
n+6
DO
n+7
tQH
DO
DO
DO
DO
DO
DO
DO
n+1
n+2
n+3
n+4
n+5
n+6
n+7
DO
DO
DO
DO
DO
DO
DO
n+3
n+1
n+2
n+4
n+5
n+6
n+7
Data valid
DO
n
DO
n
tQH
DO
n
NOP
T5
tHZDQ
Don’t Care
(MAX)
NOP
T10
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at
T0.
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to VDDQ/2 and DLL on and locked.
6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within
a burst.
NOP
T1
Figure 74: Data Output Timing – tDQSQ and Data Valid Window
4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
157
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4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
tHZ
and tLZ transitions occur in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the device output is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Figure 76 (page 159) shows a method of calculating the point when the device is no longer
driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ, by measuring the signal
at two different voltages. The actual voltage measurement points are not critical as long
as the calculation is consistent. The parameters tLZDQS, tLZDQ, tHZDQS, and tHZDQ
are defined as single-ended.
Figure 75: Data Strobe Timing – READs
RL measured
to this point
T0
T1
T2
T3
T4
T5
T6
CK
CK#
tDQSCK
tLZDQS
tDQSCK
(MIN)
(MIN)
tQSH
tDQSCK
(MIN)
tQSL
tQSH
tDQSCK
(MIN)
tHZDQS
(MIN)
(MIN)
tQSL
DQS, DQS#
early strobe
tRPST
tRPRE
Bit 0
tLZDQS
Bit 1
tDQSCK
(MAX)
Bit 2
Bit 3
tDQSCK
(MAX)
Bit 4
Bit 5
tDQSCK
(MAX)
Bit 6
Bit 7
tDQSCK
(MAX)
tHZDQS
(MAX)
(MAX)
tRPST
DQS, DQS#
late strobe
tRPRE
tQSH
Bit 0
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tQSL
Bit 1
tQSH
Bit 2
158
tQSL
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
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4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
Figure 76: Method for Calculating tLZ and tHZ
VOH - xmV
VTT + 2xmV
VOH - 2xmV
VTT + xmV
tLZDQS, tLZDQ
tHZDQS, tHZDQ
T2
T1
tHZDQS, tHZDQ
VOL + 2xmV
VTT - xmV
VOL + xmV
VTT - 2xmV
T1
T2
tLZDQS, tLZDQ
end point = 2 × T1 - T2
begin point = 2 × T1 - T2
1. Within a burst, the rising strobe edge is not necessarily fixed at tDQSCK (MIN) or tDQSCK
(MAX). Instead, the rising strobe edge can vary between tDQSCK (MIN) and tDQSCK
(MAX).
2. The DQS HIGH pulse width is defined by tQSH, and the DQS LOW pulse width is defined
by tQSL. Likewise, tLZDQS (MIN) and tHZDQS (MIN) are not tied to tDQSCK (MIN) (early
strobe case), and tLZDQS (MAX) and tHZDQS (MAX) are not tied to tDQSCK (MAX) (late
strobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by tRPRE (MIN). The minimum pulse width of the READ postamble is defined by tRPST (MIN).
Notes:
Figure 77: tRPRE Timing
CK
VTT
CK#
tA
tB
DQS
VTT
Single-ended signal provided
as background information
tC
tD
VTT
DQS#
Single-ended signal provided
as background information
T1
begins
tRPRE
DQS - DQS#
tRPRE
T2
ends
Resulting differential
signal relevant for
tRPRE specification
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0V
tRPRE
159
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4Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
Figure 78: tRPST Timing
CK
VTT
CK#
tA
DQS
Single-ended signal, provided
as background information
t
VTT
B
tC
tD
DQS#
VTT
Single-ended signal, provided
as background information
tRPST
DQS - DQS#
Resulting differential
signal relevant for
tRPST specification
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T1
begins
tRPST
0V
T2
ends
tRPST
160
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4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
WRITE Operation
WRITE bursts are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or
disabled for that access. If auto precharge is selected, the row being accessed is precharged at the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in Figure 81 (page 163) through Figure 89 (page 168), auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered on a rising edge of
DQS following the WRITE latency (WL) clocks later and subsequent data elements will
be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of
posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior
to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,
DQS#) and specified as the WRITE preamble shown in Figure 81 (page 163). The half
cycle on DQS following the last data-in element is known as the WRITE postamble.
The time between the WRITE command and the first valid edge of DQS is WL clocks
±tDQSS. Figure 82 (page 164) through Figure 89 (page 168) show the nominal case
where tDQSS = 0ns; however, Figure 81 (page 163) includes tDQSS (MIN) and tDQSS
(MAX) cases.
Data may be masked from completing a WRITE using data mask. The data mask occurs
on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH, that bit of data is masked.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will remain High-Z, and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide a continuous flow of input data. The new WRITE command can be tCCD clocks
following the previous WRITE command. The first data element from the new burst is
applied after the last element of a completed burst. Figure 82 (page 164) and Figure 83
(page 164) show concatenated bursts. An example of nonconsecutive WRITEs is shown
in Figure 84 (page 165).
Data for any WRITE burst may be followed by a subsequent READ command after tWTR
has been met (see Figure 85 (page 165), Figure 86 (page 166), and Figure 87
(page 167)).
Data for any WRITE burst may be followed by a subsequent PRECHARGE command,
providing tWR has been met, as shown in Figure 88 (page 168) and Figure 89
(page 168).
Both tWTR and tWR starting time may vary, depending on the mode register settings
(fixed BC4, BL8 versus OTF).
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4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
Figure 79: tWPRE Timing
CK
VTT
CK#
T1
begins
tWPRE
DQS - DQS#
0V
tWPRE
T2
Resulting differential
signal relevant for
tWPRE specification
tWPRE
ends
Figure 80: tWPST Timing
CK
VTT
CK#
tWPST
DQS - DQS#
Resulting differential
signal relevant for
tWPST specification
0V
T1
begins
tWPST
T2
ends
tWPST
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4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
Figure 81: WRITE Burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command1
WL = AL + CWL
Address2
Bank,
Col n
tDQSS
tWPRE
(MIN)
tDQSS tDSH
tDSH
tDSH
tDSH tWPST
DQS, DQS#
tDQSH
tDQSL
tDQSH
DI
n
DQ3
tDQSS
DI
n+1
tWPRE
(NOM)
tDQSL
tDQSH
DI
n+2
tDQSL
DI
n+3
tDSH
tDQSH
DI
n+4
tDQSL
DI
n+5
tDSH
tDQSH
DI
n+6
tDQSL
DI
n+7
tDSH
tDSH
tWPST
tDQSH
tDQSL
DQS, DQS#
tDQSH
tDQSL
tDQSH
tDSS
tDQSH
tDSS
DI
n
DQ3
tDQSL
DI
n+1
tDQSL
tDQSH
tDQSL
tDSS
DI
n+2
DI
n+3
tDSS
DI
n+4
DI
n+5
tDSS
DI
n+6
DI
n+7
tDQSS
tDQSS
tWPRE
(MAX)
tWPST
DQS, DQS#
tDQSH
tDQSL
tDQSH
tDSS
DI
n
DQ3
tDQSL
tDQSH
tDSS
DI
n+1
tDQSL
tDQSH
tDSS
DI
n+2
DI
n+3
tDQSL
tDQSH
tDSS
DI
n+4
DI
n+5
tDQSL
tDSS
DI
n+6
DI
n+7
Transitioning Data
Notes:
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Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
the WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. tDQSS must be met at each rising clock edge.
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
163
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Valid
Address2
NOP
T1
Notes:
tCCD
NOP
T2
Valid
WRITE
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
164
Valid
Address2
DQ3
DQS, DQS#
WRITE
T0
Command1
CK
CK#
NOP
T1
Notes:
tCCD
1.
2.
3.
4.
5.
NOP
T2
WL = 5
DI
n+3
DI
n+4
NOP
T7
DI
n+5
DI
n+6
NOP
T8
DI
n+7
DI
b
NOP
T9
DI
b+1
DI
b+2
NOP
T10
tBL
DI
b+3
DI
b+4
= 4 clocks
NOP
T11
DI
b+5
DI
b+6
NOP
T12
Transitioning Data
DI
b+7
tWPST
NOP
T13
NOP
Don’t Care
tWTR
tWR
T14
Valid
WRITE
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
WL = 5
DI
n+3
tWPST
NOP
NOP
T8
tWPRE
DI
b
NOP
T9
DI
b+1
DI
b+2
NOP
T10
DI
b+3
tWPST
tBL
= 4 clocks
NOP
T11
NOP
T12
Transitioning Data
NOP
T13
NOP commands are shown for ease of illustration; other commands may be valid at these times.
BC4, WL = 5 (AL = 0, CWL = 5).
DI n (or b) = data-in for column n (or column b).
The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4.
If set via MRS (fixed) tWR and tWTR would start T11 (2 cycles earlier).
WL = 5
NOP
T3
T7
NOP
Don’t Care
tWTR
tWR
T14
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at
T0 and T4.
3. DI n (or b) = data-in for column n (or column b).
4. BL8, WL = 5 (AL = 0, CWL = 5).
WL = 5
NOP
T3
Figure 83: Consecutive WRITE (BC4) to WRITE (BC4) via OTF
DQ3
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Figure 82: Consecutive WRITE (BL8) to WRITE (BL8)
4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
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Valid
Address
NOP
T1
Notes:
NOP
T2
NOP
T4
1.
2.
3.
4.
165
DQ4
DQS, DQS#
Address3
Command1
CK
CK#
Valid
WRITE
T0
Notes:
NOP
T1
Valid
WRITE
T5
NOP
T6
DI
n
NOP
T7
DI
n+1
NOP
T9
DI
n+2
DI
n+3
DI
n+4
WL = CWL + AL = 7
NOP
T8
DI
n+5
DI
n+6
NOP
T10
DI
n+7
NOP
T11
DI
b
NOP
T12
DI
b+1
DI
b+2
NOP
T13
DI
b+3
DI
b+4
NOP
T14
DI
b+5
WL = 5
NOP
T3
NOP
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
DI
n+3
DI
n+4
NOP
T7
DI
n+5
DI
n+6
NOP
T8
DI
n+7
tWPST
NOP
T10
Indicates break
in time scale
NOP
T9
NOP
T11
Transitioning Data
tWTR2
DI
b+7
NOP
T16
Transitioning Data
DI
b+6
NOP
T15
Don’t Care
Valid
READ
Ta0
Don't Care
NOP
T17
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T9.
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command
at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
4. DI n = data-in for column n.
5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
T2
T4
DI n (or b) = data-in for column n (or column b).
Seven subsequent elements of data-in are applied in the programmed order following DO n.
Each WRITE command may be to any bank.
Shown for WL = 7 (CWL = 7, AL = 0).
WL = CWL + AL = 7
NOP
T3
Figure 85: WRITE (BL8) to READ (BL8)
DM
DQ
DQS, DQS#
WRITE
T0
Command
CK
CK#
Figure 84: Nonconsecutive WRITE to WRITE
4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
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Valid
Address3
DQ4
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Notes:
NOP
T1
WL = 5
NOP
T3
NOP
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
DI
n+3
tWPST
NOP
T7
Indicates break
in time scale
NOP
T8
Transitioning Data
tWTR2
NOP
T9
Don’t Care
Valid
READ
Ta0
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T7.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at
Ta0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
NOP
T2
Figure 86: WRITE to READ (BC4 Mode Register Setting)
4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
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Valid
Address3
DQ4
DQS, DQS#
WRITE
T0
Command1
CK
CK#
Notes:
NOP
T1
WL = 5
NOP
T3
NOP
T4
tWPRE
DI
n
NOP
T5
DI
n+1
DI
n+2
NOP
T6
NOP
= 4 clocks
DI
n+3
tWPST
tBL
T7
NOP
T8
NOP
T9
Indicates break
in time scale
tWTR2
NOP
T10
Transitioning Data
NOP
T11
RL = 5
Don’t Care
Valid
READ
Tn
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ
command at Tn.
4. DI n = data-in for column n.
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
NOP
T2
Figure 87: WRITE (BC4 OTF) to READ (BC4 OTF)
4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
167
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4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
Figure 88: WRITE (BL8) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Address
Valid
CK#
CK
Valid
tWR
WL = AL + CWL
DQS, DQS#
DI
n
DQ BL8
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
Indicates break
in time scale
Notes:
Transitioning Data
Don’t Care
1. DI n = data-in from column n.
2. Seven subsequent elements of data-in are applied in the programmed order following
DO n.
3. Shown for WL = 7 (AL = 0, CWL = 7).
Figure 89: WRITE (BC4 Mode Register Setting) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
Ta0
Ta1
Command
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
Address
Valid
CK#
CK
Valid
tWR
WL = AL + CWL
DQS, DQS#
DI
n
DQ BC4
DI
n+1
DI
n+2
DI
n+3
Indicates break
in time scale
Notes:
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Transitioning Data
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data is shown at T7. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0.
4. DI n = data-in for column n.
5. BC4 (fixed), WL = 5, RL = 5.
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4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
Figure 90: WRITE (BC4 OTF) to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tn
CK#
CK
Command1
PRE
tWR2
Address3
Bank,
Col n
Valid
tWPRE
tWPST
DQS, DQS#
DI
n
DQ4
DI
n+1
DI
n+2
DI
n+3
WL = 5
Indicates break
in time scale
Notes:
Transitioning Data
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The write recovery time (tWR) is referenced from the rising clock edge at T9. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command
at T0.
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
DQ Input Timing
Figure 81 (page 163) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25tCK of the clock transitions, as limited by tDQSS. All
data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.
The WRITE preamble and postamble are also shown in Figure 81 (page 163). One clock
prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for
a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,
tWPRE. Likewise, DQS must be kept LOW by the controller after the last data is written
to the DRAM during the WRITE postamble, tWPST.
Data setup and hold times are also shown in Figure 81 (page 163). All setup and hold
times are measured from the crossing points of DQS and DQS#. These setup and hold
values pertain to data input and data mask input.
Additionally, the half period of the data input strobe is specified by tDQSH and tDQSL.
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4Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
Figure 91: Data Input Timing
DQS, DQS#
tWPRE
DQ
tDQSH
tWPST
tDQSL
DI
b
DM
tDS
tDH
tDS
tDH
Transitioning Data
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Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
PRECHARGE Operation
PRECHARGE Operation
Input A10 determines whether one bank or all banks are to be precharged and, in the
case where only one bank is to be precharged, inputs BA[2:0] select the bank.
When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a
bank is precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued.
SELF REFRESH Operation
The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled and reset upon exiting SELF REFRESH.
All power supply inputs (including V REFCA and V REFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. V REFDQ may float or not
drive V DDQ/2 while in self refresh mode under certain conditions:
•
•
•
•
VSS < V REFDQ < V DD is maintained.
VREFDQ is valid and stable prior to CKE going back HIGH.
The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid.
All other self refresh mode exit timing requirements are met.
The DRAM must be idle with all banks in the precharge state (tRP is satisfied and no
bursts are in progress) before a self refresh entry command can be issued. ODT must
also be turned off before self refresh entry by registering the ODT ball LOW prior to the
self refresh entry command (see On-Die Termination (ODT) ( for timing requirements).
If RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
After the self refresh entry command is registered, CKE must be held LOW to keep the
DRAM in self refresh mode.
After the DRAM has entered self refresh mode, all external control signals, except CKE
and RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH command internally within the tCKE period when it enters self refresh mode.
The requirements for entering and exiting self refresh mode depend on the state of the
clock during self refresh mode. First and foremost, the clock must be stable (meeting
tCK specifications) when self refresh mode is entered. If the clock remains stable and
the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit
self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR
later than when CKE was registered LOW). Since the clock remains stable in self refresh
mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the
clock is altered during self refresh mode (if it is turned-off or its frequency changes),
then tCKSRE and tCKSRX must be satisfied. When entering self refresh mode, tCKSRE
must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh
mode, tCKSRX must be satisfied prior to registering CKE HIGH.
When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS
is required for the completion of any internal refresh already in progress and must be
satisfied before a valid command not requiring a locked DLL can be issued to the device. tXS is also the earliest time self refresh re-entry may occur. Before a command requiring a locked DLL can be applied, a ZQCL command must be issued, tZQOPER timing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL.
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4Gb: x4, x8, x16 DDR3L SDRAM
SELF REFRESH Operation
Figure 92: Self Refresh Entry/Exit Timing
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Valid
Valid
CK#
CK
tCKSRX1
tCKSRE1
tIS
tIH
tCPDED
tIS
CKE
tCKESR
(MIN)1
tIS
ODT2
Valid
ODTL
RESET#2
Command
NOP
SRE (REF)3
NOP4
SRX (NOP)
NOP5
Address
tRP8
Valid 6
Valid 7
Valid
Valid
tXS6, 9
tXSDLL7, 9
Enter self refresh mode
(synchronous)
Exit self refresh mode
(asynchronous)
Indicates break
in time scale
Notes:
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Don’t Care
1. The clock must be valid and stable, meeting tCK specifications at least tCKSRE after entering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the
clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not
apply; however, tCKESR must be satisfied prior to exiting at SRX.
2. ODT must be disabled and RTT off prior to entering self refresh at state T1. If both
RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming “Don’t Care.”
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6. tXS is required before any commands not requiring a locked DLL.
7. tXSDLL is required before any commands requiring a locked DLL.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
example, all banks must be precharged, tRP must be met, and no data bursts can be in
progress.
9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising
clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that
tISXR is satisfied at Tc1.
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4Gb: x4, x8, x16 DDR3L SDRAM
Extended Temperature Usage
Extended Temperature Usage
Micron’s DDR3 SDRAM support the optional extended case temperature (TC) range of
0°C to 95°C. Thus, the SRT and ASR options must be used at a minimum.
The extended temperature range DRAM must be refreshed externally at 2x (double refresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The external refresh requirement is accomplished by reducing the refresh period from 64ms to
32ms. However, self refresh mode requires either ASR or SRT to support the extended
temperature. Thus, either ASR or SRT must be enabled when T C is above 85°C or self
refresh cannot be used until T C is at or below 85°C. Table 75 summarizes the two extended temperature options and Table 76 summarizes how the two extended temperature
options relate to one another.
Table 75: Self Refresh Temperature and Auto Self Refresh Description
Field
MR2 Bits
Description
Self Refresh Temperature (SRT)
SRT
If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate TOPER during self refresh:
*MR2[7] = 0: Normal operating temperature range (0°C to 85°C)
*MR2[7] = 1: Extended operating temperature range (0°C to 95°C)
If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is
supported
*MR2[7] = 0: SRT is disabled
7
Auto Self Refresh (ASR)
ASR
6
When ASR is enabled, the DRAM automatically provides SELF REFRESH power management functions, (refresh rate for all supported operating temperature values)
* MR2[6] = 1: ASR is enabled (M7 must = 0)
When ASR is not enabled, the SRT bit must be programmed to indicate TOPER during SELF REFRESH
operation
* MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT)
Table 76: Self Refresh Mode Summary
MR2[6] MR2[7]
(ASR)
(SRT) SELF REFRESH Operation
Permitted Operating Temperature
Range for Self Refresh Mode
0
0
Self refresh mode is supported in the normal temperature
range
0
1
Self refresh mode is supported in normal and extended temper- Normal and extended (0°C to 95°C)
ature ranges; When SRT is enabled, it increases self refresh
power consumption
1
0
Self refresh mode is supported in normal and extended temper- Normal and extended (0°C to 95°C)
ature ranges; Self refresh power consumption may be temperature-dependent
1
1
Illegal
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Normal (0°C to 85°C)
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down IDD specifications are not applicable
until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 77). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 93 (page 176) through Figure 102 (page 180).
Table 77: Command to Power-Down Entry Parameters
DRAM Status
Last Command Prior to
CKE LOW1
Parameter (Min)
Parameter Value
Figure
Idle or active
ACTIVATE
tACTPDEN
1tCK
Figure 100 (page 179)
Idle or active
PRECHARGE
tPRPDEN
1tCK
READ or READAP
tRDPDEN
Active
WRITE: BL8OTF, BL8MRS,
BC4OTF
tWRPDEN
Active
WRITE: BC4MRS
Active
Active
WRITEAP: BL8OTF, BL8MRS,
BC4OTF
Active
WRITEAP: BC4MRS
tWRAPDEN
Figure 101 (page 180)
1tCK
Figure 96 (page 177)
tWR/tCK
Figure 97 (page 178)
WL + 2tCK + tWR/tCK
Figure 97 (page 178)
RL +
WL +
4tCK
4tCK
+
1tCK
Figure 98 (page 178)
WL + 2tCK + WR + 1tCK
Figure 98 (page 178)
WL +
4tCK
+
+ WR +
Idle
REFRESH
tREFPDEN
Power-down
REFRESH
tXPDLL
Greater of 10tCK or 24ns
Figure 103 (page 181)
Idle
MODE REGISTER SET
tMRSPDEN
tMOD
Figure 102 (page 180)
Note:
1tCK
Figure 99 (page 179)
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asynchronous tANPD prior to CKE going LOW and remains asynchronous until tANPD +
tXPDLL after CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 197) for detailed ODT usage requirements in slow
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
exit mode precharge power-down. A summary of the two power-down modes is listed in
Table 78 (page 175).
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for powerdown duration is tPD (MAX) (9 × tREFI).
The power-down states are synchronously exited when CKE is registered HIGH (with a
required NOP or DES command). CKE must be maintained HIGH until tCKE has been
satisfied. A valid, executable command may be applied after power-down exit latency,
tXP, and tXPDLL have been satisfied. A summary of the power-down modes is listed below.
For specific CKE-intensive operations, such as repeating a power-down-exit-to-refreshto-power-down-entry sequence, the number of clock cycles between power-down exit
and power-down entry may not be sufficient to keep the DLL properly updated. In addition to meeting tPD when the REFRESH command is used between power-down exit
and power-down entry, two other conditions must be met. First, tXP must be satisfied
before issuing the REFRESH command. Second, tXPDLL must be satisfied before the
next power-down may be entered. An example is shown in Figure 103 (page 181).
Table 78: Power-Down Modes
MR0[12]
DLL State
PowerDown Exit
Active (any bank open)
“Don’t Care”
On
Fast
tXP
to any other valid command
Precharged
(all banks precharged)
1
On
Fast
tXP
to any other valid command
Slow
tXPDLL
DRAM State
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0
Off
175
Relevant Parameters
to commands that require the DLL to be
locked (READ, RDAP, or ODT on);
tXP to any other valid command
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 93: Active Power-Down Entry and Exit
T0
T1
T2
Ta1
Ta2
Ta3
Ta4
NOP
NOP
NOP
Valid
Ta0
CK#
CK
Command
tCK
tCH
tCL
NOP
Valid
NOP
tPD
tIS
CKE
Address
tIH
tIH
tCKE
tIS
(MIN)
Valid
Valid
tXP
tCPDED
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Don’t Care
Figure 94: Precharge Power-Down (Fast-Exit Mode) Entry and Exit
T0
T1
T2
T4
T5
NOP
NOP
T3
Ta0
Ta1
NOP
Valid
CK#
CK
t
t
CK
t
CH
Command
NOP
CL
NOP
t
t
CPDED
t
t
IS
CKE (MIN)
IH
CKE
t
IS
t
t
PD
Enter power-down
mode
XP
Exit power-down
mode
Indicates break
in time scale
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Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 95: Precharge Power-Down (Slow-Exit Mode) Entry and Exit
T0
T1
T2
T4
Ta
NOP
NOP
T3
Ta1
Tb
CK#
CK
tCK
Command
tCH
tCL
NOP
PRE
NOP
tCKE
tCPDED
Valid 1
Valid 2
(MIN)
tXP
tIH
tIS
CKE
tXPDLL
tIS
tPD
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Notes:
Don’t Care
1. Any valid command not requiring a locked DLL.
2. Any valid command requiring a locked DLL.
Figure 96: Power-Down Entry After READ or READ with Auto Precharge (RDAP)
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
READ/
RDAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Ta7
Ta8
Ta9
Ta10
Ta11
Ta12
CK
Command
NOP
tIS
NOP
tCPDED
CKE
Address
Valid
tPD
RL = AL + CL
DQS, DQS#
DQ BL8
DQ BC4
DI
n
DI
DI
n+1 n+2
DI
n
DI
n+1
DI
n+3
DI
n+4
DI
n+ 5
DI
n+6
DI
n+7
DI
DI
n+2 n+3
tRDPDEN
Power-down or
self refresh entry
Indicates break
in time scale
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177
Transitioning Data
Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 97: Power-Down Entry After WRITE
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb1
Tb2
Tb3
Tb4
CK
Command
NOP
tIS
NOP
tCPDED
CKE
Address
Valid
tWR
WL = AL + CWL
tPD
DQS, DQS#
DQ BL8
DI
n
DI
DI
n+1 n+2
DI
n+3
DQ BC4
DI
n
DI
n+1
DI
n+3
DI
n+2
DI
n+4
DI
DI
n+5 n+6
DI
n+7
tWRPDEN
Power-down or
self refresh entry1
Indicates break
in time scale
Note:
Transitioning Data
Don’t Care
1. CKE can go LOW 2tCK earlier if BC4MRS.
Figure 98: Power-Down Entry After WRITE with Auto Precharge (WRAP)
CK#
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
Tb2
WRAP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb3
Tb4
CK
Command
tIS
tCPDED
CKE
Address
Valid
A10
WR1
WL = AL + CWL
tPD
DQS, DQS#
DQ BL8
DI
n
DI
n+1
DI
DI
DI
n+2 n+3 n+4
DQ BC4
DI
n
DI
n+1
DI
DI
n+2 n+3
DI
n+5
DI
n+6
DI
n+7
tWRAPDEN
Start internal
precharge
Power-down or
self refresh entry2
Indicates break
in time scale
Notes:
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Transitioning Data
Don’t Care
1. tWR is programmed through MR0[11:9] and represents tWRmin (ns)/tCK rounded up to
the next integer tCK.
2. CKE can go LOW 2tCK earlier if BC4MRS.
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 99: REFRESH to Power-Down Entry
T0
T1
T2
T3
NOP
NOP
Ta1
Ta0
Ta2
Tb0
CK#
CK
tCK
Command
tCH
tCL
REFRESH
NOP
tCPDED
NOP
tCKE
Valid
(MIN)
tPD
tIS
CKE
tREFPDEN
tXP
tRFC
(MIN)
(MIN)1
Indicates break
in time scale
Note:
Don’t Care
1. After CKE goes HIGH during tRFC, CKE must remain HIGH until tRFC is satisfied.
Figure 100: ACTIVATE to Power-Down Entry
T0
T1
T2
T3
NOP
NOP
T5
T4
T6
T7
CK#
CK
Command
Address
tCK
tCH
tCL
ACTIVE
Valid
tCPDED
tIS
tPD
CKE
tACTPDEN
Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 101: PRECHARGE to Power-Down Entry
T0
T1
T2
T3
NOP
NOP
T4
T5
T6
T7
CK#
CK
tCK
Command
tCH
tCL
PRE
All/single
bank
Address
tCPDED
tIS
tPD
CKE
tPREPDEN
Don’t Care
Figure 102: MRS Command to Power-Down Entry
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
CK#
CK
tCK
Command
MRS
Address
Valid
tCH
NOP
tCPDED
tCL
NOP
NOP
NOP
tMRSPDEN
NOP
tPD
tIS
CKE
Indicates break
in time scale
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4Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
Figure 103: Power-Down Exit to Refresh to Power-Down Entry
T0
T1
T2
T3
T4
Ta0
NOP
REFRESH
Ta1
Tb0
CK#
CK
Command
tCK
tCH
NOP
tCL
NOP
NOP
tCPDED
NOP
NOP
tXP1
tIH
tIS
CKE
tIS
tPD
tXPDLL2
Enter power-down
mode
Enter power-down
mode
Exit power-down
mode
Indicates break
in time scale
Notes:
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Don’t Care
1. tXP must be satisfied before issuing the command.
2. tXPDLL must be satisfied (referenced to the registration of power-down exit) before the
next power-down can be entered.
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4Gb: x4, x8, x16 DDR3L SDRAM
RESET Operation
RESET Operation
The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it
drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes
LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT
(RTT) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to
RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized
as though a normal power-up was executed. All refresh counters on the DRAM are reset,
and data stored in the DRAM is assumed unknown after RESET# has gone LOW.
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4Gb: x4, x8, x16 DDR3L SDRAM
RESET Operation
Figure 104: RESET Sequence
System RESET
(warm boot)
Stable and
valid clock
T0
T1
tCK
Tc0
Tb0
Ta0
Td0
CK#
CK
tCL
tCL
t CKSRX1
T = 100ns (MIN)
RESET#
tIOZ
= 20ns
T = 10ns (MIN)
tIS
Valid
CKE
tIS
tIS
Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static HIGH or LOW
ODT
Valid
tIS
MRS
MRS
MRS
MRS
Address
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
Command
NOP
Valid
ZQCL
DM
BA[2:0]
DQS
DQ
RTT
Valid
A10 = H
Valid
Valid
High-Z
High-Z
High-Z
T = 500μs (MIN)
MR2
All voltage
supplies valid
and stable
tMRD
tMRD
tXPR
MR3
DRAM ready
for external
commands
tMRD
MR1 with
DLL ENABLE
tMOD
MR0 with
DLL RESET
ZQCAL
tZQinit
tDLLK
Normal
operation
Indicates break
in time scale
Note:
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Don’t Care
1. The minimum time required is the longer of 10ns or 5 clocks.
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4Gb: x4, x8, x16 DDR3L SDRAM
On-Die Termination (ODT)
On-Die Termination (ODT)
On-die termination (ODT) is a feature that enables the DRAM to enable/disable and
turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8
configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is applied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 configuration.
ODT is designed to improve signal integrity of the memory channel by enabling the
DRAM controller to independently turn on/off the DRAM’s internal termination resistance for any grouping of DRAM devices. ODT is not supported during DLL disable
mode (simple functional representation shown below). The switch is enabled by the internal ODT control logic, which uses the external ODT ball and other control information.
Figure 105: On-Die Termination
ODT
To other
circuitry
such as
RCV,
...
VDDQ/2
RTT
Switch
DQ, DQS, DQS#,
DM, TDQS, TDQS#
Functional Representation of ODT
The value of RTT (ODT termination resistance value) is determined by the settings of
several mode register bits (see Table 84 (page 188)). The ODT ball is ignored while in
self refresh mode (must be turned off prior to self refresh entry) or if mode registers
MR1 and MR2 are programmed to disable ODT. ODT is comprised of nominal ODT and
dynamic ODT modes and either of these can function in synchronous or asynchronous
mode (when the DLL is off during precharge power-down or when the DLL is synchronizing). Nominal ODT is the base termination and is used in any allowable ODT state.
Dynamic ODT is applied only during writes and provides OTF switching from no RTT or
RTT,nom to RTT(WR).
The actual effective termination, RTT(EFF), may be different from RTT targeted due to
nonlinearity of the termination. For RTT(EFF) values and calculations, see Table 30
(page 51).
Nominal ODT
ODT (NOM) is the base termination resistance for each applicable ball; it is enabled or
disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or
off via the ODT ball.
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4Gb: x4, x8, x16 DDR3L SDRAM
On-Die Termination (ODT)
Table 79: Truth Table – ODT (Nominal)
Note 1 applies to the entire table
MR1[9, 6, 2]
ODT Pin
DRAM Termination State
DRAM State
Notes
000
0
RTT,nom disabled, ODT off
Any valid
2
000
1
RTT,nom disabled, ODT on
Any valid except self refresh, read
3
000–101
0
RTT,nom enabled, ODT off
Any valid
2
000–101
1
RTT,nom enabled, ODT on
Any valid except self refresh, read
3
110 and 111
X
RTT,nom reserved, ODT on or off
Illegal
Notes:
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 186) when enabled).
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
for it to be off during writes.
3. ODT must be disabled during reads. The RTT,nom value is restricted during writes. Dynamic ODT is applicable if enabled.
Nominal ODT resistance RTT,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1
(MR1) Definition. The R TT,nom termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple RTT,nom values based on RZQ/n where n
can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. RTT,nom termination is allowed any time after the
DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.
Write accesses use RTT,nom if dynamic ODT (RTT(WR)) is disabled. If RTT,nom is used during writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 83 (page 187)). ODT
timings are summarized in Table 80 (page 185), as well as listed in the Electrical Characteristics and AC Operating Conditions table.
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 192).
Table 80: ODT Parameters
Symbol
Description
Begins at
Definition for All
DDR3L Speed Bins
Unit
±tAON
CWL + AL - 2
tCK
Defined to
ODTLon
ODT synchronous turn-on delay
ODT registered HIGH
RTT(ON)
ODTLoff
ODT synchronous turn-off delay
ODT registered HIGH
RTT(OFF) ±tAOF
CWL + AL - 2
tCK
tAONPD
ODT asynchronous turn-on delay
ODT registered HIGH
RTT(ON)
2–8.5
ns
tAOFPD
ODT asynchronous turn-off delay
ODT registered HIGH
RTT(OFF)
2–8.5
ns
ODT registered
LOW
4tCK
tCK
ODTH4
ODT minimum HIGH time after ODT ODT registered HIGH
assertion or write (BC4)
or write registration
with ODT HIGH
ODTH8
ODT minimum HIGH time after
write (BL8)
Write registration
with ODT HIGH
ODT registered
LOW
6tCK
tCK
tAON
ODT turn-on relative to ODTLon
completion
Completion of
ODTLon
RTT(ON)
See Electrical Characteristics and AC Operating Conditions table
ps
tAOF
ODT turn-off relative to ODTLoff
completion
Completion of
ODTLoff
RTT(OFF)
0.5tCK ± 0.2tCK
tCK
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4Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
Dynamic ODT
In certain application cases, and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the DDR3 SDRAM can be changed without
issuing an MRS command, essentially changing the ODT termination on the fly. With
dynamic ODT RTT(WR)) enabled, the DRAM switches from nominal ODT RTT,nom) to dynamic ODT RTT(WR)) when beginning a WRITE burst and subsequently switches back to
nominal ODT RTT,nom) at the completion of the WRITE burst. This requirement is supported by the dynamic ODT feature, as described below.
Dynamic ODT Special Use Case
When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special use case: the ODT ball can be wired high (via a current limiting resistor preferred) by having RTT,nom disabled via MR1 and RTT(WR) enabled via MR2. This will allow
the ODT signal not to have to be routed yet the DRAM can provide ODT coverage during write accesses.
When enabling this special use case, some standard ODT spec conditions may be violated: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not
LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this
would appear to be a problem since RTT(WR) can not be used (should be disabled) and
RTT(NOM) should be used. For Write leveling during this special use case, with the DLL
locked, then RTT(NOM) maybe enabled when entering Write Leveling mode and disabled
when exiting Write Leveling mode. More so, R TT(NOM) must be enabled when enabling
Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via
same MR1 load if RTT(NOM) is to be used.
ODT will turn-on within a delay of ODTLon + tAON + tMOD + 1CK (enabling via MR1)
or turn-off within a delay of ODTLoff + tAOF + tMOD + 1CK. As seen in the table below,
between the Load Mode of MR1 and the previously specified delay, the value of ODT is
uncertain. this means the DQ ODT termination could turn-on and then turn-off again
during the period of stated uncertainty.
Table 81: Write Leveling with Dynamic ODT Special Case
Begin RTT,nom Uncertainty
MR1 load mode command:
End RTT,nom Uncertainty
ODTLon +
tAON
ODTLoff +
tAOFF
+
tMOD
+
tMOD
+ 1CK
I/Os
RTT,nom Final State
DQS, DQS#
Drive RTT,nom value
DQs
No RTT,nom
DQS, DQS#
No RTT,nom
DQs
No RTT,nom
Enable Write Leveling and RTT(NOM)
MR1 load mode command:
+ 1CK
Disable Write Leveling and RTT(NOM)
Functional Description
The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic
ODT is not supported during DLL disable mode so RTT(WR) must be disabled. The dynamic ODT function is described below:
• Two RTT values are available—RTT,nom and RTT(WR).
– The value for RTT,nom is preselected via MR1[9, 6, 2].
– The value for RTT(WR) is preselected via MR2[10, 9].
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Dynamic ODT
• During DRAM operation without READ or WRITE commands, the termination is controlled.
– Nominal termination strength RTT,nom is used.
– Termination on/off timing is controlled via the ODT ball and latencies ODTLon and
ODTLoff.
• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
and if dynamic ODT is enabled, the ODT termination is controlled.
– A latency of ODTLcnw after the WRITE command: termination strength R TT,nom
switches to RTT(WR)
– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)
after the WRITE command: termination strength R TT(WR) switches back to RTT,nom.
– On/off termination timing is controlled via the ODT ball and determined by ODTLon, ODTLoff, ODTH4, and ODTH8.
– During the tADC transition window, the value of RTT is undefined.
ODT is constrained during writes and when dynamic ODT is enabled (see the table below, Dynamic ODT Specific Parameters). ODT timings listed in the ODT Parameters table in On-Die Termination (ODT) also apply to dynamic ODT mode.
Table 82: Dynamic ODT Specific Parameters
Definition for All
DDR3L Speed
Bins
Unit
Symbol
Description
Begins at
Defined to
ODTLcnw
Change from RTT,nom to
RTT(WR)
Write registration
RTT switched from RTT,nom
to RTT(WR)
WL - 2
tCK
ODTLcwn4
Change from RTT(WR) to
RTT,nom (BC4)
Write registration
RTT switched from RTT(WR)
to RTT,nom
4tCK + ODTL off
tCK
ODTLcwn8
Change from RTT(WR) to
RTT,nom (BL8)
Write registration
RTT switched from RTT(WR)
to RTT,nom
6tCK + ODTL off
tCK
tADC
RTT change skew
ODTLcnw completed
RTT transition complete
0.5tCK ± 0.2tCK
tCK
Table 83: Mode Registers for RTT,nom
MR1 (RTT,nom)
M9
M6
M2
RTT,nom (RZQ)
RTT,nom (Ohm)
RTT,nom Mode Restriction
0
0
0
Off
Off
n/a
0
0
1
RZQ/4
60
Self refresh
0
1
0
RZQ/2
120
0
1
1
RZQ/6
40
1
0
0
RZQ/12
20
1
0
1
RZQ/8
30
1
1
0
Reserved
Reserved
n/a
1
1
1
Reserved
Reserved
n/a
Note:
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Self refresh, write
1. RZQ = 240Ω. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
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Dynamic ODT
Table 84: Mode Registers for RTT(WR)
MR2 (RTT(WR))
M10
M9
RTT(WR) (RZQ)
RTT(WR) (Ohm)
0
0
Dynamic ODT off: WRITE does not affect RTT,nom
0
1
RZQ/4
1
0
RZQ/2
120
1
1
Reserved
Reserved
60
Table 85: Timing Diagrams for Dynamic ODT
Figure and Page
Title
Figure 106 (page 189)
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Figure 107 (page 189)
Dynamic ODT: Without WRITE Command
Figure 108 (page 190)
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Figure 109 (page 191)
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 110 (page 191)
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
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NOP
T0
NOP
T1
Notes:
NOP
T3
Valid
WRS4
T4
ODTH4
NOP
T6
RTT,nom
ODTLcnw
(MAX)
(MIN)
tAON
tAON
NOP
T5
WL
189
DQ
DQS, DQS#
RTT
ODT
Address
Command
CK#
CK
Valid
T0
Notes:
Valid
T1
tADC
tADC
(MAX)
(MIN)
NOP
T8
ODTLcwn4
NOP
T7
DI
n
NOP
T9
DI
n+ 1
RTT(WR)
DI
n+ 2
NOP
T10
DI
n+ 3
NOP
T11
(MAX)
(MIN)
tADC
tADC
NOP
T12
NOP
T13
T15
NOP
NOP
T16
Transitioning
ODTLoff
RTT,nom
NOP
T14
Don’t Care
(MAX)
(MIN)
tAOF
tAOF
NOP
T17
Valid
T3
(MIN)
(MAX)
Valid
T4
Valid
T5
Valid
RTT,nom
Valid
T7
T9
(MAX)
Valid
T10
Transitioning
tAOF
tAOF
(MIN)
Valid
ODTLoff
Valid
T8
Don’t Care
Valid
T11
1. AL = 0, CWL = 5. RTT,nom is enabled and RTT(WR) is either enabled or disabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
tAON
tAON
ODTH4
ODTLon
Valid
T2
T6
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
ODTH4
ODTLon
NOP
T2
Figure 107: Dynamic ODT: Without WRITE Command
DQ
DQS, DQS#
RTT
ODT
Address
Command
CK#
CK
Figure 106: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
4Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
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DQ
DQS, DQS#
RTT
ODT
Address
Command
CK
CK#
NOP
T0
Notes:
Valid
WRS8
T1
190
ODTLon
ODTLcnw
NOP
T3
WL
ODTH8
NOP
T4
tAON
(MAX)
(MIN)
tADC
NOP
T5
ODTLcwn8
DI
b
NOP
T6
DI
b+1
DI
b+2
RTT(WR)
NOP
T7
DI
b+3
DI
b+ 4
NOP
T8
DI
b+5
ODTLoff
DI
b+6
NOP
T9
DI
b+ 7
(MAX)
tAOF
Transitioning
tAOF
NOP
T10
(MIN)
Don’t Care
NOP
T11
1. Via MRS or OTF; AL = 0, CWL = 5. If RTT,nom can be either enabled or disabled, ODT can be HIGH. RTT(WR) is enabled.
2. In this example, ODTH8 = 6 is satisfied exactly.
NOP
T2
Figure 108: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
4Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
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4Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
Figure 109: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
ODTLcnw
Address
Valid
ODTH4
ODTLoff
ODT
ODTLon
tADC
tADC
(MAX)
RTT(WR)
RTT
tAON
tADC
(MIN)
tAOF
(MIN)
RTT,nom
tAOF
(MAX)
(MIN)
(MAX)
ODTLcwn4
DQS, DQS#
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL
Transitioning
Notes:
Don’t Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 110: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
ODTLcnw
Address
Valid
ODTLoff
ODTH4
ODT
tADC
ODTLon
tAOF
(MAX)
(MIN)
RTT(WR)
RTT
tAON
tAOF
(MIN)
(MAX)
ODTLcwn4
DQS, DQS#
WL
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
Transitioning
Notes:
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Don’t Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,
ODT can remain HIGH. RTT(WR) is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
191
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4Gb: x4, x8, x16 DDR3L SDRAM
Synchronous ODT Mode
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either RTT,nom or RTT(WR) is enabled. Based on the power-down definition, these
modes are:
•
•
•
•
•
Any bank active with CKE HIGH
Refresh mode with CKE HIGH
Idle mode with CKE HIGH
Active power-down mode (regardless of MR0[12])
Precharge power-down mode if DLL is enabled by MR0[12] during precharge powerdown
ODT Latency and Posted ODT
In synchronous ODT mode, RTT turns on ODTLon clock cycles after ODT is sampled
HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around
each clock edge (see Table 86 (page 193)). The ODT latency is tied to the WRITE latency
(WL) by ODTLon = WL - 2 and ODTLoff = WL - 2.
Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL),
the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal.
The device’s internal ODT signal is delayed a number of clock cycles defined by the AL
relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL +
AL - 2.
Timing Parameters
Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff,
ODTH4, ODTH8, tAON, and tAOF. The minimum R TT turn-on time (tAON [MIN]) is the
point at which the device leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on.
Both are measured relative to ODTLon. The minimum R TT turn-off time (tAOF [MIN]) is
the point at which the device starts to turn off ODT resistance. The maximum R TT turn
off time (tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured
from ODTLoff.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE command is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 112 (page 194)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.
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193
RTT
ODT
CKE
CK#
CK
T0
T1
T3
T5
T6
T7
(MAX)
(MIN)
tAON
tAON
T8
Completion of ODTLoff
Completion of ODTLon
T9
AL = 3
ODT registered HIGH or write registration with ODT HIGH
tCK
6tCK
T11
T12
RTT,nom
ODTLoff = CWL + AL - 2
T10
RTT(OFF)
RTT(ON)
CWL - 2
ODT registered LOW
T14
Transitioning
T13
t
(MAX)
Don’t Care
tAOF
AOF (MIN)
T15
0.5tCK ± 0.2tCK
tCK
ps
tCK
4tCK
ODT registered LOW
See Electrical Characteristics and AC Operating Conditions table
tCK
CWL +AL - 2
RTT(OFF) ±tAOF
RTT(ON)
tCK
Unit
CWL + AL - 2
Definition for All
DDR3L Speed Bins
±tAON
Defined to
1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. RTT,nom is enabled.
ODTLon = CWL + AL - 2
ODTH4 (MIN)
AL = 3
Note:
T2
T4
ODT turn-off relative to ODTLoff
completion
tAOF
Figure 111: Synchronous ODT
ODT turn-on relative to ODTLon
completion
ODT minimum HIGH time after WRITE Write registration with ODT HIGH
(BL8)
ODTH8
tAON
ODT minimum HIGH time after ODT
assertion or WRITE (BC4)
ODTH4
ODT registered HIGH
ODT synchronous turn-off delay
ODTLoff
ODT registered HIGH
Begins at
ODT synchronous turn-on delay
Description
ODTLon
Symbol
Table 86: Synchronous ODT Parameters
4Gb: x4, x8, x16 DDR3L SDRAM
Synchronous ODT Mode
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RTT
ODT
Command
CKE
CK#
CK
NOP
T0
NOP
T1
Notes:
NOP
T2
NOP
T4
NOP
T5
NOP
T6
ODTH4 (MIN)
NOP
T8
(MAX)
(MIN)
tAON
tAON
ODTH4
NOP
T9
RTT,nom
tAOF
ODTLon = WL - 2
ODTLoff = WL - 2
WRS4
T7
tAOF
(MIN)
NOP
T10
(MAX)
tAON
NOP
T11
(MIN)
tAON
(MAX)
NOP
T12
NOP
T14
RTT,nom
ODTLoff = WL - 2
NOP
T13
NOP
T16
Transitioning
NOP
T15
Don’t Care
(MAX)
(MIN)
tAOF
tAOF
NOP
T17
WL = 7. RTT,nom is enabled. RTT(WR) is disabled.
ODT must be held HIGH for at least ODTH4 after assertion (T1).
ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7).
ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the
WRITE command with ODT HIGH to ODT registered LOW.
5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must
also be satisfied from the registration of the WRITE command at T7.
1.
2.
3.
4.
ODTLon = WL - 2
ODTH4
NOP
T3
Figure 112: Synchronous ODT (BC4)
4Gb: x4, x8, x16 DDR3L SDRAM
Synchronous ODT Mode
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4Gb: x4, x8, x16 DDR3L SDRAM
Synchronous ODT Mode
ODT Off During READs
Because the device cannot terminate and drive at the same time, RTT must be disabled
at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if
either RTT,nom or RTT(WR) is enabled). RTT may not be enabled until the end of the postamble, as shown in the following example.
Note: ODT may be disabled earlier and enabled later than shown in Figure 113
(page 196).
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Valid
Address
DQ
DQS, DQS#
RTT
ODT
READ
T0
Command
CK#
CK
NOP
T1
Note:
NOP
T2
NOP
T5
NOP
T6
RL = AL + CL
RTT,nom
ODTLoff = CWL + AL - 2
NOP
T4
NOP
T7
NOP
T8
NOP
T9
(MAX)
(MIN)
tAOF
tAOF
NOP
T11
DI
b
DI
b+1
DI
b+2
NOP
T12
ODTLon = CWL + AL - 2
NOP
T10
DI
b+3
DI
b+4
NOP
T13
DI
b+5
DI
b+6
NOP
T14
tAON
NOP
T17
Don’t Care
(MAX)
RTT,nom
NOP
T16
Transitioning
DI
b+7
NOP
T15
1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL
+ CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8. RTT,nom is enabled. RTT(WR) is a “Don’t
Care.”
NOP
T3
Figure 113: ODT During READs
4Gb: x4, x8, x16 DDR3L SDRAM
Synchronous ODT Mode
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4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
Asynchronous ODT Mode
Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when
either RTT,nom or RTT(WR) is enabled; however, the DLL is temporarily turned off in precharged power-down standby (via MR0[12]). Additionally, ODT operates asynchronously when the DLL is synchronizing after being reset. See Power-Down Mode (page 174)
for definition and guidance over power-down details.
In asynchronous ODT timing mode, the internal ODT command is not delayed by AL
relative to the external ODT command. In asynchronous ODT mode, ODT controls RTT
by analog time. The timing parameters tAONPD and tAOFPD replace ODTLon/tAON
and ODTLoff/tAOF, respectively, when ODT operates asynchronously.
The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termination circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turnon time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD
(MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH.
The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termination circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD
[MAX]) is the point at which ODT has reached High-Z. tAOFPD (MIN) and tAOFPD
(MAX) are measured from ODT being sampled LOW.
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T0
T1
Note:
T2
tIS
T4
(MIN)
tAONPD
tAONPD
T5
1. AL is ignored.
tIH
T3
(MAX)
T6
T7
T8
T9
Description
Asynchronous RTT turn-on delay (power-down with DLL off)
Asynchronous RTT turn-off delay (power-down with DLL off)
Symbol
tAONPD
tAOFPD
Table 87: Asynchronous ODT Timing Parameters for All Speed Bins
RTT
ODT
CKE
CK#
CK
Figure 114: Asynchronous ODT Timing with Fast ODT Transition
RTT,nom
T10
tIH
T11
tIS
T12
2
2
Min
T14
(MAX)
(MIN)
tAOFPD
tAOFPD
T13
Max
8.5
8.5
T16
Transitioning
T15
ns
ns
Unit
Don’t Care
T17
4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
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4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period occurs if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW,
and ends when CKE is first registered LOW. tANPD is equal to the greater of ODTLoff +
1tCK or ODTLon + 1tCK. If a REFRESH command has been issued, and it is in progress
when CKE goes LOW, power-down entry ends tRFC after the REFRESH command, rather than when CKE is first registered LOW. Power-down entry then becomes the greater
of tANPD and tRFC - REFRESH command to CKE registered LOW.
ODT assertion during power-down entry results in an RTT change as early as the lesser
of tAONPD (MIN) and ODTLon × tCK + tAON (MIN), or as late as the greater of tAONPD
(MAX) and ODTLon × tCK + tAON (MAX). ODT de-assertion during power-down entry
can result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTLoff × tCK +
tAOF (MIN), or as late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF (MAX).
Table 88 (page 200) summarizes these parameters.
If AL has a large value, the uncertainty of the state of RTT becomes quite large. This is
because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL.
Figure 115 (page 200) shows three different cases:
• ODT_A: Synchronous behavior before tANPD.
• ODT_B: ODT state changes during the transition period with tAONPD (MIN) <
ODTLon × tCK + tAON (MIN) and tAONPD (MAX) > ODTLon × tCK + tAON (MAX).
• ODT_C: ODT state changes after the transition period with asynchronous behavior.
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WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
200
DRAM RTT C
asynchronous
ODT C
asynchronous
DRAM RTT B
asynchronous
or synchronous
ODT B
asynchronous
or synchronous
DRAM RTT A
synchronous
ODT A
synchronous
Command
CKE
CK#
CK
NOP
T0
REF
T1
Note:
NOP
T2
RTT,nom
T5
tANPD
NOP
ODTLoff
NOP
T4
NOP
T6
NOP
T8
NOP
T9
RTT,nom
(MAX)
PDE transition period
(MIN)
(MIN)
tAOF
tAOF
tRFC
NOP
T7
1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.
RTT,nom
NOP
T3
NOP
T11
(MIN)
(MAX)
NOP
T12
ODTLoff + tAOFPD (MAX)
tAOFPD
tAOFPD
ODTLoff + tAOFPD (MIN)
NOP
T10
NOP
Ta0
Indicates break
in time scale
NOP
T13
Figure 115: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
tANPD
tAOFPD
NOP
Ta3
Don’t Care
(MAX)
(MIN)
NOP
Ta2
tAOFPD
Transitioning
NOP
Ta1
Greater of: tAOFPD (MAX) (8.5ns) or
ODTLoff × tCK + tAOF (MAX)
Lesser of: tAOFPD (MIN) (2ns) or
ODTLoff × tCK + tAOF (MIN)
+ tXPDLL
- refresh to CKE LOW
Max
ODT to RTT turn-off delay
(ODTLoff = WL - 2)
tANPD
or
tRFC
Greater of: tAONPD (MAX) (8.5ns) or
ODTLon × tCK + tAON (MAX)
Greater of:
tANPD
Lesser of: tAONPD (MIN) (2ns) or
ODTLon × tCK + tAON (MIN)
Min
ODT to RTT turn-on delay
(ODTLon = WL - 2)
Power-down exit transition period
(power-down exit)
Power-down entry transition period
(power-down entry)
Description
Table 88: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
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4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit)
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins
tANPD prior to CKE first being registered HIGH, and ends tXPDLL after CKE is first registered HIGH. tANPD is equal to the greater of ODTLoff + 1tCK or ODTLon + 1tCK. The
transition period is tANPD + tXPDLL.
ODT assertion during power-down exit results in an RTT change as early as the lesser of
tAONPD (MIN) and ODTLon × tCK + tAON (MIN), or as late as the greater of tAONPD
(MAX) and ODTLon × tCK + tAON (MAX). ODT de-assertion during power-down exit
may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTLoff × tCK +
tAOF (MIN), or as late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF (MAX).
Table 88 (page 200) summarizes these parameters.
If AL has a large value, the uncertainty of the RTT state becomes quite large. This is because ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL. Figure 116 (page 202) shows three different cases:
• ODT C: Asynchronous behavior before tANPD.
• ODT B: ODT state changes during the transition period, with tAOFPD (MIN) < ODTLoff × tCK + tAOF (MIN), and ODTLoff × tCK + tAOF (MAX) > tAOFPD (MAX).
• ODT A: ODT state changes after the transition period with synchronous response.
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DRAM RTT C
synchronous
ODT C
synchronous
ODT B
asynchronous
or synchronous
RTT B
asynchronous
or synchronous
DRAM RTT A
asynchronous
ODT A
asynchronous
COMMAND
CKE
CK#
CK
T0
RTT,nom
T1
(MIN)
tANPD
Ta0
NOP
Ta1
NOP
Ta2
tAOFPD
NOP
Ta3
NOP
Ta5
(MIN)
tXPDLL
NOP
Ta6
(MAX)
RTT,nom
ODTLoff + tAOF (MAX)
tAOFPD
ODTLoff + tAOF (MIN)
PDX transition period
NOP
Ta4
1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8.
RTT,nom
(MAX)
Note:
tAOFPD
tAOFPD
T2
NOP
Tb0
NOP
Tb1
NOP
Tb2
Indicates break
in time scale
NOP
Tc0
NOP
Tc1
Figure 116: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit
Transitioning
ODTLoff
NOP
Tc2
(MIN)
(MAX)
NOP
Td1
Don’t Care
tAOF
tAOF
NOP
Td0
4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit)
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4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit)
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)
If the time in the precharge power-down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods overlap. When
overlap occurs, the response of the DRAM’s RTT to a change in the ODT state can be
synchronous or asynchronous from the start of the power-down entry transition period
to the end of the power-down exit transition period, even if the entry period ends later
than the exit period.
If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the response of the DRAM’s RTT to a change in the ODT state may be synchronous or asynchronous from the start of power-down exit transition period to the end of the powerdown entry transition period.
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204
Command
CK#
CK
EKC
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REF
T0
Note:
NOP
T1
tANPD
NOP
T3
NOP
T5
NOP
T7
(MIN)
tANPD
tRFC
T8
NOP
NOP
T9
PDX transition period
PDE transition period
NOP
T6
Short CKE low transition period (R TT change asynchronous or synchronous)
NOP
T4
1. AL = 0, WL = 5, tANPD = 4.
NOP
T2
tXPDLL
NOP
Ta1
Indicates break
in time scale
NOP
Ta0
NOP
T0
Note:
NOP
T1
tANPD
NOP
T3
NOP
T4
NOP
T5
NOP
T6
tXPDLL
tANPD
NOP
T7
NOP
T8
1. AL = 0, WL = 5, tANPD = 4.
Short CKE HIGH transition period (RTT change asynchronous or synchonous)
NOP
T2
NOP
T9
Ta1
NOP
Indicates break
in time scale
NOP
Ta0
Figure 118: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping
CKE
Command
CK#
CK
Figure 117: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
Transitioning
NOP
Ta2
Ta3
NOP
Ta3
NOP
Transitioning
NOP
Ta2
Don’t Care
NOP
Ta4
Don’t Care
NOP
Ta4
4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (PowerDown Exit)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef8591e091
4Gb_DDR3L_EDJ.pdf - Rev. A 03/14 EN
205
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.