TIDA-00607 Test Report
Powering the Altera® MAX® 10 with TPS65218 Power
Management IC
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TIDA-00607
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Report Contents
Figure 1 - Top Side
Block Diagram: TPS65218/MAX® 10
Efficiency Curves
Load Regulation Curves
Startup (No Load)
Output Ripple Voltage
Load Transients
Design Considerations
Feature Applications
Factory Automation
ePos
Motor Control
System Management
Industrial Networking
Figure 2 - Bottom Side
Description
The TIDA-00607 design is a compact, integrated power solution for Altera® MAX® 10 SoC (out of the
MAX® series family of products). This design showcases TPS65218 as an all-in-one IC used to supply
the rails needed for powering the MAX® 10 SoC. Altera offers a single supply and dual supply solution
for the MAX 10. This TI Design is for the MAX 10 Dual Supply solution. The total board area needed for
TPS65218, including passive components, to supply the power rails to the MAX® 10 is just 1.594 in2.
The TPS65218 has the flexibility to support either DDR3L or DDR3 memory. It also integrates 3 Load
Switches allowing external periphereals on the system offsetting power consumption. This power
TIDA-00607 - Test Report
Powering the Altera® MAX® 10 with TPS65218 Power Management IC
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management IC can be run from a single 5V supply or from a single cell Li-Ion battery. This design has
been tested and verified for industrial applications (-40°C to 105°C)
TPS65218/MAX® 10 Block Diagram (Return to Top)
The Altera MAX 10 supports Instant-On Support which allows the SoC to wake up very quickly to
begin operation. With instant-on feature, MAX 10 device can directly enter configuration mode
without any POR delay after the POR trips for the monitored power supplies. This TI Design is
for normal operation of the Altera MAX 10. Figure 4 shows the connection diagram and
sequencing number to support Instant-On.
Power Supply Block Diagram
Figure 3 – 3.3 - 5V Supply Diagram
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Figure 4 – Instant-On Connection and Sequence Diagram
Typical Voltage and Current Requirements in End Applications
The table below highlights the typical current consumptions for the MAX® 10 seen in end
applications.
MAX 10 Supply Rails
VCCINT
VCC_CORE
VCCD_PLL
VCCA
VCCA_ADC
VDDR3
VCCIO
VCCIO
Voltage
1.2V
1.2V
1.2V
2.5V
2.5V
1.5V
1.5V
1.5V - 3.3V
Current Consumption (A)
0.5
1.7
0.01
0.10
0.03
0.13
Scalable
Scalable
Note: The current consumption numbers above are only estimates and the actual current
consumption may vary depending on the application.
Maximum Power Output Block Diagram
The TPS65218 has the ability to output up to 1.8A on DCDC1-3 converters, 1.0A on DCDC4 and
400mA on the LDO. The flexibility allows for multiple applications utilizing the Altera MAX 10.
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Figure 5 – Max Supply Current Block Diagram
Note: The current consumption numbers above are only estimates and the actual current
consumption may vary depending on the application.
Efficiency Curves (Return to Top)
DCDC1 (Vout=1.5V) – VCCIO, VDDR3
DCDC1 Efficiency vs Load Current @ Ta=25°C
100%
Efficinecy
80%
60%
40%
20%
0%
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 6 - DCDC1 Efficiency @ 25C
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DCDC2 (Vout=1.2V) – VCC_CORE, VCCD_PLL
Efficinecy
DCDC2 Efficiency vs Load Current @ Ta=25°C
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 7 - DCDC2 Efficiency @ 25C
DCDC3 (Vout=1.2V) – VCCINT
Efficinecy
DCDC3 Efficiency vs Load Current @ Ta=25°C
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.000
0.200
0.400
0.600
0.800
1.000
1.200
1.400
1.600
1.800
2.000
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 8 - DCDC3 Efficiency @ 25C
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DCDC4 (Vout=2.5V) – VCCA, VCCA_ADC
Efficinecy
DCDC4 Efficiency vs Load Current @ Ta=25°C
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 9 - DCDC4 Efficiency @ 25C
Load Regulation (Return to Top)
Below is the table showing the Voltage Ripple requirement for the MAX 10.
Max 10 Supply Rail
VCC
VCCIO
VCCA
VCCD_PLL
VCCA_ADC
VCCINT
TIDA-00607 – Test Report
Voltage Tolerance (%)
5
5
5
3
2
3
DC/DC
DCDC2
DCDC1
DCDC4
DCDC2
DCDC4
DCDC3
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DCDC1 (Vout=1.5V) – VCCIO, VDDR3
DCDC1 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.6
1.8
2.0
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 10 – DCDC1 Load Regulation @ 25C
DCDC2 (Vout=1.2V) – VCC_CORE, VCCD_PLL
DCDC2 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 11 – DCDC2 Load Regulation @ 25C
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DCDC3 (Vout=1.2V) – VCCINT
DCDC3 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 12 – DCDC3 Load Regulation @ 25C
DCDC4 (Vout=1.8V) – VCCA, VCCA_ADC
DCDC4 Load Regulation @ Ta=25°C
2.0%
Load Regulation
1.5%
1.0%
0.5%
0.0%
-0.5%
-1.0%
-1.5%
-2.0%
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Iout (A)
Vin = 3.3V
Vin = 5.0V
Figure 13 – DCDC4 Load Regulation @ 25C
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Startup (No Load) (Return to Top)
1.5V
1.2V
1.2V
2.5V
Figure 14 - Startup (No Load) Voltage and Timing Waveforms
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Output Ripple Voltage (Return to Top)
DCDC1 (Vout = 1.5V) – VCCIO, VDDR3 (MAX Typical Load)
Figure 15 – DCDC1 Output Ripple Voltage @ 25C
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DCDC2 (Vout = 1.2V) – VCC_Core (MAX Typical Load)
Figure 16 – DCDC2 Output Ripple Voltage @ 25C
DCDC3 (Vout = 1.2V) – VCC_INT, VCCD_PLL (MAX Typical Load)
Figure 16 – DCDC3 Output Ripple Voltage @ 25C
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DCDC4 (Vout = 2.5V) – VCCA, VCCA_ADC (MAX Typical Load)
Figure 17 – DCDC4 Output Ripple Voltage @ 25C
Load Transients (Return to Top)
Load transients for each of the DC-DC converters were completed by applying a load step of
0mA to at least 50% of the MAX load for the converter under test. The table below shows the
transient requirements for the MAX 10. All converters were tested and exceed MAX 10
requirements.
Max 10 Supply Rail
VCC
VCCIO
VCCA
VCCD_PLL
VCCA_ADC
VCCINT
TIDA-00607 – Test Report
Voltage Tolerance (%)
5
5
5
3
2
3
DC/DC
DCDC2
DCDC1
DCDC4
DCDC2
DCDC4
DCDC3
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DCDC1 (Vout = 1.5V) – VCCIO, VDDR3 Load Step (0mA to 975mA; Rise Time: 10µS, Fall
Time: 10µS)
Figure 18 – DCDC1 Load Transient Response @ 25C
DCDC2 (Vout = 1.2V) – VCC_CORE Load Step (0mA to 975mA; Rise Time: 10µS, Fall Time:
10µS)
Figure 19 – DCDC2 Load Transient Response @ 25C
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DCDC3 (Vout = 1.2V) – VCCINT, VCCD_PLL Load Step (0mA to 975mA; Rise Time: 10µS, Fall
Time: 10µS)
Figure 20 – DCDC3 Load Transient Response @ 25C
DCDC4 (Vout = 2.5V) – VCCA, VCCA_ADC (0mA to 500mA; Rise Time: 10µS, Fall Time: 10µS)
Figure 21 – DCDC4 Load Transient Response @ 25C
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Design Considerations (Return to Top)
Altera® MAX® 10 Design Considerations
For reference, the sequencing requirements from the Altera MAX 10 datasheet are shown below:
Power pin name and description for MAX 10 dual-supply:
Pin Name
VCC
VCCIO
VCCA
Description
Power supply pin for core and peripherals
I/O supply voltage pins
Power supply pins for analog PLL
VCCD_PLL
VCCA_ADC
VCC_INT
Power supply pins for digital PLL
Power supply for ADC block
Power supply for ADC digital block
For MAX 10 single-supply devices, only one power supply is required—3.0 V or 3.3 V to power
the core of the FPGA. The same power supply can be used to power the I/O if the same 3.0 V or
3.3 V voltage is required. If different I/O voltage is used, then additional voltage regulators will be
needed.
For MAX 10 dual-supply devices, two power supplies are required to supply power to the device
core, periphery, phase-locked loop (PLL), and analog-to-digital converters (ADC) blocks—1.2 V
and 2.5 V. Depending on the I/O standard voltage requirement, you may use two or more voltage
regulators. During power-up, the output buffers are tri-stated and the internal weak pull-up
resistors are disabled by default.
Even though the MAX 10 does not require power sequencing, Altera recommends designing
sequencing for the best device reliability. This can help prevent problems with long-term device
reliability in multi-rail power systems. The TPS65218 and this TI Design support a power
sequence to increase system reliability.
Instant-On Support
In some applications, it is necessary for a device to wake up very quickly to begin operation. The
MAX 10 device offers the instant-on feature to support fast wake-up time applications. With
instant-on feature, MAX 10 device can directly enter configuration mode without any POR
(Power on Reset) delay after the POR trips for the monitored power supplies.
Power Supply Option
Single-supply device
Power-Up Sequence
VCCIO rail must ramp up to full rail before VCCA and VCC_ONE start ramping
Dual-supply device
All power supplies must ramp up to full rail before VCC starts ramping
If your application does not require instant-on support, you can use the power sequence that is
provided in the TI Design. Figure 4 in this document shows the connection diagram and
sequencing order for Instant-On Support.
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Pin Connection Guidelines
For reference, the sequencing requirements from the Altera MAX 10 pin connection guidelines are shown
below:
Connect VCCA to a 2.5V supply even if the PLL is not being used. All VCCA pins must
be powered up and down at the same time.
Connect VCCD_PLL to 1.2V supply even if the digital PLL is not being used.
TPS65218 Power Sequencing
Wake-up and Power up/Down Sequencing
The TPS65218 has a pre-defined power-up / power-down sequence which in a typical
application does not need to be changed. However, it is possible to define custom sequences
under I2C control.
The power-up sequence is defined by a series of ten strobes and nine delay times. Each output
rail is assigned to a strobe to determine the order in which the rails are enabled. A rail can be
assigned to only one strobe but multiple rails can be assigned to the same strobe. The delay
times in-between strobes are selectable between 2ms and 5ms.
Power-up sequencing
When the power-up sequence initiates, STROBE1 occurs, and any rail assigned to this strobe is
enabled. After a delay time of DLY1, STROBE2 occurs and the rail assigned to this strobe is
powered up. The sequence continues until all strobes occur and all DLYx times execute. Strobe
assignments and delay times are defined in the SEQx registers, and are changed under I2C
control. Below is a timing diagram detailing the power sequence when PWN_EN is the. For
further information on power up/down sequence, please consult the TPS65218 datasheet, click
here.
Figure 22 – Power Sequence Detail
TPS65218 Passive Design and Component Selection
Output Filter Design
The step down converters (DCDC1, DCDC2, and DCDC3) on TPS65218 are designed to
operate with effective inductance values in the range of 1.0µH to 2.2µH and with effective output
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capacitance in the range of 10µF to 100µF The internal compensation is optimized to operate
with an output filter of L = 1.5µH and Cout = 10µF.
The buck boost converter (DCDC4) on TPS65218 is designed to operate with effective
inductance values in the range of 1.2µH to 2.2µH. The internal compensation is optimized to
operate with an output filter of L = 1.5µH and Cout = 47µF.
The two battery backup converters (DCDC5 and DCDC6) are designed to operate with effective
inductance values in the range of 4.7µH to 22µH.
The internal compensation is optimized with an output filter of L = 10µH and Cout = 20µF.
Larger or smaller inductor/capacitance values can be used to optimize performance of the device
for specific operation conditions.
Inductor Selection for Buck Converters
The inductor value affects its peak to peak ripple current, the PWM to PFM transition point, the
output voltage ripple, and the efficiency. The selected inductor must be rated for its DC
resistance and saturation current. The inductor ripple current (∆L) decreases with higher
inductance and increases with higher Vin or Vout. Equation 1 calculates the MAXimum inductor
current ripple under static load conditions. The saturation current of the inductor should be rated
higher than the Maximum inductor current as calculated with Equation 2. This is recommended
as during heavy load transient the inductor current will rise above the calculated value.
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The following inductors have been used with the TPS65218:
PART NUMBER
VALUE
SIZE (MM)
MANUFACTURER
INDUCTORS FOR DCDC1, DCDC2, DCDC3, DCDC4
1.5 µH, 2.8 A, 77
SPM3012T-1R5M
3.2 x 3.0 x 1.2 (LxWxH)
mΩ
1.5 µH, 4.0 A, 28.5
IHLP1212BZER1R5M11
3.6 x 3.0 x 2.0 (LxWxH)
mΩ
INDUCTORS FOR DCDC5, DCDC6
10 µH, 110 mA, 300
2012 / 0805 (2.00 x
MLZ2012N100L
mΩ
1.25 x 1.25 LxWxH)
Vishay
10 µH, 100 mA, 300
mΩ
Murata
LQM21FN100M80
2012 / 0805 (2.00 x
1.25 x 1.25 LxWxH)
TDK
TDK
Output Capacitor Selection
The hysteretic PWM control scheme of the TPS65218 switching converters allows the use of tiny
ceramic capacitors. Ceramic capacitors with low ESR values have the lowest output voltage
ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric.
At light load currents the converter operates in Power Save Mode, and the output voltage ripple
is dependent on the output capacitor value and the PFM peak inductor current. Higher output
capacitor values minimize the voltage ripple in PFM Mode and tighten DC output accuracy in
PFM Mode.
The two battery backup converters (DCDC5 and DCDC6) always operate in PFM mode. For
these converters at least 20 uF is recommended on the output to help minimize voltage ripple.
The Buck-Boost converter requires additional output capacitance to help maintain converter
stability during high load conditions. At least 40 uF of output capacitance is recommended and
an additional 100 nF capacitor can be added to further filter output ripple.
Power Supply Recommendations
The device is designed to operate with an input voltage supply range between 2.7V and 5.5V.
This input supply can be from a single cell Li-Ion battery or other externally regulated supply. If
the input supply is located more than a few inches from the TPS65218 additional bulk
capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 47uF is a typical choice. The coin cell back up input is designed to
operate with a input voltage supply between 2.2V and 3.3V This input should be supplied by a
coin cell battery with 3V nominal voltage.
Layout Guidelines
The IN_X pins should be bypassed to ground with a low ESR ceramic bypass capacitor.
The typical recommended bypass capacitance is 4.7-µF with a X5R or X7R dielectric.
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The optimum placement is closest to the IN_X pins of the device. Care should be taken to
minimize the loop area formed by the bypass capacitor connection, the IN_X pin, and the
Power Pad of the device.
The Power Pad should be tied to the PCB ground plane with multiple vias.
The LX trace should be kept on the PCB top layer and free of any vias.
The FBX traces should be routed away from any potential noise source to avoid coupling.
DCDC4 Output capacitance should be placed immediately at the DCDC4 pin. Excessive
distance between the capacitance and DCDC4 pin may cause poor converter
performance.
Layout Example
Figure 23 – Layout Example
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QFN Package Information
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QFP Package Information
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