Application Note

Application Note
General Biasing Considerations for AWB, AWM
and AWT Series of Power Amplifier Modules
Rev 0
Relevant products
•AWT6264
•AWT6283
•
•
AWM6268
AWB Series PAs
Topics Covered
VREF Biasing
VCC1/VCC2 and VREF RF Sequencing
VREF Switching
VATT Biasing and Termination
VDET Termination
Measuring On/Off Switching Speed
VREF BIASING
ANADIGICS’ lineup of 3G/4G LTE/WiMAX/WCDMA
Power Amplifier Modules (PAMs) incorporate a
reference voltage, “VREF,” which is an external bias
voltage independent of the nominal VCC1/VCC2 supplies.
The VREF is used to place the amplifier module into
either the “active” or the “idle” state, and to set the
operating points of the amplifier’s constituent gain
stages. This section reviews the general guidelines
that should be followed with respect to biasing the
VREF, and discusses the effect of variations in VREF bias
magnitude on overall amplifier performance.
The internal bias points for each amplifier part number
must be set differently, due to the wide range of
operating frequencies and output power levels that
are supported by the product portfolio. Please consult
the appropriate data sheet for the range of VCC1/VCC2
and VREF voltages that are recommended for a specific
device. Data sheets also contain information regarding
the nominal reference current “IREF” consumed by each
product’s VREF circuit.
Achieving the optimum linearity, gain, and efficiency at
the specified level of output power is predicated upon
maintaining the proper biasing at both the VCC and the
VREF ports. Performance will be compromised if the
magnitude of the VREF voltage is allowed to deviate
outside of the recommended range. A lower-than
specified VREF voltage will result in abnormally low
current consumption which may cause degradation in
the device performance, especially over the operating
temperature range.
In fact, it is strongly advised that the magnitude of VREF
should never be allowed to fall below 2.80Vdc under
any circumstances. Conversely, an excessively high
VREF will over-stress the amplifiers and reduce their
operational lifetimes. Figures 1 thru 4 depict typical
variations in EVM, Spectrum Mask (SM), Spectrum
Emission Mask (SEM), and ICC/Efficiency that result
as the VREF is adjusted over the range from 2.70Vdc
to 3.00Vdc at a temperature of +25 °C. Note that the
excursions in linearity performance will be greater at
reduced or elevated operating temperatures if the
VREF is not precisely controlled. In addition, the VREF
voltage is the primary determinant that governs the
device’s overall current consumption.
VCC1/VCC2 & VREF SEQUENCING
Power-up and power-down sequencing
recommendations must be followed to avoid damage
to the PA Module. Power-up is initiated by applying
the specified DC voltage to VCC1/VCC2 with the VREF
bias at 0V. Next, the bias voltage is applied to VREF.
RF Drive is applied during the duration of time that
the VREF is active.
Power-down is performed in reverse. First, the
RF Drive is disabled. Next, the VREF bias voltage
is disabled. And, finally, the VCC1/VCC2 voltage is
removed. Alternatively, the PA Module may be
powered-down by removing the bias from V REF
while maintaining the voltage at VCC1/VCC2. Under no
circumstances should VREF be applied when no voltage
is present at VCC1/VCC2.
VREF SWITCHING
Dynamic switching of the amplifier module between
the “active” state and the “idle” state is accomplished
by switching the magnitude of the bias voltage
applied to the VREF pin. The “active” state voltage
is equivalent to the normal operating VREF voltage
(2.85Vdc) referenced above. The nominal required
“idle” state voltage is 0.0Vdc with a maximum level
of 0.5Vdc allowed.
Each ANADIGICS Power Amplifier Module Evaluation
Board (EVB) assembly is supplied with a large-value
bypass capacitor (0.1uF) that is attached from the VREF
12/2012
General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
4.5
4.0
EVM (%)
3.5
3.0
2.75V
3.00V
2.71V
2.90V
2.85V
2.80V
2.5
2.0
1.5
2.500
2.525
2.550
2.575
2.600
2.625
FREQUENCY (GHz)
2.650
2.675
2.700
Figure 1: Typical EVM as a function of VREF at +25 °C
-45
SPECTRUM MASK (dBc)
2.71V
2.90V
-47
2.85V
-49
-51
-53
-55
-57
-59
-61
-63
-10
-5
0
5
OFFSET (MHz)
Figure 2: Typical SPECTRUM MASK as a function of VREF at +25 °C
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Application Note - Rev 0
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
-15
-20
2.70V
2.75V
SEM (dBm)
-25
-30
2.85V
2.90V
-35
3.00V
-40
-F
-E
-D
-C
-B
-A
+A
OFFSET
+B
+C
+D
+E
+F
Figure 3: Typical SPECTRUM EMISSION MASK as a function of VREF at +25 °C
425
27
400
25
ICC (mA)
375
23
2.85V
2.71V
350
21
325
19
2.71V
2.85V
2.90V
300
275
2.11
2.12
2.13
2.14
17
2.15
2.16
15
2.17
FREQUENCY (GHz)
Figure 4: Typical ICC/EFFICIENCY as a function of VREF at +25 °C
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EFFICIENCY (%)
2.90V
General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
pin to ground. This amount of bypassing/filtering is
desirable when operating the amplifier in a steady-state
mode during initial amplifier evaluation and system
calibration. However, all reactive elements must be
removed from the VREF pin if dynamic operation is
to be implemented, especially if operation in a TDD
Wireless System is to be implemented.
It is recommended that a well-regulated voltage be
applied to the VREF. A simple resistive divider is not
recommended due to the variation in resistance as
well as the current through the VREF pin over extended
operating temperature. The current that must be
sourced to the VREF pin varies with each amplifier type
and is within a range of 3mA to 15mA.
Most generally available Wireless Transceiver chips
incorporate an optional regulated output voltage
designated as “AMPLIFIER BIAS”, “PA BIAS”, or
equivalent. An internal DAC combines with an LDO
to generate the desired magnitudes of voltage and
current and is programmable in conjunction with the
other transceiver functions. Dynamic switching of
the amplifier bias including turn-on and turn-off delay
intervals are user-programmable as well.
However, not all Wireless Transceiver chips are
capable of sourcing the appropriate amount of current
that is necessary to drive the VREF. An alternative
option is to incorporate a dedicated voltage regulator in
combination with a switching transistor. This approach
is illustrated below in Figures 5 - 6 and Table 1 that
depict the schematic, bill-of-materials, input/output
transfer function, and VREF voltage over temperature.
The worst-case switching speed of this circuit has been
verified to be 100nSec with a current load of 20mA,
and the stability of the VREF voltage is within +/-20mV
from -55 °C to +100 °C. Note that the TXEN must be
pulled “low” to enable the amplifier according to the
Truth Table contained within the schematic diagram.
A “floating” TXEN forces the amplifier to a disabled
condition.
Circuit Considerations
The NATIONAL LP2980-ADJ voltage regulator is
designed as a low-dropout/low-noise adjustableoutput unit. The value of regulator output voltage
is determined by the combination of R1 and R2 as
defined by the equation published in the data sheet.
The R1/R2 voltage divider result is fed back into the
regulator (pin 4) and compared to an internal voltage
2.875
2.870
2.865
VREF (Vdc)
2.860
2.855
2.850
2.845
2.840
2.835
2.830
2.825
-55 -45 -35 -25 -15
-5
5 15 25 35 45
Temperature (degC)
55
65
75
85
95 105
Figure 5: External VREF Switching Circuit Voltage over Temperature
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
VCC2
3.3V
TRUTH TABLE
TXEN
VREF
L
H
2.85V
0V
C1
1uF
+
VREF
R4
560
LP2980-ADJ
1 V
IN
3
VCC1
U1
VOUT
ON/OFF
GND
VADJ
2
4
3
Q1
NTK3139P
1
2
5
C2 7pF
R3
R1
360k
+
68.1k
C3
4.7uF
R2
49.9k
TXEN
Figure 6: External High Current VREF Switching Circuit
Ref.
Desig.
Value
EIA
Footprint
Manufacturer
Manufacturer P/N
Description
C1
1uF
0402
MURATA
GRM155R60J105KE19D
CAP ML CER 1uF 6.3V X5R 0402
C2
7pF
0201
MURATA
GRM0335C1E7R0DD01D
CAP ML CER 7pF 25V C0G 0201
C3
4.7uF
1206
VISHAY/SPRAGUE
TR3A475K010C1000
CAP TANT 4.7uF 10V 1206
R1
68.1k
0201
VISHAY/DALE
CRCW020168K1FKED
RES THK FLM 1% 68.1K 0201
1/20W
R2
49.9k
0201
VISHAY/DALE
CRCW020149K9FKED
RES THK FLM 1% 49.9K 0201
1/20W
R3
360k
0201
ROHM
MCR006YZPJ364
RES THK FLM 5% 360K 0201
1/20W
R4
560
0201
ROHM
MCR006YZPJ561
RES THK FLM 5% 560 0201
1/20W
Q1
NTK3139P
SOT-723
ON
SEMICONDUCTOR
NTK3139P
MOSFET, P-CHANNEL
NATIONAL
LP2980IM5-ADJ/NOPB
V REG, LDO, 50mA,
ADJUSTABLE
U1
LP2980-ADJ SOT-23 (5L)
Table 1: External High Current VREF Switching Circuit Bill-of-Materials
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
reference. It is recommended that high-precision 1%
tolerance resistors be used for R1 and R2 to facilitate
proper adjustment of the output voltage.
The ON NTK3139P MOSFET is selected as the
best available compromise of package size, power
dissipation capability, turn-on threshold, and switching
speed. Note that a small but discernable voltage drop
will be present across the MOSFET. Therefore, the final
values of R1 and R2 should be determined from the
voltage as measured at pin 3 (drain) of the MOSFET
and not pin 5 of the voltage regulator.
Capacitive elements (C1, C2, C3) are as-recommended
in the voltage regulator data sheet. They should be
located as close to the voltage regulator as possible.
Special attention must be given to the composition of
capacitor C3. A high-quality solid tantalum capacitor
must be used because its characteristic ESR (effective
series resistance) is approximately 1Ω. This resistance
is recommended to maintain voltage regulator stability.
A ceramic capacitor characterized by an ultra-low
series resistance (50mΩ) may be substituted for a
solid tantalum capacitor only if a 1Ω series resistor is
installed as well.
Resistor R3 (360kΩ) serves as a “pull-up” element to
maintain a nominal gate-to-source voltage in the event
that the TXEN is allowed to float. Resistor R4 (560Ω)
provides a termination for the MOSFET drain during
high-speed dynamic switching while adding only 5mA
to the total current consumption.
VATT BIASING and TERMINATION
Some PA modules incorporate a 20dB attenuator
that can be enabled via the VATT pin. The attenuator
is activated when a logic level “high” is applied to
VATT. The VATT must be pulled to a logic level “low” to
disable the attenuator during normal operation. The
VATT must be biased either “high” or “low” at all times
and must not be allowed to “float” because stray noise,
transients, or a random lock-up condition may induce
unintended attenuator activation. It is recommended
6
that the VATT pin be grounded through a 100kΩ resistor
if the Attenuator function is not being utilized.
VDET TERMINATION
Various PA modules feature an internal “detector”
circuit that generates a DC voltage whose magnitude
is proportional to the RF Output signal level. This
section of the application note reviews the general
guidelines that should be followed to enable proper
detector functionality.
Theory of Operation
The internal detector circuit samples and rectifies a
small portion of the RF Output waveform. The resultant
pseudo-DC voltage is available via a pin designated
as “VDET”. The voltage is conditioned by an externallyapplied circuit as described below.
External Termination Circuit
A simple passive RC “termination network” is
connected to the VDET pin, as shown in Figure 7,
to filter ripple and other perturbations that may be
present in the output voltage. The resulting curve of
VDET voltage as a function of the RF output power is
graphed in Figure 8.
The elemental values yield a large RC Time Constant
that is suited to eliminating low-frequency noise.
This characteristic is desirable when operating the
amplifier in a steady-state mode during initial amplifier
evaluation and system calibration.
However, it may be necessary to evaluate the
VDET output when the amplifier is being operated
dynamically in a “burst-mode” in a TDD system. In this
condition the RF Output (via the Vref or VENABLE pin) is
actively switched very rapidly between the “on” and the
“off” states at a rate that may exceed the response-time
of the VDET termination circuit. Dynamic testing can be
accomplished by modifying the component values to
yield a lower RC time-constant for a faster response
time. The recommended circuit diagram shown in
Figure 9 satisfies this requirement.
Application Note - Rev 0
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
Figure 7: Standard VDET Circuit (as Published in Datasheets)
1.40
Vdet vs Pout
1.35
Vdet (Vdc)
1.30
1.25
1.20
1.15
1.10
1.05
1.00
20
21
22
23
24
25
26
27
28
Pout (dBm)
Figure 8: Typical VDET Voltage Versus RF Output Power
Switching Times
Equations 1.0 and 1.1 define the percentage (%) of the
final voltage value that is present in an RC network as
a function of the quantity of time-constants that have
elapsed. Equation 1.0 is associated with a “charging”
condition and equation 1.1 represents the “discharging”
condition.
Equation 1.0: Charging % = 100(1 – e –t/RC)
Equation 1.1: Discharging % = 100e –t/RC
When Equations 1.0 and 1.1 are graphed, as in Figures
10 and 11, it can be seen that the time required to either
charge or discharge the voltage of an RC network
to within 1% of its terminal value is approximately 4
time-constants (4t). The total expected charge or
discharge times for each of the two external circuits are
listed in the lower-left hand corner of Figures 7 and 9.
The recommended resistor and capacitor values are
a compromise between minimal response-time and
adequate DC filtering.
Where R is the resistance in Ω, C is the capacitance
in Farads, and t is the quantity of Time-constants.
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
Figure 9: VDET Circuit Modified for Faster Response Time
100
Percent of Final Charge (%)
90
80
70
60
50
40
30
20
10
0
0
1
2
3
RC Time Constants (t)
Figure 10: % = 100(1 – e –t/RC)
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4
5
General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
100
Percent of Discharge (%)
90
80
70
60
50
40
30
20
10
0
0
1
2
3
4
5
RC Time Constants (t)
Figure 11: % = 100e –t/RC
Floating VDET pin:
The VDET output pin must be terminated at all times
and not be allowed to “float”. Failure to terminate
this pin may induce unpredictable and undesirable
behavior. For example, the magnitude of the resultant
VDET voltage may not be reliable and consistent,
especially over the permissible ranges of ambient
operating temperature and output load impedance,
and at elevated levels of output power. It is possible
for the polarity of the VDET voltage to reverse itself and
become “negative” at elevated levels of output power,
if the VDET output pin is not properly terminated.
In addition, externally coupled stray noise impulses
may propagate into the amplifier stages from the VDET
pin and modulate the RF output waveform thereby
causing degradation in the linearity performance. As
the internal VDET circuit has a limited amount of forward
and reverse isolation, it is recommended that a single
resistive termination (100kΩ) be implemented as
shown in Figure 12 if the VDET function is not required.
VREF Voltage Effects on VDET:
The internal VDET circuit derives its DC biasing from
the VREF supply voltage. Therefore, the recommended
value of VREF voltage, as published in the data sheet,
should be maintained to within +/-1.8% whenever
possible. Excessive deviations in the VREF voltage
9
may decrease the accuracy of the VDET voltage, as
well as degrade the nominal linearity performance of
the RF amplifier.
Amplifier Response Time:
Although the RF Output waveform is sampled by the
detector circuit during normal operation, the VDET output
should not be utilized as a direct monitoring point or as a
test point for characterization of the slew-rate of the RF
Output waveform when the amplifier is cycled between
the “on” and the “off” states. Internal propagation
delays artificially lengthen the observed settling time
of the RF output waveform. It is recommended that
a signal analyzer of sufficient bandwidth be used to
directly evaluate the performance of the RF amplifier
section in the time-domain.
Closed-loop Power Control:
The overall accuracy of the VDET output voltage
may be influenced by non-optimal values of load
impedance presented to the amplifier RF Output port.
The VDET circuit is passive in nature and hence the
overall directivity is limited. It responds equally well
to both forward and reflected power. Hence, it is not
recommended that the VDET voltage be used as the
primary driver in a closed-loop feedback power control
circuit.
Application Note - Rev 0
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
VDET
(IC pin)
100k
Figure 12: Recommended Termination for Unused VDET
MEASURING ON/OFF SWITCHING SPEED
The Switching Speed is defined as the time that
elapses between the initial application of control
voltage into the VREF and the instance at which the
detected RF envelope completes the transition from
10% to 90% of its final value as shown in Figure 13. It
is recommended, for best accuracy, to use an external
high-speed, wide-bandwidth detector such as the
ANALOG DEVICES AD8318 for this measurement
as outlined in the Block Diagram in Figure 14A. The
internal VDET circuit can be used as shown in Figure
14B if an external detector is unavailable; however,
the VDET lacks the necessary bandwidth to generate
an accurate response-time profile. Therefore, it is
recommended that the V DET pin not be used for
Switching Speed measurements.
The Switching Speed characterization of an AWB7227
is illustrated in Figures 15 and 16 as an example of
the typical detected on/off waveforms that can be
2.85V
2.57V
90% V CONTROL
V CONTROL
0.00V
90% RF
DETECTED 10% RF
RF ENVELOPE
TON
TOFF
Figure 13: Waveform Definitions
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
expected with the ANADIGICS PA Modules. The
upper trace represents the detected waveform.
The waveform polarity in Figures 15A and 16A are
inverted due the design of the AD8318. The lower
trace represents the driving square wave. Note the
differences in response times between the internal
VDET and the external detector. The external switching
circuit previously presented in Figure 6 may be used
as a buffer between the Waveform Generator and
the VREF if it is determined that the generator lacks
sufficient current-sourcing capability to drive the load
presented by the VREF circuit.
The values of the external components terminating the
VDET and the VREF pins must be verified as outlined in
previous sections prior to commencing the Switching
Speed measurement. Specifically, the external VDET
circuit must be modified for dynamic operation. In
addition, all bypass capacitors must be removed from
the VREF.
Function Generator
20dB power
attn pads
Vref
RFin
cw signal
@2.14GHz
Out
EVB
w/ modifications
Frequency: 100Hz
Duty cycle: 50%
Waveform: Square pulses
Amplitude: 2.85V measured at
oscilloscope
Sync
RFin RFout
AD8318 RF detector
with rise/fall time
of 10 to 12 nsec
RFout
Ch1
Ch2
Ext Trig
Oscilloscope
Figure 14A: Switching Speed Test Setup using External Detector (Recommended)
Function Generator
Out
RFin
cw signal
@ 2.14GHz
Vref
RFout
Pout = +28dBm
@ Vcc = 4.5V
EVB
w/ modifications
Vdet
Ch1
Oscilloscope
Frequency: 100Hz
Duty cycle: 50%
Waveform: Square pulses
Amplitude: 2.85V measured at
oscilloscope
Sync
Ch2
Ext Trig
Figure 14B: Switching Speed Test Setup using Internal VDET (Not Recommended)
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
Figure 15A: “Off-to-On” Switching Speed using External Detector (Recommended)
Figure 15B: “Off-to-On” Switching Speed using Internal VDET (Not Recommended)
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
Figure 16A: “On-to-Off” Switching Speed using External Detector (Recommended)
Figure 16B: “On-to-Off” Switching Speed using Internal VDET (Not Recommended)
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General Biasing Considerations for AWB, AWM and AWT Series of Power Amplifier Modules
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
warning
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
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