DLP-HS-FPGA LEAD-FREE USB - FPGA MODULE (PRELIMINARY) FEATURES: • • • • • • • • • Xilinx XC3S200A-4FTG256C FPGA Micron 32M x 8 DDR2 SDRAM Memory Built-In Configuration Loader; Writes the Bit File Directly to SPI Flash via High-Speed USB 2.0 Interface 63 User I/O Channels: 24 Differential Pairs and 8 Global Clocks 66 MHz Oscillator 133 MHz DDR2 Interface Reference Design Provided USB Port Powered or 5V External Power Barrel Jack USB 1.1 and 2.0 Compatible Interface Small Footprint: 3.0 x 1.2 Inch PCB and Standard 50-Pin, 0.9-Inch DIP Interface Rev. 1.4 (June 2010) 1 © DLP Design, Inc. APPLICATIONS: • • • • • Rapid Prototyping Educational Tool Industrial/Process Control Data Acquisition/Processing Embedded Processor 1.0 INTRODUCTION The DLP-HS-FPGA module is a low-cost, compact prototyping tool that can be used for rapid proof of concept or within educational environments. The module is based on the Xilinx Spartan™ 3A and Future Technology Devices International’s FT2232H Dual-Channel High-Speed USB IC. The DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to developing FPGA-based designs. When combined with the free ISE™ WebPACK™ tools from Xilinx, this module is more than sufficient for creating anything from basic logical functions to a highly complex system controller. As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files directly to the SPI Flash—no external programmer is required. This represents a savings of as much as $200 in that no additional programming cable is required for configuring the FPGA. All that is needed to load bit files to the DLP-HS-FPGA is a Windows software utility (free with purchase), a Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool environment using a Xilinx programming cable (purchased separately). The DLP-HS-FPGA is fully compatible with the free ISE™ WebPACK™ tools from Xilinx. ISE WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and simulation, implementation, device fitting and JTAG programming. The DLP-HS-FPGA has on-board voltage regulators that generate all required power supply voltages from a single 5-volt source. Power for the module can be taken from either the host USB port or from a user-supplied, external 5-volt power supply via an onboard standard barrel connector. Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025 square inch post DIP header on the bottom of the board, and a 26-pin, 0.05-inch wide top side 2x13 header. The bottom side 50-pin header provides access to 41 of the FPGA user input/output pins. The top side header provides access to 22 of the FPGA user input/output pins. The bottom side header mates with a user-supplied standard 50-pin, 0.9-inch spaced DIP socket. The top side header mates with a user-supplied 0.05-inch spaced 2x13 connector such as the FFSD-13-D-xx.xx-01 (xx.xx = cable length) ribbon cable assembly from Samtec. Rev. 1.4 (June 2010) 2 © DLP Design, Inc. DIP Socket Ribbon Cable Other on-board features include a 32M x 8 DDR2 SDRAM memory IC for user projects and both JTAG and SPI Flash interface ports for connection to Xilinx programming tools. 2.0 REFERENCE DESIGN A 10,000-line reference design is available for the Spartan™ 3A FPGA on the DLP-HS-FPGA to those who purchase the module. The design was written in VHDL and built using the free Xilinx ISE™ WebPACK™ tools. The reference design consists of the following blocks: It contains a USB Interface Block, a User I/0 Block, a DDR2 SDRAM interface, a Heartbeat Pulse Generator and a Clock Generator. The SPI Flash is used to store the design’s FPGA configuration file. The USB interface captures, interprets and returns command and data information sent from the host PC through the FTDI USB interface to the FPGA. Commands include Ping, Return Status, Loopback Data, Set a User I/O Pin High or Low, Read a User I/O Pin, Initialize the DDR2 SDRAM Memory and Read or Write the DDR2 SDRAM Memory. (Section 11 explains these in detail.) The User I/O Block controls access to the 63 user I/O pins accessible through the top and bottom side headers. Every one of these pins can be either an input or an output. The User I/O Block can configure these pins as inputs and read their state, or as outputs and drive them high or low. (As a Rev. 1.4 (June 2010) 3 © DLP Design, Inc. side note, 48 of these user I/O pins can be configured as 24 differential pairs, 8 can be configured as global clock inputs and 6 can be configured as regional clock inputs.) The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle and the read and write access. Read and write access is available in 4-byte bursts. The traces between the DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at 266 Mbit/s (clocked at 133MHz). The interface creates and aligns the Data Strobes (DQS) based on an external feedback trace that matches two times the trace length between the FPGA and the DDR2 SDRAM. The Initialization, Read, and Write commands are initiated by the USB interface block and executed by the DDR2 SDRAM interface block. The Heartbeat Pulse Generator takes the internal system clock and divides it down so that the onboard Heartbeat LED will be turned on and off for a duration of approximately one-half second. The Clock Generator Block receives the 66-MHz clock and produces both the 133-MHz clocks required to run the DDR2 SDRAM memory device and the 100-MHz clock for the remaining internal logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks. The design occupies the following FPGA resources: More reference designs are planned. Please contact DLP Design with any specific requests. 3.0 FPGA SPECIFICATIONS The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan™ 3A: XC3S200A-4FTG256 Rev. 1.4 (June 2010) 4 © DLP Design, Inc. • • • Part Number: System Gates: Equivalent Logic Cells: • CLB Array: • • • • XC3S200A-4FTG256C 200,000 4,032 Rows: Columns: Total CLB’s: Total Slices: Total Flip Flops: Total 4-Input LUT’s: 32 16 448 1,792 3,584 3,584 Distributed RAM Bits: Block RAM Bits: Dedicated Multipliers: DCM’s: 28K 288K 16 4 The DLP-HS-FPGA was designed with pin migration in mind for the Xilinx Spartan™ 3A family FPGA’s using the FTG256 package. The larger Xilinx Spartan™ 3A family FPGA that will work on the current PCB design is the XC3S400A. Contact DLP Design for details. 4.0 ABSOLUTE MAXIMUM RATINGS Stresses above those listed here may cause permanent damage to the DLP-HS-FPGA: Operating Temperature: 0-70°C Voltage on Digital Inputs with Respect to Ground: -0.5V to +4.1 V Sink/Source Current on Any I/O: 24 mA (using LVTTL as the FPGA I/O standard) 5.0 WARNINGS • Unplug from the host PC and power adapter before connecting to I/O on the DLP-HS-FPGA. • Isolate the bottom of the board from all conductive surfaces. • Observe static precautions to prevent damage to the DLP-HS-FPGA module. 6.0 BITLOADAPP SOFTWARE Windows software is provided for use with the DLP-HS-FPGA that will load an FPGA configuration (*.bit) file directly to the SPI Flash device via the USB interface. This application (illustrated below) will allow the user to erase the flash, verify the erasure and then program and verify the flash: Rev. 1.4 (June 2010) 5 © DLP Design, Inc. 7.0 JTAG INTERFACE The easiest way to load an FPGA configuration (*.bit) file to the FPGA is to run the BitLoadApp software, then select and program a file from the local hard drive directly to the SPI Flash. Once written to the SPI Flash, the configuration will load to the FPGA and execute. Alternatively, a traditional JTAG header location is provided on the DLP-HS-FPGA giving the user access to the specific pins required by the development tools. (Refer to the schematic contained within this datasheet for details.) 8.0 EEPROM SETUP / MPROG The DLP-HS-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively to load an FPGA configuration (*.bit) file to the SPI Flash. This configuration data is automatically transferred to the FPGA when power is applied to the module or when the PROG Pin is driven low and then released by the application software. Channel B is used for communication between the FPGA and host PC at run time. A 93LC56B EEPROM connected to the USB interface IC is used to store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID (VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX) and port type (UART serial or FIFO parallel). As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI Flash, and Channel B is used for communication between the host PC and the DLP-HS-FPGA. As such, the D2XX drivers and 245 FIFO mode must be selected in the EEPROM for Channel A. Channel B must use the 245 FIFO mode, but can use either the VCP or D2XX drivers. The VCP drivers make the DLP-HS-FPGA appear as an RS232 port to the host application. The D2XX drivers provide faster throughput, but require working with a *.lib or *.dll library in the host application. The operational modes and other EEPROM selections are written to the EEPROM using the MPROG utility. This utility and its manual are available for download from the bottom of the page at www.dlpdesign.com. Rev. 1.4 (June 2010) 6 © DLP Design, Inc. 9.0 TEST BIT FILE A test file is provided as a download from the DLP Design website that provides rudimentary access to the I/O features of the DLP-HS-FPGA. The following features are provided: • Ping • Read the High/Low State of the Input-Only Pins • Drive I/O Pins High/Low or Read their High/Low State • Simple Loopback on Channel B • 4 Byte Read/Write Access of Row, Column, and Bank Address in the DDR2 SDRAM This bit file is available from the DLP-HS-FPGA’s download page. The command structure that supports these features is explained in Section 11. 10.0 USB DRIVERS USB drivers for the following operating systems are available for download from the DLP Design website at www.dlpdesign.com: OPERATING SYSTEM SUPPORT Windows Vista, Vista x64 Mac OSX Windows XP, XP x64 Mac OS9 Windows Server 2008, x64 Mac OS8 Windows Server 2003, x64 Linux Windows 2000 Windows CE 4.2 – 6.0 Notes: 1. The bit file load utility only runs on the Windows platforms. 2. The bit file load utility requires the use of USB channel A, and channel A is dedicated to this function. 3. If you are utilizing the dual-mode drivers from FTDI (CDM2.x.x) and you want to use the Virtual COM Port (VCP) drivers, then it may be necessary to disable the D2XX drivers first via Device Manager. To do so, right click on the entry under USB Controllers that appears when the DLP-HS-FPGA is connected, select Properties, select the Advanced tab, check the option for “Load VCP” and click OK. Then unplug and replug the DLP-HS-FPGA, and a COM port should appear in Device Manager under Ports (COM & LPT). Rev. 1.4 (June 2010) 7 © DLP Design, Inc. 11.0 USING THE DLP-HS-FPGA Select a power source via Header Pins 23 and 24, and connect the DLP-HS-FPGA to the PC to initiate the loading of USB drivers. The easiest way to do this is to connect Pins 23 and 24 to each other. This will result in operational power being taken from the host PC. Once the drivers are loaded, the DLP-HS-FPGA is ready for use. Simply connect the DLP-HS-FPGA to the PC to initiate the loading of USB drivers. Once the USB drivers are loaded, the DLP-HS-FPGA is ready for use. All commands are issued as multi-byte command packets consisting of at least two bytes. You can either utilize the Test Application available from http://www.dlpdesign.com/test.shtml with the DLP-HS-FPGA (as described in Section 12), or you can write your own program in your language of choice. If you are using the VCP drivers, begin by opening the COM port, and send multi-byte commands as shown in Table 1 below. There is no need to set the baud rate because the DLP-HS-FPGA uses a parallel interface between the USB IC and the FPGA. (The Ping Command can be used to locate the correct COM port used for communicating with the DLP-HS-FPGA, or you can look in Device Rev. 1.4 (June 2010) 8 © DLP Design, Inc. Manager to see which port was assigned by Windows.) If you are using the D2XX drivers as with the Test Application, no COM port selection is necessary. TABLE 1 Command Packets Command Packet Ping Description Issues Ping Byte 0 Read Version/ Status Accesses the internal version/ status registers 0 1 Loopback Returns the data byte received Returns the compliment of data byte received Reads the state of one of the user I/O pins 0 1 Loopback Compliment Read Pin Clear Pin Set Pin Initialize Memory Forces the selected user I/O pin low Forces the selected user I/O pin high Initializes DDR2 SDRAM Rev. 1.4 (June 2010) 0 1 Hex Value Return/Comments 0x00 Ping Command - 0x56 will be returned indicating that the DLP-HS-FPGA is found on the selected port 0x10 Read Version/Status Registers Command 0xnn Register Address: 0xnn = 0x00 = Board ID (0x11 = Revision 1.1) 0x01 = FPGA Type ID (0x3A = Spartan™ 3A) 0x02 = Design Version ID 1 (0x09 = September) 0x03 = Design Version ID 2 (0x01 = Day) 0x04 = Design Version ID 3 (0x09 = Year) 0x05 = Design Version ID 4 (0xA1 = Version A1) 0x06 = DDR2 Status: 0x00 = Not Initialized 0x01 = Initialized 0x20 Loopback Command 0xnn The byte sent to the DLP-HS-FPGA (0xnn) will be returned back 0x21 Loopback Compliment Command 0xnn The byte sent to the DLP-HS-FPGA (0xnn) will be complimented and returned back 0 1 0x30 0x00 – 0x3E 0 1 0x40 0x00 – 0x3E 0x41 0x00 – 0x3E 0x70 0 1 0 Read Pin Command The user I/O pin numbers are described in Table 2. User I/O pin 0xnn is read and returns: 0x00 = User I/O pin 0xnn is low 0x01 = User I/O pin 0xnn is high Clear Pin Command The user I/O pin numbers are described in Table 2. User I/O pin 0xnn is cleared. The specified user I/O number is returned. Set Pin Command The user I/O pin numbers are described in Table 2. User I/O pin 0xnn is set. The specified user I/O number is returned. The Initialize Memory Command configures the DDR2 SDRAM for access by the FPGA. The memory cannot be accessed without being initialized. 9 © DLP Design, Inc. Important Note on DDR2 SDRAM Data Access: DDR2 SDRAM data accesses using the reference design on the DLP-HS-FPGA module are always performed 4 bytes at a time due to the fact that the device is configured for a burst length of four. What this means is column address bits 0 and 1 only change the order of the read or write bytes, they still refer to the same 4 bytes. Therefore to increment the DDR2 SDRAM address for consecutive memory locations, the column address must be incremented by 4. Incrementing the column address by anything less than 4 simply changes the order that the 4 bytes specified by column address 9:3 are written to the memory, or returned to the user. For example a write to a column starting address of 0, will write to column locations 0,1,2, and 3. But if the user then writes to column address 1, they will actually be writing to column locations 1,2,3, and 0, which will overwrite the previous write operation. More details on how the DDR2 SDRAM column bits 1 and 0 function can be found in figure 4 and table 40 of the Micron™ MT47H32M8 datasheet. For details how the bank, row, and column bits are sent via USB to the memory, refer to the commands below. 0 0x8n Reads 4 bytes from the DDR2 SDRAM starting with the Memory Reads 4 address specified. The command byte is OR’d with the Read bytes from Most Significant Row Address Bit (24). the DDR n = 0 the Most Sig Row Address Bit is low (0x80) SDRAM n = 1 the Most Sig Row Address Bit is high (0x81) 1 0xah Bits 23-16 Middle 8 bits of Row Address to be read from 2 0xam Bits 15-12 Lower 4 bits of Row Address to be read from Bits 11-8 Upper 4 bits Column Address to be read from 3 0xal Bits 7-2: Lower 6 bits of column address to be read from NOTE: refer to text above regarding column bits 1 and 0 (equates to 0xal bits 3-2). Bits 1-0: Bank Address to be read from NOTE: If the memory has not been initialized, the data returned will be invalid and the command returned will be 0xE7 indicating the error. 0 0x9n Writes 4 bytes to the DDR2 SDRAM starting with the Memory Writes 4 address specified. The command byte is OR’d with the Write bytes to the Most Significant Row Address bit (24). DDR n = 0 the Most Sig Row Address bit is low (0x90) SDRAM n = 1 the most Sig Row Address bit is high (0x91) 1 0xah Bits 23-16 Middle 8 bits of Row Address to be written tp 2 0xam Bits 15-12 Lower 4 bits of Row Address to be written to Bits 11-8 Upper 4 bits Column Address to be written to 3 0xal Bits 7-2: Lower 6 bits of column address to be written to NOTE: refer to text above regarding column bits 1 and 0 (equates to 0xal bits 3-2). Bits 1-0: Bank Address to be written 10 4 0xd0 Data Byte 0 written to Address specified 5 0xd1 Data Byte 1 written to Address specified + 1 6 0xd2 Data Byte 2 written to Address specified + 2 7 0xd3 Data Byte 3 written to Address specified + 3 Returns the 4 bytes written followed by an echo back of the command and address data sent. NOTE: If the memory has not been initialized, the command returned will be 0xE7 indicating the error. Rev. 1.4 (June 2010) 10 © DLP Design, Inc. The USER I/O Pin Read/Set/Clear commands I/O number mapping to the physical I/O pins on the DLP-HS-FPGA board are described in the following table: TABLE 2 User I/O 0x00 (0) 0x01 (1) 0x02 (2) 0x03 (3) DLP-HSFPGA Pin J1 Pin 2 J1 Pin 3 J1 Pin 4 J1 Pin 5 XC3S200A Pin D13 C13 D11 C12 XC3S200A Bank 0 0 0 0 0x04 (4) J1 Pin 6 C10 0 0x05 (5) J1 Pin 7 D9 0 0x06 (6) J1 Pin 8 C8 0 0x07 (7) J1 Pin 9 D8 0 0x08 (8) 0x09 (9) 0x0A (10) 0x0B (11) 0x0C (12) 0x0D (13) J1 Pin 10 J1 Pin 12 J1 Pin 13 J1 Pin 14 J1 Pin 15 J1 Pin 16 A14 A13 A6 B6 C11 A11 0 0 0 0 0 0 0x0E (14) J1 Pin 17 B8 0 0x0F (15) J1 Pin 18 A8 0 0x10 (16) 0x11 (17) 0x12 (18) 0x13 (19) 0x14 (20) 0x15 (21) 0x16 (22) 0x17 (23) 0x18 (24) 0x19 (25) 0x1A (26) 0x1B (27) 0x1C (28) 0x1D (29) 0x1E (30) 0x1F (31) 0x20 (32) 0x21 (33) 0x22 (34) 0x23 (35) 0x24 (36) J1 Pin 19 J1 Pin 20 J1 Pin 21 J1 Pin 22 J1 Pin 27 J1 Pin 29 J1 Pin 30 J1 Pin 31 J1 Pin 32 J1 Pin 33 J1 Pin 34 J1 Pin 35 J1 Pin 36 J1 Pin 37 J1 Pin 38 J1 Pin 39 J1 Pin 41 J1 Pin 42 J1 Pin 43 J1 Pin 44 J1 Pin 45 C5 A5 B3 A3 F3 G4 C2 C1 E1 D1 J6 J4 H6 H5 M4 N3 E3 E2 H3 J3 K1 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 I/O Number Rev. 1.4 (June 2010) 11 FPGA Pin Configurations Available Digital Input, Output, Differential Pair 0+ Digital Input, Output, Differential Pair 0Digital Input, Output, Differential Pair 1Digital Input, Output, Differential Pair 1+ Digital Input, Output, Differential Pair 2+, Global Clock Digital Input, Output, Differential Pair 2-, Global Clock Digital Input, Output, Differential Pair 3+, Global Clock Digital Input, Output, Differential Pair 3-, Global Clock Digital Input, Output, Differential Pair 4+ Digital Input, Output, Differential Pair 4Digital Input, Output, Differential Pair 5+ Digital Input, Output, Differential Pair 5Digital Input, Output, Differential Pair 6+ Digital Input, Output, Differential Pair 6Digital Input, Output, Differential Pair 7-, Global Clock Digital Input, Output, Differential Pair 7+, Global Clock Digital Input, Output, Differential Pair 8Digital Input, Output, Differential Pair 8+ Digital Input, Output, Differential Pair 9Digital Input, Output, Differential Pair 9+ Digital Input, Output, Differential Pair 10+ Digital Input, Output, Differential Pair 10Digital Input, Output, Differential Pair 11+ Digital Input, Output, Differential Pair 11Digital Input, Output, Differential Pair 12Digital Input, Output, Differential Pair 12+ Digital Input, Output, Differential Pair 13Digital Input, Output, Differential Pair 13+ Digital Input, Output, Differential Pair 14+ Digital Input, Output, Differential Pair 14Digital Input, Output, Differential Pair 15Digital Input, Output, Differential Pair 15+ Digital Input, Output, Differential Pair 16+ Digital Input, Output, Differential Pair 16Digital Input, Output, Differential Pair 17+ Digital Input, Output, Differential Pair 17Digital Input, Output, Differential Pair 18-, © DLP Design, Inc. 0x25 (37) J1 Pin 46 K3 3 0x26 (38) 0x27 (39) 0x28 (40) 0x29 (41) 0x2A (42) 0x2B (43) 0x2C (44) 0x2D (45) 0x2E (46) 0x2F (47) 0x30 (48) 0x31 (49) 0x32 (50) 0x33 (51) 0x34 (52) 0x35 (53) 0x36 (54) 0x37 (55) 0x38 (56) 0x39 (57) 0x3A (58) 0x3B (59) 0x3C (60) 0x3D (61) 0x3E (62) SUSPEND AWAKE +5V IN +5V USB J1 Pin 47 J1 Pin 48 J1 Pin 49 J4 Pin 1 J4 Pin 3 J4 Pin 5 J4 Pin 7 J4 Pin 9 J4 Pin 11 J4 Pin 13 J4 Pin 15 J4 Pin 17 J4 Pin 19 J4 Pin 21 J4 Pin 2 J4 Pin 4 J4 Pin 6 J4 Pin 8 J4 Pin 10 J4 Pin 12 J4 Pin 14 J4 Pin 16 J4 Pin 18 J4 Pin 20 J4 Pin 22 J4 Pin 23 J4 Pin 24 J1 Pin 23 J1 Pin 24 J1 Pin 28, J4 Pin 26 J1 Pin 1, J1 Pin 11, J1 Pin 25, J1 Pin 26, J1 Pin 40, J1 Pin 50, J4 Pin 25 P1 N2 T9 B15 A12 B10 A10 A9 N1 E7 C4 C7 K4 R1 A7 A4 B4 F1 G1 H1 J1 L1 M1 M3 L4 R16 T11 - 3 3 2 0 0 0 0 0 3 0 0 0 3 3 0 0 0 3 3 3 3 3 3 3 3 1 2 - - - - - +3.3V OUT GND Rev. 1.4 (June 2010) 12 Regional Clock Digital Input, Output, Differential Pair 18+, Regional Clock Digital Input, Output, Differential Pair 19Digital Input, Output, Differential Pair 19+ Digital Input, Output, Global Clock Digital Input, Output Digital Input, Output Digital Input, Output, Differential Pair 20+ Digital Input, Output, Differential Pair 20Digital Input, Output, Global Clock Digital Input, Output Digital Input, Output Digital Input, Output Digital Input, Output Digital Input, Output Digital Input, Output Digital Input, Output Digital Input, Output, Differential Pair 21+ Digital Input, Output, Differential Pair 21Digital Input, Output, Differential Pair 22+ Digital Input, Output, Differential Pair 22Digital Input, Output, Regional Clock Digital Input, Output, Regional Clock Digital Input, Output Digital Input, Output Digital Input, Output, Differential Pair 23+ Digital Input, Output, Differential Pair 23Force Suspend Mode (when enabled) Return from Suspend Mode operation +5V input to the DLP-HS-FPGA +5V supplied by host PC USB port +3.3V supplied by the onboard DLP-HSFPGA regulator after module enumerated Ground © DLP Design, Inc. 12.0 USING THE DLP TEST APPLICATION (OPTIONAL) Users can design their own application interface to send USB commands to the DLP-HS-FPGA module or utilize the test application tool available from DLP Design. The DLP Test Application is available in a free version for download from the DLP Design website at www.dlpdesign.com/test.shtml. Using this tool, single- and multi-byte commands can be sent to the DLP-HS-FPGA board. Once installed the test application is used as follows: The commands used to interface to the DLP-HS-FPGA are detailed in Section 10 of this datasheet. Rev. 1.4 (June 2010) 13 © DLP Design, Inc. 13.0 MECHANICAL DIMENSIONS IN INCHES (MM) (PRELIMINARY) Rev. 1.4 (June 2010) 14 © DLP Design, Inc. 14.0 DISCLAIMER © DLP Design, Inc., 2000-2010 Neither the whole nor any part of the information contained herein nor the product described in this manual may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis, and no warranty as to their suitability for any particular purpose is either made or implied. DLP Design, Inc. will not accept any claim for damages whatsoever arising as a result of the use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. 15.0 CONTACT INFORMATION DLP Design, Inc. 1605 Roma Lane Allen, TX 75013 Phone: Fax: Email Sales: Email Support: Website URL: 469-964-8027 415-901-4859 [email protected] [email protected] http://www.dlpdesign.com Rev. 1.4 (June 2010) 15 © DLP Design, Inc. D 5 1 3 2 DC:+3.6 to +6.0V CN2 U3 1 2 3 4 DC BARREL JACK 5VIN PORTVCC R19 0 8 7 6 5 VCC NC NC/ORG GND 93LC46 R7 5V0 CS SK DIN DOUT 10K 5V0 2 C8 1.0uF/0603 D4 EECS EESK EEDATA 1 6 3 2 U2 NCP605-3.3V VIN VOUT VIN EN SENSE GND 4 5 C6 500 mA C4 C77 C2 4.7uF .1uF 3V3 .1uF P5V0 C3 .1uF R3 10K C12 27pF C11 27pF 4 C39 3V3 VPLL VPHY P1V8 13 3 2 63 62 61 7 8 14 6 49 50 TEST 1 FB2 240-1018-1 VPHY 3V3 3 FB3 240-1018-1 1 2 C26 2 .1uF C85 C25 C49 4.7uF C48 .1uF C33 C47 .1uF .1uF C46 .1uF 27 27 FTDI_D0 FTDI_D1 FTDI_D2 FTDI_D3 FTDI_D4 FTDI_D5 FTDI_D6 FTDI_D7 R16 R17 PWREN# 5V0 10K 5% R28 1 2.2K R24 VPLL 3V3 C9 .1uF D5 150 R13 UPLOAD R27 24.9K 1 Q2 IRLML6402 2 C17 0.1uF R32 RED Downloading FPGA Code 3 Q4 MMBT3904L 0 2 2 C18 0.1uF USER_IO0_DP0 USER_IO1_DN0 USER_IO2_DN1 USER_IO3_DP1 USER_IO4_DP2_GC USER_IO5_DN2_GC USER_IO6_DP3_GC USER_IO7_DN3_GC USER_IO8_DP4 USER_IO9_DN4 USER_IO10_DP5 USER_IO11_DN5 USER_IO12_DP6 USER_IO13_DN6 USER_IO14_DN7_GC USER_IO15_DP7_GC USER_IO16_DN8 USER_IO17_DP8 USER_IO18_DN9 USER_IO19_DP9 5VIN PORTVCC USER_IO41 USER_IO42 USER_IO43_DP20 USER_IO44_DN20 USER_IO45_GC USER_IO46 USER_IO47 USER_IO48 USER_IO49 USER_IO50 USER_IO51 FPGA_SUSPEND C19 10/10 Tant VCCSW SPI_PROG DNS PROG Disable JP3 For FPGA configuration via SPI only. FTDI_RXF FTDI_TXE 3V3 FTDI_RD FTDI_WR FTDI_SI FPGA_SUSPEND FPGA_AWAKE TP5 SPARE_ACBUS6 TP6 SPARE_ACBUS7 FPGA_RESET TP4 SPARE_ACBUS1 SPI_CSO_B SPI_CLK SPI_MOSI SPI_DIN .1uF 16 17 18 19 21 22 23 24 26 27 28 29 30 32 33 34 38 39 40 41 43 44 45 46 48 52 53 54 55 57 58 59 60 36 3 1 1 .1uF C10 1 4.7uF 3V3 ADBUS0/TXD/D0/TCK SK ADBUS1/RXD/D1/TDI DO ADBUS2/RTS#/D2/TDO DI ADBUS3/CTS#/D3/TMS CS ADBUS4/DTR#/D4/GPIOL0 ADBUS5/DSR#/D5/GPIOL1 ADBUS6/DCD#/D6/GPIOL2 ADBUS7/RI#/D7/GPIOL3 ACBUS0/TXDEN/RXF#/GPIOH0 ACBUS1/WRSTB#/TXE#/GPIOH1 ACBUS2/RDSTB#/RD#/GPIOH2 ACBUS3/TXLED#/WR#/GPIOH3 ACBUS4/RXLED#/SIWUA/GPIOH4 ACBUS5/-/CLKOUT/GPIOH5 ACBUS6/-/OE#/GPIOH6 ACBUS7/-/-/GPIOH7 BDBUS0/TXD/DO/TCK SK BDBUS1/RXD/D1/TDI DO BDBUS2/RTS#/D2/TDO DI BDBUS3/CTS#/D3/TMS CS BDBUS4/DTR#/D4/GPIOL0 BDBUS5/DSR#/D5/GPIOL1 BDBUS6/DCD#/D6/GPIOL3 BDBUS7/RI#/D7/GPIOL4 PWREN# SUSPEND# BCBUS0/TXDEN/RXF#/GPIOH0 OSCI BCBUS1/WRSTB#/TXE#/GPIOH1 BCBUS2/RDSTB#/RD#/GPIOH2 BCBUS3/TXLED#/WR#/GPIOH3 BCBUS4/RXLED#/SIWUB/GPIOH4 OSCO BCBUS5/-/-/GPIOH5 BCBUS6/-/-/GPIOH6 BCBUS7/PWRSAV#/PWRSAV#/GPIOH7 EECS EECLK EEDATA DM DP RESET# REF VREGOUT VREGIN U1 FT1232HQ 3V3 10uF/10V 3V3 Y1 12MHz R6 10K R2 12K R31 1K .1uF C34 10/10 Tant FB1 240-1018-1 MBR130T1G 1 C1 .01 1 2 3 4 R4 2.2K GND GND GND GND GND GND GND GND 1 5 11 15 25 35 47 51 CN1 CN-USB 3V3 C5 .1uF 4 2 1 20 31 42 56 VCCIO VCCIO VCCIO VCCIO 12 37 64 VCORE VCORE VCORE 4 9 VPHY VPLL AGND 10 C B A 5 3 2 5 1 PRELIMINARY DLP-HS-FPGA v1.2 Page 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 J1 CONN PCB 25x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 USER_IO52 USER_IO53_DP21 USER_IO54_DN21 USER_IO55_DP22 USER_IO56_DN22 USER_IO57_RC USER_IO58_RC USER_IO59 USER_IO60 USER_IO61_DP23 USER_IO62_DN23 FPGA_AWAKE VCCSW USER_IO31_DP15 USER_IO30_DN15 USER_IO29_DN14 USER_IO28_DP14 USER_IO27_DP13 USER_IO26_DN13 USER_IO25_DP12 USER_IO24_DN12 USER_IO23_DN11 USER_IO22_DP11 USER_IO21_DN10 VCCSW USER_IO20_DP10 USER_IO40_GC USER_IO39_DP19 USER_IO38_DN19 USER_IO37_DP18_RC USER_IO36_DN18_RC USER_IO35_DN17_RC USER_IO34_DP17_RC USER_IO33_DN16 USER_IO32_DP16 Bottom side FPGA IO (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 4 6 8 10 12 14 16 18 20 22 24 26 J4 CONN HDR 13x2 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Top side FPGA IO 1 3 5 7 9 11 13 15 17 19 21 23 25 1 D C B A D C B A A1 T1 F2 K2 C3 P3 E5 M5 F6 R6 B7 K7 G8 J8 H9 K9 G10 R10 B11 L11 E12 M12 C14 P14 G15 L15 A16 T16 1V8 U5F GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCAUX VCCAUX VCCAUX VCCAUX 1 6 7 5 2 GND 1 2 U5E D2 GREEN TDI TMS DONE TDO TCK PROG_B G7 H8 K8 G9 J9 K10 F5 M6 E11 L12 DNS JP1 PROG VREF VTT XC3S200A_FT256 VSENSE AVIN PVIN VDDQ SD# U6 LP2997 SOIC8 XC3S200A_FT256 VCCSW C75 0.1uF 330 4.7K B1 B2 T15 B16 A15 A2 Use Ceramic caps C72 2.2 uF VCCSW R25 JTAG_DIN JTAG_TMS LEDG_DONE JTAG_DOUT JTAG_TCK SPI_PROG VCCSW R21 5 1V2 VCCSW 4 8 3 C73 22 uF C62 2.2 uF 0603 C69 2.2 uF 0603 C74 0.1uF J2 C63 0.1uF C13 0.1uF C64 0.01uF 4 C65 0.1uF C70 0.1uF JTAG_TCK JTAG_DOUT JTAG_DIN JTAG_TMS C32 0.01uF VCCSW VREF_0V9 VTT_0V9 1 2 3 4 5 6 Traditional JTAG DNS 4 C66 0.01uF C71 0.01uF C67 0.1uF C68 0.01uF DDR2_A12 DDR2_A7 DDR2_A3 DDR2_WEn VTT_0V9 DDR2_RFU_A13 DDR2_A8 DDR2_ODT DDR2_A2 VTT_0V9 C76 0.1uF VCCSW DDR2_RFU_BA2 DDR2_BA1 DDR2_BA0 DDR2_A4 VTT_0V9 1 2 3 4 5 6 J3 Xilinx Parallel Cable Header DNS DNS DNS VCCSW R11 4.7K R9 4.7K R10 4.7K VCCSW 3 RN1 DNS 5 4 3 2 1 DDR II parallel terminations 6 7 8 9 10 RN2 5 4 3 2 1 CAT25-500JALF 50 Ohm DNS DNS 5 4 3 2 1 CAT25-500JALF 50 Ohm 6 7 8 9 10 RN3 R18 50 OUT 3 DNS VCCSW SPI Flash SPI_MOSI SPI_DIN SPI_CSO_B SPI_CLK FXO-HC735-66.666MHZ VDD GND EN Y2 CAT25-500JALF 50 Ohm 6 7 8 9 10 1 4 2 >Din <Dout C S W HOLD M25P20 U4 5 2 6 1 3 7 VCCSW R5 4.7K TDI TDO TMS TCK R8 4.7K 3 8 VCC VSS 4 VTT_0V9 DDR2_A9 DDR2_RFU_A14 DDR2_A5 DDR2_A1 VTT_0V9 DDR2_CASn DDR2_A0 DDR2_CSn DDR2_RASn VTT_0V9 DDR2_A6 DDR2_RFU_A15 DDR2_A11 DDR2_CKE DDR2_A10 R1 27 VCCSW CLKIN 2 2 C23 4.7uF 0603 EN GND IN BYPASS OUT 4 5 200mA Maximum 1.8V REGULATOR 1 2 3 U7 TPS79318DBVR / SOT23-5 FB SW U8 ST1S03 DFN6 VIN_SW VIN_A INHIBIT GND 3 1 DNS 1.5A Maximum 1.2V REGULATOR 4 5 6 2 R15 49.9K 1% R12 220K 5% 1 1V8 C14 0.01 uF 0603 L1 3.3uH R14 0 R30 Q3 IRLML6401 C20 0.1uF 0603 C15 2.2 uF 0603 1V2 C22 22 uF TANT 100 5% 2.5 mS ramp up C42 0.1uF 0603 PRELIMINARY DLP-HS-FPGA V1.2 Page 2 1 D C B A 5 VCCSW 1 2 DNS DDR2_ODT DDR2_RFU_A14 DDR2_CASn DDR2_WEn DDR2_CSn DDR2_RASn JP2 SUSPEND 1 R16 N13 N14 R15 P15 P16 N16 K11 K12 M13 M14 L13 K13 M15 M16 L14 L16 J10 J11 J12 J13 K15 K14 K16 J16 H10 H11 J14 C41 0.01uF 4 SUSPEND IO_L01P_1/HDC IO_L01N_1/LDC2 IO_L02P_1/LDC1 IO_L02N_1/LDC0 IO_L03P_1/A0 IO_L03N_1/A1 IP_L04P_1 IP_L04N_1/VREF_1 IO_L05P_1 IO_L05N_1/VREF_1 IO_L06P_1/A2 IO_L06N_1/A3 U5B C45 0.1uF SPI_CSO_B C38 0.01uF VCCSW N4 P4 N5 R2 T2 R3 T3 L7 N6 P5 M7 T4 R5 T5 T6 N7 P6 P7 N8 R7 T7 M8 P8 T8 N9 P9 H14 H15 H16 G16 F16 H13 G14 E16 F15 G13 F14 E14 F13 G12 G11 D16 D15 E13 D14 C16 C15 F12 F11 H12 E15 J15 N15 C29 0.01uF IO_L14N_1/RHCLK5 IO_L15P_1/IRDY1/RHCLK6 IO_L15N_1/RHCLK7 IO_L16P_1/A10 IO_L16N_1/A11 IO_L17P_1/A12 IO_L17N_1/A13 IO_L18P_1/A14 IO_L18N_1/A15 IO_L19P_1/A16 IO_L19N_1/A17 IO_L20P_1/A18 IO_L20N_1/A19 IP_L21P_1/VREF_1 IP_L21N_1 IO_L22P_1/A20 IO_L22N_1/A21 IO_L23P_1/A22 IO_L23N_1/A23 IO_L24P_1/A24 IO_L24N_1/A25 IP_L25P_1/VREF_1 IP_L25N_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 C50 2.2 uF 0603 1 VIA FTDI_RD FDTI_WR FTDI_TXE FTDI_RXF FTDI_SI FTDI_D0 FDTI_D1 FDTI_D2 FDTI_D3 FTDI_D4 FTDI_D5 FDTI_D6 FDTI_D7 USER_IO15_DP7_GC USER_IO14_DN7_GC USER_IO52 USER_IO49 USER_IO47 USER_IO10_DP5 USER_IO11_DN5 USER_IO17_DP8 USER_IO16_DN8 USER_IO53_DP21 USER_IO54_DN21 USER_IO19_DP9 USER_IO18_DN9 USER_IO48 VCCSW 3 DDR2_RFU_A13 DDR2_A10 DDR2_A9 DDR2_DQ7 DDR2_DQ6 DDR2_DQ5 DDR2_DQ4 DDR2_DQS DDR2_DQSn DDR2_DQ3 DDR2_DQ2 DDR2_DQ1 DDR2_DQ0 VREF_0V9 DDR2_A12 DDR2_A11 VREF_0V9 FDBK 1V8 C7 0.1uF C28 0.01uF C30 0.1uF DDR2_A0 DDR2_A1 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 L8 R9 T9 N10 M10 L9 T10 P10 T11 R11 P11 N11 L10 T12 P12 T13 R13 N12 P13 M11 T14 R14 R4 R8 M9 R12 C37 0.01uF C44 0.1uF H8 H3 H7 J2 J8 J3 J7 K2 K8 K3 H2 K7 L2 G2 G3 E8 F8 B7 A8 F2 G7 F7 F3 G8 U1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 CK CK# DQS DQS# 1V8 MT47H32M8BP-37E USER_IO25_DP12 USER_IO24_DN12 VCCSW R29 4.7K USER_IO20_DP10 USER_IO21_DN10 SPI_INIT USER_IO55_DP22 USER_IO56_DN22 DDR2_ERROR FPGA_RESET DDR2_IDONE USER_IO28_DP14 DDR2_DVALID USER_IO29_DN14 SPI_DIN USER_IO57_RC SPI_CLK USER_IO34_DP17_RC USER_IO35_DN17_RC VCCSW 2 A9 C1 C3 C7 C9 USER_IO22_DP11 USER_IO23_DN11 VCCSW D3 GREEN HEARTBEAT CKE CAS RAS WE CS A1 E9 H9 L1 LEDR_HEARTB SPI_MOSI USER_IO32_DP16 FPGA_AWAKE USER_IO33_DN16 CLKIN USER_IO40 R26 330 DDR2_DQS DDR2_DQSn DDR2_CK DDR2_CKn DDR2_BA0 DDR2_BA1 DDR2_CKE DDR2_CASn DDR2_RASn DDR2_WEn DDR2_CSn DDR2_CK DDR2_CKn C40 0.01uF XC3S200A_FT256 C61 2.2 uF 0603 IO_L01P_2/M1 IP_2 IO_L01N_2/M0 IO_L12P_2/GCLK2 IP_2/VREF_2 IO_L12N_2/GCLK3 IO_L02P_2/M2 IO_L13P_2 IO_L02N_2/CSO_B IO_L13N_2 IO_L03P_2/RDWR_B IP_2/VREF_2 IO_L03N_2/VS2 IO_L14P_2 IP_2 IO_L14N_2/MOSI/CSI_B IO_L04P_2/VS1 IO_L15P_2/AWAKE IO_L04N_2/VS0 Variant Select = IO_L15N_2/DOUT IP_2/VREF_2 IO_L16P_2 111 (Fast Read IO_L05P_2 IO_L16N_2 0x0B) IO_L05N_2 IP_2/VREF_2 IO_L06P_2/D7 IO_L17P_2/INIT_B IO_L06N_2/D6 IO_L17N_2/D3 IO_L07P_2 IO_L18P_2/D2 IO_L07N_2 IO_L18N_2/D1 IO_L08P_2/D5 IO_L19P_2 IO_L08N_2/D4 IO_L19N_2 IO_L09P_2/GCLK12 IP_2/VREF_2 IO_L09N_2/GCLK13 IO_L20P_2/D0/DIN/MISO IP_2/VREF_2 IO_L20N_2/CCLK IO_L10P_2/GCLK14 VCCO_2 IO_L10N_2/GCLK15 VCCO_2 IO_L11P_2/GCLK0 VCCO_2 IO_L11N_2/GCLK1 VCCO_2 U5C Mode 001 = SPI Flash IO_L07P_1/A4 XC3S200A_FT256 IO_L07N_1/A5 IO_L08P_1/A6 IO_L08N_1/A7 IP_L09P_1/VREF_1 IP_L09N_1 IO_L10P_1/A8 IO_L10N_1/A9 IO_L11P_1/RHCLK0 IO_L11N_1/RHCLK1 IO_L12P_1/RHCLK2 IO_L12N_1/TRDY1/RHCLK3 IP_L13P_1 IP_L13N_1 IO_L14P_1/RHCLK4 A8 B8 A7 C7 F8 E7 A6 B6 F7 D7 C6 A5 C5 D6 A4 B4 A3 B3 E6 C4 D5 B5 E8 B9 B13 C43 0.1uF 3 E1 VDDL Suspend powered by Vccaux (3.3V) FPGA_SUSPEND R23 4.7K VREF_0V9 DDR2_RFU_BA0 VREF_0V9 DDR2_BA0 DDR2_CKE DDR2_A0 DDR2_BA1 DDR2_A2 DDR2_A1 VREF_0V9 UNUSED_J11 VIA DDR2_A4 DDR2_A3 DDR2_A6 DDR2_A5 DDR2_A8 DDR2_A7 C31 0.1uF IO_L12P_0/GCLK10 IO_L12N_0/GCLK11 IO_L13P_0 IO_L13N_0 IO_L14P_0 IO_L14N_0/VREF_0 IO_L15P_0 IO_L15N_0 IP_0 IO_L16P_0 IO_L16N_0 IO_L17P_0 IO_L17N_0 IP_0 IO_L18P_0 IO_L18N_0 IO_L19P_0 IO_L19N_0 IP_0 IO_L20P_0/VREF_0 IO_L20N_0/PUDC_B VCCO_0 VCCO_0 VCCO_0 VCCO_0 DDR2_RFU_A15 IO_L01P_0 IO_L01N_0 IP_0 IO_L02P_0/VREF_0 IO_L02N_0 IO_L03P_0 IO_L03N_0 IO_L04P_0 IO_L04N_0 IO_L05P_0 IO_L05N_0 IO_L06P_0 IO_L06N_0/VREF_0 IO_L07P_0 IO_L07N_0 IP_0 IO_L08P_0 IO_L08N_0 IO_L09P_0/GCLK4 IO_L09N_0/GCLK5 IP_0/VREF_0 IO_L10P_0/GCLK6 IO_L10N_0/GCLK7 IO_L11P_0/GCLK8 IO_L11N_0/GCLK9 IP_0 U5A PRELIMINARY D13 C13 D12 B15 B14 C12 D11 A14 A13 B12 A12 D10 1 E10 C11 A11 F10 B10 A10 C10 D9 E9 C9 A9 C8 D8 F9 DLP-HS-FPGA v1.2 Page 3 USER_IO41 USER_IO0_DP0 USER_IO1_DN0 USER_IO42 USER_IO3_DP1 USER_IO2_DN1 USER_IO8_DP4 USER_IO9_DN4 UNUSED_E10 VIA USER_IO12_DP6 USER_IO13_DN6 USER_IO43_DP20 USER_IO44_DN20 USER_IO4_DP2_GC USER_IO5_DN2_GC USER_IO45_GC USER_IO6_DP3_GC USER_IO7_DN3_GC XC3S200A_FT256 C21 0.01uF 4 R20 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM ODT VREF C2 C1 D4 D3 D1 E1 E4 F4 E3 E2 G6 G5 F3 G4 F1 G1 G3 H4 H6 H5 G2 H1 H3 J3 H7 J7 J2 C51 2.2 uF 0603 C8 C2 D7 D3 D1 D9 B1 B9 B3 E2 F9 G1 L8 L3 L7 A2 C53 0.1uF C54 0.01uF C58 0.1uF C55 0.1uF C59 0.1uF TP1 DDR2_ERROR TP2 DDR2_DVALID TP3 DDR2_IDONE C27 0.1uF C24 0.1uF 1 C56 0.01uF C57 0.1uF C16 0.1uF D C A USER_IO58_RC USER_IO37_DP18_RC USER_IO36_DN18_RC B USER_IO59 USER_IO27_DP13 USER_IO26_DN13 USER_IO50 USER_IO61_DP23 USER_IO62_DN23 USER_IO60 USER_IO46 VIA UNUSED_K5 USER_IO39_DP19 USER_IO38_DN19 USER_IO51 VCCSW USER_IO31_DP15 USER_IO30_DN15 C36 0.1uF J1 K3 K1 L1 L2 J4 J6 K4 L3 M3 L4 M1 N1 K5 1 K6 N2 P1 R1 P2 N3 M4 L5 L6 D2 H2 M2 J5 C60 0.01uF 1 C35 0.01uF IO_L14N_3/LHCLK5 IO_L15P_3/TRDY2/LHCLK6 IO_L15N_3/LHCLK7 IO_L16P_3/VREF_3 IO_L16N_3 IO_L17P_3 IO_L17N_3 IO_L18P_3 IO_L18N_3 IO_L19P_3 IO_L19N_3 IO_L20P_3 IO_L20N_3 IP_L21P_3 IP_L21N_3 IO_L22P_3 IO_L22N_3 IO_L23P_3 IO_L23N_3 IO_L24P_3 IO_L24N_3 IP_L25P_3 IP_L25N_3/VREF_3 VCCO_3 VCCO_3 VCCO_3 VCCO_3 1 1 1 DDR2_RFU_BA2 DDR2_RFU_A13 DDR2_RFU_A14 DDR2_RFU_A15 DDR2_ODT VREF_0V9 DDR2_DQ0 DDR2_DQ1 DDR2_DQ2 DDR2_DQ3 DDR2_DQ4 DDR2_DQ5 DDR2_DQ6 DDR2_DQ7 C52 0.1uF DDR2_ERROR DDR2_IDONE DDR2_DVALID XC3S200A_FT256 IO_L01P_3 IO_L01N_3 IO_L02P_3 IO_L02N_3 IO_L03P_3 IO_L03N_3 IP_L04P_3 IP_L04N_3/VREF_3 IO_L05P_3 IO_L05N_3 IP_L06P_3 IP_L06N_3/VREF_3 IO_L07P_3 IO_L07N_3 IO_L08P_3 IO_L08N_3/VREF_3 IO_L09P_3 IO_L09N_3 IO_L10P_3 IO_L10N_3 IO_L11P_3/LHCLK0 IO_L11N_3/LHCLK1 IO_L12P_3/LHCLK2 IO_L12N_3/IRDY2/LHCLK3 IP_L13P_3 IP_L13N_3 IO_L14P_3/LHCLK4 U5D RDSQ#/NU RFU_BA2 RFU_A13 RFU_A14 RFU_A15 VDDQ VDDQ VDDQ VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VSSQ A7 B2 B8 D2 D8 VSSDL E7 R22 100 100 VDD VDD VDD VDD VSS VSS VSS VSS A3 E3 J1 K9 D C B A 5 UNUSED_R3