AN4660 Application note Migration of microcontroller applications from STM32F42xxx/STM32F43xxx to STM32F74xxx/STM32F75xxx Introduction Designers of STM32 microcontroller applications must have the possibility to easily replace one microcontroller type with another one from the same product Series. Reasons for migrating an application to a different microcontroller can be for example: • To fulfill higher product requirements, extra demands on memory size, or an increased number of I/Os. • To meet cost reduction constraints that require to switch to smaller components and shrink the PCB area. This application note is written as an help with the analysis of the steps involved when migrating from an existing STM32F42xxx/STM32F43xxx device to STM32F74xxx/STM32F75xxx device based design. This application note provides a guideline on hardware migration and peripheral migration. To better understand the information inside this application note, the user should be familiar with the STM32 microcontroller family. For additional information, please refer to STM32F42xxx/STM32F43xxx and STM32F74xxx/STM32F75xxx reference manuals (RM0090 and RM0385) and datasheets. Documents are available for download at www.st.com. Table 1. Applicable products Type Part number STM32F427AG, STM32F427AI, STM32F427IG, STM32F427II, STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI STM32F437AI, STM32F437IG, STM32F437II, STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI STM32F429AG, STM32F429AI, STM32F429BE, STM32F429BI, STM32F429IE, STM32F429IG, STM32F429II, STM32F429NE, STM32F429NI, STM32F429VE, STM32F429VG, STM32F429VI, STM32F429ZE, STM32F429ZG, STM32F429ZI Microcontrollers STM32F439AI, STM32F439BG, STM32F439BI, STM32F439IG, STM32F439II, STM32F439JG, STM32F439NG, STM32F439NI, STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI STM32F745ZG, STM32F745VG, STM32F745ZE, STM32F745IE, STM32F745VE STM32F746VG, STM32F746ZG, STM32F746IG, STM32F746BG, STM32F746NG, STM32F746IE, STM32F746VE, STM32F746ZE, STM32F746BE, STM32F746NE STM32F756VG, STM32F756ZG, STM32F756IG, STM32F756BG, STM32F756NG May 2015 DocID027558 Rev 2 1/27 www.st.com 1 Contents AN4660 Contents 1 2 Hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Pinout compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Boot mode compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 System bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 External interrupt lines (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 RCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8.1 Maximum frequency according to power scale parameter . . . . . . . . . . 16 2.9 PWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.11 U(S)ART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.12 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.13 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.14 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.15 USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.16 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.16.1 External trigger for regular channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.16.2 External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 DocID027558 Rev 2 AN4660 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F42xxx/F43xxx and STM32F74xxx/F75xxx pinout differences (LQFP100) . . . . . . . 4 Boot mode selection comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM32F42xxx/F43xxx and STM32F74xxx/F75xxx bootloader communication peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM32 peripheral compatibility analysis STM32F42xxx/F43xxx versus STM32F74xxx/F75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IP bus mapping differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . 10 Flash memory differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . 11 Flash module 1 Mbyte single bank organization (STM32F74xxx/F75xxx) . . . . . . . . . . . . . 12 FMC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . 13 Interrupt vector differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . 14 EXTI line differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . 14 RCC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . 15 Maximum frequency comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PWR differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . 17 RTC comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . 18 U(S)ART differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . 19 I2C differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. . . . . . . . . . . 20 SPI differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . . 20 CRC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . 21 USB OTG differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . 22 External trigger for regular channel differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External trigger for injected channel differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DocID027558 Rev 2 3/27 3 Hardware migration AN4660 1 Hardware migration 1.1 Pinout compatibility The STM32F74xxx/F75xxx devices are fully pin-to-pin compatible with the STM32F42xxx/F43xxx devices except for the LQFP100 package, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1. Incompatible board design for LQFP100 package 670)[[[670)[[[ 3& 9'' 966$ 95() 9''$ 3$:.83 3$ 3$ 9'' 3% 9&$3 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3& 3% 3& 3$ 3$ 3$ 3$ 9'' 3$ 3& 966$ 95() 9''$ 3$:.83 3$ 3$ 3$ 966 670)[[[670)[[[ 3LQVWRDUHQRWFRPSDWLEOH 966 9'' 9&$3 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 3% 3& 3& 3$ 3$ 3$ 3$ 9'' 966 06Y9 Table 2 presents the pinout differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx for the LQFP100 package. Table 2. STM32F42xxx/F43xxx and STM32F74xxx/F75xxx pinout differences (LQFP100) 4/27 LQFP100 STM32F42xxx/F43xxx pinout STM32F74xxx/F75xxx pinout 19 VDD VSSA 20 VSSA VREF+ 21 VREF+ VDDA 22 VDDA PA0-WKUP 23 PA0-WKUP PA1 24 PA1 PA2 DocID027558 Rev 2 AN4660 Hardware migration Table 2. STM32F42xxx/F43xxx and STM32F74xxx/F75xxx pinout differences (LQFP100) (continued) LQFP100 STM32F42xxx/F43xxx pinout STM32F74xxx/F75xxx pinout 25 PA2 PA3 26 PA3 VSS 27 VSS VDD 28 VDD PA4 29 PA4 PA5 30 PA5 PA6 31 PA6 PA7 32 PA7 PC4 33 PC4 PC5 34 PC5 PB0 35 PB0 PB1 36 PB1 PB2 37 PB2 PE7 38 PE7 PE8 39 PE8 PE9 40 PE9 PE10 41 PE10 PE11 42 PE11 PE12 43 PE12 PE13 44 PE13 PE14 45 PE14 PE15 46 PE15 PB10 47 PB10 PB11 48 PB11 VCAP1 49 VCAP1 VSS DocID027558 Rev 2 5/27 26 Hardware migration 1.2 AN4660 Boot mode compatibility The STM32F42xxx/F43xxx boot space is based on boot mode selection pins: BOOT0 and BOOT1 while STM32F74xxx/F75xxx is based on BOOT0 and boot address option bytes as described in Table 3. For STM32F74xxx/F75xxx, the boot base address supports any address in the range from 0x0000 0000 to 0x2004 FFFF. Table 3. Boot mode selection comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx STM32F74xxx/F75xxx Boot mode selection Boot address Option Bytes Boot space BOOT 0 BOOT_ADD0 [15:0] Boot address defined by user option byte BOOT_ADD0[15:0] - ST programmed value: Flash on ITCM at 0x0020 0000 1 BOOT_ADD1 [15:0] Boot address defined by user option byte BOOT_ADD1[15:0] - ST programmed value: system bootloader at 0x0010 0000 STM32F42xxx/F43xxx Boot mode selection Pins Boot Mode Aliasing BOOT1 BOOT0 6/27 x 0 Main Flash memory Main Flash memory is selected as the boot space at 0x0800 0000 0 1 System memory System memory is selected as the boot space at 0x1FFF 0000 DocID027558 Rev 2 AN4660 1.3 Hardware migration System bootloader The system bootloader is located in the system memory, programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces. Table 4 shows the supported communication peripherals by the system bootloader. Table 4. STM32F42xxx/F43xxx and STM32F74xxx/F75xxx bootloader communication peripherals System bootloader peripherals STM32F42xxx/F43xxx I/O pin STM32F74xxx/F75xxx I/O pin DFU USB OTG FS (PA11 / PA12) in device mode USART1 PA9 / PA10 USART3 PB10 / PB11 and PC10 / PC11 CAN2 PB5 / PB13 I2C1 NA PB6 / PB9 I2C2 NA PF0 / PF1 I2C3 NA PA8 / PC9 By default, in STM32F74xxx/F75xxx, when the boot from system bootloader is selected, the code is executed from ITCM interface. It could be reprogrammed by option byte executed from AXIM interface. For more details on system bootloader refer to AN2606. DocID027558 Rev 2 7/27 26 Peripheral migration AN4660 2 Peripheral migration 2.1 STM32 product cross-compatibility The STM32 Series embed a set of peripherals which can be classed in three categories: • The first category is for the peripherals which are by definition common to all products. Those peripherals are identical, so they have the same structure, registers and control bits. There is no need to perform any firmware change to keep the same functionality at the application level after migration. All the features and behavior remain the same. • The second category is for the peripherals which are shared by all STM32 products but have only minor differences (in general to support new features), so migration from one product to another is very easy and does not need any significant new development effort. • The third category is for peripherals which have been considerably changed from one product to another (new architecture, new features...). For this category of peripherals, the migration will require a new development at application level. • The SW compatibility mentioned in the Table 5 only refers to the register description for "low level" drivers. The Cube Hardware Abstraction Layer (HAL) is compatible between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 5 shows STM32 peripheral compatibility between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 5. STM32 peripheral compatibility analysis STM32F42xxx/F43xxx versus STM32F74xxx/F75xxx STM32F42xxx/ STM32F74xxx/ F43xxx F75xxx Peripherals - - - Flash memory in Kbyte 2048 1024 System 256 (115+16+64+64) 320 (240+16+64) Instruction NA 16 Backup 4 4 GP 10 Advanced control SRAM(KB) Timers 8/27 Compatibility SW Comments - - 10 Yes - 2 2 Yes - Basic 2 2 Yes - Low-power NA 1 NA - DocID027558 Rev 2 AN4660 Peripheral migration Table 5. STM32 peripheral compatibility analysis STM32F42xxx/F43xxx versus STM32F74xxx/F75xxx (continued) STM32F42xxx/ STM32F74xxx/ F43xxx F75xxx Peripherals QuadSPI No SPI / I2S 6/2 (full duplex) I2C 3 4 No Programmable clock source for STM32F74xxx/F75xxx USART/UART 4/4 4/4 No Additional features on STM32F74xxx/F75xxx USB OTG FS Yes Yes No Dedicated VDDUSB More endpoints on STM32F74xxx/F75xxx USB OTG HS Yes Yes No More endpoints and host channels CAN 2 2 Yes - SAI 1 2 Yes - SDIO/SDMMC1 Yes Yes Yes New clock source for SDMMC1 on STM32F74xxx/F75xxx SPDIFRX No 4 inputs NA - RNG Yes Yes Yes - FMC memory controller Yes Yes Yes - Ethernet Yes Yes Yes - HDMI-CEC No Yes NA - DCMI Yes Yes Yes - WWDG Yes Yes Yes - IWDG Yes Yes Yes - CRC Yes Yes Yes Additional features on STM32F74xxx/F75xxx LCD-TFT No | Yes(2) Yes Yes - Yes - Communication interfaces DMA Yes Compatibility NA 4/3 (simplex) No / 6/3 (simplex)(1) Yes DMA1-DMA2 (8 stream each) I2S compatible. Chrom-ART-Acc (DMA2D) Yes Yes Yes - Crypto Yes Yes Yes - Hash Yes Yes Yes - GPIO Up to 168 Up to 168 Yes - 12 bits 3 3 Number of channels Yes 16|24 16|24 ADC Timer Trigger not compatible ADC DocID027558 Rev 2 9/27 26 Peripheral migration AN4660 Table 5. STM32 peripheral compatibility analysis STM32F42xxx/F43xxx versus STM32F74xxx/F75xxx (continued) STM32F42xxx/ STM32F74xxx/ F43xxx F75xxx Peripherals DAC 12 bits Yes Yes Number of channels 2 2 EXTI Yes RCC RTC Compatibility Yes - Yes Yes New EXTI line for LPTIM1 Yes Yes Yes New LSE drive modes. Yes Yes Yes Additional features on STM32F74xxx/F75xxx PWR Yes Yes New wakeup pins with configurable polarity Yes on STM32F74xxx/F75xxx SYSCFG Yes Yes Yes - 1. SPI / I2S: - 4/3 for 100 pin package and 6/3 for other packages. 2. LCD - TFT: - No: not available for STM32F437xx. - Yes: available for STM32F439xx. 2.2 Memory mapping Table 6 presents the peripheral address mapping differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 6. IP bus mapping differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx Peripheral STM32F42xxx/F43xxx STM32F74xxx/F75xxx Base address Base address Bus QuadSPI control register AHB3 NA 0xA000 1000 - 0xA0001FFF SAI2 APB2 NA 0x4001 5C00 - 0x4001 5FFF HDMI-CEC NA 0x4000 6C00 - 0x4000 6FFF I2C4 NA 0x4000 6000 - 0x4000 63FF 0x4000 4000 - 0x4000 43FF NA SPDIFRX NA 0x4000 4000 - 0x4000 43FF I2S2ext 0x4000 3400 - 0x4000 37FF NA LPTIM1 NA 0x4000 2400 - 0x4000 27FF I2S3ext APB1 10/27 DocID027558 Rev 2 AN4660 2.3 Peripheral migration Flash memory Table 7 presents the differences between the Flash memory interface of STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. The STM32F74xxx/F75xxx devices instantiate a different Flash module both in terms of architecture and interface. For more information on programming, erasing and protection of the STM32F74xxx/F75xxx Flash memory, please refer to the STM32F74xxx and STM32F75xxx reference manual (RM0385). Table 7. Flash memory differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx Flash Main/program memory Features – – – – – STM32F42xxx/F43xxx STM32F74xxx/F75xxx 0x0800 0000 – 0x081F FFFF 0x0800 0000 - 0x080F FFFF (on AXIM interface) Up to 2 Mbyte Split in 2 Banks 4 sectors of 16 Kbyte 1 sector of 64 Kbyte 6 sectors of 128 Kbyte – 128 bit wide data read – Read while Write (RWW) – – – – – Up to 1 Mbyte Split in 1 Bank 4 sectors of 32 Kbyte 1 sector of 128 Kbyte 3 sectors of 256 Kbyte – 256 bit wide data read Wait State Up to 8 (depending on the supply voltage and frequency) Up to 9 (depending on the supply voltage and frequency) One time programmable (OTP) 512 OTP bytes 1024 OTP bytes Flash interface register Option Bytes Option Bytes 0x4002 3C00 - 0x4002 3FFF 0x1FFF C000 - 0x1FFF C00F 0x1FFE C000 - 0x1FFE C00F Base address FLASH_ OPTCR register – – – – – – – – – – Bit 31 SPRMOD Bit 30 DB1M Bits 29:28 Reserved Bits 27:16 nWRP[11:0] Bits 15:8 RDP Bits 7:5 USER - Bit 7: nRST_STDBY - Bit 6: nRST_STOP - Bit 5: WDG_SW Bit 4 BFB2 Bits 3:2 BOR_LEV Bit 1 OPTSTRT Bit 0 OPTLOCK DocID027558 Rev 2 0x1FFF 0000 - 0x1FFF 001F (on AXIM interface) – – – – – – – – – – Bit 31 IWDG_STOP Bit 30 IWDG_STDBY Bits 29:24 Reserved Bits 23:16 nWRP[7:0] Bits 15:8 RDP[7:0] Bits 7:4 USER - Bit 7: nRST_STDBY - Bit 6: nRST_STOP - Bit 5: IWDG_SW Bit 4: WWDG_SW Bits 3:2 BOR_LEV[1:0] Bit 1 OPTSTRT Bit 0 OPTLOCK 11/27 26 Peripheral migration 2.4 AN4660 Embedded Flash memory The main memory and information block organization are shown in Table 8. Table 8. Flash module 1 Mbyte single bank organization (STM32F74xxx/F75xxx) Block Main memory block Information block 12/27 Bloc base addresses on Block base addresses Sector AXIM interface on ITCM interface size Sector 0 0x0800 0000 - 0x0800 7FFF 0x0020 0000 - 0x0020 7FFF 32 KB Sector 1 0x0800 8000 - 0x0800 FFFF 0x0020 8000 - 0x0020 FFFF 32 KB Sector 2 0x0801 0000 - 0x0801 7FFF 0x0021 0000 - 0x0021 7FFF 32 KB Sector 3 0x0801 8000 - 0x0801 FFFF 0x0021 8000 - 0x0021 FFFF 32 KB Sector 4 0x0802 0000 - 0x0803 FFFF 0x0022 0000 - 0x0023 FFFF 128 KB Sector 5 0x0804 0000 - 0x0807 FFFF 0x0024 0000 - 0x0027 FFFF 256 KB Sector 6 0x0808 0000 - 0x080B FFFF 0x0028 0000- 0x002B FFFF 256 KB Sector 7 0x080C 0000 - 0x080F FFFF 0x002C 0000 - 0x02F FFFF 256 KB System memory 0x1FF0 0000 - 0x1FF0 EDBF 0x0010 0000- 0x0010 EDBF 60 Kbyte OTP 0x1FF0 F000 - 0x1FF0 F41F 0x0010 F000 - 0x0010 F41F 1024 byte Option bytes 0x1FFF 0000 - 0x1FFF 001F - 32 byte Name DocID027558 Rev 2 AN4660 2.5 Peripheral migration Flexible memory controller (FMC) Table 9 presents the FMC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 9. FMC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx FMC STM32F42xxx/F43xxx – – – – SRAM NOR/NAND memories PSRAM Two banks of NAND Flash memory with ECC hardware – 16-bit PC Card compatible devices External memory interfaces Data bus width STM32F74xxx/F75xxx – – – – SRAM NOR/NAND memories PSRAM NAND Flash memory with ECC hardware 8-,16- or 32-bit Bank1 4×64MB NOR/PSRAM/SRAM Bank2 4×64MB NOR/PSRAM/SRAM Reserved NAND Flash memory FMC Bank memory mapping Bank3 4×64MB NAND Flash memory Bank4 4×64MB PC Card Reserved SDRAM SDRAM NOR/PSRAM/SRAM 256MB SDRAM bank1 256MB NAND bank1 256MB SDRAM bank2 256MB SDRAM bank1 256MB NAND bank3 256MB SDRAM bank2 256MB Reserved Reserved Reserved NAND bank2 256MB NOR/PSRAM/SRAM 256MB PC card 256MB Reserved SDRAM bank1 4×64MB SDRAM bank2 4×64MB Memory mapping swap: (SYSCFG_MEMRMP) Bits 11:10 SWP_FMC[1:0] = 01b DocID027558 Rev 2 13/27 26 Peripheral migration 2.6 AN4660 Interrupt vectors Table 10 presents the interrupt vector differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 10. Interrupt vector differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx 2.7 Position STM32F42xxx/F43xxx STM32F74xxx/F75xxx 91 NA SAI2 92 NA QuadSPI 93 NA LPTIM1 94 NA HDMI-CEC 95 NA I2C4_EV 96 NA I2C4_ER 97 NA SPDIFRX External interrupt lines (EXTI) Table 11 presents the EXTI line differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 11. EXTI line differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx EXTI line STM32F74xxx/F75xxx 0 to 15 16 external interrupt lines 16 PVD output 17 RTC alarm event 18 USB OTG FS wakeup event 19 Ethernet wakeup event 20 USB OTG HS (configured in FS) wakeup event 21 RTC tamper and TimeStamp events 22 RTC wakeup event 23 14/27 STM32F42xxx/F43xxx NA DocID027558 Rev 2 LPTIM1 asynchronous event AN4660 2.8 Peripheral migration RCC Table 12 presents the main differences related to the RCC (Reset and Clock Controller) between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 12. RCC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx STM32F42xxx/F43xxx STM32F74xxx/F75xxx Peripherals Clock sources USB OTG FS RNG SDIO/SDMMC1 U(S)ARTs – PLL48MHz derived from main PLL VCO (PLLQ Clock) – PLL48MHz derived from main PLL VCO (PLLQ Clock) – PLLSAI VCO (PLLSAI clock) – PLL48CLK – PLL48CLK – SYSCLK – APB1 or APB2 clock (PCLK1 or PCLK2) – – – – System clock (SYSCLK) HSI clock LSE clock APB1 or APB2 clock (PCLK1 or PCLK2) – System clock (SYSCLK) – HSI clock – APB1 or APB2 clock (PCLK1 or PCLK2) I2Cs – APB1 clock (PCLK1) I2S – PLLI2S – External clock mapped on I2S_CKIN pin SAI1 – PLLI2S_Q – PLLSAI_Q – External clock mapped on the I2S_CKIN pin. SAI2 LTDC LPTIM1 USB OTG HS ETHERNET MAC NA – PLLI2S_Q – PLLSAI_Q – External clock mapped on the I2S_CKIN pin. NA – – – – – PLLSAI_R LSI clock LSE clock HSI clock APB1 clock (PCLK1) – 24 to 60 MHz to external PHY – 25 to 50 MHz external PHY SPDIFRX NA – PLLI2SP VCO HDMI-CEC NA – LSE clock – HSI clock divided by 488 DocID027558 Rev 2 15/27 26 Peripheral migration AN4660 Table 12. RCC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx (continued) STM32F42xxx/F43xxx STM32F74xxx/F75xxx Peripherals Clock sources – LSE clock – LSI clock – HSE clock divided by 32 RTC IWDG LSI LSE NA RCC dedicated clock configuration register 2.8.1 Configurable LSE drive in RCC_BDCR register: LSEDRV[1:0]: – 00: Low drive – 10: Medium low drive – 01: Medium high drive – 11: High drive – RCC_DKCFGR1 – RCC_DKCFGR2 – RCC_DCKCFGR Maximum frequency according to power scale parameter Table 13 shows the comparison of maximum frequency that the MCU can reach between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 13. Maximum frequency comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx Symbol fHCLK Parameter Internal AHB clock frequency Conditions F4 max Freq F7 max Freq Power scale 3 (Over-drive OFF) 120 144 Over-drive OFF 144 168 Over-drive ON 168 180 Over-drive OFF 168 180 Over-drive ON 180 216 Unit Power scale 2 Power scale 1 fPCLK1 fPCLK2 16/27 Internal APB1 clock frequency Over-drive OFF 42 45 Over-drive ON 45 54 Internal APB2 clock frequency Over-drive OFF 84 90 Over-drive ON 90 108 DocID027558 Rev 2 MHz AN4660 2.9 Peripheral migration PWR Table 14 presents the PWR controller differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 14. PWR differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx PWR Power supplies Standby mode wakeup sources – – – – STM32F42xxx/F43xxx STM32F74xxx/F75xxx NA – Independent USB transceivers supply: VDDUSB: range is from 3.0 V to 3.6 V and is completely independent from VDD or VDDA – WKUP pin with configurable polarity on rising or falling edge: – PA0 – PA2 WKUP pin PA0 on rising edge – PC1 RTC event (RTC ALARM, – PC13 Tamper event,Time stamp event) – PI8 IWDG reset – PI11 External reset in NRST pin – RTC event (RTC ALARM, tamper event, time stamp event) – IWDG reset – External reset in NRST pin PWR_CR PWR_CSR PWR_CR1 PWR_CSR1 PWR_CR2 PWR_CSR2 Power control registers NA DocID027558 Rev 2 Comment : – PWR_CR2: Used to configure the wakeup pin polarity, or to clear the wakeup pins flags. – PWR_CSR2: Used either to enable the wakeup pins or used to detect an event on the wakeup pin 17/27 26 Peripheral migration 2.10 AN4660 RTC Table 15 shows the RTC comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 15. RTC comparison between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx RTC STM32F42xxx/F43xxx STM32F74xxx/F75xxx Calendar in BCD Yes Calendar sub seconds access Yes Resolution down to RTCCLK Calendar synchronization on the fly Yes Alarm on calendar 2 w/ subseconds Calendar calibration Calibration window: 8s/16s/32s Calibration step: 3.81ppm/1.91ppm/0.95 ppm Range [-480ppm +480ppm] Synchronization on mains Yes Periodic wakeup Yes Timestamp Yes Sec, Min, Hour, Date, Sub seconds Timestamp on VBAT switch No Yes 2 pins/ 2 events 3 pins/ 3 events Tamper Edge or level detection with configurable filtering External interrupt and trigger with filtering No Yes 32-bit backup registers 20 32 RTC in VBAT 18/27 Yes DocID027558 Rev 2 AN4660 2.11 Peripheral migration U(S)ART The U(S)ART is not SW compatible with STM32F42xxx/F43xxx and includes new additional features detailed in Table 16. Table 16. U(S)ART differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx U(S)ART STM32F42xxx/F43xxx UART/USART STM32F74xxx/F75xxx 4/4 – Up to 4x11.25 Mbit/s – Up to 13.5 Mbit/s – (clock frequency is 100 MHz and oversampling is by 8) Clock – Single clock domain – Dual clock domain: Convenient baud rate programming independent from the PCLK reprogramming Data – Word length: Programmable (8 or 9 bits) – Word length: Programmable (7, 8 or 9 bits) – Programmable data order with MSBfirst or LSB-first shifting – 10 interrupt sources with flags – 14 interrupt sources with flags Baud rate interrupt – – – – – – – Features LIN mode SPI Master IrDA SIR ENDEC block Hardware flow control (CTS/RTS) Continuous communication using DMA Multiprocessor communication Single-wire half-duplex communication Smartcard mode T = 0 and T= 1 has to be implemented by software. Number of stop bits: 0.5, 1, 1.5, 2 NA U(S)ART registers Support the T=0 and T=1 asynchronous protocols. Number of stop bits: 1, 1.5, 2 smartcard operation. – Support for ModBus communication - Timeout feature - CR/LF character recognition – Receiver timeout interrupt – Auto baud rate detection – Driver Enable – Swappable Tx/Rx pin configuration – Software not compatible DocID027558 Rev 2 19/27 26 Peripheral migration 2.12 AN4660 I2C The STM32F42xxx/F43xxx and STM32F74xxx/F75xxx share the same features on the I2C, but the software and register configuration are not compatible. Table 17 presents the I2C differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 17. I2C differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx I2C STM32F42xxx/F43xxx Instances STM32F74xxx/F75xxx – x3 (I2C1, I2C2, I2C3) – – – – Features – x4 (I2C1, I2C2, I2C3, I2C4) 7-bit and 10-bit addressing mode SMBus Standard mode (up to 100 kbit/s) Fast mode (up to 400 kbit/s) – Single clock source I2C registers 2.13 – Programmable clock source – Software not compatible. SPI The STM32F42xxx/F43xxx and STM32F74xxx/F75xxx implement different features on the SPI. Table 18 presents the SPI differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 18. SPI differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx SPI STM32F42xxx/F43xxx STM32F74xxx/F75xxx Instances x6 x4 | x6 Features SPI + I2S Data size Fixed, configurable to 8 or 16 bits Programmable from 4 to 16-bit Data buffer Tx & Rx 16-bit buffers (single data frame) Two 32-bit embedded Rx and Tx FIFOs (up to 4 data frames) Data packing No (16-bit access only) Yes Mode SPI TI mode SPI Motorola mode SPI TI SPI Motorola mode NSSP mode Speed up to 45Mbits/s Up to 50Mbits/s (TBC) SPI registers 20/27 Software not compatible DocID027558 Rev 2 AN4660 2.14 Peripheral migration CRC The STM32F74xxx/F75xxx implements similar CRC (Cyclic redundancy check) calculation unit as STM32F42xxx/F43xxx. Table 19 presents the CRC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 19. CRC differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx CRC STM32F42xxx/F43xxx STM32F74xxx/F75xxx – Single input/output 32-bit data register – CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size – General-purpose 8-bit register (can be used for temporary storage) Features – Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7 – Handles 32-bit data size CRC registers – Fully programmable polynomial with programmable size (7, 8, 16, 32bits) – Handles 8-,16-, 32-bit data size – Programmable CRC initial value – Input buffer to avoid bus stall during calculation – Reversibility option on I/O data – Software compatible. – STM32F74xxx/F75xxx include new features. DocID027558 Rev 2 21/27 26 Peripheral migration 2.15 AN4660 USB OTG Table 20 presents USB OTG differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. Table 20. USB OTG differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx USB STM32F42xxx/F43xxx STM32F74xxx/F75xxx – Universal Serial Bus revision 2.0 – Full support for the USB On-The-Go (USB OTG). Features FS mode: – 1 bidirectional control endpoint – 3 IN endpoints (bulk, interrupt, isochronous) – 3 OUT endpoints (bulk, interrupt, isochronous FS mode: – 1 bidirectional control endpoint – 5 IN endpoints (bulk, interrupt, isochronous) – 5 OUT endpoints (bulk, interrupt, isochronous) HS mode: – 6 bidirectional endpoints (including EP0) – 12 host mode channels HS mode: – 8 bidirectional endpoints (including EP0) – 16 host channels with periodic – USB internal connect/disconnect feature with an internal pull-up resistor on the USB D + (USB_DP) line. NA Buffer memory FS mode: FS mode: – 1.25Kbytes data FIFOs – 1.25Kbytes data FIFOs – Management of up to 6 Tx FIFOs – Management of up to 4 Tx FIFOs (1 for (1 for each IN end point) + 1 Rx each IN end point) + 1 Rx FIFO. FIFO. HS mode: HS mode: – 4 KB total RAM – 4 KB total RAM FS mode: – USB suspend and resume Low-power modes HS mode: – No LPM supported Configuration 22/27 – Independent VDDUSB power supply allowing lower VDDCORE while using USB. – SW not compatible DocID027558 Rev 2 FS mode: – USB suspend and resume – Link power management (LPM) support HS mode: – Yes LPM supported AN4660 2.16 Peripheral migration ADC The STM32F74xxx/F75xxx devices embed the same ADC peripherals with the same features except for external triggers in regular and injected channels. Table 21 and Table 22 present the differences of external trigger for regular channels and injected channels between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx. 2.16.1 External trigger for regular channels Table 21. External trigger for regular channel differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx Source Type Internal signal from on-chip timers External pin EXTSEL[3:0] STM32F42xxx/F43xxx STM32F74xxx/F75xxx 0000 TIM1_CH1 event TIM1_CC1 event 0001 TIM1_CH2 event TIM1_CC2 event 0010 TIM1_CH3 event TIM1_CC3 event 0011 TIM2_CH2 event TIM2_CC2 event 0100 TIM2_CH3 event TIM5_TRGO event 0101 TIM2_CH4 event TIM4_CC4 event 0110 TIM2_TRGO event TIM3_CC4 0111 TIM3_CH1 event TIM8_TRGO event 1000 TIM3_TRGO event TIM8_TRGO(2) event 1001 TIM4_CH4 event TIM1_TRGO event 1010 TIM5_CH1 event TIM1_TRGO(2) event 1011 TIM5_CH2 event TIM2_TRGO event 1100 TIM5_CH3 event TIM4_TRGO event 1101 TIM8_CH1 event TIM6_TRGO event 1110 TIM8_TRGO event NA 1111 EXTI line11 DocID027558 Rev 2 23/27 26 Peripheral migration 2.16.2 AN4660 External trigger for injected channels Table 22. External trigger for injected channel differences between STM32F42xxx/F43xxx and STM32F74xxx/F75xxx Source Type Internal signal from on-chip timers External pin 24/27 EXTSEL[3:0] STM32F42xxx/F43xxx STM32F74xxx/F75xxx 0000 TIM1_CH4 event TIM1_TRGO event 0001 TIM1_TRGO event TIM1_CC4 event 0010 TIM2_CH1 event TIM2_TRGO event 0011 TIM2_TRGO event TIM2_CC1 event 0100 TIM3_CH2 event TIM3_CC4 event 0101 TIM3_CH4 event TIM4_TRGO event 0110 TIM4_CH1 event NA 0111 TIM4_CH2 event TIM8_CC4 event 1000 TIM4_CH3 event TIM1_TRGO(2) event 1001 TIM4_TRGO event TIM8_TRGO event 1010 TIM5_CH4 event TIM8_TRGO(2) event 1011 TIM5_TRGO event TIM3_CC3 event 1100 TIM8_CH2 event TIM5_TRGO event 1101 TIM8_CH3 event TIM3_CC1 event 1110 TIM8_CH4 event TIM6_TRGO event 1111 EXTI line15 NA DocID027558 Rev 2 AN4660 3 Conclusion Conclusion This application note is a useful complement to the datasheets and reference manuals, which gives a simple guideline to migrate from an existing STM32F42xxx/F43xxx device to STM32F74xxx/F75xxx device. DocID027558 Rev 2 25/27 26 Revision history 4 AN4660 Revision history Table 23. Document revision history Date Revision 31-Mar-2015 1 Initial release. 2 Updated: – Section 2.1: STM32 product cross-compatibility with a new paragraph about software compatibility, – Table 5: STM32 peripheral compatibility analysis STM32F42xxx/F43xxx versus STM32F74xxx/F75xxx for RNG, ADC, and DAC peripherals, – Section 2.8.1: Maximum frequency according to power scale parameter setting F7 max at 216 MHz, 108 MHz and 54 MHz in over-drive ON conditions, – Section 2.11: U(S)ART with baud rate up to 13.5 Mbit/s. 26-May-2015 26/27 Changes DocID027558 Rev 2 AN4660 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027558 Rev 2 27/27 27