AT73C260-EK1 Evaluation Kit User Guide

AT73C260-EK1 Evaluation Kit
.................................................................................................................
User Guide
11071A–PMAAC–17-Sep-10
1-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Section 1
Introduction .................................................................................................................1-1
1.1
Scope ................................................................................................................................. 1-1
1.2
AT73C260-EK1 Features................................................................................................... 1-2
1.3
Deliverables ....................................................................................................................... 1-2
Section 2
Getting Started............................................................................................................2-1
2.1
Jumper Electrostatic Warning ............................................................................................ 2-1
2.2
Requirements..................................................................................................................... 2-1
2.3
Instructions......................................................................................................................... 2-1
2.3.1
To start the AT73C260-EK1 board ...................................................................... 2-1
2.3.2
To turn off the AT73C260-EK1 evaluation board................................................. 2-2
2.4
Block Diagram.................................................................................................................... 2-2
2.5
Typical Application Connections ........................................................................................ 2-3
2.6
Switch and Jumpers configuration according Interchip Mode.......................................... 2-13
2.6.1
Mode PHY_6_SE0............................................................................................. 2-14
2.6.2
Mode PHY_4_SE0............................................................................................. 2-15
2.6.3
Mode PHY_6_DPDM ......................................................................................... 2-16
2.6.4
Mode PHY_4_DPDM ......................................................................................... 2-17
2.6.5
Mode PHY_3_ULPI ........................................................................................... 2-18
2.6.6
Mode S7_ICC .................................................................................................... 2-19
2.6.7
Mode S7_ICC_BB ............................................................................................. 2-20
2.6.8
Mode S7_ICC_TK.............................................................................................. 2-21
2.6.9
Mode ICC_S7 .................................................................................................... 2-22
2.6.10 Mode VCC ......................................................................................................... 2-23
2.7
Configuration Pads........................................................................................................... 2-24
Section 3
Technical Specifications .............................................................................................3-1
Section 4
Schematics .................................................................................................................4-1
Section 5
Revision History..........................................................................................................5-1
5.1
Revision History ................................................................................................................. 5-1
AT73C260-EK1 Evaluation Kit User Guide
1-1
11071A–PMAAC–17-Sep-10
1-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Section 1
Introduction
Congratulations on your purchase of the AT73C260-EK1. It is designed to give designers a quick start to
evaluate the Interchip USB Transceiver capability of the AT73C260 and for prototyping and testing of
new designs.
1.1
Scope
This document describes the AT73C260-EK1. This board is designed to allow an easy evaluation of the
functionalities and the various interchip configuration modes.
To increase its capabilities for demonstration, this standalone board has several configuration modes
according the interconnection between host and device.
This User Guide acts as a general getting started guide as well as a complete technical reference for
advanced users.
This document refers the AT73C260 Datasheet.
Typical Applications:
„
Mobile USB UICC (ETSI 102 600)
„
PC USB UICC
„
Token USB
AT73C260-EK1 Evaluation Kit User Guide
1-1
11071A–PMAAC–17-Sep-10
1.2
AT73C260-EK1 Features
The AT73C260-EK1 provides the following features:
„
Power Supply:
– VBUS Connector for Host Connection
„
On-board resources:
– USB Connector Type A,
– USB Connector Type B,
– 2 Micro USB Connector Type AB,
– UICC Interface Connector,
– Smart Card Reader Connector,
– Connector for FPGA interconnection.
„
On-board jumpers:
– Jumpers for M<2:0> pads, in order to configure the modes of interchip connection,
– Jumpers for PVRF configuration,
– Jumpers for set of the pull-down resistors on PDP, PDM,
– Jumpers for UICC Connector configuration,
– Jumpers for load connection on power supplies.
1.3
Deliverables
The AT73C260-EK1 package contains the following items:
„
An AT73C260-EK1 board,
„
One CD-ROM containing the AT73C260-EK1 User Guide and a full AT73C260 Datasheet.
1-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Figure 1-1.
AT73C260-EK1 Top View (card photo)
AT73C260-EK1
The AT73C260 is located in the center of the AT73C260-EK1 on the Components Side.
Figure 1-2.
AT73C260-EK1Card With Available Connections
AT73C260-EK1
AT73C260-EK1 Evaluation Kit User Guide
1-3
11071A–PMAAC–17-Sep-10
Figure 1-3.
AT73C260-EK1 Components Side
AT73C260
1-4
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Section 2
Getting Started
2.1
Jumper Electrostatic Warning
The AT73C260-EK1 evaluation board is shipped in protective anti-static packaging. The board must not
be subjected to high electrostatic potentials. A grounding strap or similar protective device should be
connected when handling the board. Avoid touching the components pins or any metallic element.
2.2
Requirements
In order to set up the AT73C260-EK1 evaluation kit the following items are needed:
1. The AT73C260-EK1 evaluation board itself.
2. One or more of the following connections:
– USB Type A Cable, USB Type B Cable, Micro USB Type AB Cable
– FPGA Cable, UICC Connector
3. Input/Output devices for upstream and downstream connection.
2.3
Instructions
2.3.1
To start the AT73C260-EK1 board
„
Configure the on-board jumpers as in the relevant paragraph below and connect the dedicated
connections:
1. Digital 6 Wires DAT_SE0 to IC_USB1.0: Section 2.6.1 ”Mode PHY_6_SE0” on page 2-14
2. Digital 4 Wires DAT_SE0 to IC_USB1.0: Section 2.6.2 ”Mode PHY_4_SE0” on page 2-15
3. Digital 6 Wires DP_DM to IC_USB1.0: Section 2.6.3 ”Mode PHY_6_DPDM” on page 2-16
4. Digital 4 Wires DP_DM to IC_USB1.0: Section 2.6.4 ”Mode PHY_4_DPDM” on page 2-17
5. Digital 3 Wires ULPI to IC_USB1.0: Section 2.6.5 ”Mode PHY_3_ULPI” on page 2-18
6. USB2.0 Section 7 to IC_USB1.0: Section 2.6.6 ”Mode S7_ICC” on page 2-19
7. PC USB2.0 Section 7 to IC_USB1.0 with VCC driven by DBB: Section 2.6.7 ”Mode S7_ICC_BB”
on page 2-20
8. USB2.0 Section 7 to IC_USB1.0 with VCC fixed by PVRF: Section 2.6.8 ”Mode S7_ICC_TK” on
page 2-21
9. IC_USB1.0 to USB2.0 Section 7: Section 2.6.9 ”Mode ICC_S7” on page 2-22
10. Voltage Class Converter: Section 2.6.10 ”Mode VCC” on page 2-23
AT73C260-EK1 Evaluation Kit User Guide
2-1
11071A–PMAAC–17-Sep-10
2.3.2
To turn off the AT73C260-EK1 evaluation board
„
2.4
Release all the connections made between Host/Device and AT73C260-EK1 Evaluation Kit
Block Diagram
Figure 2-1.
AT73C260 Block Diagram
9
AT73C260
PVRF
1
12
HVCC
PVCC
Vref
3.3Volt
4
VBUS
13
RCV
6
10
HDMO
PDM
7
HDPO
8
OE_N
2
11
HDP
PDP
3
HDM
M<2> M<1> M<0> GND
14
2-2
11071A–PMAAC–17-Sep-10
15
16
5
AT73C260-EK1 Evaluation Kit User Guide
2.5
Typical Application Connections
Figure 2-2.
Application Connections: Mode PHY_6_SEO
9
PVRF
AT73C260
1
12
HVCC
PVCC
C4
HVCC
PVCC
GND
VBUS
rx_dm
rx_dp
tx_enable_n
tx_dat
tx_se0
rx_rcv
rx_dm
6
rx_dp
7
tx_enable_n
8
tx_dat
2
tx_se0
3
RCV
VCC
10
HDMO
PDM
IC_DM
USB UICC
rx_rcv
13
HDPO
OE_N
11
HDP
ISO/IEC 7816-3
DIGITAL WRAPPER
UTMI
Vref
3.3Volt
4
ASIC/FPGA : 6 WIRES DAT_SE0
C5
IC_DP
PDP
HDM
M<2> M<1> M<0> GND
14
15
16
5
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
AT73C260-EK1 Evaluation Kit User Guide
2-3
11071A–PMAAC–17-Sep-10
Figure 2-3.
Application Connections: Mode PHY_4_SEO
9
AT73C260
PVRF
1
12
HVCC
GND
PVCC
C4
PVCC
VBUS
rx_rcv 13
RCV
VCC
rx_dm
6
nc
HDMO
rx_dp
7
nc
HDPO
tx_enable_n
tx_enable_n 8
10
11
HDP
tx_se0/rx_dm 3
tx_se0
ISO/IEC 7816-3
IC_DM
OE_N
tx_dat/rx_dp 2
tx_dat
PDM
USB UICC
DIGITAL WRAPPER
rx_rcv
C5
Vref
3.3Volt
4
ASIC/FPGA : 4 WIRES DAT_SE0
UTMI
HVCC
IC_DP
PDP
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
2-4
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Figure 2-4.
Application Connections: Mode PHY_6_DPDM
9
AT73C260
PVRF
1
HVCC
C4
12
PVCC
HVCC
PVCC
GND
VBUS
rx_dm
rx_dp
tx_enable_n
tx_dat
tx_se0
rx_rcv
rx_dm
6
rx_dp
7
tx_enable_n
8
tx_dp
2
tx_dm
3
RCV
VCC
10
PDM
HDMO
IC_DM
USB UICC
rx_rcv
13
HDPO
OE_N
11
ISO/IEC 7816-3
DIGITAL WRAPPER
UTMI
Vref
3.3Volt
4
ASIC/FPGA : 6 WIRES DP_DM
C5
IC_DP
PDP
HDP
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
AT73C260-EK1 Evaluation Kit User Guide
2-5
11071A–PMAAC–17-Sep-10
Figure 2-5.
Application Connections: Mode PHY_4_DPDM
9
PVRF
AT73C260
C4
1
12
HVCC
PVC
HVCC
PVCC
GND
VBUS
rx_rcv
RCV
VCC
rx_dm
6
nc
HDMO
rx_dp
7
nc
HDPO
tx_enable_n
tx_enable_n 8
tx_dp/rx_dp 2
tx_dat
tx_dm/rx_dm 3
tx_se0
10
PDM
IC_DM
OE_N
11
HDP
ISO/IEC 7816-3
rx_rcv 13
USB UICC
DIGITAL WRAPPER
UTMI
Vref
3.3Volt
4
ASIC/FPGA : 4 WIRES DP_DM
C5
IC_DP
PDP
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
2-6
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Figure 2-6.
Application Connections: Mode PHY_3_ULPI
9
PVRF
AT73C260
1
HVCC
C4
12
PVCC
HVCC
PVCC
GND
Vref
3.3Volt
4
ASIC/FPGA : 3 WIRES DAT, SE0, OE_N
C5
VBUS
DIGITAL WRAPPER
13
RCV
VCC
rx_dm
6
nc
HDMO
rx_dp
7
nc
HDPO
tx_enable_n
tx_enable_n 8
rx_rcv/tx_dat 2
tx_dat
rx_se0/tx_se0 3
tx_se0
10
PDM
IC_DM
OE_N
11
HDP
ISO/IEC 7816-3
nc
USB UICC
UTMI
rx_rcv
IC_DP
PDP
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Exa,mple:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
AT73C260-EK1 Evaluation Kit User Guide
2-7
11071A–PMAAC–17-Sep-10
Figure 2-7.
Application Connections: Mode S7_ICC
9
PVRF
AT73C260
1
12
HVCC
C4
GND
HVCC
PVCC
C5
PVCC
Vref
3.3Volt
4
VBUS
13
RCV
VCC
6
nc
HDMO
7
nc
HDPO
10
PDM
8
HVCC
OE_N
11
2
D+
HDP
ISO/IEC 7816-3
IC_DM
USB UICC
nc
IC_DP
PDP
3
D-
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
2-8
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Figure 2-8.
Application Connections: Mode S7_ICC_BB
RST
Digital
Base Band
CLK
I/O
9
PVRF
AT73C260
1
12
PVCC
HVCC
C4
HVCC
PVCC
GND
R3
C5
Vref
3.3Volt
4
VBUS
VBUS
C3
13
VCC
RCV
10
HDMO
7
nc
HDPO
PDM
IC_DM
8
HVCC
OE_N
ISO/IEC 7816-3
6
nc
USB UICC
nc
Host USB2.0 section7 with cable
R1
Downstream
section 7
port
D+
2
11
IC_DP
PDP
HDP
C1
3
D-
R2
HDM
C2
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is fixed at 3.3V. It is supplied by VBUS.
„
PVCC is fixed and controlled by PVRF delivered by Digital Base Band Chip. (Voltage Range: 1.65V <
PVCC < 3.6V)
AT73C260-EK1 Evaluation Kit User Guide
2-9
11071A–PMAAC–17-Sep-10
Figure 2-9.
Application Connections: Mode S7_ICC_TK
PVRF = PVCC = HVCC * R5/(R5+R4)
R4
R5
9
PVRF
AT73C260
1
12
HVCC
HVCC
C4
PVCC
GND
R3
PVCC
C5
Vref
3.3Volt
4
VBUS
VBUS
C3
13
RCV
VCC
6
nc
HDMO
7
nc
HDPO
10
PDM
8
HVCC
OE_N
ISO/IEC 7816-3
IC_DM
USB UICC
nc
Host USB2.0 section7 with cable
R1
Downstream
section 7
port
D+
2
11
IC_DP
PDP
HDP
C1
3
D-
R2
HDM
C2
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is fixed at 3.3V. It is supplied by VBUS.
„
PVCC is fixed by external resistor ratio R4/R5 on PVRF. (Voltage Range: 1.65V < PVCC < 3.6V)
2-10
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Figure 2-10. Application Connections: Mode ICC_S7
9
PVRF
HVCC
AT73C260
1
12
PVCC
C4 HVCC
C5
PVCC
GND
Vref
3.3Volt
4
VBUS
13
nc
6
nc
RCV
10
D-
PDM
HDMO
R6
7
nc
HVCC
IC_DP
HDPO
8
OE_N
11
2
D+
PDP
HDP
R7
IC_DM
3
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.3V. (Voltage Range: 1.65V < PVCC < 3.6V)
AT73C260-EK1 Evaluation Kit User Guide
2-11
11071A–PMAAC–17-Sep-10
Figure 2-11. Application Connections: Mode VCC
9
PVRF
AT73C260
1
12
HVCC
PVCC
C4
HVCC
PVCC
GND
C5
Vref
3.3Volt
4
VBUS
13
RCV
VCC
10
HDMO
7
nc
HDPO
PDM
IC_DM
8
HVCC
IC_DP
IC_DM
OE_N
11
2
ISO/IEC 7816-3
6
nc
USB UICC
nc
IC_DP
PDP
HDP
3
HDM
M<2> M<1> M<0> GND
14
15
16
5
HVCC
Hardware Setup Example:
„
HVCC is forced at 3.3V. (Voltage Range: 1.65V < HVCC < 3.6V)
„
PVCC is forced at 3.0V. (Voltage Range: 1.65V < PVCC < 3.6V)
2-12
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
2.6
Switch and Jumpers configuration according Interchip Mode
The AT73C260-EK1 can be used for various interchip configurations. These modes and the configuration to acheive in order to operate in this mode are described below. The following configuration modes
are described:
„
Digital 6 Wires unidirectional DAT_SE0 to IC_USB1.0: “Mode PHY_6_SE0” on page 2-14
„
Digital 4 Wires bidirectional DAT_SE0 to IC_USB1.0: “Mode PHY_4_SE0” on page 2-15
„
Digital 6 Wires unidirectional DP_DM to IC_USB1.0: “Mode PHY_6_DPDM” on page 2-16
„
Digital 4 Wires bidirectional DP_DM to IC_USB1.0: “Mode PHY_4_DPDM” on page 2-17
„
Digital 3 Wires bidirectional ULPI to IC_USB1.0: “Mode PHY_3_ULPI” on page 2-18
„
USB2.0 Section 7 to IC_USB1.0: “Mode S7_ICC” on page 2-19
„
PC’s USB2.0 Section 7 to IC_USB1.0 with VCC driven by DBB: “Mode S7_ICC_BB” on page 2-20
„
USB2.0 Section 7 to IC_USB1.0 with VCC fixed by PVRF: “Mode S7_ICC_TK” on page 2-21
„
IC_USB1.0 to USB2.0 Section 7: “Mode ICC_S7” on page 2-22
„
Voltage Class Converter: “Mode VCC” on page 2-23
AT73C260-EK1 Evaluation Kit User Guide
2-13
11071A–PMAAC–17-Sep-10
2.6.1
Mode PHY_6_SE0
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground.
„
Force M<2:0> pins to ground by switching SW1, SW2 and SW3 to ground.
„
Connect HOST FPGA connector on J24.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Three devices choices are possibles:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed Jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-12. On Board Jumpers, Switches and Connectors Description
HOST
POWER
UICC
FPGA
CONNECTOR
DEVICE
2-14
11071A–PMAAC–17-Sep-10
DEVICE
POWER
AT73C260-EK1 Evaluation Kit User Guide
2.6.2
Mode PHY_4_SE0
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground.
„
Force M<2> pin to HVCC by switching SW1 to HVCC and close J21 Jumper.
„
Force M<1:0> pins to ground by switching SW2 and SW3 to ground.
„
Connect HOST FPGA connector on J24.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-13. On Board Jumpers, Switches and Connectors
HOST
POWER
UICC
FPGA
CONNECTOR
DEVICE
AT73C260-EK1 Evaluation Kit User Guide
DEVICE
POWER
2-15
11071A–PMAAC–17-Sep-10
2.6.3
Mode PHY_6_DPDM
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground.
„
Force M<1> pin to HVCC by switching SW2 to HVCC and close J22 Jumper.
„
Force M<0> and M<2> pins to ground by switching SW1 and SW3 to ground.
„
Connect HOST FPGA connector on J24.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-14. On Board Jumpers, Switches and Connectors
HOST
POWER
UICC
FPGA
CONNECTOR
DEVICE
2-16
11071A–PMAAC–17-Sep-10
DEVICE
POWER
AT73C260-EK1 Evaluation Kit User Guide
2.6.4
Mode PHY_4_DPDM
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground.
„
Force M<1:0> pins to HVCC by switching SW1 ans SW2 to HVCC. Close J21 and J22 Jumpers.
„
Force M<2> pin to ground by switching SW3 to ground.
„
Connect HOST FPGA connector on J24.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-15. On Board Jumpers, Switches and Connectors
HOST
POWER
UICC
FPGA
CONNECTOR
DEVICE
AT73C260-EK1 Evaluation Kit User Guide
DEVICE
POWER
2-17
11071A–PMAAC–17-Sep-10
2.6.5
Mode PHY_3_ULPI
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground.
„
Force M<0> and M<2> pins to HVCC. Switch SW1 and SW3 to HVCC. Close J21 and J23 Jumpers.
„
Force M<1> pin to ground by switching SW2 to ground.
„
Connect HOST FPGA connector on J24.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-16. On Board Jumpers, Switches and Connectors
HOST
POWER
UICC
FPGA
CONNECTOR
DEVICE
2-18
11071A–PMAAC–17-Sep-10
DEVICE
POWER
AT73C260-EK1 Evaluation Kit User Guide
2.6.6
Mode S7_ICC
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened. Close G1 and G2 Copper Pads.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground. Force OE_N pin to HVCC
„
Force M<1> and M<2> pins to HVCC. Switch SW2 and SW3 to HVCC. Close J22 and J23 Jumpers.
„
Force M<0> pin to ground by switching SW1 to ground.
„
Connect HOST on connector J1 or J17.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-17. On Board Jumpers, Switches and Connectors
HOST
POWER
UICC
HOST
HVCC
AT73C260-EK1 Evaluation Kit User Guide
DEVICE
DEVICE
POWER
2-19
11071A–PMAAC–17-Sep-10
2.6.7
Mode S7_ICC_BB
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Connect Digital Base Band Reference on TP15 Test Point. (PVRF)
„
Close G1 and G2 as specified in the top view below.
„
Apply VBUS on P1 pad (VBUS-IN). Close J12 and J16 Jumpers.
„
Force OE_N pin to HVCC level.
„
Force M<1> and M<2> pins to HVCC. Switch SW2 and SW3 to HVCC. Close J22 and J23 Jumpers.
„
Force M<0> pin to ground by switching SW1 to ground.
„
Connect HOST on connector J1 or J17.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-18. On Board Jumpers, Switches and Connectors
UICC
HOST
USB
POWER
2-20
11071A–PMAAC–17-Sep-10
HVCC
DEVICE
AT73C260-EK1 Evaluation Kit User Guide
2.6.8
Mode S7_ICC_TK
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount resistors R7 and R8 in order to obtain the expected ratio.
„
Close G1 and G2 as specified in the top view below.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Close J11 Jumper. Close J12 and J16 Jumpers.
„
Force OE_N pin to HVCC
„
Force M<1> and M<2> pins to HVCC. Switch SW2 and SW3 to HVCC. Close J22 and J23 Jumpers.
„
Force M<0> pin to ground by switching SW1 to ground.
„
Connect HOST on connector J1 or J17.
„
Apply VBUS on P1 pad (VBUS-IN).
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-19. On Board Jumpers, Switches and Connectors
UICC
HOST
USB
POWER
AT73C260-EK1 Evaluation Kit User Guide
HVCC
DEVICE
2-21
11071A–PMAAC–17-Sep-10
2.6.9
Mode ICC_S7
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened.
„
Close G1 and G2 Copper Pads.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground.
„
Force OE_N pin to HVCC
„
Force M<2:0> pins to HVCC. Switch SW1, SW2 and SW3 to HVCC.
„
Close J21, J22, J23, J2 and J3 Jumpers.
„
Connect HOST on connector J1 or J17.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Two devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
Figure 2-20. On Board Jumpers, Switches and Connectors
HOST
POWER
HOST
HVCC
2-22
11071A–PMAAC–17-Sep-10
DEVICE
DEVICE
POWER
AT73C260-EK1 Evaluation Kit User Guide
2.6.10
Mode VCC
First of all, the configuration for this mode means that initially all the jumpers must be removed.
„
Mount a 0 Ω resistor on R8. J11 Jumper must be opened. Close G1 and G2 Copper Pads.
„
Close J5 Jumper between pin 1 & 2. PVRF must be connected to REFP_LDOH.
„
Force Pin1 of the Jumper J12 (VBUS) to ground. Force OE_N pin to HVCC
„
Force M<2:0> pins to HVCC. Switch SW1, SW2 and SW3 to HVCC.
„
Close J21, J22 and J23 Jumpers.
„
Connect Power Supply of the Host on P3 pad and close J14 Jumper.
„
Connect Power Supply of the Device on P6 pad and close J13 Jumper.
„
Connect HOST on connector J1 or J17.
„
Three devices choices are possible:
– Connect Device on J18 Connector
– or Connect Device on J15 connector
– or Connect UICC on J10 connector
„
For this last device configuration, it is necessary to set the listed jumpers as follows:
– Close Jumper J25
– Mount a 100kΩ resistor on R9, R10, R11 and R12 (if necessary).
– Close J6, J7, J8 Jumpers between pin 2 & 3. All nets must be connected to GROUND.
– Close J9 Jumper between pin 1 & 2. C6_SWP must pull-up at PVCC level.
Figure 2-21. On Board Jumpers, Switches and Connectors
HOST
POWER
UICC
HOST
HVCC
AT73C260-EK1 Evaluation Kit User Guide
DEVICE
DEVICE
POWER
2-23
11071A–PMAAC–17-Sep-10
2.7
Configuration Pads
A Configuration Pad configures the AT73C260-EK1 Evaluation Board for a custom application. The configuration is programmable by soldering a specific part of the Configuration Pad. To return to the initial
configuration, the customer has to solder a short jumper.
Figure 2-22. Configuration Pads with 2 Options
Connected
Solder
Not connected
No solder
2-24
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Section 3
Technical Specifications
„
System Unit
– Physical Dimensions..................................................................L= 119.27 mm x W=65.97 mm x H=2.5 mm
– Weight.........................................................................................................................................................70 g
„
Operating Conditions
– External Voltage Supply (On HVCC Pad)..................................................................3.3V Typical (3.6V Max)
– External Voltage Supply (On PVCC Pad)........................................................1.8V / 3.0V Typical (3.6V Max)
– USB Voltage Supply (on VBUS Pad)..............................................................................................5.0V +/- 5%
„
Connections
–
–
–
–
–
FPGA Communication Connector........................................................................................2x5 pins Header
Smart Card Reader Connector............................................................................................1x10 pins Header
USB Host Connector...........................................................................1 USB Type B / 1 Micro USB Type AB
USB Device Connector.......................................................................1 USB Type A / 1 Micro USB Type AB
Mini Smart Card Connector..................................................................................................2x4 pins Contact
AT73C260-EK1 Evaluation Kit User Guide
3-1
11071A–PMAAC–17-Sep-10
3-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Section 4
Schematics
Figure 4-1.
AT73C260-EK1 Schematic
AT73C260-EK1 Evaluation Kit User Guide
4-1
11071A–PMAAC–17-Sep-10
4-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Section 5
Revision History
5.1
Revision History
Table 5-1. Revision History
Document
Date
Comments
11071A
17-Sep-10
First Issue, 17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Change
Request Ref.
5-1
11071A–PMAAC–17-Sep-10
5-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Atmel Asia
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
Hong Kong
Tel: (852) 2245-6100
Fax: (852) 2722-1369
Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Technical Support
pmaac@atmel.com
Sales Contacts
www.atmel.com/contacts/
Product Contact
Web Site
www.atmel.com
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2010 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof and others, are registered trademarks or trademarks of
Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
11071A–PMAAC–17-Sep-10
/0M
6-2
11071A–PMAAC–17-Sep-10
AT73C260-EK1 Evaluation Kit User Guide