DS07-16316-2E

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16316-2E
32-bit Proprietary Microcontrollers
CMOS
FR30
MB91F158 Series
MB91F158
■ DESCRIPTION
The MB91F158 series is a microcontroller for CD/DVD using a RISC-CPU (FR 30 series) as its core.
■ FEATURES
1. CPU
•
•
•
•
•
•
•
•
•
32-bit RISC (FR30) , load/store architecture, 5-stage pipeline
General-purpose registers : 32 bits × 16
16-bit fixed-length instructions (basic instructions) , 1 instruction/ 1 cycle
Memory-to-memory transfer, bit processing, barrel shift processing : Optimized for embedded applications
Function entrance/exit instructions, and multiple load/store instructions of register contents, instruction systems
supporting high level languages
Register interlock functions, efficient assembly language description
Branch instructions with delay slots : Reduced overhead time in branching executions
Internal multiplier/supported at instruction level
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupt (PC and PS saving) : 6 cycles, 16 priority levels
2. Bus Interface
•
•
•
•
•
24-bit address output, 8/16-bit data input and output
Basic bus cycle : 2-clock cycle
Support for interface for various types of memory
Unused data/address pins can be configured us input/output ports
Support for little endian mode
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2003-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.10
MB91F158 Series
3. Internal ROM
FLASH products : 510 Kbytes
4. Internal RAM
2 Kbytes
5. Internal Data RAM
6 Kbytes
6. Bit Search Module
Searches in one cycle for the position of the bit that changes from the MSB in one word to the initial I/O.
7. Timers
•
•
•
•
16-bit OCU × 4 channels, ICU × 4 channels, Free-run timer × 1 channel
8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel)
16-bit PPG timer × 4 channels. The output pulse cycle and duty can be varied as desired
16-bit reload timer × 2 channels
8. D/A Converter
• 8-bit × 3 channels
9. A/D Converter (Sequential Comparison Type)
• 10-bit × 8 channels
• Sequential conversion method (conversion time : 5.2 µ[email protected] MHz)
• Single conversion or scan conversion can be selected, and one-shot or continuous or stop conversion mode
can be set respectively.
• Conversion starting function by hardware/software.
10. Serial I/O
• UART × 2 channels. Any of them is capable of serial transfer in sync with clock attached with the LSB/MSB
switching function.
• Serial data output and serial clock output are selectable by push-pull/open drain software.
• A 16-bit timer (U-timer) is contained as a dedicated baud rate generator allowing any baud rate to be generated.
11. Clock Switching Function
• Gear function : Operating clock ratios to the basic clock can be set independently for the CPU and peripherals
from four types, 1 : 1, 1 : 2, 1 : 4 or 1 : 8.
12. Interrupt Controller
External interrupt input (16 channels in total) :
• Allows the rising edge/falling edge ”H” level/” L” level to be set.
Internal interrupt factors :
• Interrupt by resources and delay interrupt
13. Others
•
•
•
•
•
•
2
Reset cause : Power on reset/watchdog timer/software reset/external reset
Low power consumption mode : Sleep/stop mode
Package : 120-pin LQFP
CMOS technology (0.35 µm)
Power supply voltage : 3.2 V to 3.5 V
Operation frequency upper limit
CPU
: 32 MHz
Peripheral circuit : 32 MHz
External bus
: 25 MHz
DS07-16316-2E
MB91F158 Series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MB91F158
TOP VIEW
(LQFP-120)
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3
PE2
PE1
PE0
VCC
VSS
PD7/INT15/ATG
PD6/INT14
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1/TRG3
PD2/INT10/AIN1/TRG2
PD1/INT9/BIN0/TRG1
PD0/INT8/AIN0/TRG0
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
P67/A23
VSS
VCC
P80/RDY
P81/BGRNT
P82/BRQ
P83/RD
P84/WR0
P85/WR1
P86/CLK
MD2
MD1
MD0
RST
VCC
X1
X0
VSS
PC0/INT0
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
VSS
VCC
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
PK7/AN7
PK6/AN6
PK5/AN5
PK4/AN4
PK3/AN3
PK2/AN2
PK1/AN1
PK0/AN0
AVSS
AVRL
AVRH
AVCC
DAVC
DAVS
DA0
DA1
DA2
SSEL
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
VSS
VCC
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
■ PIN ASSIGNMENT
(FPT-120P-M24)
DS07-16316-2E
3
MB91F158 Series
■ PIN DESCRIPTION
Circuit
type
Function
Pin No.
Pin name
1
2
3
4
5
6
7
8
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
C
Bit 16 to bit 23 of external data bus
These pins are enabled only in 16-bit external bus mode.
These pins are available as ports in single-chip and 8-bit external bus
modes.
9
10
11
12
13
14
15
16
D24/P30
D25/P31
D26/P32
D27/P33
D28P34
D29/P35
D30/P36
D31/P37
C
Bit 24 to bit 31 of external data bus
These pins are available as ports in single-chip mode.
17
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57
F
Bit 0 to bit 15 of external address bus
These pins are enabled in external bus mode.
These pins are available as ports in single-chip mode.
35
36
37
38
39
40
41
42
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
O
Bit 16 to bit 23 of external address bus
These pins are available as ports when the address bus is not in use.
C
External RDY input
This function is enabled when external RDY input is allowed.
Input “0” when the bus cycle being executed does not end.
This pin is available as a port when external RDY input is not in use.
45
RDY/P80
(Continued)
4
DS07-16316-2E
MB91F158 Series
Pin No.
46
47
Pin name
BGRNT/P81
BRQ/P82
Circuit
type
Function
F
External bus release acceptance output
This function is enabled when external bus release acceptance output is
allowed.
Output “L” upon releasing of the external bus.
This pin is available as a port when external bus release acceptance
output is not allowed.
C
External bus release request input
This function is enabled when external bus release request input is
allowed.
Input “1” when the release of the external bus is desired.
This pin is available as a port when external bus release request input is
not in use.
48
RD/P83
F
External bus read strobe output
This function is enabled when external bus read strobe output is allowed.
This pin is available as a port when external bus read strobe output is not
allowed.
49
WR0/P84
F
External bus write strobe output
This function is enabled in external bus mode.
This pin is available as a port in single chip mode.
50
WR1/P85
F
External bus write strobe output
This function is enabled in external bus mode when the bus width is 16
bits.
This pin is available as a port in single chip mode or when the external bus
width is 8 bits.
51
CLK/P86
F
System clock output
The pin outputs the same clock as the external bus operating frequency.
The pin is available as a port when it is not used to output the clock.
52
53
54
MD2
MD1
MD0
G
Mode pins
To use these pins, connect them directly to either VCC or VSS.
Use these pins to set the basic MCU operating mode.
55
RST
B
External reset input
57
58
X1
X0
A
High-speed clock oscillation pins
H
External interrupt request input 0 to 3
Since this input is used more or less continuously when the corresponding
external interrupt is allowed, output by the port needs to be stopped except when it is performed intentionally.
Since this port is allowed to input also in standby mode, it can be used to
reset the standby state.
These pins are available as ports when external interrupt request input is
not in use.
60
61
62
63
INT0/PC0
INT1/PC1
INT2/PC2
INT3/PC3
(Continued)
DS07-16316-2E
5
MB91F158 Series
Pin No.
Pin name
Circuit
type
64
65
66
67
INT4/PC4/CS0
INT5/PC5/CS1
INT6/PC6/CS2
INT7/PC7/CS3
H
68
69
70
71
72
73
PD0/AIN0/INT8/TRG0
PD1/BIN0/INT9/TRG1
PD2/AIN1/INT10/TRG2
PD3/BIN1/INT11/TRG3
PD4/ZIN0/INT12
PD5/ZIN1/INT13
H
74
PD6/INT14
H
75
PD7/ATG/INT15
H
78
79
80
81
82
83
84
85
PE0
PE1
PE2
PE3
PE4/OC4
PE5/OC5
PE6/OC6
PE7/OC7
Function
These pins also serve as the chip select output and external interrupt request input 4 to 7.
When the chip select output is not allowed, these pins are available
as external interrupt requests or ports.
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed intentionally.
Since this port is also allowed to input in standby mode, the port can
be used to reset the standby state.
These pins are available as ports when external interrupt request
input and chip select output are not in use.
External interrupt request input 8 to 13
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed intentionally.
[AIN, BIN] Up/down timer input.
[TRG] PPG external trigger input.
Since this input is used more or less continuously while input is
allowed, output by the port needs to be stopped except when it is
performed intentionally.
These pins are available as ports when the external interrupt
request input, up timer counter input, and PPG external trigger input
are not in use.
External interrupt request input 14
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed intentionally.
External interrupt request input 15
Since this input is used more or less continuously when the corresponding external interrupt is allowed, output by the port needs to
be stopped except when it is performed intentionally.
[ATG] A/D converter external trigger input.
Since this input is used more or less continuously when selected as
an A/D activation factor, output by the port needs to be stopped
except when it is performed intentionally.
This pin is available as a port when it is not in use as the external
interrupt request input or DMA external transfer end output.
F
General-purpose I/O ports
F
Output compare output
These pins are available as ports when output compare output is
not allowed.
(Continued)
6
DS07-16316-2E
MB91F158 Series
Pin No.
Pin name
Circuit
type
Function
86
87
88
89
PF0/IN0
PF1/IN1
PF2/IN2
PF3/IN3
F
Input capture input
This function is enabled when the input capture operation is input.
These pins are available as ports when input capture input is not in use.
90
PF4
F
General purpose I/O port
91
92
93
94
PG0/PPG0
PG1/PPG1
PG2/PPG2
PG3/PPG3
F
PPG timer output
This function is enabled when PPG timer output is allowed.
These pins are available as ports when PPG timer output is not allowed.
97
PI2/SCK2/TO2
P
UART2 clock I/O, Reload timer 2 output
When UART2 clock output is not allowed, reload timer 2 can be output by
allowing it.
This pin is available as a port when neither UART2 clock output nor reload
timer output is allowed.
98
PI1/SOT2
P
UART2 data output
This function is enabled when UART2 data output is allowed.
This pin is available as a port when UART2 clock output is not allowed.
P
UART2 data input
Since this input is used more or less continuously while UART2 is
engaged in input operations, output by the port needs to be stopped
except when it is performed intentionally.
This pin is available as a port when UART2 data input is not in use.
99
PI0/SIN2
100
PH2/SCK0/TO0
P
UART0 clock I/O, Reload timer 0 output
When UART0 clock output is not allowed, reload timer 0 can be output by
allowing it.
This pin is available as a port when neither UART0 clock output nor reload
timer output is allowed.
101
PH1/SOT0
P
UART0 data output
This function is enabled when UART0 data output is allowed.
This pin is available as a port when UART0 clock output is not allowed.
102
PH0/SIN0
P
UART0 data input
Since this input is used more or less continuously while UART0 is
engaged in input operations, output by the port needs to be stopped
except when it is performed intentionally.
This pin is available as a port when UART0 data input is not in use.
103
SSEL
G
Sector mode switching pin of FLASH
This pin should be connected to VCC or VSS.
104
105
106
DA2
DA1
DA0
⎯
D/A converter output
This function is enabled when D/A converter output is allowed.
107
DAVS
⎯
Power supply pin for D/A converter
108
DAVC
⎯
Power supply pin for D/A converter
109
AVCC
⎯
VCC power supply pin for A/D converter
(Continued)
DS07-16316-2E
7
MB91F158 Series
(Continued)
Pin No.
Pin name
Circuit
type
Function
110
AVRH
⎯
A/D converter reference voltage (high potential side)
Be sure to turn on/off this pin with potential higher than AVRH applied to
VCC.
111
AVRL
⎯
A/D converter reference voltage (low potential side)
112
AVSS
⎯
VSS power supply for A/D converter.
113
114
115
116
117
118
119
120
AN0/PK0
AN1/PK1
AN2/PK2
AN3/PK3
AN4/PK4
AN5/PK5
AN6/PK6
AN7/PK7
N
A/D converter analog input
These pins are enabled when the AIC register is designated for analog
input.
These pins are available as ports when A/D converter analog input is not
in use.
19, 44,
56, 77,
95
VCC
⎯
Power supply pin (VCC) for digital circuit
Always all Vcc pins must be connected to the power supply.
18, 43,
59, 76,
96
VSS
⎯
Earth level (VSS) for digital circuit
Always all Vss pins must be connected to the power supply.
Note : On the majority of pins listed above, the I/O port and the resource I/O are multiplexed, such as XXXX/Pxx.
When the port and the resource output compete against each other on these pins, priority is given to the
resource.
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DS07-16316-2E
MB91F158 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
Xout
A
• High-speed oscillation circuit
Oscillation feedback resistor =
approx. 1 MΩ
X0
Standby control signal
• CMOS hysteresis input pin
CMOS hysteresis input
(standby control not attached)
Pullup resistor
B
Digital input
Pout
Nout
C
• CMOS level I/O pin
CMOS level output
CMOS level input
(attached with standby control)
IOL = 4 mA
R
CMOS level input
Standby control
Pout
Nout
F
• CMOS hysteresis I/O pin
CMOS level output
CMOS hysteresis input
(attached with standby control)
IOL = 4 mA
R
CMOS hysteresis input
Standby control
(Continued)
DS07-16316-2E
9
MB91F158 Series
Type
Circuit
Remarks
• CMOS level input pin
CMOS level input
(standby control not attached)
G
R
Digital input
Pullup control
Pout
R
H
Nout
R
CMOS hysteresis input
Pout
Nout
N
R
CMOS level input
• CMOS hysteresis I/O pin with
pullup control
CMOS level output
CMOS hysteresis input
(standby control not attached)
Pullup resistance =
approx. 50 kΩ (Typ)
IOL = 4 mA
• Analog/CMOS level I/O pin
CMOS level output
CMOS level input
(attached with standby control)
Analog input (Analog input is enabled when AIC’s corresponding
bit is set to “1”.)
IOL = 4 mA
Standby control
Analog input
(Continued)
10
DS07-16316-2E
MB91F158 Series
(Continued)
Type
Circuit
Remarks
Pullup control
Pout
R
O
Nout
R
CMOS hysteresis input
• CMOS hysteresis I/O pin
with pullup control
CMOS level output
CMOS hysteresis input
(attached with standby control)
Pullup resistance = approx. 50 kΩ
(Typ)
IOL = 4 mA
Standby control
Pullup control
Open drain control
R
P
Nout
R
• CMOS hysteresis I/O pin
with pullup control.
CMOS level output
(attached with open drain control)
CMOS hysteresis input
(attached with standby control)
Pullup resistance = approx. 50 kΩ
(Typ)
CMOS hysteresis input
Standby control
DS07-16316-2E
IOL = 4 mA
11
MB91F158 Series
■ HANDLING DEVICES
1. Preventing Latchup
In CMOS ICs, applying voltage higher than VCC or lower than VSS to input/output pin or applying voltage over
rating across VCC and VSS may cause latchup.
This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the
device. Make sure to prevent the voltage from exceeding the maximum rating.
2. Treatment of Pins
• Treatment of unused pins
Unused pins left open may cause malfunctions. Make sure to connect them to pull-up or pull-down resistors.
• Treatment of open pins
Be sure to use open pins in open state.
• Treatment of output pins
Shortcircuiting an output pin with the power supply or with another output pin or connecting a large-capacity
load may causes a flow of large current. If this conditions continues for a long period of time, the device
deteriorates. Take great care not to exceed the absolute maximum ratings.
• Mode pins (MD0-MD2)
These pins should be used directly connected to either VCC or VSS. In order to prevent noise from causing
accidental entry into test mode, keep the pattern length as short as possible between each mode pin and VCC
or VSS on the board and connect them with low impedance.
• Power supply pins
When there are several VCC and VSS pins, each of them is equipotentially connected to its counterpart inside
of the device, minimizing the risk of malfunctions such as latch up. To further reduce the risk of malfunctions,
to prevent EMI radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and
to observe the total output current standard, connect all VCC and VSS pins to the power supply or GND.
It is preferred to connect VCC and VSS of this device to power supply with minimal impedance possible.
It is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 µF between VCC
and VSS at a position as close as possible to this device.
• Crystal oscillator circuit
Noises around X0 and X1 pins may cause malfunctions of this device. In designing the PC board, layout X0,
X1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible.
It is strongly recommended to design PC board so that X0 and X1 pins are surrounded by grounding area for
stable operation.
3. Precautions
• External Reset Input
It takes at least 5 machine cycle to input “L” level to the RST pin and to ensure inner reset operation properly.
• External Clocks
When using an external clock, normally, a clock of which the phase is opposite to that of X0 must be supplied
to the X0 and X1 pins simultaneously. However, when using the clock along with STOP (oscillation stopped)
mode, the X1 pin stops when “H” is output in STOP mode. To prevent one output from competing against
another, an external resistor of about 1 kΩ should be provided.
12
DS07-16316-2E
MB91F158 Series
The following figure shows an example usage of an external clock.
Figure 3.1 An example usage of an external clock
X0
X1
MB91F158 series
• Care during operating of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
• Watchdog timer function
The watchdog timer supported by the FR family monitors the program that performs the reset delay operation
for a specified time. If the program hangs and the reset delay operation is not performed, the watchdog timer
resets the CPU. Therefore, once the watchdog timer is enabled, operation continues until the CPU is reset.
As an exception, a reset delay automatically occurs if the CPU stops program execution. For the conditions
that apply to this exception, refer to the section that describes the watchdog function.
4. Care during Powering Up
• When powering up
When turning on the power supply, never fail to start from setting the RST pin to “L” level. And after the power
supply voltage goes to VCC level, at least after ensuring the time for 5 machine cycle, then set to “H” level.
• Source oscillation input
At turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing
waiting.
• Power on resetting
When powering up or when turning the power back on after the supply voltage drops below the operation
assurance range, be sure to reset the power.
• Power on sequence
Turn on the power in the order of VCC, AVCC and AVRH. The power should be disconnected in inverse order.
• Even when an A/D converter is not in use, connect AVCC to the VCC level and AVSS to the VSS level.
• Even when a D/A converter is not in use, connect DAVC to the VCC level and DAVS to the VSS level.
DS07-16316-2E
13
MB91F158 Series
■ BLOCK DIAGRAM
• MB91F158
Bus
Control
( )
E
P
O
R
T
6
/
5
/
4
P40/A0
24
P86/CLK (O)
P85/WR1 (O)
P84/WR0
P83/RD (O)
P82/BRQ (I)
P81/BGRNT (O)
P80/RDY (I)
P
O
R
T
( )
P67/A23 (O)
P50/A8
P47/A7
P
O
R
T
Data RAM
6 KB
8
P
O
R
T
Bit Search
D - bus
R - bus
D - bus
C - bus
External
Bus CTL
8
7
RAM
2 KB
ROM
510 KB
UART 2 ch
UTIMER 2 ch
Output
Compare
PG3/PPG3
PG2/PPG2
PG1/PPG1
PG0/PPG0
P
O
R
T
PH0/SIN0
PH1/SOT0
PH2/SCK0/TO0
G
4
I - bus
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
PE3
PE2
PE1
PE0
( )
16
( )
P20/D16
P60/A16
P57/A15
Address
P
O
R
T
3
/
2
PPG
H
( )
P30/D24
P27/D23
D - bus
4
( )
DATA
FR30 CPU Core
I - bus
3
16 bit
Reload Timer
2 ch
P
O
R
T
16 bit
Free-run Timer
1 ch
( )
P37/D31 (IO)
M
O
D
E
( )
MD0
MD1
MD2
RST
PI0/SIN2
PI1/SOT2
PI2/SCK2/TO2
UART
TOX:
Reload
Timer
I
3
16 bit PPG
4 ch
14
Interrupt
Controller
16 bit
Output Compare
4 ch
K
10 bit 8 input
A/D converter
)
D
P
O
R
T
C
8
8 bit
Up/Down
Counter
2 ch
External
Interrupt
16 ch
8
P
O
R
T
F
( )
8
( )
Clock
Control
5
8 bit 3 output
D/A converter
D
A
( )
External
Interrupt
P
O
R
T
(
Up/Down
Counter
PD7/INT15/ATG (I)
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
PD2/INT10/AIN1
PD1/INT9/BIN0 (I)
PD0/INT8/AIN0 (I)
PC7/INT7/CS3
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0 (I)
OSC
(2)
)
A/D
DMAC
X0 (I)
X1 (I)
P
O
R
T
3
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
PF4
PF3/IN3
PF2/IN2
PF1/IN1
PF0/IN0
A/D
Input
Capture
DA2
DA1
DA0
(
Clock
16 bit
Input Capture
4 ch
DS07-16316-2E
MB91F158 Series
■ CPU CORE
1. Memory Space
The FR family has a logical address space of 4 Gbytes (232 bytes) and the CPU linearly accesses the memory
space.
• Direct addressing area
The following area in the address space is used for I/O.
This area is called direct addressing area and an operand address can be specified directly in an instruction.
The direct addressing area varies with the data size to be accessed as follows :
→ byte data access :
0-0FFH
→ half word data access : 0-1FFH
→ word data access :
0-3FFH
2. Memory Map
• Memory Space
External ROMexternal bus mode
Internal ROMexternal bus mode
Single-chip mode
I/O
I/O
I/O
I/O
I/O
I/O
Not accessible
Not accessible
Not accessible
6 KB
internal RAM
6 KB
internal RAM
6 KB
internal RAM
Not accessible
Not accessible
Not accessible
0000 0000H
0000 0400H
Direct
addressing
area
0000 0800H
0000 1000H
0000 2800H
0001 0000H
0001 0000H
External area
Not accessible
0008 0000H
External area
2 KB internal RAM
2 KB internal RAM
510 KB
internal ROM
510 KB
internal ROM
0008 0800H
0010 0000H
External area
FFFF FFFFH
Not accessible
FFFF FFFFH
Note : External areas are not accessible in single-chip mode.
DS07-16316-2E
15
MB91F158 Series
3. Registers
The family of FR microcontrollers has two types of registers : the registers residing in the CPU which are dedicated
to applications and the general-purpose registers residing in the memory.
• Dedicated registers :
Program counter (PC)
Program status (PS)
Tablebase register (TBR)
: A 32-bit register to indicate the location where an instructions is stored.
: A 32-bit register to store a register pointer or a condition code.
: Holds the vector table lead address used when EIT (exceptions/interrupt/
trap) is processed.
Return pointer (RP)
: Holds the address to return from a subroutine.
System stack pointer (SSP) : Points to the system stack space.
User stack pointer (USP)
: Points to the user stack space.
Multiplication and division result register (MDH/MDL) : A 32-bit multiplication and division register.
Initial value
32 bits
PC
Program counter
PS
Program status
XXXX XXXXH (Undefined)
Tablebase register
000F FC00H
Return pointer
XXXX XXXXH (Undefined)
SSP
System stack pointer
0000 0000H
USP
User stack pointer
XXXX XXXXH (Undefined)
TBR
RP
MDH
Multiplication and division register
XXXX XXXXH (Undefined)
XXXX XXXXH (Undefined)
MDL
• Program status (PS)
The PS register holds program status and is further divided into three registers which are a Condition Code
Register (CCR) , a System condition Code Register (SCR) , and an Interrupt Level Mask register (ILM) .
31
PS
⎯
20
19
18
16
ILM4 ILM3 ILM2 ILM1 ILM0
ILM
16
17
⎯
10
9
8
7
6
5
4
3
2
1
0
D1
D0
T
⎯
⎯
S
I
N
Z
V
C
SCR
CCR
DS07-16316-2E
MB91F158 Series
• Condition Code Register (CCR)
S flag : Designates the stack pointer for use as R15.
I flag
: Controls enabling and disabling of user interrupt requests.
N flag : Indicates the sign when arithmetic operation results are considered to be an integer represented
by 2’s complement.
Z flag : Indicates if arithmetic results were “0”.
V flag : Considers the operand used for an arithmetic operation to be an integer represented by 2’s complement and indicates if the operation resulted in an overflow.
C flag : Indicates whether or not an arithmetic operation resulted in a carry or a borrow from the most significant bit.
• System condition Code Register (SCR)
T flag : Designates whether or not to enable step trace trap.
• Interrupt Level Mask register (ILM)
ILM4 to ILM0
: Holds an interrupt level mask value to be used for level masking.
An interrupt request is accepted only if the corresponding interrupt level among interrupt
requests input to the CPU is higher than the value indicated by the ILM register.
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-Low
0
0
0
0
0
0
Higher
0
1
0
0
0
15
1
1
1
1
1
31
DS07-16316-2E
Lower
17
MB91F158 Series
■ GENERAL-PURPOSE REGISTERS
General-purpose registers are CPU registers R0 through R15 and used as accumulators during various operations and as memory access pointers (fields indicating addresses) .
• Register Bank Configuration
32 bits
R0
Initial value
XXXX XXXXH
R1
R12
R13
AC (Accumulator)
R14
FP (Frame Pointer)
XXXX XXXXH
R15
SP (Stack Pointer)
0000 0000H
Of the 16 general-purpose registers, the following registers are assumed for specific applications. For this reason,
some instructions are enhanced.
R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)
Initial values to which R0 through R14 are reset are not defined. The initial value of R15 is 0000 0000H (the SSP
value) .
18
DS07-16316-2E
MB91F158 Series
■ SETTING MODE
1. Mode Pins
As shown in Table 1 three pins, MD2, 1, and 0 are used to indicate an operation.
Table 1 Mode pins and set modes
Mode pin
Reset vector
External data
Mode name
access area
bus width
MD2 MD1 MD0
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
0
1
0
External vector mode 2
External
32 bits
0
1
1
External vector mode
Internal
(Mode register)
1
⎯
⎯
⎯
⎯
⎯
External ROM bus mode
Not available on this
product type
Single-chip mode
Not available
2. Mode Data
The data which the CPU writes to “0000 07FFH” after reset is called mode data.
It is the mode register (MODR) that exists at “0000 07FFH.” Once a mode is set in this register, operations will
take place in that mode. The mode register can be written only once after reset.
The mode specified in the register is enabled immediately after it is written.
MODR
Address : 0000 07FFH
M1
Initial value Access
XXXXXXXX
W
M0
Bus mode setting bits
W : Write only, X : Undefined
[bit 7, bit 6] : M1, M0
These are bus mode setting bits. Specify the bus mode to be set to after writing to the mode register.
M1
M0
Function
Remarks
0
0
Single-chip mode
0
1
Internal ROM-external bus mode
1
0
External ROM-external bus mode
1
1
⎯
Setting not allowed
[bit 5 to bit0] : *
These bits are reserved for the system.
“0” should be written to these bits at all times.
DS07-16316-2E
19
MB91F158 Series
[Precautions when Writing to the MODR]
Before writing to the MODR, be sure to set AMD0 through AMD5 and determine the bus width in each CS (Chip
Select) area.
The MODR does not have bus width setting bits.
The bus width value set with mode pins MD2 through MD0 is enabled before writing to the MODR and the bus
width value set with BW1 and BW0 of AMD0 through AMD5 is enabled after writing to the MODR.
For example, the external reset vector is normally executed with area 0 (the area where CS0 is active) and the
bus width at that time is determined by pins MD2 through MD0. Suppose that the bus width is set to 32 or 16
bits in MD2 though MD0 but no value is specified in AMD0. If the MODR is written in this state, area 0 then
switches to 8-bit bus mode and operates the bus since the initial bus width in AMD0 is set to 8 bits. This causes
a malfunction.
In order to prevent this type of problem, AMD0 through AMD5 must always be set before writing to the MODR.
Writing to the MODR.
RST (Reset)
Designated bus width : MD2,1,0
20
AMD0 to AMD5 BW1, 0
DS07-16316-2E
MB91F158 Series
■ I/O MAP
Register
Address
+0
+1
000000H
PDR3 (R/W)
XXXXXXXX
PDR2 (R/W)
XXXXXXXX
000004H
⎯
PDR6 (R/W)
XXXXXXXX
+2
PDR5 (R/W)
XXXXXXXX
PDR4 (R/W)
XXXXXXXX
PDR8 (R/W)
- XXXXXXX
⎯
00000CH
Port Data Register
000010H
PDRF (R/W)
- - - XXXXX
PDRE (R/W)
XXXXXXXX
PDRD (R/W)
XXXXXXXX
PDRC (R/W)
XXXXXXXX
000014H
⎯
PDRI (R/W)
- - - - - XXX
PDRH (R/W)
- - - - - XXX
PDRG (R/W)
- - - - XXXX
⎯
PDRK (R/W)
XXXXXXXX
SCR0 (R/W, W)
00000100
SMR0 (R/W)
00000 - 00
⎯
000018H
00001CH
SIDR0/SODR0
(R, W)
XXXXXXXX
SSR0 (R, R/W)
00001000
⎯
000020H
000024H
SIDR2/SODR2
(R, W)
XXXXXXXX
SSR2 (R, R/W)
00001000
SCR2 (R/W, W)
00000100
SMR2 (R/W)
00000 - 00
TMRLR0 (W)
XXXXXXXX XXXXXXXX
TMR0 (R)
XXXXXXXX XXXXXXXX
000030H
⎯
TMCSR0 (R/W)
- - - - 0000 00000000
⎯
TMRLR2 (W)
XXXXXXXX XXXXXXXX
TMR2 (R)
XXXXXXXX XXXXXXXX
000040H
⎯
TMCSR2 (R/W)
- - - - 0000 00000000
00004CH
000050H
000054H
to
000058H
⎯
⎯
⎯
Reload Timer 2
Reserved
⎯
CDCR0 (R/W)
0 - - - 0000
⎯
⎯
CDCR2 (R/W)
0 - - - 0000
⎯
⎯
Reload Timer 0
Reserved
00003CH
000044H
to
000048H
UART2
Reserved
00002CH
000034H
to
000038H
UART0
Reserved
⎯
000028H
Block
⎯
⎯
000008H
+3
Communications
prescaler 1
Reserved
(Continued)
DS07-16316-2E
21
MB91F158 Series
Address
00005CH
000060H
000064H
000068H
00006CH
000070H
Register
+0
+1
+2
+3
RCR1 (W)
RCR0 (W)
UDCR1 (R)
UDCR0 (R)
00000000
00000000
00000000
00000000
CCRH0 (R/W)
CCRL0 (R/W, W)
CSR0 (R/W, R)
⎯
00000000
- 000X000
00000000
CCRH1 (R/W)
CCRL1 (R/W, W)
CSR1 (R/W, R)
⎯
- 0000000
- 000X000
00000000
IPCP1 (R)
IPCP0 (R)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
IPCP3 (R)
IPCP2 (R)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
ICS23 (R/W)
ICS01 (R/W)
⎯
⎯
00000000
00000000
000074H
to
000078H
00007CH
000080H
⎯
OCCP5 (R/W)
XXXXXXXX XXXXXXXX
OCCP7 (R/W)
XXXXXXXX XXXXXXXX
000088H
00008CH
000090H
000094H
000098H
00009CH
0000A0H
0000A4H
0000A8H
0000ACH
0000B0H
0000B4H
OCS6, 7 (R/W)
XXX00000 0000XX00
TCDT (R/W)
00000000 00000000
STPR0 (R/W)
STPR1 (R/W)
0-0----0 - 0 - 0 - 00
GCN1 (R/W)
00110010 00010000
PTMR0 (R)
11111111 11111111
PDUT0 (W)
XXXXXXXX XXXXXXXX
PTMR1 (R)
11111111 11111111
PDUT1 (W)
XXXXXXXX XXXXXXXX
PTMR2 (R)
11111111 11111111
PDUT2 (W)
XXXXXXXX XXXXXXXX
PTMR3 (R)
11111111 11111111
PDUT3 (W)
XXXXXXXX XXXXXXXX
8/16 bit Up/down
Counter
16 bit ICU
Reserved
OCCP4 (R/W)
XXXXXXXX XXXXXXXX
OCCP6 (R/W)
XXXXXXXX XXXXXXXX
⎯
000084H
Block
16 bit OCU
Reserved
OCS4, 5 (R/W)
XXX00000 0000XX00
TCCS (R/W)
0 - - - - - - - 00000000
STPR2 (R/W)
⎯
0000 - - - GCN2 (R/W)
⎯
00000000
PCSR0 (W)
XXXXXXXX XXXXXXXX
PCNH0 (R/W)
PCNL0 (R/W)
0000000 00000000
PCSR1 (W)
XXXXXXXX XXXXXXXX
PCNH1 (R/W)
PCNL1 (R/W)
0000000 00000000
PCSR2 (W)
XXXXXXXX XXXXXXXX
PCNH2 (R/W)
PCNL2 (R/W)
0000000 00000000
PCSR3 (W)
XXXXXXXX XXXXXXXX
PCNH3 (R/W)
PCNL3 (R/W)
0000000 00000000
16 bit OCU
16 bit Free-run Timer
Stop Register 0, 1, 2
PPG controler
PPG0
PPG1
PPG2
PPG3
(Continued)
22
DS07-16316-2E
MB91F158 Series
Register
Address
+0
+1
0000B8H
to
0000C4H
0000C8H
+2
+3
⎯
EIRR0 (R/W)
00000000
ENIR0 (R/W)
00000000
0000CCH
0000D0H
to
0000D8H
Reserved
EIRR1 (R/W)
00000000
ELVR0 (R/W)
00000000 00000000
ENIR1 (R/W)
00000000
ELVR1 (R/W)
00000000 00000000
⎯
0000DCH
0000E0H
Reserved
DACR2 (R/W)
-------0
DACR1 (R/W)
-------0
DACR0 (R/W)
-------0
⎯
DADR2 (R/W)
XXXXXXXX
DADR1 (R/W)
XXXXXXXX
DADR0 (R/W)
XXXXXXXX
ADCS1 (R/W, W)
00000000
ADCS0 (R/W)
00000000
A/D Converter
(Sequential type)
AICK (R/W)
00000000
Analog Input Control
⎯
0000E8H
0000ECH
to
0000F0H
⎯
D/A Converter
Reserved
0000F4H
PCRI (R/W)
- - - - - 000
PCRH (R/W)
- - - - - 000
0000F8H
OCRI (R/W)
- - - - - 000
OCRH (R/W)
- - - - - 000
0000FCH
DDRF (R/W)
- - - 00000
DDRE (R/W)
00000000
DDRD (R/W)
00000000
DDRC (R/W)
00000000
000100H
⎯
DDRI (R/W)
- 0 - - - 000
DDRH (R/W)
- - - - - 000
DDRG (R/W)
- - - - 0000
000104H
External interrupt
⎯
ADCR (R, W)
00101- XX XXXXXXXX
0000E4H
Block
PCRD (R/W)
00000000
PCRC (R/W)
00000000
⎯
Pullup Control
Open Drain Control
Data Direction
Register
DDRK (R/W)
00000000
⎯
000108H
to
0003ECH
⎯
0003F0H
BSD0 (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003E4H
BSD1 (R/W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC (W)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR (R)
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
Bit Search Module
(Continued)
DS07-16316-2E
23
MB91F158 Series
Address
000400H
000404H
000408H
00040CH
+0
ICR00 (R/W)
- - - - 1111
ICR04 (R/W)
- - - - 1111
ICR08 (R/W)
- - - - 1111
ICR012 (R/W)
- - - - 1111
000410H
⎯
000414H
⎯
Register
+1
+2
ICR01 (R/W)
ICR02 (R/W)
- - - - 1111
- - - - 1111
ICR05 (R/W)
ICR06 (R/W)
- - - - 1111
- - - - 1111
ICR10 (R/W)
⎯
- - - - 1111
⎯
ICR15 (R/W)
- - - - 1111
ICR17 (R/W)
- - - - 1111
ICR21 (R/W)
- - - - 1111
⎯
⎯
⎯
ICR23 (R/W)
- - - - 1111
ICR27 (R/W)
- - - - 1111
000418H
⎯
⎯
00041CH
ICR28 (R/W)
- - - - 1111
000420H
⎯
000424H
ICR36 (R/W)
- - - - 1111
ICR29 (R/W)
- - - - 1111
ICR33 (R/W)
- - - - 1111
ICR37 (R/W)
- - - - 1111
000428H
⎯
⎯
⎯
ICR44 (R/W)
- - - - 1111
DICR (R/W)
-------0
⎯
ICR46 (R/W)
- - - - 1111
000430H
HRCL (R/W)
- - - - 1111
000434H
to
00047CH
000480H
000484H
000488H
⎯
ICR43 (R/W)
- - - - 1111
ICR47 (R/W)
- - - - 1111
Delay int
Reserved
PDRR (R/W)
- - - - 0000
WPR (W)
XXXXXXXX
CTBR (W)
XXXXXXXX
PLL Control
⎯
000600H
DDR3 (W)
00000000
000604H
⎯
DDR2 (W)
00000000
DDR6 (W)
00000000
⎯
Clock Control unit
⎯
⎯
00048CH
to
0005FCH
000608H
ICR35 (R/W)
- - - - 1111
⎯
STCR (R/W, W)
000111- -
Interruput Control
Unit
⎯
⎯
RSRR/WTCR
(R, W)
1-XXX-00
GCR (R/W, R)
110011-1
PTCR (R/W)
00XX0XXX
Block
⎯
⎯
ICR26 (R/W)
- - - - 1111
ICR30 (R/W)
- - - - 1111
ICR34 (R/W)
- - - - 1111
ICR38 (R/W)
- - - - 1111
00042CH
+3
ICR03 (R/W)
- - - - 1111
ICR07 (R/W)
- - - - 1111
Reserved
⎯
⎯
DDR5 (W)
00000000
DDR4 (W)
00000000
DDR8 (W)
- 0000000
Data Direction
Register
(Continued)
24
DS07-16316-2E
MB91F158 Series
(Continued)
Register
Address
00060CH
000610H
000614H
000618H
00061CH
000620H
000624H
000628H
+0
+1
ASR1 (W)
00000000 00000001
ASR2 (W)
00000000 00000010
ASR3 (W)
00000000 00000011
ASR4 (W)
00000000 00000100
ASR5 (W)
00000000 00000101
AMD0 (R/W)
AMD1 (R/W)
- - - 00111
0 - - 00000
AMD5 (R/W)
0 - - 00000
EPCR0 (W)
- - - - 1100 -1111111
AMR1 (W)
00000000 00000000
AMR2 (W)
00000000 00000000
AMR3 (W)
00000000 00000000
AMR4 (W)
00000000 00000000
AMR5 (W)
00000000 00000000
AMD32 (R/W)
AMD4 (R/W)
00000000
0 - - 00000
000634H
to
0007BCH
External bus
interface
EPCR1 (W)
- - - - - - - - 11111111
Reserved
⎯
Pullup Control
⎯
FLCR (R/W, R)
000XXXX0
FWTC (R/W, W)
10010100
Reserved
⎯
FLASH Control
⎯
0007C8H
to
0007F8H
0007FCH
Block
⎯
PCR6 (R/W)
00000000
⎯
000630H
0007C4H
+3
⎯
00062CH
0007C0H
+2
⎯
⎯
Reserved
LER (W)
- - - - - 000
MODR (W)
XXXXXXXX
Little Endian
Register
Mode Register
Note : Do not execute RMW instructions on registers having a write-only bit.
RMW instructions (RMW : Read Modify Write)
AND
Rj, @Ri
OR
Rj, @Ri
EOR
Rj, @Ri
ANDH Rj, @Ri
ORH Rj, @Ri
EORH Rj, @Ri
ANDB Rj, @Ri
ORB Rj, @Ri
EORB Rj, @Ri
BANDL #u4, @Ri
BORL #u4, @Ri
BEORL #u4, @Ri
BANDH #u4, @Ri
BORH #u4, @Ri
BEORH #u4, @Ri
Data is undefined in “Reserved” or (⎯) areas.
()
R/W
R
W
⎯
X
: Access
: Readable/writable
: Read only
: Write only
: Not in use
: Undefined
DS07-16316-2E
25
MB91F158 Series
■ INTERRUPT FACTORS AND ASSIGNMENT OF INTERRUPT VECTORS AND RESISTERS
Interrupt No.
Decimal
Hex.
Interrupt
level
Offset
Default TBR
address
Reset
0
00
⎯
3FCH
000FFFFCH
Reserved for the system
1
01
⎯
3F8H
000FFFF8H
Reserved for the system
2
02
⎯
3F4H
000FFFF4H
Reserved for the system
3
03
⎯
3F0H
000FFFF0H
Reserved for the system
4
04
⎯
3ECH
000FFFECH
Reserved for the system
5
05
⎯
3E8H
000FFFE8H
Reserved for the system
6
06
⎯
3E4H
000FFFE4H
Reserved for the system
7
07
⎯
3E0H
000FFFE0H
Reserved for the system
8
08
⎯
3DCH
000FFFDCH
Reserved for the system
9
09
⎯
3D8H
000FFFD8H
Reserved for the system
10
0A
⎯
3D4H
000FFFD4H
Reserved for the system
11
0B
⎯
3D0H
000FFFD0H
Reserved for the system
12
0C
⎯
3CCH
000FFFCCH
Reserved for the system
13
0D
⎯
3C8H
000FFFC8H
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
Reserved for the system
15
0F
⎯
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
External interrupts 8 - 15
24
18
ICR08
39CH
000FFF9CH
Reserved for the system
25
19
⎯
398H
000FFF98H
UART0 (receiving complete)
26
1A
ICR10
394H
000FFF94H
Reserved for the system
27
1B
ICR11
390H
000FFF90H
UART2 (receiving complete)
28
1C
ICR12
38CH
000FFF8CH
Reserved for the system
29
1D
ICR13
388H
000FFF88H
Reserved for the system
30
1E
⎯
384H
000FFF84H
UART0 (sending complete)
31
1F
ICR15
380H
000FFF80H
Reserved for the system
32
20
ICR16
37CH
000FFF7CH
UART2 (sending complete)
33
21
ICR17
378H
000FFF78H
Factor
(Continued)
26
DS07-16316-2E
MB91F158 Series
Interrupt No.
Decimal
Hex.
Interrupt
level
Offset
Default TBR
address
Reserved for the system
34
22
ICR18
374H
000FFF74H
Reserved for the system
35
23
ICR19
370H
000FFF70H
Reserved for the system
36
24
ICR20
36CH
000FFF6CH
Reload timer 0
37
25
ICR21
368H
000FFF68H
Reserved for the system
38
26
ICR22
364H
000FFF64H
Reload timer 2
39
27
ICR23
360H
000FFF60H
Reserved for the system
40
28
ICR24
35CH
000FFF5CH
A/D (sequential type)
42
2A
ICR26
354H
000FFF54H
PPG0
43
2B
ICR27
350H
000FFF50H
PPG1
44
2C
ICR28
34CH
000FFF4CH
PPG2
45
2D
ICR29
348H
000FFF48H
PPG3
46
2E
ICR30
344H
000FFF44H
Reserved for the system
47
2F
ICR31
340H
000FFF40H
Reserved for the system
48
30
ICR32
33CH
000FFF3CH
Up/down counter 0
(compare/underflow, overflow, up-down
inversion)
49
31
ICR33
338H
000FFF38H
Up/down counter 1
(compare/underflow, overflow, up-down
inversion)
50
32
ICR34
334H
000FFF34H
ICU0 (Load)
51
33
ICR35
330H
000FFF30H
ICU1 (Load)
52
34
ICR36
32CH
000FFF2CH
ICU2 (Load)
53
35
ICR37
328H
000FFF28H
ICU3 (Load)
54
36
ICR38
324H
000FFF24H
Reserved for the system
55
37
ICR39
320H
000FFF20H
Reserved for the system
56
38
ICR40
31CH
000FFF1CH
Reserved for the system
57
39
ICR41
318H
000FFF18H
Reserved for the system
58
3A
ICR42
314H
000FFF14
OCU4/5 (Match)
59
3B
ICR43
310H
000FFF10H
OCU6/7 (Match)
60
3C
ICR44
30CH
000FFF0CH
Reserved for the system
61
3D
⎯
308H
000FFF08H
16-bit free-run timer
62
3E
ICR46
304H
000FFF04H
Delay interrupt factor bit
63
3F
ICR47
300H
000FFF00H
Factor
(Continued)
DS07-16316-2E
27
MB91F158 Series
(Continued)
Interrupt No.
Decimal
Hex.
Interrupt
level
Offset
Default TBR
address
Reserved for the system
(used by REALOS*)
64
40
⎯
2FCH
000FFEFCH
Reserved for the system
(used by REALOS*)
65
41
⎯
2F8H
000FFEF8H
Reserved for the system
66
42
⎯
2F4H
000FFEF4H
Reserved for the system
67
43
⎯
2F0H
000FFEF0H
Reserved for the system
68
44
⎯
2ECH
000FFEECH
Reserved for the system
69
45
⎯
2E8H
000FFEE8H
Reserved for the system
70
46
⎯
2E4H
000FFEE4H
Reserved for the system
71
47
⎯
2E0H
000FFEE0H
Reserved for the system
72
48
⎯
2DCH
000FFEDCH
Reserved for the system
73
49
⎯
2D8H
000FFED8H
Reserved for the system
74
4A
⎯
2D4H
000FFED4H
Reserved for the system
75
4B
⎯
2D0H
000FFED0H
Reserved for the system
76
4C
⎯
2CCH
000FFECCH
Reserved for the system
77
4D
⎯
2C8H
000FFEC8H
Reserved for the system
78
4E
⎯
2C4H
000FFEC4H
Reserved for the system
79
4F
⎯
2C0H
000FFEC0H
Used with the INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
Factor
* : REALOS/FR uses 0X40 and 0X41 interrupts for system codes.
28
DS07-16316-2E
MB91F158 Series
■ PERIPHERAL RESOURCES
1. I/O Port
(1) Port Block Diagram
This LSI is available as an I/O port when the resource associated with each pin is set not to use a pin for input/
output.
The pin level is read from the port (PDR) when it is set for input. When the port is set for output, the value in the
data register is read. The same also applies to reload by read modify write.
When switching from input to output, output data is set in the data register beforehand. However, if a read modify
write instruction (such as bit set) is used at that time, keep in mind that it is the input data from the pin that is
read, not the latch value of the data register.
• Basic I/O Port
Data bus
Resource input
0
1
PDR read
Pin
0
PDR
Resource output
1
Resource output
allowed
DDR
PDR : Port Data Register
DDR : Data Direction Register
Figure PORT-1 Basic port block
The I/O port consists of the PDR (Port Data Register) and the DDR (Data Direction Register) .
In input mode (DDR = “0”) → PDR read : Reads the level of the corresponding external pin.
PDR write : Writes the set value to the PDR.
In output mode (DDR = “1”) → PDR read : Reads the PDR value.
PDR write : Outputs the PDR value to the corresponding external pin.
Note :
AIC controls switching between the resource and port of the analog pin (A/D) .
AICK (Analog Input Control register on port-K)
The register controls whether port K should be used for analog input or as a general-purpose port.
0 : General-purpose port
1 : Analog input (A/D)
DS07-16316-2E
29
MB91F158 Series
• I/O Port (attached with a pullup resistor)
Data bus
Resource input
0
1
PDR read
Pin
0
PDR
Resource output
1
Resource output
allowed
DDR
PCR
PDR : Port Data Register
DDR : Data Direction Register
PCR : Pullup Control Register
Figure PORT-2 Port block attached with a pullup resistor
Notes : • Pullup resistor control register (PCR) R/W
Controls turning the pullup resistor on/off.
0 : Pullup resistor disabled
1 : Pullup resistor enabled
• In stop mode priority is also given to the setting of the pullup resistor control register.
• This function is not available when a relevant pin is in use as an external bus pin. Do not write “1” to this
register.
30
DS07-16316-2E
MB91F158 Series
• I/O Port (attached with the open drain output function and a pullup resistor)
Data bus
Resource input
0
1
PDR read
Pin
0
PDR
Resource output
DDR
1
Resource output
allowed
ODCR
PCR
PDR : Port Data Register
DDR : Data Direction Register
ODCR : Open Drain Control Register
PCR : Pullup Control Register
Figure PORT-3 Port block attached with the open drain output function and a pullup resistor
Notes : • Pullup resistor setup register (PCR) R/W
Controls turning the pullup resistor on/off.
0 : Pullup resistor disabled
1 : Pullup resistor enabled
• Open drain control register (ODCR) R/W
Controls open drain in output mode.
0 : Standard output port during output mode
1 : Open-drain output port during output mode
This register has no significance in input mode (output Hi-Z) . Input/output mode is determined by the
direction register (DDR) .
• Priority is also given to the setting of the pullup resistor control register in stop mode.
• When a relevant pin is used as an external bus pin, neither function is available. Do not write “1” to either
register.
DS07-16316-2E
31
MB91F158 Series
(2) Register Descriptions
• Port Data Register (PDR)
PDR2
7
6
5
4
3
2
1
0
P24
P23
P22
P21
P20
Address : 000001H
P27
P26
P25
PDR3
7
6
5
4
3
2
1
0
Address : 000000H
P37
P36
P35
P34
P33
P32
P31
P30
PDR4
7
6
5
4
3
2
1
0
Address : 000007H
P47
P46
P45
P44
P43
P42
P41
P40
PDR5
7
6
5
4
3
2
1
0
Address : 000006H
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
7
6
5
4
3
2
1
0
Address : 000005H
P67
P66
P65
P64
P63
P62
P61
P60
PDR8
7
6
5
4
3
2
1
0
Address : 00000BH
⎯
P86
P85
P84
P83
P82
P81
P80
PDRC
7
6
5
4
3
2
1
0
Address : 000013H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PDRD
7
6
5
4
3
2
1
0
Address : 000012H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PDRE
7
6
5
4
3
2
1
0
Address : 000011H
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PDRF
7
6
5
4
3
2
1
0
Address : 000010H
⎯
⎯
⎯
PF4
PF3
PF2
PF1
PF0
PDRG
7
6
5
4
3
2
1
0
Address : 000017H
⎯
⎯
⎯
⎯
PG3
PG2
PG1
PG0
PDRH
7
6
5
4
3
2
1
0
Address : 000016H
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
PDRI
7
6
5
4
3
2
1
0
Address : 000015H
⎯
⎯
⎯
⎯
⎯
PI2
PI1
PI0
PDRK
7
6
5
4
3
2
1
0
Address : 00001BH
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
- XXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
XXXXXXXXB
R/W
Initial value Access
- - - XXXXXB
R/W
Initial value Access
- - - - XXXXB
R/W
Initial value Access
- - - - - XXXB
R/W
Initial value Access
- - - - - XXXB
R/W
Initial value Access
XXXXXXXXB
R/W
PDR2 to PDRK are the I/O data registers of the I/O port.
Input/output is controlled with corresponding DDR2 to DDRK.
R/W : Readable/writable, X : Undefined, ⎯ : Not in use
32
DS07-16316-2E
MB91F158 Series
• Data Direction Register (DDR)
DDR2
7
6
5
4
3
2
1
0
Address : 000601H
P27
P26
P25
P24
P23
P22
P21
P20
DDR3
7
6
5
4
3
2
1
0
Address : 000600H
P37
P36
P35
P34
P33
P32
P31
P30
DDR4
7
6
5
4
3
2
1
0
Address : 000607H
P47
P46
P45
P44
P43
P42
P41
P40
DDR5
7
6
5
4
3
2
1
0
Address : 000606H
P57
P56
P55
P54
P53
P52
P51
P50
DDR6
7
6
5
4
3
2
1
0
Address : 000605H
P67
P66
P65
P64
P63
P62
P61
P60
DDR8
7
6
5
4
3
2
1
0
Address : 00060BH
⎯
P86
P85
P84
P83
P82
P81
P80
DDRC
7
6
5
4
3
2
1
0
Address : 0000FFH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DDRD
7
6
5
4
3
2
1
0
Address : 0000FEH
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRE
7
6
5
4
3
2
1
0
Address : 0000FDH
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRF
7
6
5
4
3
2
1
0
Address : 0000FCH
⎯
⎯
⎯
PF4
PF3
PF2
PF1
PF0
DDRG
7
6
5
4
3
2
1
0
Address : 000103H
⎯
⎯
⎯
⎯
PG3
PG2
PG1
PG0
DDRH
7
6
5
4
3
2
1
0
Address : 000102H
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
DDRI
7
6
5
4
3
2
1
0
Address : 000101H
⎯
TEST
⎯
⎯
⎯
PI2
PI1
PI0
DDRK
7
6
5
4
3
2
1
0
Address : 000107H
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
00000000B
W
Initial value Access
- 0000000B
W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
- - - 00000B
R/W
Initial value Access
- - - - 0000B
R/W
Initial value Access
- - - - - 000B
R/W
Initial value Access
- 0- - - 000B
R/W
Initial value Access
00000000B
R/W
DDR2 to DDRK control the I/O direction of the I/O port by bit.
DDR = 0 : Port input
DDR = 1 : Port output
Note : DDRI’s bit 6 is a test bit. Be sure to write “0” to the bit.
“0” is the value that is read.
R/W : Readable/writable, W : Write only, ⎯ : Not in use
DS07-16316-2E
33
MB91F158 Series
• Pullup Control Register (PCR)
PCR6
7
6
5
4
3
2
1
0
Address : 000631H
P67
P66
P65
P64
P63
P62
P61
P60
PCRC
7
6
5
4
3
2
1
0
Address : 0000F7H
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PCRD
7
6
5
4
3
2
1
0
Address : 0000F6H
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PI2
PI1
PI0
PCRH
Address : 0000F5H
PCRI
Address : 0000F4H
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
00000000B
R/W
Initial value Access
- - - - - 000B
R/W
Initial value Access
- - - - - 000B
R/W
PCR6 to PCRI control the pullup resistor when the corresponding I/O port is in input mode.
PCR = 0 : Pullup resistor not available in input mode
PCR = 1 : Pullup resistor available in input mode
The register has no significance in output mode (a pullup resistor not available) .
• Open Drain Control Register (ODCR)
OCRH
7
6
5
4
3
2
1
0
Address : 0000F9H
OCRI
Address : 0000F8H
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PI2
PI1
PI0
Initial value Access
- - - - - 000B
R/W
Initial value Access
- - - - - 000B
R/W
OCRH and OCRI control open drain when the corresponding I/O port is in output mode.
OCR = 0 : Standard output port during output mode
OCR = 1 : Open drain output port during output mode
The register has no significance in input mode (output Hi-Z) .
• Analog Input Control Register (AICR)
AICK
7
6
5
Address : 0000EBH
PK7
PK6
PK5
4
3
2
1
0
PK4
PK3
PK2
PK1
PK0
Initial value Access
00000000B
R/W
The AICK controls each pin of a corresponding I/O port as follows :
AIC = 0 : Port input mode
AIC = 1 : Analog input mode
The register is reset to “0”.
R/W : Readable/writable, ⎯ : Not in use
34
DS07-16316-2E
MB91F158 Series
2. UART
The UART is a serial I/O port for asynchronous (start and stop synchronization) communication or CLK synchronous communication. This product type contains this UART for two channels. Its features are as follows :
• Full-duplex double buffer
• Capable of asynchronous (start and stop synchronization) and CLK synchronous communication.
• Support for multiprocessor mode
• Baud rate by a dedicated baud rate generator
• Baud rate by an internal timer
The baud rate can be set with a 16-bit reload timer.
• Any baud rate can be set using an external clock.
• Error detection function (parity, framing, and overrun)
• NRZ-encoded transfer signals
DS07-16316-2E
35
MB91F158 Series
• Block Diagram
Control bus
Receive
interrupt signal
#26, 28 *
Dedicated baud rate
generator
16-bit reload timer
Receive clock
(SCK0, SCK2)
Send
interrupt signal
#31, 33 *
Send clock
Clock
selector
Pin
Receiving
control circuit
Sending
control circuit
Start bit
detection circuit
Sending start
circuit
Receive bit
counter
Send bit
counter
Receive parity
counter
Send parity
counter
Receive
shift register
Send
shift register
SIDR0, SIDR2
SODR0, SODR2
(SOT0, SOT2)
Pin
(SIN0, SIN2)
Pin
Received status
determination circuit
Sending start
Reception
error
Generated signals
(to the CPU)
Internal data bus
SMR 0,
SMR 2
registers
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR 0,
SCR 2
registers
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR 0,
SSR 2
registers
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
* : Interrupt numbers
36
DS07-16316-2E
MB91F158 Series
• Register List
Address
bit 15
bit 8
bit 0
Initial value
0000001EH
SCR0
00000100B (R/W,W)
00000026H
SCR2
00000100B (R/W,W)
0000001FH
SMR0
00000 - 00B (R/W)
00000027H
SMR2
00000 - 00B (R/W)
0000001CH
SSR0
00001000B (R, R/W)
00000024H
SSR2
00001000B (R, R/W)
0000001DH
SIDR0/SODR0
XXXXXXXX (R, W)
00000025H
SIDR2/SODR2
XXXXXXXX (R, W)
0000004EH
CDCR0
0 - - - 0000B (R/W)
00000052H
CDCR2
0 - - - 0000B (R/W)
( )
R/W
R
W
⎯
X
: Access
: Readable/writable
: Read only
: Write only
: Not in use
: Undefined
DS07-16316-2E
37
MB91F158 Series
3. PPG Timer
The PPG timer can output highly accurate PWM waveforms efficiently.
This device contains four PPG timer channels and its features are as follows :
• Each channel consists of a 16-bit down counter, a 16-bit data register attached with a frequency setting buffer,
a 16-bit compare register attached with a duty setting buffer, and a pin controller.
• The count clock for the 16-bit down counter can be selected from the following four types :
Internal clocks φ, φ/4, φ/16, and φ/64
• The counter value can be initialized by reset or counter borrow to “FFFFH”.
• PWM output (by channel)
• Block Diagram (Entire configuration)
TRG input
PWM timer channel 0
PWM0
TRG input
PWM timer channel 1
PWM1
4
TRG input
PWM timer channel 2
PWM2
4
TRG input
PWM timer channel 3
PWM3
16-bit reload timer
channel 0
General control
register 1
(Factor selection)
General control
register 2
External TRG 0 to TRG 3
38
DS07-16316-2E
MB91F158 Series
• Block Diagram (for one channel)
PDUT
PCSR
Prescaler
1/1
1/4
1 / 16
1 / ?64
Clock
cmp
Load
16-bit down counter
Start
Borrow
PPG mask
S
Peripheral system clock
Q
PWM output
R
Inverse bit
Enable
TRG input
Edge
detection
Interrupt
selection
IRQ
Soft trigger
DS07-16316-2E
39
MB91F158 Series
• Register List
Address
00000094H
00000095H
bit 15
bit 8
GCN1
00000097H
GCN2
0 0 0 0 0 0 0 0 B (R/W)
PTMR0
11111111B
(R )
11111111B
0000009AH
0000009BH
PCSR0
XXXXXXXXB
(W)
XXXXXXXXB
0000009CH
0000009DH
PDUT0
XXXXXXXXB
XXXXXXXXB (W)
0 0 0 0 0 0 0 - B (R/W)
PCNH0
0000009FH
PCNL0
0 0 0 0 0 0 0 0 B (R/W)
000000A0H
000000A1H
PTMR1
11111111B
1 1 1 1 1 1 1 1 B (R)
000000A2H
000000A3H
PCSR1
XXXXXXXXB
XXXXXXXXB (W)
000000A4H
000000A5H
PDUT1
XXXXXXXXB
XXXXXXXXB (W)
000000A6H
0 0 0 0 0 0 0 - B (R/W)
PCNH1
000000A7H
PCNL1
0 0 0 0 0 0 0 0 B (R/W)
000000A8H
000000A9H
PTMR2
11111111B
1 1 1 1 1 1 1 1 B (R)
000000AAH
000000ABH
PCSR2
XXXXXXXXB
XXXXXXXXB (W)
000000ACH
000000ADH
PDUT2
XXXXXXXXB
(W)
XXXXXXXXB
000000AEH
0 0 0 0 0 0 0 - B (R/W)
PCNH2
000000AFH
PCNL2
0 0 0 0 0 0 0 0 B (R/W)
000000B0H
000000B1H
PTMR3
11111111B
(R)
11111111B
000000B2H
000000B3H
PCSR3
XXXXXXXXB
XXXXXXXXB (W)
000000B4H
000000B5H
PDUT3
XXXXXXXXB
(W)
XXXXXXXXB
000000B6H
000000B7H
40
Initial value
00110010B
0 0 0 1 0 0 0 0 B (R/W)
00000098H
00000099H
0000009EH
(
bit 0
) : Access R/W : Readable/writable
0 0 0 0 0 0 0 - B (R/W)
PCNH3
PCNL3
0 0 0 0 0 0 0 0 B (R/W)
R : Read only W : Write only ⎯ : Not in use
X : Undefined
DS07-16316-2E
MB91F158 Series
4. 16-bit Reload Timer
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating internal
count clocks, and a control register.
The input clock can be selected from three internal clock types (2/8/32 peripheral clock divisions) .
This product type contains this 16-bit reload timer for two channels.
• Block Diagram
16
16-bit reload register
8
Reload
RELD
16
OUTE
UF
16-bit down counter
OUTL
2
OUT
CTL.
GATE
INTE
R-bus
2
IRQ
UF
CSL1
Clock selector
CNTE
CSL0
2
Retrigger
TRG
IN CTL.
EXCK
1
3
5
Clear
prescaler
3
PWM (channel 0)
A/D (channel 2)
MOD2
MOD1
Internal clocks
MOD0
3
DS07-16316-2E
41
MB91F158 Series
• Register List
Address
bit 0
Initial value
TMCSR0
----0000B
(R/W)
00000000B
00000042H
00000043H
TMCSR2
----0000B
0 0 0 0 0 0 0 0 B (R/W)
0000002EH
0000002FH
TMR0
XXXXXXXXB
(R)
XXXXXXXXB
0000003EH
0000003FH
TMR2
XXXXXXXXB
XXXXXXXXB (R)
0000002CH
0000002DH
TMRLR0
XXXXXXXXB
(W)
XXXXXXXXB
0000003CH
0000003DH
TMRLR2
XXXXXXXXB
(W)
XXXXXXXXB
( )
R/W
R
W
⎯
X
42
bit 15
00000032H
00000033H
: Access
: Readable/writable
: Read only
: Write only
: Not in use
: Undefined
DS07-16316-2E
MB91F158 Series
5. Bit Search Module
The module searches data written to the input register for “0” or “1” or a “change” and returns the detected bit
position.
• Block Diagram
Input latch
Detection
mode
D-bus
Address
decoder
Changing one detection into data
Bit search circuit
Search results
• Register List
Address
000003F0H
000003F1H
000003F2H
000003F3H
(
bit 16
BSD0
bit 0
Initial value
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB (W)
XXXXXXXXB
000003F4H
000003F5H
000003F6H
000003F7H
BSD1
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB (R/W)
XXXXXXXXB
000003F8H
000003F9H
000003FAH
000003FBH
BSDC
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB (W)
XXXXXXXXB
000003FCH
000003FDH
000003FEH
000003FFH
BSRR
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB (R)
XXXXXXXXB
) : Access
W : Write only
DS07-16316-2E
bit 31
R/W : Readable/writable
X : Undefined
R : Read only
43
MB91F158 Series
6. 8/10-bit A/D Converter (Sequential Conversion Type)
The A/D converter is a module that converts analog input voltage into a digital value. Its features are as follows :
• A minimum conversion time of 5.2 µs/ch. (Including sampling time at a 32 MHz peripheral clock)
• Contains a sample and hold circuit.
• Resolution : 10 or 8 bits selectable.
• Selection of analog input from eight channels by program
Single conversion mode
: Selects and converts one channel.
Continuous conversion mode : Converts a specified channel repeatedly.
Stop and convert mode
: Stops after converting one channel and stands by until invoked the next
time. (Conversion invoking can be synchronized.)
• Selection of an invoking factor from software, external pin trigger (falling edge) , and 16-bit reload timer (rising
edge) .
• Block Diagram
AVRL,
AVSS AVRH AVSS
MPX
D/A converter
Sequential compare
register
Input
circuit
Comparator
R-bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Decoder
Sample & hold circuit
Data register
ADCR
A/D control register 1
A/D control register 2
16-bit reload timer 2
External pin trigger
φ
44
ADCS1, 2
Operating clock
Prescaler
DS07-16316-2E
MB91F158 Series
• Register List
Initial value
Address
bit 15
bit 0
000000E4H
000000E6H
ADCS1
00101-XXB
(W, R)
(R)
00000000B
(R/W, W)
000000E7H
ADCS0
00000000B
(R/W)
000000EBH
AICK
00000000B
(R/W)
( )
R/W
R
W
⎯
X
DS07-16316-2E
ADCR
: Access
: Readable/writable
: Read only
: Write only
: Not in use
: Undefined
45
MB91F158 Series
7. Interrupt Controller
The interrupt controller accepts and arbitrates interrupts.
• Block Diagram
INT0*2
IM
Priority determination
OR
5
5
NMI*6
NMI processing
Level
determination
RI00
.
.
.
ICR00
.
.
.
Vector
determination
6
Request to
withdraw
HLDREQ
6
HLDCAN*3
VCT5
to VCT0*5
ICR47
RI47
(DLYIRQ)
.
.
Level vector
generation
4
LEVEL4
to LEVEL0*4
DLYI*1
R bus
*1 : DLY1 represents the delay interrupt module (delay interrupt generator) . (For detailed information, see
section 9, “Delay Interrupt Module”.
*2 : INT0 is a wake-up signal for the clock controller in sleep or stop mode.
*3 : HLDCAN is a bus surrender request signal for bus masters except for the CPU.
*4 : LEVEL 4 to LEVEL 0 are interrupt level outputs.
*5 : VCT 5 to VCT 0 are interrupt vector outputs.
*6 : This product type does not have the NMI function.
46
DS07-16316-2E
MB91F158 Series
• Register List
Address
bit 7
bit 0
Initial value
Address
bit 7
bit 0
Initial value
00000400H
ICR00
- - - - 1 1 1 1 B (R/W)
00000414H
ICR20
- - - - 1 1 1 1 B (R/W)
00000401H
ICR01
- - - - 1 1 1 1 B (R/W)
00000415H
ICR21
- - - - 1 1 1 1 B (R/W)
00000402H
ICR02
- - - - 1 1 1 1 B (R/W)
00000416H
ICR22
- - - - 1 1 1 1 B (R/W)
00000403H
ICR03
- - - - 1 1 1 1 B (R/W)
00000417H
ICR23
- - - - 1 1 1 1 B (R/W)
00000404H
ICR04
- - - - 1 1 1 1 B (R/W)
00000418H
ICR24
- - - - 1 1 1 1 B (R/W)
00000405H
ICR05
- - - - 1 1 1 1 B (R/W)
00000419H
ICR25
- - - - 1 1 1 1 B (R/W)
00000406H
ICR06
- - - - 1 1 1 1 B (R/W)
0000041AH
ICR26
- - - - 1 1 1 1 B (R/W)
00000407H
ICR07
- - - - 1 1 1 1 B (R/W)
0000041BH
ICR27
- - - - 1 1 1 1 B (R/W)
00000408H
ICR08
- - - - 1 1 1 1 B (R/W)
0000041CH
ICR28
- - - - 1 1 1 1 B (R/W)
00000409H
ICR09
- - - - 1 1 1 1 B (R/W)
0000041DH
ICR29
- - - - 1 1 1 1 B (R/W)
0000040AH
ICR10
- - - - 1 1 1 1 B (R/W)
0000041EH
ICR30
- - - - 1 1 1 1 B (R/W)
0000040BH
ICR11
- - - - 1 1 1 1 B (R/W)
0000041FH
ICR31
- - - - 1 1 1 1 B (R/W)
0000040CH
ICR12
- - - - 1 1 1 1 B (R/W)
00000420H
ICR32
- - - - 1 1 1 1 B (R/W)
0000040DH
ICR13
- - - - 1 1 1 1 B (R/W)
00000421H
ICR33
- - - - 1 1 1 1 B (R/W)
0000040EH
ICR14
- - - - 1 1 1 1 B (R/W)
00000422H
ICR34
- - - - 1 1 1 1 B (R/W)
0000040FH
ICR15
- - - - 1 1 1 1 B (R/W)
00000423H
ICR35
- - - - 1 1 1 1 B (R/W)
00000410H
ICR16
- - - - 1 1 1 1 B (R/W)
00000424H
ICR36
- - - - 1 1 1 1 B (R/W)
00000411H
ICR17
- - - - 1 1 1 1 B (R/W)
00000425H
ICR37
- - - - 1 1 1 1 B (R/W)
00000412H
ICR18
- - - - 1 1 1 1 B (R/W)
00000426H
ICR38
- - - - 1 1 1 1 B (R/W)
00000413H
ICR19
- - - - 1 1 1 1 B (R/W)
00000427H
ICR39
- - - - 1 1 1 1 B (R/W)
( ) : Access
R/W : Readable/writable
⎯ : Not in use
(Continued)
DS07-16316-2E
47
MB91F158 Series
(Continued)
Address
bit 7
bit 0
Initial value
00000428H
ICR40
- - - - 1 1 1 1 B (R/W)
00000429H
ICR41
- - - - 1 1 1 1 B (R/W)
0000042AH
ICR42
- - - - 1 1 1 1 B (R/W)
0000042BH
ICR43
- - - - 1 1 1 1 B (R/W)
0000042CH
ICR44
- - - - 1 1 1 1 B (R/W)
0000042DH
ICR45
- - - - 1 1 1 1 B (R/W)
0000042EH
ICR46
- - - - 1 1 1 1 B (R/W)
0000042FH
ICR47
- - - - 1 1 1 1 B (R/W)
00000431H
HRCL
- - - - 1 1 1 1 B (R/W)
00000430H
DICR
- - - - - - - 0 B (R/W)
( ) : Access
R/W : Readable/writable
⎯ : Not in use
48
DS07-16316-2E
MB91F158 Series
8. External Interrupt
The external interrupt controller controls external interrupt requests input to INT pins 0 through 15.
The level of requests to be detected can be selected from “H”, “L”, rising edge, and falling edge.
• Block Diagram
16
Interrupt enable register
16
R-bus
Interrupt
request
Gate
Factor F/F
16
32
Edge detection
circuit
16
INT0 to INT15
Interrupt source register
Request level setting register
• Register List
Address
bit 15
bit 8
bit 0
Initial value
000000C8H
000000C9H
EIRR0
ENIR0
00000000B
(R/W)
00000000B
000000CAH
000000CBH
EIRR1
ENIR1
00000000B
(R/W)
00000000B
000000CCH
000000CDH
ELVR0
00000000B
0 0 0 0 0 0 0 0 B (R/W)
000000CEH
000000CFH
ELVR1
00000000B
(R/W)
00000000B
( ) : Access
R/W : Readable/writable
9. Delay Interrupt Module
The delay interrupt is a module that generates task switching interrupts. The use of this module allows the
software to generate/cancel interrupt requests to the CPU.
For the block diagram of the delay interrupt module, see section 7, “Interrupt Controller”.
• Register List
Address
bit 7
00000430H
bit 0
DICR
Initial value
-------0
B (R/W)
( ) : Access
R/W : Readable/writable
⎯ : Not in use
DS07-16316-2E
49
MB91F158 Series
10. Clock Generator (Low power consumption mechanism)
The clock generator is responsible for the following functions :
• CPU clock generation (including the gear function)
• Peripheral clock generation (including the gear function)
• Reset generation and holding factors
• Standby function (including hardware standby)
• Contains PLL (multiplication circuit)
• Block Diagram
[Gear controller]
GCR register
CPU gear
Peripheral
gear
1/2
X0
X1
Oscillator
circuit
PLL
Internal clock
generating
circuit
M
P
X
CPU Clock
Internal bus clock
Internal
peripheral clock
[Stop/sleep controller]
Internal interrupt
Internal reset
STCR register
PDRR register
Power on
detection circuit
VCC
Status
transition
control
circuit
Stop state?
Sleep state
CPU Hold request
Reset
generating
F/F
Internal reset
[Reset factor circuit]
R
GND
RSRR register
RST pin
[Watchdog controller]
WPR register
Watchdog F/F
Count clock
CTBR register
Timebase timer
50
DS07-16316-2E
MB91F158 Series
• Register List
Address
00000480H
bit 15
bit 8
RSRR/WTCH
00000481H
00000482H
STCR
PDRR
00000483H
00000484H
CTBR
DS07-16316-2E
Initial value
1-XXX-00B
(R, W)
000111--B
(R/W, W)
----0000B
(R/W)
XXXXXXXXB (W)
110011-1B
GCR
00000485H
( )
R/W
R
W
⎯
X
bit 0
WPR
(R/W, R)
XXXXXXXXB (W)
: Access
: Readable/writable
: Read only
: Write only
: Not in use
: Undefined
51
MB91F158 Series
11. External Bus Interface
The external bus interface controls the interface between the external memory and the external I/O. Its features
are as follows :
• 24-bit (16 MB) address output
• An 8/16-bit bus width can be set by chip select area.
• Inserts an automatic and programmable memory wait (for seven cycles at maximum) .
• Unused addresses/data pins are available as I/O ports.
• Support for little endian mode
• Use of a clock doubler, 32 MHz internal and 16 MHz external bus operations
• Block Diagram
Internal Data Bus
Internal Address Bus
A-Out
Write
buffer
Switch
Read
buffer
Switch
M
U
X
External DATA Bus
DATA BLOCK
ADDRESS BLOCK
+1 or +2
Address
buffer
External
Address Bus
Shifter
Inpage
4
ASR
AMR
Comparator
CS0 to
3
RD
WR0, WR1
4
BRQ
BGRNT
RDY
CLK
External pin controller
Controls all blocks.
Registers
&
Control
52
DS07-16316-2E
MB91F158 Series
• Register List
Address
0000060CH
0000060DH
bit 31
bit 16
bit 0
ASR1
0000060EH
0000060F H
00000610 H
00000611 H
00000000B
(W)
00000010B
ASR2
AMR2
00000000B
(W)
00000100B
ASR4
AMR4
AMR5
0 - - 0 0 0 0 0 B (R/W)
AMD1
00000622 H
00000628 H
00000629 H
AMD4
000007FF H
DS07-16316-2E
----1100B
(W)
-1111111B
EPCR0
000007FEH
0 - - 0 0 0 0 0 B (R/W)
0 - - 0 0 0 0 0 B (R/W)
AMD5
0000062AH
0000062BH
( )
R/W
W
⎯
X
0 0 0 0 0 0 0 0 B (R/W)
AMD32
00000623 H
00000624 H
00000000B
(W)
00000000B
- - - 0 0 1 1 1 B (R/W)
AMD0
00000621 H
0 0 0 0 0 0 0 0 B (W)
00000000B
00000000B
(W)
00000101B
ASR5
0000061EH
0000061F H
00000620 H
00000000B
(W)
00000000B
AMR3
0000061AH
0000061BH
0000061CH
0000061DH
00000000B
(W)
00000000B
00000000B
(W)
00000011B
ASR3
00000616 H
00000617 H
00000618 H
00000619 H
00000000B
(W)
00000000B
AMR1
00000612 H
00000613 H
00000614 H
00000615 H
Initial value
00000000B
0 0 0 0 0 0 0 1 B (W)
EPCR1
--------B
(W)
11111111B
- - - - - 0 0 0 B (W)
LER
MODR
XXXXXXXXB (W)
: Access
: Readable/writable
: Write only
: Not in use
: Undefined
53
MB91F158 Series
12. Multifunction Timer
The multifunction timer unit consists of one 16-bit free-run timer, four 16-bit output compare registers, four 16bit input capture registers, and four 16-bit PPG timer channels. By using this function waveforms can be output
based on the 16-bit free-run timer and the input pulse width and external clock cycle can also be measured.
• Timer Components
• 16-bit free-run timer ( × 1)
The 16-bit free-run timer consists of a 16-bit up counter, a control register, a 16-bit compare clear register,
and a prescaler. The output value of this counter is used as the basic time (base timer) for output compare
and input capture.
• Output compare ( × 4)
The output compare consists of four 16-bit compare registers, a compare output latch, and a control register.
When the 16-bit free-run timer value agrees to the compare register value, the output level can be inverted
and an interrupt can also be generated.
• Input capture ( × 4)
The input capture consists of capture registers corresponding to four independent external input pins and a
control register. By detecting any edge of signals input from external input pins, the 16-bit free-run timer value
can be held in the capture register and an interrupt can be generated at the same time.
• 16-bit PPG timer ( × 4)
See the section, “3. PPG Timer”.
54
DS07-16316-2E
MB91F158 Series
• Block Diagram
φ
Interrupt
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
CLK0
Divider
Clock
16-bit free-run timer
16-bit compare clear register
(Channel 6's compare register)
Compare register 4/6
MS13 to 0
Compare circuit
R-bus
Compare register 5/7
Interrupt
Compare circuit
ICLR
ICRE
T
Q
OC4/6
T
Q
OC5/7
CMOD
Select
Compare circuit
IOP1
IOP0
IOE1
IOE0
Interrupt
Interrupt
Capture register 0/2
IN 0/2
Edge detection
EG11
Capture register 1/3
EG10
EG01
Edge detection
ICP0
ICP1
ICE0
EG00
IN 1/3
ICE1
Interrupt
Interrupt
DS07-16316-2E
55
MB91F158 Series
• Register List
Address
bit15
•
•
•
• • • •
bit8
bit7
•
•
• • •
bit0
Initial value
IPCP1
XXXXXXXXB (R)
XXXXXXXXB (R)
00006AH
00006BH
IPCP0
XXXXXXXXB (R)
XXXXXXXXB (R)
00006CH
00006DH
IPCP3
XXXXXXXXB (R)
XXXXXXXXB (R)
00006EH
00006FH
IPCP2
XXXXXXXXB (R)
XXXXXXXXB (R)
ICS23
000073H
56
•
000068H
000069H
000071H
(
•
ICS01
00000000B (R/W)
00000000B (R/W)
00007CH
00007DH
OCCP5
XXXXXXXXB (R/W)
XXXXXXXXB (R/W)
00007EH
00007FH
OCCP4
XXXXXXXXB (R/W)
XXXXXXXXB (R/W)
000080H
000081H
OCCP7
XXXXXXXXB (R/W)
XXXXXXXXB (R/W)
000082H
000083H
OCCP6
XXXXXXXXB (R/W)
XXXXXXXXB (R/W)
000088H
000089H
OCS7, OCS6
XXX00000B (R/W)
0000XX00B (R/W)
00008AH
00008BH
OCS5, OCS4
XXX00000B (R/W)
0000XX00B (R/W)
00008CH
00008DH
TCDT
00000000B (R/W)
00000000B (R/W)
00008EH
00008FH
TCCS
0 - - - - - - -B (R/W)
00000000B (R/W)
) : Access R/W : Readable/writable
R : Read only ⎯ : Not in use
X : Undefined
DS07-16316-2E
MB91F158 Series
13. FLASH Memory
The MB91F158 contains a 510-Kbyte (4 Mbits) flash memory. The sectors can be erased all at once or sector
by sector and that can be written with the FR-CPU by half word (16 bits) using a single 3 V power supply.
The MB91F158 accomplishes the following functions by a combination of the flash memory macro and the FRCPU interface circuit :
• Functions as the CPU program/data storage memory :
When used as a ROM, the memory is accessible with a 32-bit bus width.
Allows the CPU to read read/write/erase the memory (automatic program algorithm*) .
• Functions equivalent to the stand-alone MBM29LV400C flash memory product :
Allows a ROM programmer to read from/write to/erase the memory (automatic program algorithm*)
At this time, using the flash memory from the FR-CPU is described. For detailed information about using the
flash memory from the ROM programmer, refer to the ROM programmer instruction manual.
* : Automatic program algorithm = Embedded Algorithm
• Block Diagram
Rising edge detection
Control signal
generation
RDY/BUSY
RESET
BYTE
OE
Flash memory
WE
INTE
RDYINT
RDY
WE
Bus control signals
Interrupt requests
CE
FA18
to
FA0
Address buffer
CA18 to CA0
DI15
to
DI0
DO31
to
DO0
Data buffer
CD31 to CD0
FR-C bus (instructions/data)
SSEL pin
(Sector select)
DS07-16316-2E
57
MB91F158 Series
• Memory Map
Flash memory address mapping varies between FLASH memory mode and CPU mode. Mapping in each mode
is shown next.
Memory mapping in FLASH memory mode of MB91F158 :
(at SSEL = VSS)
0FFFFFH
SA13
SA12
SA11
FLASH
memory image
SA10
SA9
Using FLASH memory mode is prohibited,
when SSEL pin is connected to VCC.
(Using parallel writer is prohibited.)
SA8
SA7
07FFFFH
SA6
SA5
SA4
SA3
SA2
010000H
SA1
SA0
000000H
( SAn : sector address n )
FLASH memory mode
Memory mapping in CPU mode of MB91F158A :
(at SSEL = VSS)
0FFFFFH
0FFFFFH
SA6
SA13
0F8000H
0F4000H
FLASH memory area
0F0000H
SA5
SA12
SA4
SA11
SA3
SA10
SA12
0F8000H
SA4
SA11
0F0000H
SA6
SA13
SA3
SA10
SA2
SA9
SA1
SA8
SA0
SA7
0E0000H
SA2
SA9
0C0000H
RAM area
2 KB
SA5
0FC000H
0E0000H
080800H
(at SSEL = VCC)
0FFFFFH
0C0000H
SA1
SA8
080000H
0A0000H
0A0000H
SA0
0007C0H
SA7
Status register
080800H
080800H
000000H
( SAn : sector address n )
CPU mode
58
DS07-16316-2E
MB91F158 Series
• Sector Address Table (Changes the contents by the level of SSEL pin.)
< SSEL = VSS >
Sector address
Address range
Corresponding bit
positions
Sector capacity
SA7
080802, 3H to 09FFFE, FH (16 bits on LSB side)
bit15 to 0
64 Kbytes
SA8
0A0002, 3H to 0BFFFE, FH (16 bits on LSB side)
bit15 to 0
64 Kbytes
SA9
0C0002, 3H to 0DFFFE, FH (16 bits on LSB side)
bit15 to 0
64 Kbytes
SA10
0E0002, 3H to 0EFFFE, FH (16 bits on LSB side)
bit15 to 0
32 Kbytes
SA11
0F0002, 3H to 0F3FFE, FH (16 bits on LSB side)
bit15 to 0
8 Kbytes
SA12
0F4002, 3H to 0F7FFE, FH (16 bits on LSB side)
bit15 to 0
8 Kbytes
SA13
0F8002, 3H to 0FFFFE, FH (16 bits on LSB side)
bit15 to 0
16 Kbytes
SA0
080800, 1H to 09FFFC, DH (16 bits on MSB side)
bit31 to 16
64 Kbytes
SA1
0A0000, 1H to 0BFFFC, DH (16 bits on MSB side)
bit31 to 16
64 Kbytes
SA2
0C0000, 1H to 0DFFFC, DH (16 bits on MSB side)
bit31 to 16
64 Kbytes
SA3
0E0000, 1H to 0EFFFC, DH (16 bits on MSB side)
bit31 to 16
32 Kbytes
SA4
0F0000, 1H to 0F3FFC, DH (16 bits on MSB side)
bit31 to 16
8 Kbytes
SA5
0F4000, 1H to 0F7FFC, DH (16 bits on MSB side)
bit31 to 16
8 Kbytes
SA6
0F8000, 1H to 0FFFFC, DH (16 bits on MSB side)
bit31 to 16
16 Kbytes
< SSEL = VCC >
Sector address
Address range
Corresponding bit
Sector capacity
positions
SA7
080802, 3H to 09FFFE, FH (16 bits on LSB side)
bit15 to 0
64 Kbytes
SA8
0A0002, 3H to 0BFFFE, FH (16 bits on LSB side)
bit15 to 0
64 Kbytes
SA9
0C0002, 3H to 0DFFFE, FH (16 bits on LSB side)
bit15 to 0
64 Kbytes
SA10
0E0002, 3H to 0EFFFE, FH (16 bits on LSB side)
bit15 to 0
32 Kbytes
SA13
0F0002, 3H to 0F7FFE, FH (16 bits on LSB side)
bit15 to 0
16 Kbytes
SA11
0F8002, 3H to 0FBFFE, FH (16 bits on LSB side)
bit15 to 0
8 Kbytes
SA12
0FC002, 3H to 0FFFFE, FH (16 bits on LSB side)
bit15 to 0
8 Kbytes
SA0
080800, 1H to 09FFFC, DH (16 bits on MSB side)
bit31 to 16
64 Kbytes
SA1
0A0000, 1H to 0BFFFC, DH (16 bits on MSB side)
bit31 to 16
64 Kbytes
SA2
0C0000, 1H to 0DFFFC, DH (16 bits on MSB side)
bit31 to 16
64 Kbytes
SA3
0E0000, 1H to 0EFFFC, DH (16 bits on MSB side)
bit31 to 16
32 Kbytes
SA6
0F0000, 1H to 0F7FFC, DH (16 bits on MSB side)
bit31 to 16
16 Kbytes
SA4
0F8000, 1H to 0FBFFC, DH (16 bits on MSB side)
bit31 to 16
8 Kbytes
SA5
0FC000, 1H to 0FFFFC, DH (16 bits on MSB side)
bit31 to 16
8 Kbytes
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59
MB91F158 Series
• Registers
FLCR : Status register (CPU mode)
This register indicates the FLASH memory operating status. The register controls interrupts to the CPU as well
as writing to the FLASH memory.
This register is accessible only in CPU mode. Do not access this register with read modify write instructions.
0007C0H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTE
RDYINT
WE
RDY
⎯
⎯
⎯
LPM
R/W
(0)
R/W
(0)
R/W
(0)
R
(X)
⎯
(X)
⎯
(X)
⎯
(X)
R/W
(0)
R/W : Readable/writable, R : Read only, ⎯ : Not in use, X : Undefined
FWTC : Wait register
This register controls waiting for the FLASH memory in CPU mode.
The register also controls accessing to read from the FLASH memory (33 MHz operations) at high speeds.
0007C4H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
⎯
SYNC
WTC1
WTC0
W
(1)
W
(0)
W
(1)
W
(0)
W
(1)
R/W
(0)
R/W
(0)
W
(0)
R/W : Readable/writable, W : Write only, ⎯ : Not in use, X : Undefined
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MB91F158 Series
14. 8-bit D/A Converter
This block is of an 8-bit resolution, R-2R D/A converter. The block contains three channels of D/A converter and
each D/A control register can control output independently.
The D/A converter pin is a dedicated pin.
• Block Diagram
R-bus
DA27 to DA20
DA17 to DA10
DAVC
DA07 to DA00
DAVC
DAVC
DA27
DA17
DA07
DA20
DA10
DA00
DAE2
Standby control
DAE1
Standby control
DAE0
Standby control
D/A output channel 2
D/A output channel 1
D/A output channel 0
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MB91F158 Series
• Register List
bit
DADR0
00000E3H
bit
DADR1
00000E2H
bit
DADR2
00000E1H
bit
DACR0
00000DFH
bit
DACR1
00000DEH
bit
DACR2
00000DDH
7
6
5
4
3
2
1
0
DA07
DA06
DA05
DA04
DA03
DA02
DA01
DA00
15
14
13
12
11
10
9
8
DA17
DA16
DA15
DA14
DA13
DA12
DA11
DA10
23
22
21
20
19
18
17
16
DA27
DA26
DA25
DA24
DA23
DA22
DA21
DA20
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAE0
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAE1
23
22
21
20
19
18
17
16
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAE2
Initial value
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
XXXXXXXXB ( R/W )
- - - - - - - 0B ( R/W )
- - - - - - - 0B ( R/W )
- - - - - - - 0B ( R/W )
( ) : Access, R/W : Readable/writable, ⎯ : Not in use, X : Undefined
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MB91F158 Series
15. 8/16-bit Up/Down Counters/Timers
This is the up/down counter/timer block consisting of six event input pins, two 8-bit up/down counters, two 8-bit
reload/compare registers, and their control circuits.
The features of this module are as follows :
• Capable of counting in the (0) d to (256) d range by the 8-bit count register.
(In 16-bit × 1 operating mode, the register can count in the (0) d to (65535) d range.)
• Four count modes to choose from by the count clock.
• In timer mode the count clock can be selected from two internal clock types.
• In up/down count mode an external pin input signal detection edge can be selected.
• The phase-difference count mode is suitable for encoder counting, such as of motors. Rotation angles, rotating
speeds, and so on can be counted accurately and easily by inputting the output of phases A, B, and Z.
• Two types of function to choose from for the ZIN pin. (Enabled in all modes)
• Equipped with compare and reload functions which can be used individually or in combination. When combined,
these functions can count up/down at any width.
• The immediately preceding count direction can be identified by the count direction flag.
• Capable of individually controlling interrupt generation when comparison results match, at occurrence of reload
(underflow) or overflow, or when the count direction changes.
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MB91F158 Series
• Block Diagram
• 8/16-bit Up/Down Counter/Timer (channel 0)
Data bus
8 bits
CGE1
ZIN0
CGE0
RCR0
(Reload/compare register 0)
C/GS
RCUT
Reload control
UCRE
RLDE
Edge/level detection
UDCC
Counter clear
8 bits
UDCR0
(Up/down count register 0)
Carry
CES1
CES0
CMS1
CMS0
UDFF
CITE
OVFF
UDIE
Count clock
AIN0
BIN0
CMPF
Up/down count
clock selection
Prescaler
UDF1
UDF0
CDCF
CFIE
CSTR
Interrupt output
CLKS
64
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MB91F158 Series
• 8/16-bit Up/Down Counter/Timer (channel 1)
Data bus
8 bits
CGE1
CGE0
RCR1
(Reload/compare register 1)
C/GS
RCUT
Reload control
UCRE
RLDE
Edge/level detection
ZIN1
Counter clear
UDCC
8 bits
UDCR1
(Up/down count register 1)?
CMPF
UDFF
CMS1
CMS0
CES1
CES0
OVFF
M16E
CITE
UDIE
Carry
Count clock
AIN1
Up/down count
clock selection
BIN1
Prescaler
UDF1
UDF0
CDCF
CFIE
CSTR
Interrupt output
CLKS
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MB91F158 Series
• Register List
bit
7
6
5
4
Address : 00005FH
2
1
0
15
14
13
12
Address : 00005EH
11
10
9
8
7
6
5
4
Address : 00005DH
3
2
1
0
bit
15
14
13
12
Address : 00005CH
11
10
9
8
bit
7
6
5
4
Address : 000063H
3
2
1
0
bit
7
6
5
4
Address : 000067H
3
2
1
0
bit
7
6
5
4
Address : 000061H
3
2
1
0
7
6
5
4
Address : 000065H
3
2
1
0
15
14
13
12
Address : 000060H
11
10
9
8
15
14
13
12
11
CCRH1
Initial value
Initial value
00000000B
CCRH0
bit
Initial value
-000X000B (R/W, W)
CCRL1
bit
(R/W)
-000X000B (R/W, W)
CCRL0
bit
(R/W)
Initial value
00000000B
CSR1
(W)
Initial value
00000000B
CSR0
(W)
Initial value
00000000B
RCR1
(R)
Initial value
00000000B
RCR0
(R)
Initial value
00000000B
UDCR1
bit
Initial value
00000000B
UDCR0
bit
Address : 000064H
3
10
9
8
(R/W)
Initial value
-0000000B
(R/W)
( ) : Access, R/W : Readable/writable, R : Read only, W : Write only, ⎯ : Not in use, X : Undefined
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16. Peripheral STOP Control
This function can be used to stop the clock of unused resources in order to enable more low-power consumption.
• Register List
Address
bit7
bit0
Initial value
000090H
STPR0
0- 0- - - - - B ( R/W )
000091H
STPR1
0- 0- 0- 00B ( R/W )
000092H
STPR2
0000- - - - B ( R/W )
( ) : Access, R/W : Readable/writable, ⎯ : Not in use
DS07-16316-2E
67
MB91F158 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Rating
Min
Max
Unit
Remarks
Power supply voltage
VCC
VSS − 0.3
VSS + 3.5
V
Analog supply voltage
AVCC
VSS − 0.3
VSS + 3.5
V
*1
Analog reference voltage
AVRH
VSS − 0.3
VSS + 3.5
V
*1
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Analog pin input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage
VO
VSS − 0.3
VCC + 0.3
V
“L” level maximum output current
IOL
⎯
10
mA
*2
“L” level average output current
IOLAV
⎯
4
mA
*3
“L” level total maximum output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*4
IOH
⎯
−10
mA
*2
“H” level average output current
IOHAV
⎯
−4
mA
*3
“H” level total maximum output current
ΣIOH
⎯
−50
mA
ΣIOHAV
⎯
−20
mA
Power consumption
PD
⎯
500
mW
Operating temperature
TA
0
+70
°C
Tstg
−55
+150
°C
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Storage temperature
*4
*1 : Take care not to exceed VCC + 0.3 V when turning on the power, for example.
Take care also to prevent AVCC from exceeding VCC when turning on the power, for example.
*2 : The maximum output current stipulates the peak value of a single concerned pin.
*3 : The average output current stipulates the average current flowing through a single concerned pin over a period
of 100 ms.
*4 : The total average output current stipulates the average current flowing through all concerned pins over a period
of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB91F158 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Power supply voltage
VCC
Analog supply voltage
Value
Min
Max
3.2
3.5
Unit
During normal operations
V
2.0
3.5
AVCC
VSS + 3.2
VSS + 3.5
V
Analog reference voltage
(High potential side)
AVRH
AVCC − 0.3
AVCC
V
Analog reference voltage
(Low potential side)
AVRL
AVSS
AVSS + 0.3
V
TA
0
+70
°C
Operating temperature
Remarks
The RAM state is retained
when stopped.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-16316-2E
69
MB91F158 Series
3. DC Characteristics
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Pin name
Condition
VIH
Input except for
hysteresis input pin*
VIHS
Symbol
Value
Unit
Min
Typ
Max
⎯
0.65 ×
VCC
⎯
VCC + 0.3
V
Hysteresis input pin*
⎯
0.8 × VCC
⎯
VCC + 0.3
V
VIL
Input except for
hysteresis input pin*
⎯
VSS − 0.3
⎯
0.25 ×
VCC
V
VILS
Hysteresis input pin*
⎯
VSS − 0.3
⎯
0.2 × VCC
V
“H” level output
voltage
VOH
⎯
VCC = 3.2 V
IOH = 4.0 mA
VCC − 0.5
⎯
⎯
V
“L” level output
voltage
VOL
⎯
VCC = 3.2 V
IOL = 4.0 mA
⎯
0.4
V
Input leakage
current
ILI
⎯
VCC = 3.5 V,
VSS < VI < VCC
⎯
⎯
±5
µA
⎯
⎯
50
⎯
kΩ
“H” level input
voltage
“L” level input
voltage
Pullup
resistance
Power supply
current
Input capacity
RPULL RST, pullup pin
Remarks
ICC
VCC
VCC = 3.3 V
⎯
85
110
mA
ICCS
VCC
VCC = 3.3 V
⎯
60
90
mA
During sleep
mode
ICCH
VCC
VCC = 3.3 V,
TA = +25 °C
⎯
15
300
µA
During stop
mode
CIN
Other than Vcc, Vss,
AVcc, AVss, and
AVRH
⎯
⎯
5
15
pF
* : Refer to “■ I/O CIRCUIT TYPE”.
70
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MB91F158 Series
4. Flash Memory Erase and Programming Performance
(VSS = AVSS = 0 V)
Parameter
Value
Min
Typ
Max
Sector Erase Time
⎯
1 *1
15 *2
Byte Programming Time
⎯
1
Chip Programming Time
⎯
4.2 *
10000
⎯
Erase/Program Cycle
8*
Remarks
s
Excludes programming time prior to erasure
µs
Excludes system-level overhead
⎯
s
Excludes system-level overhead
⎯
cycle
3600 *
1
Unit
2
*1 : TA = +25 °C, VCC = 3.3 V, 10,000 cycles
*2 : TA = +70 °C, VCC = 3.3 V, 10,000 cycles
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MB91F158 Series
5. AC Characteristics
(1) Clock Timing Ratings
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin
name
Condition
Clock frequency
(High speed and self
oscillation)
Clock frequency
(High speed and PLL in use)
fC
tC
PWH
Clock pulse width
PWL
Input clock rising
tcr
Input clock falling
tcf
Internal
operating clock
frequency
Internal operating clock cycle
time
CPU
system
fCP
Bus
system
fCPB
Peripheral
system
fCPP
CPU
system
tCP
Bus
system
tCPB
Peripheral
system
Min
Max
Unit
X0, X1
X0, X1
16
⎯
10
16
⎯
62.5
100
⎯
25
⎯
⎯
15
⎯
⎯
8
0.625*3
32
0.625*3
25*2
0.625*3
32
Analog section
excluded. *1
1
32
Analog section *1
31.25
1600*3
40*2
1600*3
31.25
1600*3
31.25
1000
⎯
X0, X1
⎯
⎯
One wait is
set with the
wait
controller.
⎯
tCPP
MHz Range in which self
oscillation and the
use of the PLL for
external clock input
are allowed
10
⎯
X0, X1
Remarks
Range in which self
oscillation is allowed
⎯
Clock frequency
(High speed and 1/2 division
input)
Clock cycle time
Value
Range in which
MHz external clocks can
be input
ns
(tcr + tcf)
MHz
ns
Analog section
excluded. *1
Analog section *1
*1 : The target analog section is the A/D converter.
*2 : The maximum external bus operating frequency allowed is 25 MHz.
*3 : The value when a minimum clock frequency of 10 MHz is input to X0 and half a division of the oscillator circuit
and the 1/8 gear are in use.
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MB91F158 Series
tC
PWH
PWL
tcf
tcr
VCC
Supply voltage (V)
Operation assurance range
3.5
fCPP
3.2
fCP
0.625 M
Frequency (Hz)
DS07-16316-2E
32 M
73
MB91F158 Series
The relationship between the X0 input and the internal clock set with the CHC/CCK1/CCK0 bit of the GCR (Gear
Control Register) is as shown below.
X0 input
• Source oscillation × 1
(GCR CHC bit : 0)
(a) Gear × 1 internal clock
CCK1/0 : 00
(b) Gear × 1/2 internal clock
CCK1/0 : 01
tCYC
tCYC
tCYC
(c) Gear × 1/4 internal clock
CCK1/0 : 10
tCYC
(d) Gear × 1/8 internal clock
CCK1/0 : 11
• Source oscillation × 1/2
(GCR CHC bit : 1)
(a) Gear × 1 internal clock
CCK1/0 : 00
(b) Gear × 1/2 internal clock
CCK1/0 : 01
(c) Gear × 1/4 internal clock
CCK1/0 : 10
(d) Gear × 1/8 internal clock
CCK1/0 : 11
74
tCYC
tCYC
tCYC
tCYC
DS07-16316-2E
MB91F158 Series
(2) Clock Output Timing
Parameter
Cycle time
Symbol
Pin
name
tCYC
CLK
CLK↑→CLK↓
tCHCL
CLK
CLK↓→CLK↑
tCLCH
CLK
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Condition
Unit
Remarks
Min
Max
tCP
ns
tCPB
⎯
*1
On using doubler
tCYC/2−10
tCYC/2+10
ns
*2
tCYC/2−10
tCYC/2+10
ns
*3
tCYC
tCHCL
tCLCH
VOH
VOH
VOL
CLK
*1 : tCYC is a frequency for 1clock cycle including a gear cycle.
Use the doubler when CPU frequency is above 25 MHz.
*2 : Rating at a gear cycle of × 1
When a gear cycle of 1/2, 1/4, 1/8 is selected, substitute “n” in the following equations wiht 1/2, 1/4, 1/8,
respectively.
• Min : (1−n/2) × tCYC−10
• Max : (1−n/2) × tCYC+10
Select a gear sysle of × 1 when using the doubler.
*3 : Rating at a gear cycle of × 1
When a gear cycle of 1/2, 1/4, 1/8 selected, substitute “n” in the following equations wiht 1/2, 1/4, 1/8,
respectively.
• Min : n/2 × tCYC−10
• Max : n/2 × tCYC+10
Select a gear sysle of × 1 when using the doubler.
DS07-16316-2E
75
MB91F158 Series
(3) Reset Input Ratings
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Reset input time
Symbol
Pin
name
Condition
tRSTL
RST
⎯
Value
Min
Max
tCP × 5
⎯
Unit
Remarks
ns
tRSTL
RST
0.2 VCC
(4) Power On Reset
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Power supply rising time
Power supply shutoff time
Symbol
Pin
name
Condition
VCC
⎯
fR
tOFF
tR
VCC
Value
Unit
Remarks
20
ms
VCC < 0.2 V before
turning up the power
⎯
ms
Min
Max
⎯
2
tOFF
0.9 × VCC
0.2 V
A rapid change in supply voltage might activate power on reset.
When the supply voltage needs to be varied while operating, it is recommended to minimize
fluctuations to smoothly start up the voltage.
VCC
Holding RAM data.
It is recommended to keep the rising
in 50mV/ms or less.
VSS
VCC
RST
tRSTL
76
When turning on the power, start the RST pin in
“L” level state, allow as much time as for tRSTL after
reaching the VCC power supply level and then set
the pin to the “H” level.
DS07-16316-2E
MB91F158 Series
(5) Serial I/O (channel 0 to channel 4)
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Serial clock cycle time
tSCYC
⎯
SCK ↓ → SO delay time
tSLOV
⎯
Valid SI → SCK ↑
tIVSH
⎯
SCK ↑ → valid SI hold time
tSHIX
Serial clock “H” pulse width
Parameter
Condition
Value
Unit Remarks
Min
Max
4 tCPP
⎯
ns
−10
50
ns
50
⎯
ns
⎯
50
⎯
ns
tSHSL
⎯
4 tCPP − 10
⎯
ns
Serial clock “L” pulse width
tSLSH
⎯
4 tCPP − 10
⎯
ns
SCK ↓ → SO delay time
tSLOV
⎯
0
50
ns
Valid SI → SCK ↑
tIVSH
⎯
50
⎯
ns
50
⎯
ns
⎯
6 tCPP
ns
Internal
clock
External
clock
SCK ↑ → valid SI hold time
tSHIX
⎯
Serial busy period
tBUSY
⎯
SCS ↓ → SCK and SO delay time
tCLZO
⎯
⎯
50
ns
SCS ↓ → SCK input mask time
tCLSL
⎯
⎯
3 tCPP
ns
SCS ↑ → SCK and SO Hi-Z time
tCHOZ
⎯
50
⎯
ns
Internal shift clock mode
tSCYC
SCK
tSLOV
SO
SI
tSHIX
tIVSH
External shift clock mode
tCLZO
tSLSH
tSHSL
tBUSY
tCHOZ
SCK
tSLOV
SO
SI
tIVSH
tSHIX
SCS
tCLSL
DS07-16316-2E
77
MB91F158 Series
(6) External Bus Measurement Conditions
The following conditions apply to items that are not specifically stipulated.
• AC characteristics measurement conditions
VCC : 3.3 V
Input
Output
VCC
VIH
VOH
VIL
VOL
0V
VIH
2.4 V
VOH
1/2VCC
VIL
0.8 V
VOL
1/2VCC
(The input rising/falling time is
10 ns or less.)
• Load condition
Output pin
C = 50 pF
( VCC : 3.3 V )
78
DS07-16316-2E
MB91F158 Series
(7) Normal Bus Access and Read/Write Operations
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
CS0 to CS3 delay time
tCHCSL
CS0 to CS3 delay time
tCHCSH
CLK,
CS0 to CS3
Address delay time
tCHAV
Data delay time
tCHDV
RD delay time
tCLRL
RD delay time
tCLRH
WR0 - WR1 delay time
tCLWL
WR0 - WR1 delay time
tCLWH
Valid address →
valid data input time
tAVDV
RD ↓ → valid data input time
tRLDV
Data setup → RD ↑ time
tDSRH
RD ↑ → data hold time
tRHDX
Condition
Value
Unit
Remarks
Min
Max
⎯
15
ns
⎯
15
ns
CLK,
A23 to A00
⎯
15
ns
CLK,
D31 to D16
⎯
15
ns
CLK,
RD
⎯
10
ns
⎯
10
ns
CLK,
WR0, WR1
⎯
10
ns
⎯
10
ns
A23 to A00,
D31 to D16
⎯
3/2×
tCYC − 40
ns
*1, *2
⎯
tCYC − 25
ns
*1
25
⎯
ns
0
⎯
ns
RD,
D31 to D16
⎯
*1 : If the bus is extended with either automatic wait insertion or RDY input, add the (tCYC × the number of extended
cycles) time to this value.
*2 : This is the value at the time of (gear cycle × 1) .
When the gear cycle is set to 1/2, 1/4 or 1/8, substitute “n” in the following formula with 1/2, 1/4 or 1/8 respectively.
Formula : (2 − n / 2) × tCYC − 40
DS07-16316-2E
79
MB91F158 Series
tCYC
BA1
BA2
VOH
VOH
VOL
CLK
VOH
VOL
tCHCSH
tCHCSL
VOH
CS0 to CS3
VOL
tCHAV
VOH
VOL
A23 to A00
tCLRL
tCLRH
VOH
RD
VOL
tRLDV
tRHDX
tAVDV
tDSRH
VIH
VIL
D31 to D16
tCLWL
Read
VIH
VIL
tCLWH
VOH
WR0, WR1
VOL
tCHDV
D31 to D16
80
VOH
VOL
Write
DS07-16316-2E
MB91F158 Series
(8) Ready Input Timing
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
RDY setup time → CLK ↓
CLK ↓ → RDY hold time
Symbol
Pin
name
tRDYS
RDY
CLK
tRDYH
RDY
CLK
Condition
Value
Unit
Min
Max
20
⎯
ns
0
⎯
ns
Remarks
⎯
tCYC
CLK
VOH
VOH
VOL
VOL
tRDYS tRDYH
When
RDY wait
is applied
VIL
When
RDY wait
is not applied
VIH
DS07-16316-2E
tRDYS tRDYH
VIH
VIL
VIL
VIH
VIH
VIL
81
MB91F158 Series
(9) Hold Timing
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Pin
name
Symbol
BGRNT ↓ delay time
tCHBGL
BGRNT ↑ delay time
tCHBGH
Pin floating → BGRNT ↓ time
tXHAL
BGRNT ↑ → Pin valid time
tHAHV
CLK
BGRNT
Condition
⎯
BGRNT
Value
Unit
Min
Max
⎯
10
ns
⎯
10
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Remarks
Note : More than one cycle exist after BRQ is loaded and before BGRNT changes.
tcyc
CLK
VOH
VOH
VOH
BRQ
tCHBGL
tCHBGH
VOH
BGRNT
VOL
tXHAL
tHAHV
Each pin
High impedance
82
DS07-16316-2E
MB91F158 Series
6. A/D Converter Electrical Characteristics
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Resolution
⎯
⎯
Conversion time
⎯
⎯
Comparison time
⎯
⎯
Total error
⎯
⎯
Linearity error
⎯
⎯
Differential linearity error
⎯
⎯
Zero transition voltage
VOT
AN0 to
AN7
Full-scale transition
voltage
VFST
AN0 to
AN7
Analog input current
IAIN
AN0 to
AN7
Parameter
Analog input voltage
VAIN
AN0 to
AN7
Reference voltage
AVRH
AVRH
Supply
current
Reference
voltage
supply
current
Conversion
in operation
IA
Conversion
stopped
IAH
Conversion
in operation
IR
Conversion
stopped
IRH
Interchannel variation
AVCC
AVRH
⎯
AN0 to
AN7
Condition
⎯
⎯
AVCC = 3.3 V,
AVRH = 3.3 V
AVCC = 3.3 V,
AVRH = 3.3 V
Value
Unit
Min
Typ
Max
⎯
⎯
10
Bit
5.2
⎯
⎯
µs
⎯
⎯
0.2
ms
⎯
⎯
±4.0
LSB
⎯
⎯
±3.5
LSB
⎯
⎯
±2.0
LSB
AVRL −
1.5 LSB
AVRL +
0.5 LSB
AVRL +
2.5 LSB
V
AVRH −
5.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
V
⎯
0.1
10
µA
AVSS
⎯
AVRH
V
⎯
⎯
AVCC
V
⎯
3.0
5.0
mA
⎯
⎯
5.0
µA
⎯
2.0
3.0
mA
⎯
⎯
10
µA
⎯
⎯
4
LSB
Remarks
⎯
⎯
AVCC = 3.3 V
AVCC = 3.3 V,
AVRH = 3.3 V
⎯
Notes : • The smaller the |AVRH - AVRL| is, the greater the error is in general.
• The external circuit output impedance of analog input should be used in compliance with the following
requirements :
External circuit output impedance ≤ 2 (kΩ)
If the output impedance of the external circuit is too high, an analog voltage sampling duration shortage
might occur. (Sampling duration = 1.41 µs : @32 MHz)
DS07-16316-2E
83
MB91F158 Series
• A/D Converter Glossary
• Resolution
: Analog changes that are identifiable by the A/D converter.
• Linearity error
: The deviation of the straight line connecting the zero transition point
(00 0000 0000 ←→ 00 0000 0001) with the full-scale transition point
(11 1111 1110 ←→ 11 1111 1111) from actual conversion characteristics.
• Differential linearity error : The deviation of input voltage needed to change the output code by one LSB
from the theoretical value.
• Total error
: The difference between actual and theoretical conversion values including a
zero transition/full-scale transition/linearity error.
Total error
3FF
3FE
Digital output
3FD
Actual conversion
characteristics
{1 LSB' ( N − 1 ) + 0.5 LSB'}
1.5 LSB'
004
VNT
(Actual measurement)
Actual conversion
characteristics
003
002
Theoretical characteristics
001
0.5 LSB'
AVRL
Analog input
1 LSB’ (theoretical value) =
AVRH − AVRL
1024
VOT’ (theoretical value) =
AVRL + 0.5 LSB’ [V]
AVRH
[V]
VFST’ (theoretical value) = AVRH − 1.5 LSB’ [V]
Total error of digital output N =
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
VNT : Voltage at which digital output changes from (N + 1) to N.
(Continued)
84
DS07-16316-2E
MB91F158 Series
(Continued)
Linearity error
Differential linearity error
3FF
Actual conversion
characteristics
VFST
(Actual
measurement)
Digital output
3FD
004
VNT
(Actual
measurement)
Actual conversion
characteristics
Theoretical characteristics
003
002
AVRH
Analog input
1 LSB =
VFST
(Actual
measurement)
N−2
AVRL
Differential linearity error =
of digital output N
N
VNT
(Actual
measurement)
VOT
(Actual measurement)
=
Theoretical
characteristics
N−1
001
Linearity error of digital
output N
Actual conversion
characteristics
N+1
{1 LSB ( N − 1 ) + VOT}
Digital output
3FE
Actual conversion
characteristics
AVRL
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
[LSB]
V (N + 1) T − VNT
1 LSB
[LSB]
VFST − VOT
1022
−1
AVRH
Analog input
[V]
VOT : Voltage at which digital output changes from (000) H to (001) H.
VFST : Voltage at which digital output changes from (3FE) H to (3FF) H.
7. D/A Converter Electrical Characteristics
(VCC = 3.2 V to 3.5 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Value
Symbol
Pin
name
Condition
Min
Typ
Max
Resolution
⎯
⎯
⎯
⎯
⎯
8
Bit
Differential linearity error
⎯
⎯
⎯
⎯
⎯
1
LSB
Conversion time
⎯
⎯
⎯
⎯
⎯
20
µs
Analog output impedance
⎯
⎯
⎯
⎯
29
⎯
kΩ
Parameter
Remarks
Unit
*
* : CL = 20 pF
DS07-16316-2E
85
MB91F158 Series
■ EXAMPLE CHARACTERISTICS
(1) “H” level output voltage
(2) “L” level output voltage
“H” level output voltage vs. Power supply voltage
“L” level output voltage vs. Power supply voltage
5
400
350
300
VOL [mV]
VOH [V]
4
3
2
250
200
150
100
1
50
0
3.1
3.2
3.3
3.4
VCC [V]
3.5
0
3.1
3.6
(3) Pullup resistance
70
50
ICC [mA]
R [kΩ]
60
40
30
20
10
86
3.5
3.6
Power supply current vs. Voltage
80
3.2
3.3
3.4
VCC [V]
(4) Power supply current
Pullup resistance vs.
Power supply voltage
0
3.1
3.2
3.3
3.4
VCC [V]
3.5
3.6
110
100
90
80
70
60
50
40
30
20
10
0
3.1
3.2
3.3
3.4
VCC [V]
3.5
3.6
DS07-16316-2E
MB91F158 Series
(5) Power supply at sleeping
(6) Power supply at stopping
Power supply (Stopping) vs. Voltage
90
100
80
90
70
80
60
70
ICCH [µA]
ICCS [mA]
Power supply (sleeping) vs. Voltage
50
40
30
60
50
40
30
20
20
10
10
0
3.1
3.2
3.3
3.4
3.5
0
3.1
3.6
3.2
VCC [V]
(7) A/D conversion power supply (32 MHz)
A/D conversion power supply vs.
Power supply voltage
3.3
3.4
VCC [V]
3.5
3.6
(8) A/D conversion reference voltage supply current
(32 MHz)
A/D conversion reference voltage supply current vs.
Voltage
5
3.0
2.5
4
IR [mA]
IA [mA]
2.0
3
2
1.0
1
0
3.1
1.5
0.5
3.2
3.3
3.4
VCC [V]
3.5
3.6
0.0
3.1
3.2
3.3
3.4
VCC [V]
3.5
3.6
(9) A/D conversion reference voltage supply current
per 1 ch (32 MHz)
A/D conversion voltage supply current per 1 ch vs.
Power supply voltage
5
IADA [mA]
4
3
2
1
0
3.1
DS07-16316-2E
3.2
3.3
3.4
VCC [V]
3.5
3.6
87
MB91F158 Series
■ ORDERING INFORMATION
Part number
MB91F158PMC1
88
Package
Remarks
120-pin plastic LQFP
(FPT-120P-M24)
DS07-16316-2E
MB91F158 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP120-14×14-0.40
(FPT-120P-M24)
120-pin plastic LQFP
(FPT-120P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8˚
LEAD No.
1
0.40(.016)
30
0.16±0.05
(.006±.002)
0.07(.003)
M
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
©2006-2008
FUJITSU MICROELECTRONICS LIMITED F120036S-c-1-2
C
2006 FUJITSU LIMITED F120036S-c-1-1
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16316-2E
89
MB91F158 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
⎯
⎯
Changed the package code.
FPT-120P-M05 → FPT-120P-M24
⎯
⎯
Changed the series name;
MB91F158 → MB91F158 series
41
■ PERIPHERAL RESOURCES
4. 16-bit Reload Timer
44
■ PERIPHERAL RESOURCES
6. 8/10-bit A/D Converter
(Sequential Conversion Type)
57
■ PERIPHERAL RESOURCES
13. FLASH Memory
Corrected power supply voltage value.
0.3 V → 3 V
77
■ ELECTRICAL CHARACTERISTICS
5. AC Characteristics
(5) Serial I/O (channel 0 to channel 4)
Changed the value of serial clock cycle time.
Min : 8tCPP → 4tCPP
■ ELECTRICAL CHARACTERISTICS
6. A/D Converter Electrical Characteristics
Changed the items of “Zero transition voltage” and
“Full-scale transition voltage”.
transition error → transition voltage
Unit : LSB → V
AVSS/AVRH ± value → AVRL/AVRH ± value LSB
83
84
Changed the operating clock name of peripheral
resources.
machine clock → peripheral clock
Changed the analog input of reference voltage for lowvoltage side.
AVss → AVRL
85
88
■ ORDERING INFORMATION
Changed the order information.
MB91F158PFF → MB91F158PMC1
89
■ PACKAGE DIMENSION
Changed the package figure.
FPT-120P-M05 → FPT-120P-M24
The vertical lines marked in the left side of the page show the changes.
90
DS07-16316-2E
MB91F158 Series
MEMO
DS07-16316-2E
91
MB91F158 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
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#05-08 New Tech Park 556741 Singapore
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http://www.fmal.fujitsu.com/
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Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
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