Manual - Spansion

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CM71-10149-2ES
FR60
32-BIT MICROCONTROLLER
MB91460N Series
HARDWARE MANUAL
(SUPPLEMENTARY MANUAL)
PREFACE
■ Objective of This Supplementary Manual
This manual is supplementary manual concerning "MB91460N Series HARDWARE MANUAL".
Before using "MB91460N Series HARDWARE MANUAL", replace "Chapter 42 Flash Memory" "Chapter
43 Flash Security" in "MB91460N Series HARDWARE MANUAL" with this supplementary manual.
■ Object document
Document name : FR60 32-BIT MICROCONTROLLER
MB91460N Series HARDWARE MANUAL
Document code : CM71-10149-2E
i
Main changes
Page
-
Changes (For details, refer to main body.)
Revised the entire of "Chapter 42 Flash Memory" and "Chapter 43 Flash Security".
ii
Chapter 42 Flash Memory
42.1 Overview
MB91460N Series
Chapter 42 Flash Memory
This chapter explains the flash memory.
42.1 Overview
Flash memory is rewritable built-in program memory.
■ Overview
Flash memory operates as built-in program memory. It allows data to be read by word, half word and byte.
As instruction codes can be fetched from the flash memory, the CPU can execute programs on the flash
memory.
The flash memory is rewritable. Its data-write function enables data to be written by half word. The data
written through the data-write operation is saved to the flash memory and maintained even after the power is
switched off. The flash memory is divided into sectors and this allows data to be erased by sector. It can also
erase data from all of the sectors at once.
The flash security function allows user to configure write protection and read protection for each sector. The
write-protected sectors are protected against both data-write and erase function. For the flash security
function, see "Chapter 43 Flash Security".
■ Features
Features of the flash memory are as follows:
• Data Write/Erase is possible according to the program execution of CPU.
• Commands can be performed automatically using automatic algorithms (equivalent to Embedded
Algorithm).
• The hardware sequence flag detects the execution status of the automatic algorithm.
• Data can be written by half word (16 bits).
• Data can be erased by sector or all sectors at once (chip erase).
• In flash memory mode, a parallel flash programmer can perform Data Write/Erase through external
pins.
■ Size and Products of Flash Memory
Table 42.1-1 shows the product lineup of the flash memory.
Table 42.1-1 Product Lineup of Flash Memory
Product
MB91F463NC
MB91F463NA/F463NB
Flash memory size
288 Kbytes
288 Kbytes
Flash memory area
000C: 0000H to 000F: FFFFH
0014: 8000H to 0014: FFFFH
000C: 0000H to 000F: FFFFH
0014: 8000H to 0014: FFFFH
Sector configuration
8 Kbytes × 4 sectors
64 Kbytes × 4 sectors
8 Kbytes × 4 sectors
64 Kbytes × 4 sectors
The sector configuration of the flash memory is different in MB91F463NC and MB91F463NA/ F463NB.
Code : CM71-00502-2E
CM71-10149-2ES
FUJITSU MICROELECTRONICS LIMITED
1
Chapter 42 Flash Memory
42.1 Overview
MB91460N Series
■ Block Diagram
Figure 42.1-1 shows the block diagram of the flash memory.
Figure 42.1-1 Block Diagram of Flash Memory
CPU
Flash memory interface
Flash memory
Control signal
Control signal
Control signal
A0 to A20
A0 to A20
CPU core
Address
DQ0 to DQ31
32 bits
32 bits
DQ0 to DQ31
data
Control
signal
Address
16 bits
Flash writer
interface
(at flash
memory mode)
data
■ Operating Clock
Table 42.1-2 shows the operating clock of the flash memory. This operating clock applies to the flash
memory interface when the flash memory is accessed from the CPU in CPU mode. In flash memory mode, it
does not apply when the flash memory is accessed from external pins.
Table 42.1-2 Operating Clock of Flash Memory
2
Operation mode
Operating clock
CPU mode
CPU cock (CLKB)
Flash memory mode
Not applied
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CM71-10149-2ES
Chapter 42 Flash Memory
42.2 Address Map and Sector Configuration
MB91460N Series
42.2 Address Map and Sector Configuration
The flash memory area is divided into sectors.
■ Flash Memory Area
Figure 42.2-1 shows the address map of the flash memory area.
Figure 42.2-1 Address Map of Flash Memory Area
FFFF:FFFFH
0014:FFFFH
Flash memory
(32 Kbytes)
8-Kbytes sector area
Flash memory
(256 Kbytes)
64-Kbytes sector area
0014:8000H
000F:FFFFH
000C:0000H
0000:0000H
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3
Chapter 42 Flash Memory
42.2 Address Map and Sector Configuration
MB91460N Series
■ Sector Configuration
Table 42.2-1 shows the sector configuration of MB91F463NC. 288 Kbytes from SA7 to SA4 and from SA19
to SA16 are available.
Table 42.2-1 Sector Configuration of MB91F463NC
Sector
Address Range
adrs+3
adrs+2
adrs+1
0014: FFFFH to 0014: E000H
SA7 (8 Kbytes)
0014: DFFFH to 0014: C000H
SA6 (8 Kbytes)
0014: BFFFH to 0014: A000H
SA5 (8 Kbytes)
0014: 9FFFH to 0014: 8000H
SA4 (8 Kbytes)
0014: 7FFFH to 0014: 0000H
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
0013: FFFFH to 0010: 0000H
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
000F: FFFFH to 000F: 0000H
SA19 (64 Kbytes)
000E: FFFFH to 000E: 0000H
SA18 (64 Kbytes)
000D: FFFFH to 000D: 0000H
SA17 (64 Kbytes)
000C: FFFFH to 000C: 0000H
SA16 (64 Kbytes)
000B: FFFFH to 0004: 0000H
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
adrs+0
adrs : Address that is a multiple of 4 within the address range
(Note) The reserved area
4
cannot be used.
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Chapter 42 Flash Memory
42.2 Address Map and Sector Configuration
MB91460N Series
Table 42.2-2 shows the sector configuration of MB91F463NA/NB. In MB91F463NA/NB, sectors are switched
by word. 288 Kbytes from SA7 to SA4 and from SA19 to SA16 are available.
Table 42.2-2 Sector Configuration of MB91F463NA/NB
Sector
Address Range
adrs+7
adrs+6
adrs+5
adrs+4
adrs+3
adrs+2
adrs+1
0014:FFFFH to 0014:C000H
SA6 (8 Kbytes)
SA7 (8 Kbytes)
0014:BFFFH to 0014:8000H
SA4 (8 Kbytes)
SA5 (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
000F:FFFFH to 000E:0000H
SA18 (64 Kbytes)
SA19 (64 Kbytes)
000D:FFFFH to 000C:0000H
SA16 (64 Kbytes)
SA17 (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
0014:7FFFH to 0014:0000H
0013:FFFFH to 0010:0000H
000B:FFFFH to 0004:0000H
adrs+0
adrs : Address that is a multiple of 8 within the address range
(Note) The reserved area
CM71-10149-2ES
cannot be used.
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5
Chapter 42 Flash Memory
42.3 Registers
MB91460N Series
42.3 Registers
The flash memory has registers that control Data Write/Erase operations.
■ Flash Memory Registers
Table 42.3-1 shows the registers of the flash memory interface.
Table 42.3-1 Registers of Flash Memory Interface
Mnemonic
Register Name
Address
Size
FMCS
Flash Memory Control Status Register
0000: 7000H
Byte
FMCR
Flash Memory Control Register
0000: 7001H
Byte
This section explains the following bits when using Data Write/Erase of the flash memory. For flash memory
control status register (FMCS) and flash memory control register (FMCR), see "Chapter 11 Memory
Controller".
- RDY status hold bit :
(FMCS: RDYEG)
- Automatic algorithm ready-status bit : (FMCS: RDY)
6
- 16-bit access enable bit :
(FMCS:RW16)
- 64-bit read mode enable bit :
(FMCR:RD64)
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Chapter 42 Flash Memory
42.3 Registers
MB91460N Series
42.3.1 Flash Memory Control Status Register (FMCS)
This register indicates the status and controls the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 42.3-1 shows the Bit configuration of Flash Memory Control Status Register (FMCS).
Figure 42.3-1 Bit configuration of Flash Memory Control Status Register (FMCS)
bit
FMCS
7
6
5
Reserved Reserved Reserved
4
3
2
1
0
RDYEG
RDY
Reserved
RW16
Reserved
Bit attribute
R/W0
R/W1
R/W1
R,WX
R,WX
R/W0
R/W
R/W0
Initial value
0
1
1
0
1
0
0
0
[bit4] RDYEG : RDY status hold
This bit indicates that the automatic algorithm of the flash memory has been completed. The RDYEG
bit is set when the value of FMCS:RDY bit is changed from "0" to "1". After data is read from the
FMCS register, the RDYEG bit is cleared. The initial value of the RDYEG bit is "0".
RDYEG
RDY status hold
0
Automatic algorithm is not activated or not yet completed.
1
Automatic algorithm has been completed since the previous read access.
If the frequency of CPU clock (CLKB) is lower than 1 MHz, the behavior of RDYEG bit isn't
guaranteed.
[bit3] RDY : Automatic algorithm ready-status
This bit indicates the execution status of the automatic algorithm of the flash memory. The RDY bit
detects the status of the flash memory by hardware. The RDY bit is a read-only bit. Writing does not
affect the value of the RDY bit. The initial value of the RDY bit is "1".
RDY
Automatic algorithm ready-status
0
Read/reset state (ready status)
1
Automatic algorithm is being executed (busy status)
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Chapter 42 Flash Memory
42.3 Registers
MB91460N Series
[bit1] RW16 : 16-bit access enable
This bit enables 16-bit access to the flash memory. When the RW16 bit is set to "1", the flash memory
is accessed by half word. When the RW16 bit is set to "1", instructions cannot be fetched and executed
on the flash memory. The initial value of the RW16 bit is "0".
8
RW16
16-bit access enable
0
32-bit access
1
16-bit access
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Chapter 42 Flash Memory
42.3 Registers
MB91460N Series
42.3.2 Flash Memory Control Register (FMCR)
This register controls the flash memory.
■ Flash Memory Control Register (FMCR)
Figure 42.3-2 shows the Bit configuration of Flash Memory Control Register (FMCR).
Figure 42.3-2 Bit configuration of Flash Memory Control Register (FMCR)
bit
7
6
5
4
3
2
1
0
-
-
-
-
LOCK
Reserved
PF2I
RD64
Bit attribute
RX,WX
RX,WX
RX,WX
RX,WX
R/W
R/W0
R/W
R/W0
Initial value
X
X
X
X
0
0
0
0
FMCR
[bit0] RD64 : 64-bit read mode enable
This bit enables 64-bit read access to the flash memory. For this series, always write "0" to this bit. The
read value is "0", the value written to it. The initial value of the RD64 bit is "0".
CM71-10149-2ES
RD64
64-bit read mode enable
0
Disables 64-bit read mode
1
Enables 64-bit read mode
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9
Chapter 42 Flash Memory
42.4 Setting Access Mode
MB91460N Series
42.4 Setting Access Mode
Access mode can be set for the flash memory. Set the access mode before performing Data
Write/Erase operation of the flash memory.
■ Access Mode
Access mode can be selected by setting the 16-bit access enable bit (FMCS:RW16) and the 64-bit read
mode enable bit (FMCR:RD64). Table 42.4-1 shows the Setting of access mode for flash memory.
Table 42.4-1 Setting of access mode for flash memory
FMCS:RW16
FMCR:RD64
Access mode
Read
Write
Execution of
instructions
1
0
16-bit CPU mode
❍
❍
✕
0
0
32-bit CPU mode
❍
✕
❍
1
1
Setting disabled
⎯
⎯
⎯
0
1
Setting disabled
⎯
⎯
⎯
❍: Access-enabled
✕: Access-disabled
■ 16-bit CPU Mode
In this mode, the flash memory is accessed by half word (16 bits). It allows for read and write operations to
the flash memory. Program execution on the flash memory is not possible. To perform Data Write/Erase
operation, select this 16-bit CPU mode.
■ 32-bit CPU Mode
In this mode, the flash memory is accessed by word (32 bits). It allows for read operations and execution of
instructions on the flash memory. Once the MCU is reset, it is initialized to the 32-bit CPU mode. To return to
execution of a program after completing Data Write/Erase operation, select the 32-bit CPU mode.
■ Changing Access Mode
Change the access mode using a program on the ID-RAM. Copy a program that changes the access mode
to the ID-RAM, and then execute it on the ID-RAM.
The access mode can be set by following the steps below:
1. Disable the flash instruction cache.
2. Copy the program code to the ID-RAM.
3. Branch to the copied program on the ID-RAM.
4. Set the access mode to the 16-bit CPU mode.
5. Change the access timing setting of the flash memory.
6. Perform Data Write/Read operations to the flash memory.
7. Set the access mode to the 32-bit CPU mode.
8. Change the access timing setting of the flash memory back to the original setting.
9. Flush all entries in the flash instruction cache, and then enable the flash instruction cache.
10. Return to the program on the flash memory.
To perform Data Write/Erase operation of the flash memory, change the access setting of the flash memory.
For the access timing setting of the flash memory and the flash instruction cache, see "Chapter 11 Memory
Controller".
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
42.5 Automatic Algorithm
On the flash memory, Data Write/Erase operation is performed using an automatic algorithm.
42.5.1 Command Sequence
The flash memory executes the automatic algorithm when a command sequence is written to it.
■ Command Sequence
Issue a command by writing command sequence to the flash memory. Once the command is issued, the
automatic algorithm is activated. The automatic algorithm stops automatically after performing Data Write/
Erase operation, and then the flash memory returns to the read/reset state. The flash memory has the
following commands:
(1)
(2)
(3)
(4)
(5)
(6)
Reset command
Data write command
Chip erase command
Sector erase command
Sector erase suspend command
Sector erase resume command
Write the command sequence continuously in the flash memory area. If data other than the command
sequence is written to the flash memory area in the middle of the command sequence, the command will not
be issued correctly. The command sequence has meanings in both the address and data. Write the
command sequence to a sector of the flash memory area that is allowed for write operation.
Set the flash memory to the 16-bit CPU mode and write the command sequence by half-word access. The
upper byte of data, except for writing data (PD) by the data write command, is ignored. For example, apply a
upper byte to the same value as lower byte (AAH) like AAAAH.
Write the command sequence correctly. If data is written to an improper address or written in an incorrect
order, the flash memory returns to the read/reset state.
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
Table 42.5-1 shows the command sequence of MB91F463NC. Table 42.5-2 shows the command sequence
of MB91F463NA/NB.
Table 42.5-1 Command Sequence of MB91F463NC
Command
First writing Second writing Third writing Fourth writing
Address XXXXXXXeH
Fifth writing
Sixth writing
-
-
-
-
-
-
-
-
-
-
XXXXo554H
XXXXeAAAH
-
-
-
5555H
F0F0H
-
-
-
XXXXo554H
XXXXeAAAH
PA
-
-
5555H
A0A0H
PD
-
-
Reset
Data
F0F0H
Address XXXXeAAAH
Reset
Data
AAAAH
Address XXXXeAAAH
Data write
Data
AAAAH
Address XXXXeAAAH
XXXXo554H
XXXXeAAAH XXXXeAAAH XXXXo554H XXXXeAAAH
Chip erase
Data
AAAAH
Address XXXXeAAAH
5555H
XXXXo554H
8080H
AAAAH
5555H
1010H
XXXXeAAAH XXXXeAAAH XXXXo554H
SA
Sector erase
5555H
8080H
AAAAH
5555H
3030H
XXXXXXXeH
Sector erase Address
Suspend
B0B0H
Data
-
-
-
-
-
-
-
-
-
-
XXXXXXXeH
Sector erase Address
Resume
3030H
Data
-
-
-
-
-
-
-
-
-
-
Data
AAAAH
PA : Data writing address (Half-word address)
PD : Write data (Half-word data)
SA : Erase sector address
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
o : Odd hexadecimal number (1, 3, 5, 7, 9, B, D, F)
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
Table 42.5-2 Command Sequence of MB91F463NA/NB
Command
First writing
Second writing Third writing Fourth writing
Fifth writing
Sixth writing
Address
XXXXXXXeH
-
-
-
-
-
Data
F0F0H
-
-
-
-
-
Address
XXXXm55sH
XXXXnAAsH
XXXXm55sH
-
-
-
Data
AAAAH
5555H
F0F0H
-
-
-
Address
XXXXm55sH
XXXXnAAsH
XXXXm55sH
PA
-
-
Data
AAAAH
5555H
A0A0H
PD
-
-
Address
XXXXm55sH
XXXXnAAsH
Data
AAAAH
5555H
Address
XXXXm55sH
XXXXnAAsH
Data
AAAAH
5555H
8080H
AAAAH
5555H
3030H
Sector erase Address
Suspend
Data
XXXXXXXeH
-
-
-
-
-
B0B0H
-
-
-
-
-
Sector erase Address
Resume
Data
XXXXXXXeH
-
-
-
-
-
3030H
-
-
-
-
-
Reset
Reset
Data write
XXXXm55sH XXXXm55sH XXXXnAAsH XXXXm55sH
Chip erase
8080H
AAAAH
5555H
XXXXm55sH XXXXm55sH XXXXnAAsH
1010H
SA
Sector erase
PA : Data writing address (Half-word address)
PD : Write data (Half-word data)
SA : Erase sector address
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
m : Hexadecimal number, and one of 1, 5, 9 or D
n : Hexadecimal number, and one of 2, 6, A or E
s : Hexadecimal number, and one of 0, 4, 8 or C
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
42.5.2 Reset Command
The flash memory can be placed in read/reset state by issuing reset command.
■ Reset Command
Table 42.5-3 and Table 42.5-4 show the command sequence of the reset command. The reset command
has two patterns of the command sequence, both have the same function.
Table 42.5-3 Command Sequence 1 of Reset Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
First writing
Formula
Value
(adrs & FFFF:FFFEH)
XXXXXXXeH
F0F0H
Data
Formula
Value
(adrs & FFFF:FFFEH)
XXXXXXXeH
F0F0H
adrs: Address in a sector of the flash memory area that is allowed for write operation
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
Table 42.5-4 Command Sequence 2 of Reset Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
Formula
Value
Data
Formula
(adrs & FFFF:C004H)
XXXXeAAAH AAAAH
+ 1550H
Value
First writing
(adrs & FFFF:E000H)
+ 0AAAH
Second writing
(adrs & FFFF:E000H)
+ 1554H
XXXXo554H
5555H
(adrs & FFFF:C004H)
+ 2AA8H
XXXXnAAsH
5555H
Third writing
(adrs & FFFF:E000H)
+ 0AAAH
XXXXeAAAH
F0F0H
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
F0F0H
XXXXm55sH AAAAH
adrs: Address in a sector of the flash memory area that is allowed for write operation
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
o : Odd hexadecimal number (1, 3, 5, 7, 9, B, D, F)
m : Hexadecimal number, and one of 1, 5, 9 or D
n : Hexadecimal number, and one of 2, 6, A or E
s : Hexadecimal number, and one of 0, 4, 8 or C
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CM71-10149-2ES
Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
42.5.3 Data Write Command
The half word data can be written in the flash memory by issuing the data write command.
■ Data Write Command
Table 42.5-5 shows the command sequence of the data write command.
Table 42.5-5 Command Sequence of Data Write Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
Formula
First (adrs & FFFF:E000H)
writing + 0AAAH
Value
Data
Formula
XXXXeAAAH AAAAH
Value
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
AAAAH
Second (adrs & FFFF:E000H)
writing + 1554H
XXXXo554H
5555H
(adrs & FFFF:C004H)
+ 2AA8H
XXXXnAAsH
5555H
Third (adrs & FFFF:E000H)
writing + 0AAAH
XXXXeAAAH
A0A0H
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
A0A0H
Fourth
(adrs & FFFF:FFFEH)
writing
PA
PD
(adrs & FFFF:FFFEH)
PA
PD
adrs: Address in a sector of the flash memory area that is allowed for write operation
PA : Data writing address (Half-word address)
PD : Write data (Half-word data)
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
o : Odd hexadecimal number (1, 3, 5, 7, 9, B, D, F)
m : Hexadecimal number, and one of 1, 5, 9 or D
n : Hexadecimal number, and one of 2, 6, A or E
s : Hexadecimal number, and one of 0, 4, 8 or C
The flash memory starts the automatic algorithm for data-write operation when the address and data of the
fourth writing of the command sequence is written. During the execution of the automatic algorithm for datawrite operation, only the reset command can be issued. And any write access to the flash memory (issuing
the command) other than the reset command is ignored.
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
42.5.4 Chip Erase Command
The contents of all sectors of the flash memory can be erased by issuing the chip erase command.
■ Chip Erase Command
Table 42.5-6 shows the command sequence of the chip erase command.
Table 42.5-6 Command Sequence of Chip Erase Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
Formula
Value
Data
Formula
Value
First
writing
(adrs &
FFFF:E000H)
+ 0AAAH
XXXXeAAAH
AAAAH
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
AAAAH
Second
writing
(adrs &
FFFF:E000H)
+ 1554H
XXXXo554H
5555H
(adrs & FFFF:C004H)
+ 2AA8H
XXXXnAAsH
5555H
Third
writing
(adrs &
FFFF:E000H)
+ 0AAAH
XXXXeAAAH
8080H
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
8080H
Fourth
writing
(adrs &
FFFF:E000H)
+ 0AAAH
XXXXeAAAH
AAAAH
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
AAAAH
Fifth
writing
(adrs &
FFFF:E000H)
+ 1554H
XXXXo554H
5555H
(adrs & FFFF:C004H)
+ 2AA8H
XXXXnAAsH
5555H
Sixth
writing
(adrs &
FFFF:E000H)
+ 0AAAH
XXXXeAAAH
1010H
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
1010H
adrs: Address in a sector of the flash memory area that is allowed for write operation
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
o : Odd hexadecimal number (1, 3, 5, 7, 9, B, D, F)
m : Hexadecimal number, and one of 1, 5, 9 or D
n : Hexadecimal number, and one of 2, 6, A or E
s : Hexadecimal number, and one of 0, 4, 8 or C
The flash memory starts the automatic algorithm for chip erase operations when the sixth writing of the
command sequence are written. During the execution of the automatic algorithm for chip erase operations,
only the reset command can be issued. And any write access to the flash memory (issuing the command)
other than the reset command is ignored.
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
42.5.5 Sector Erase Command
The contents of each sector of the flash memory can be erased by issuing the sector erase command.
■ Sector Erase Command
Table 42.5-7 shows the command sequence of the sector erase command.
Table 42.5-7 Command Sequence of Sector Erase Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
Formula
Value
Data
Formula
Value
First
writing
(adrs & FFFF:E000H)
+ 0AAAH
XXXXeAAAH
AAAAH
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
AAAAH
Second
writing
(adrs & FFFF:E000H)
+ 1554H
XXXXo554H
5555H
(adrs & FFFF:C004H)
+ 2AA8H
XXXXnAAsH
5555H
Third
writing
(adrs & FFFF:E000H)
+ 0AAAH
XXXXeAAAH
8080H
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
8080H
Fourth
writing
(adrs & FFFF:E000H)
+ 0AAAH
XXXXeAAAH
AAAAH
(adrs & FFFF:C004H)
+ 1550H
XXXXm55sH
AAAAH
Fifth
writing
(adrs & FFFF:E000H)
+ 1554H
XXXXo554H
5555H
(adrs & FFFF:C004H)
+ 2AA8H
XXXXnAAsH
5555H
Sixth
writing
(adrs & FFFF:FFFEH)
SA
3030H
(adrs & FFFF:FFFEH)
SA
3030H
adrs: Address in a sector of the flash memory area that is allowed for write operation
SA : Erase sector address
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
o : Odd hexadecimal number (1, 3, 5, 7, 9, B, D, F)
m : Hexadecimal number, and one of 1, 5, 9 or D
n : Hexadecimal number, and one of 2, 6, A or E
s : Hexadecimal number, and one of 0, 4, 8 or C
When the command sequence is written, the flash memory starts the automatic algorithm for sector erase
operation.
The sixth writing of the command sequence is a sector erase code. Writing the sector erase code of the
command sequence starts a sector erase time-out period. The next sector erase codes can be written during
this sector erase time-out period. Multiple target sectors can be specified for sector erase operation by
writing the sector erase code more than once.
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
Table 42.5-8 shows the sector erase code.
Table 42.5-8 Sector Erase Code
Address
Data
After seventh writing
Formula
Value
(adrs & FFFF:FFFEH)
SA
3030H
adrs: Address in a sector of the flash memory area that is allowed for write operation
SA : Erase sector address
During the execution of the automatic algorithm for sector erase operations, only the sector erase suspend
command and the reset command can be issued.
42.5.6 Sector Erase Suspend Command
The sector erase operation can be suspended temporarily by issuing sector erase suspend command.
■ Sector Erase Suspend Command
Table 42.5-9 shows the command sequence of the sector erase suspend command.
Table 42.5-9 Command Sequence of Sector Erase Suspend Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
First
writing
Formula
Value
(adrs & FFFF:FFFEH)
XXXXXXXeH
B0B0H
Data
Formula
Value
(adrs & FFFF:FFFEH)
XXXXXXXeH
B0B0H
adrs: Address in a sector of the flash memory area that is allowed for write operation
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
If the sector erase suspend command is issued during the execution of the automatic algorithm for sector
erase operations, the flash memory temporarily suspends the sector erase operation. During the suspension
of the sector erase operation, data can be read from and written to sectors other than the sector that was
specified for the erase target by preceding sector erase command. Even if the sector erase suspend
command is reissued during the suspension of the sector erase operation, that command is ignored.
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Chapter 42 Flash Memory
42.5 Automatic Algorithm
MB91460N Series
42.5.7 Sector Erase Resume Command
The suspended sector erase operation can be resumed by issuing sector erase resume command.
■ Sector Erase Resume Command
Table 42.5-10 shows the command sequence of the sector erase resume command.
Table 42.5-10 Command Sequence of Sector Erase Resume Command
MB91F463NC
MB91F463NA/NB
Address
Address
Data
First
writing
Formula
Value
(adrs & FFFF:FFFEH)
XXXXXXXeH
3030H
Data
Formula
Value
(adrs & FFFF:FFFEH)
XXXXXXXeH
3030H
adrs: Address in a sector of the flash memory area that is allowed for write operation
e : Even hexadecimal number (0, 2, 4, 6, 8, A, C, E)
When the sector erase resume command is issued during the suspension of a sector erase operation, the
flash memory resumes the sector erase operation. Even if the sector erase resume command is issued at a
time other than during the suspension of a sector erase operation, that command is ignored.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
42.6 Hardware Sequence Flag
During the execution of the automatic algorithm for the Data Write/Erase operation, data reading
from the flash memory area is the hardware sequence flag. The hardware sequence flag indicates the progress/completion of the automatic algorithm.
42.6.1 Reading Hardware Sequence Flag
The hardware sequence flag can be read by reading from the flash memory area after the automatic algorithm is activated.
■ Hardware Sequence Flag
The hardware sequence flag consists of the following bits:
• Data polling flag (DQ7)
• Toggle bit flag (DQ6)
• Timing limit exceeded flag (DQ5)
• Sector erase timer flag (DQ3)
• Toggle bit 2 flag (DQ2)
■ Bit Configuration of Hardware Sequence Flag
Figure 42.6-1 shows the bit configuration of hardware sequence flag. The read value of undefined bits of the
hardware sequence flag is indeterminate.
Figure 42.6-1 Bit Configuration of Hardware Sequence Flag
bit
Hardware
Sequence Flag
7
DPOLL
(DQ7)
R
6
5
4
3
TOGGLE TLOVER
SETIMR
Undefined
(DQ6)
(DQ5)
(DQ3)
R
R
R
R
2
1
0
TOGGL2
Undefined Undefined
(DQ2)
R
R
R
Table 42.6-1 shows the list of states of hardware sequence flag. "End of execution (read/reset state)" in
Table 42.6-1 is not a result of the hardware sequence flag but a result of a usual read. To make easily to
compare, the item is shown in the table.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
Table 42.6-1 List of States of Hardware Sequence Flag
Execution status of automatic algorithm
DPOLL
(DQ7)
TOGGLE
(DQ6)
TLOVER
(DQ5)
SETIMR
(DQ3)
TOGGL2
(DQ2)
End of execution (read/reset state)
DATA[7]
DATA[6]
DATA[5]
DATA[3]
DATA[2]
Data write
PD[7]
Toggle
0
0
1
Chip erase
0
Toggle
0
1
Toggle
Timeout period
1
Toggle
0
0
Toggle
Erasing
0
Toggle
0
1
Toggle
Read
(sector to be erased)
1
1
0
0
Toggle
Read
(sectors not to be erased)
DATA[7]
DATA[6]
DATA[5]
DATA[3]
DATA[2]
Data write
PD[7]
Toggle
0
0
1
Data write
PD[7]
Toggle
1
0
1
Chip erase
0
Toggle
1
1
Toggle
Sector erase
0
Toggle
1
1
Toggle
Sector erase
Execution
in progress
Sector erase
suspend
Timing limit
exceeded
PD[7] : Value reversed from bit 7 of write data specified by data write command
DATA : Data written to the read address
■ Reading Hardware Sequence Flag
Read the hardware sequence flag by half-word assess or byte access. When it is read by half-word access,
the lower byte represents the hardware sequence flag. In case of byte access, read it from the oddnumbered address. Figure 42.6-2 shows the position of the hardware sequence flag.
Figure 42.6-2 Position of Hardware Sequence Flag
bit
15 14 13 12 11 10 9 8
7
(Undefined)
Half word access
5
4
3
2
1
0
Hardware sequence flag
bit
Byte access (odd number address)
6
7
6
5
4
3
2
1
0
Hardware sequence flag
Place one or more other instructions between the instructions (LD instruction etc.) that read the hardware
sequence flag when read the hardware sequence flag continuously. Other instructions are either the NOP
instruction or an instruction that do not read the hardware sequence flag. When the instruction to which CPU
reads the hardware sequence flag without placing other instructions is continuously executed, toggle bit flag
(DQ6) and toggle bit 2 flag (DQ2) cannot be read correctly.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
42.6.2 Data Polling Flag (DQ7)
The data polling flag (DQ7) indicates that the automatic algorithm is currently being executed.
■ Data Write Operation
The data polling flag (DQ7) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for writing data. Figure 42.6-3 shows the state transition of the data
polling flag (DQ7) at the data write.
Figure 42.6-3 State Transition of Data Polling Flag (DQ7) at Data Write
DATA WRITE
COMMAND
READ/RESET STATE
DQ7=DATA[7]
DATA WRITE
DQ7=PD[7]
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ7=PD[7]
When the data polling flag (DQ7) is read during the execution of the automatic algorithm, its read value is the
value reversed from bit 7 of the write data (PD). The read address is any address in the flash memory area.
The write data (PD) is the data specified by the data write command.
When the flag is read after the completion of the automatic algorithm, the read value is bit 7 of the data at
that address. The flash memory returns to the read/reset state. The data written in the flash memory is read
as normal read data.
Read the address (PA) specified by the data write command as the data polling flag (DQ7). During the
execution of the automatic algorithm, it indicates the value reversed from bit 7 of the write data (PD). After
the completion of the automatic algorithm, it indicates the value of bit 7 of the write data (PD). Although the
written data (DATA) is read after the completion of the automatic algorithm, that value is actually the same
as the write data (PD).
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Chip Erase Operation
The data polling flag (DQ7) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for chip erase operations. Figure 42.6-4 shows the state transition of
the data polling flag (DQ7) at the chip erase.
Figure 42.6-4 State Transition of Data Polling Flag (DQ7) at Chip Erase
CHIP ERASE
COMMAND
READ/RESET STATE
DQ7=DATA[7]
CHIP ERASE
DQ7= 0
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ7= 0
When the data polling flag (DQ7) is read during the execution of the automatic algorithm, its read value is
"0". The read address is any address in the flash memory area.
When the flag is read after the completion of the automatic algorithm, the read value is "1". The flash
memory returns to the read/reset state. After the completion of the automatic algorithm, "1" is actually read
as the erased data from the flash memory.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Sector Erase Operation
The data polling flag (DQ7) can be read by making read access to the sector to be erased in the flash
memory area during the execution of the automatic algorithm for sector erase operations. Figure 42.6-5
shows the state transition of the data polling flag (DQ7) at the sector erase.
Figure 42.6-5 State Transition of Data Polling Flag (DQ7) at Sector Erase
SECTOR ERASE
COMMAND
SECTOR ERASE
READ/RESET STATE
TIMEOUT PERIOD
DQ7= 1
DQ7=DATA[7]
RESET
COMMAND
TIMEOUT PERIOD
END
NORMAL END
SECTOR ERASE
PERIOD
DQ7= 0
ABNORMAL STATE
DQ7= 0
TIMING LIMIT
EXCESS
The data polling flag (DQ7) can be read by making read access to the sector to be erased during the
execution of the automatic algorithm. In this series, the read value of the data polling flag (DQ7) is set to "1"
when the sector erase command is issued. Then, after the sector erase timeout period is reached, the read
value is changed to "0". Once the sector erase timeout period is reached, the read value is "0" during the
execution of the automatic algorithm.
When the flag is read after the completion of the automatic algorithm, the read value is "1". The flash
memory returns to the read/reset state. After the completion of the automatic algorithm, "1" is actually read
as the erased data from the flash memory.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Sector Erase Suspend Operation
The data polling flag (DQ7) can be read by making read access to the sector to be erased in the flash
memory area during the suspension of a sector erase operation. Figure 42.6-6 shows the state transition of
the data polling flag (DQ7) at the suspending sector erase.
Figure 42.6-6 State Transition of Data Polling Flag (DQ7) at Suspending Sector Erase
DATA WRITE
SECTOR ERASE
SUSPEND
COMMAND
SECTOR ERASE
TIMEOUT PERIOD
DQ7= 1
SUSPENDING
SECTOR ERASE
DQ7= 1
SECTOR ERASE
SUSPEND
COMMAND
SECTOR ERASE
DQ7= 0
SECTOR ERASE
RESUME
COMMAND
READ
(NOT ERASE
TARGET SECTOR)
DQ7=DATA[7]
When the data polling flag (DQ7) is read during the suspension of a sector erase operation, its read value is
"1". The read address is the address of the sector to be erased in the flash memory area. When the sector
erase operation is resumed, the read value of the data polling flag (DQ7) is changed to "0".
If a sector that is not to be erased is read during the suspension of a sector erase operation, the read value
is bit 7 of the data at that address. The data written in the flash memory is read as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
42.6.3 Toggle Bit Flag (DQ6)
The toggle bit flag (DQ6) indicates, through its toggle operation, that the automatic algorithm is
currently being executed.
■ Data Write Operation
The toggle bit flag (DQ6) can be read by making read access to the flash memory area during the execution
of the automatic algorithm for data-write operation. Figure 42.6-7 shows the state transition of the toggle bit
flag (DQ6) at the data write.
Figure 42.6-7 State Transition of Toggle Bit Flag (DQ6) at Data Write
DATA WRITE
COMMAND
READ/RESET STATE
DQ6=DATA[6]
DATA WRITE
DQ6= TOGGLE
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ6= TOGGLE
The toggle bit flag (DQ6) performs a toggle operation through which it indicates "1" and "0" alternatively
every time it is read during the execution of the automatic algorithm. The read address is any address in the
flash memory area.
When the flag is read after the completion of the automatic algorithm, its read value is bit 6 of the data at that
address. The flash memory returns to the read/reset state. The data written in the flash memory is read as
normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Chip Erase/Sector Erase Operations
The toggle bit flag (DQ6) can be read by making read access to the sector that is to be erased in the flash
memory area during the execution of the automatic algorithm for a chip erase or sector erase operation.
Figure 42.6-8 shows the state transition of the toggle bit flag (DQ6) at the chip erase/sector erase.
Figure 42.6-8 State Transition of Toggle Bit Flag (DQ6) at Chip Erase/Sector Erase
CHIP ERASE/
SECTOR ERASE
COMMAND
CHIP ERASE/
SECTOR ERASE
DQ6= TOGGLE
READ/RESET STATE
DQ6=DATA[6]
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ6= TOGGLE
The toggle bit flag (DQ6) performs a toggle operation through which it indicates "1" and "0" alternatively
every time it is read during the execution of the automatic algorithm. The read address for the chip erase
operation is any address in the flash memory area. The read address for the sector erase operation is the
address of the sector to be erased in the flash memory area.
When the flag is read after the completion of the automatic algorithm, its read value is "1". The flash memory
returns to the read/reset state. After the completion of the automatic algorithm, "1" is actually read as the
erased data from the flash memory.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Sector Erase Suspend Operation
The toggle bit flag (DQ6) can be read by making read access to the sector that is to be erased in the flash
memory area during the suspension of a sector erase operation. Figure 42.6-9 shows the state transition of
the toggle bit flag (DQ6) at the suspending sector erase.
Figure 42.6-9 State Transition of Toggle Bit Flag (DQ6) at Suspending Sector Erase
DATA WRITE
SECTOR ERASE
SUSPEND
COMMAND
SUSPENDING
SECTOR ERASE
DQ6= 1
SECTOR ERASE
DQ6=TOGGLE
SECTOR ERASE
RESUME
COMMAND
READ
(NOT ERASE
TARGET SECTOR)
DQ6=DATA[6]
When the toggle bit flag (DQ6) is read during the suspension of a sector erase operation, its read value is
"1". The read address is the address of the sector to be erased in the flash memory area. When the sector
erase operation is resumed, the read value of the toggle bit flag (DQ6) performs a toggle operation.
When a sector that is not to be erased is read during the suspension of a sector erase operation, the read
value is bit 6 of the data at that address. The data written in the flash memory is read as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
42.6.4 Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) indicates that the execution of the automatic algorithm has
exceeded the time specified within the flash memory.
■ Data Write/Chip Erase/Sector Erase Operations
The time limit exceeded flag (DQ5) can be read by making read access to the flash memory area during the
execution of the automatic algorithm. Figure 42.6-10 shows the state transition of the timing limit exceeded
flag (DQ5).
Figure 42.6-10 State Transition of Timing Limit Exceeded Flag (DQ5)
COMMAND
EXECUTE
AUTOMATIC ALGORITHM
DQ5= 0
READ/RESET STATE
DQ5=DATA[5]
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ5= 1
If the specified time (required for the Data Write/Erase operation) has not yet been reached when the flag is
read during the execution of the automatic algorithm, the read value is "0". If the specified time has already
been exceeded, the read value is "1".
If the data polling flag (DQ7) or the toggle bit flag (DQ6) indicates that the automatic algorithm is currently
being executed when the timing limit exceeded flag (DQ5) becomes "1", the Data Write/Erase operation can
be determined as unsuccessful. In such cases, issue the reset command to the flash memory.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
42.6.5 Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) indicates the end of the sector erase timeout period.
■ Data Write Operation
The sector erase timer flag (DQ3) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for data-write operation. Figure 42.6-11 shows the state transition of the
sector erase timer flag (DQ3) at the data write.
Figure 42.6-11 State Transition of Sector Erase Timer Flag (DQ3) at Data Write
DATA WRITE
COMMAND
READ/RESET STATE
DQ3=DATA[3]
DATA WRITE
DQ3= 0
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ3= 0
When the sector erase timer flag (DQ3) is read during the execution of the automatic algorithm, its read
value is "0". The read address is any address in the flash memory area.
When the flag is read after the completion of the automatic algorithm, the read value is bit 3 of the data at
that address. The flash memory returns to the read/reset state. The data written in the flash memory is read
as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Chip Erase Operation
The sector erase timer flag (DQ3) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for chip erase operations. Figure 42.6-12 shows the state transition of
the sector erase timer flag (DQ3) at the chip erase.
Figure 42.6-12 State Transition of Sector Erase Timer Flag (DQ3) at Chip Erase
CHIP ERASE
COMMAND
READ/RESET STATE
CHIP ERASE
DQ3=DATA[3]
DQ3= 1
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ3= 1
When the sector erase timer flag (DQ3) is read during the execution of the automatic algorithm, its read
value is "1". The read address is any address in the flash memory area.
When the flag is read after the completion of the automatic algorithm, the read value is "1". The flash
memory returns to the read/reset state. The data erased from the flash memory is read as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Sector Erase Operation
The sector erase timer flag (DQ3) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for sector erase operation. Figure 42.6-13 shows the state transition of
the sector erase timer flag (DQ3) at the sector erase.
Figure 42.6-13 State Transition of Sector Erase Timer Flag (DQ3) at Sector Erase
SECTOR ERASE
COMMAND
SECTOR ERASE
TIMEOUT PERIOD
READ/RESET STATE
DQ3=DATA[3]
DQ3= 0
TIMEOUT PERIOD
END
RESET
COMMAND
NORMAL END
SECTOR ERASE
PERIOD
ABNORMAL STATE
DQ3= 1
DQ3= 1
TIMING LIMIT
EXCESS
When the sector erase command is issued, the read value of the sector erase timer flag (DQ3) is set to "0".
After that, when the sector erase timeout period is reached, the read value is changed to "1". After the sector
erase timeout period is reached, the read value is "1" during the execution of the automatic algorithm.
When the flag is read after the completion of the automatic algorithm, the read value is "1". The flash
memory returns to the read/reset state. The data erased from the flash memory is read as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Sector Erase Suspend Operation
The sector erase timer flag (DQ3) can be read by making read access to the sector that is to be erased in
the flash memory area during the suspension of a sector erase operation. Figure 42.6-14 shows the state
transition of the sector erase timer flag (DQ3) at the suspend sector erase.
Figure 42.6-14 State Transition of Sector Erase Timer Flag (DQ3) at Suspend Sector Erase
DATA WRITE
SECTOR ERASE
SUSPEND
COMMAND
SECTOR ERASE
TIMEOUT PERIOD
DQ3= 0
SUSPENDING
SECTOR ERASE
DQ3= 0
SECTOR ERASE
SUSPEND
COMMAND
SECTOR ERASE
DQ3= 1
SECTOR ERASE
RESUME
COMMAND
READ
(NOT ERASE
TARGET SECTOR)
DQ3=DATA[3]
When the sector erase timer flag (DQ3) is read during the suspension of a sector erase operation, its read
value is "0". The read address is the address of the sector to be erased in the flash memory area. When the
sector erase operation is resumed, the read value of the sector erase timer flag (DQ3) is changed to "1".
When the sector that is not to be erased is read during the suspension of a sector erase operation, the read
value is bit 3 of the data at that address. The data written in the flash memory is read as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
42.6.6 Toggle Bit 2 Flag (DQ2)
The toggle bit 2 flag (DQ2) indicates, through its toggle operation, the automatic algorithm is being executed and the sector whose contents are being erased.
■ Data Write Operation
The toggle bit 2 flag (DQ2) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for writing data. Figure 42.6-15 shows the state transition of the toggle
bit 2 flag (DQ2) at the data write.
Figure 42.6-15 State Transition of Toggle Bit 2 Flag (DQ2) at Data Write
DATA WRITE
COMMAND
READ/RESET STATE
DQ2=DATA[2]
DATA WRITE
DQ2= 1
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ2= 1
When the toggle bit 2 flag (DQ2) is read during the execution of the automatic algorithm, its read value is "1".
The read address is any address in the flash memory area.
When the flag is read after the completion of the automatic algorithm, the read value is bit 2 of the data at
that address. The flash memory returns to the read/reset state. The data written in the flash memory is read
as normal read data.
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Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Chip Erase/Sector Erase Operations
The toggle bit 2 flag (DQ2) can be read by making read access to the flash memory area during the
execution of the automatic algorithm for chip erase and sector erase operations. Figure 42.6-16 shows the
state transition of the toggle bit 2 flag (DQ2) at the chip erase/sector erase.
Figure 42.6-16 State Transition of Toggle Bit 2 Flag (DQ2) at Chip Erase/Sector Erase
CHIP ERASE/
SECTOR ERASE
COMMAND
CHIP ERASE/
SECTOR ERASE
DQ2=TOGGLE
READ/RESET STATE
DQ2=DATA[2]
NORMAL END
TIMING LIMIT
EXCESS
RESET
COMMAND
ABNORMAL STATE
DQ2=TOGGLE
If the same address is read more than once during the execution of the automatic algorithm, the toggle bit 2
flag (DQ2) performs a toggle operation through which it indicates "1" and "0" alternatively every time it is
read. The read address is any address in the flash memory area.
When the flag is read after the completion of the automatic algorithm, the read value is bit 2 of the data at
that address. The flash memory returns to the read/reset state. The data erased from the flash memory is
read as normal read data.
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35
Chapter 42 Flash Memory
42.6 Hardware Sequence Flag
MB91460N Series
■ Sector Erase Suspend Operation
The toggle bit 2 flag (DQ2) can be read by making read access to the sector that is to be erased in the flash
memory area during the suspension of a sector erase operation. Figure 42.6-17 shows the state transition of
the toggle bit 2 flag (DQ2) at the suspending sector erase.
Figure 42.6-17 State Transition of Toggle Bit 2 Flag (DQ2) at Suspending Sector Erase
DATA WRITE
SECTOR ERASE
SUSPEND
COMMAND
SUSPENDING
SECTOR ERASE
DQ2=TOGGLE
SECTOR ERASE
DQ2=TOGGLE
SECTOR ERASE
RESUME
COMMAND
READ
(NOT ERASE
TARGET SECTOR)
DQ2=DATA[2]
If the address of the sector to be erased is read more than once during the suspension of a sector erase
operation, the toggle bit 2 flag (DQ2) performs a toggle operation through which it indicates "1" and "0"
alternatively every time it is read. In this case, the read value of the toggle bit flag (DQ6) is "1". When the
sector erase operation is resumed, the read value of the toggle bit 2 flag (DQ2) performs a toggle operation.
When a sector that is not to be erased is read during the suspension of a sector erase operation, the read
value is bit 2 of the data at that address. The data written in the flash memory is read as normal read data.
When the data write command is issued during the suspension of a sector erase operation and a sector that
is not to be erased is read during the execution of the automatic algorithm, the read value of the toggle bit 2
flag (DQ2) is "1". In this case, the toggle bit flag (DQ6) performs a toggle operation.
36
FUJITSU MICROELECTRONICS LIMITED
CM71-10149-2ES
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
42.7 Explanation of Operations
This section explains the operations of the flash memory and how to use them.
42.7.1 Read Operation
Data can be read from the flash memory when it is in the read/reset state. No command needs
to be issued for the read operation. Just do a read access to read out a data from flash memory.
■ Read Operation
When the flash memory is in 32-bit CPU mode, data access from the flash memory and the execution of a
program on the flash memory are enabled. When the flash memory is in 16-bit CPU mode, however, only
data access from the flash memory is enabled.
The flash memory goes to the read/reset state when the power is turned on, the MCU is reset, the automatic
algorithm is completed, or the reset command is issued.
42.7.2 Resetting Flash Memory
The flash memory goes to the read/reset state when the reset command is issued to the flash
memory.
■ Resetting Flash Memory
If the timing limit exceeded flag (DQ5) indicates "1" because the Data Write/Erase operation has not been
completed within a specified time, it can be determined that an error has occurred. In such cases, issue the
reset command to the flash memory to put it back to the read/reset state.
CM71-10149-2ES
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37
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
42.7.3 Writing Data
A half-word data can be written by issuing the data write command to the flash memory.
■ Writing Data
The unit used for writing data is half word. Each time the data write command is issued, one half-word is
written. There is no restriction in the order of the address where a data is written. Data can also be written to
a different sector of the flash memory by changing the sector.
The flash memory can change a bit value from "1" to "0" or keep a bit value, through data write operations.
However, bit value "0" cannot be changed to "1". Written data can be overwritten. Table 42.7-1 shows the
example of writable bit patterns at data write.
Table 42.7-1 Example of Writable Bit Pattern at Data Write
Old data
Write data
Old data
Write data
1111111111111111B
0000000000000000B
1111111111000000B
1111111110000000B
1111111111111111B
1111111111111111B
1111111110000000B
1111101000000000B
1111111111111010B
1010111111111010B
1100101010101100B
0100101010101100B
0000000000010000B
0000000000000000B
1111111111111111B
1111111111101111B
■ Write Protection
The data write operation is only enabled to the sectors of the flash memory that are allowed for write
operations.
■ Procedure for Writing Data
Issue the data write command when the flash memory is in the read/reset state. Once the data write
command is issued, the flash memory performs the automatic algorithm to write data automatically.
After issuing the data write command to the flash memory, read the hardware sequence flag to check if the
automatic algorithm is completed. The data polling flag (DQ7) or the toggle bit flag (DQ6) can be used to
confirm if the data write operation is completed.
The timing limit exceeded flag (DQ5) can be checked to detect an unsuccessful data write operation. The
data polling flag (DQ7) may change almost at the same time as the timing limit exceeded flag (DQ5). Check
the data polling flag (DQ7) again after the timing limit exceeded flag (DQ5) indicates "1".
Similarly, the toggle bit flag (DQ6) may also stop its toggle operation almost at the same time as the timing
limit exceeded flag (DQ5). Check the toggle bit flag (DQ6) again after the timing limit exceeded flag (DQ5)
indicates "1".
Figure 42.7-1 shows the example of the flash memory data write procedure using the data polling flag (DQ7).
38
FUJITSU MICROELECTRONICS LIMITED
CM71-10149-2ES
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
Figure 42.7-1 Example of Flash Memory Data Write Procedure
Start
Issue data write command
Read hardware sequence flag
(DQ7, DQ5)
YES
DQ7=PD[7]?
NO
YES
DQ5= "0" ?
NO
Read hardware sequence flag
(DQ7)
NO
DQ7=PD[7]?
YES
All data finished ?
NO
YES
Write error
CM71-10149-2ES
End
PD[7] : Bit 7 of data specified by
data write command
FUJITSU MICROELECTRONICS LIMITED
39
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
42.7.4 Chip Erase Operation
The contents of all sectors can be erased by issuing the chip erase command to the flash memory.
■ Chip Erase Operation
The chip erase operation erases data from all of the sectors of the flash memory. When the contents of a
sector are erased, all bits of the sector are set to "1".
■ Write Protection
The chip erase operation is enabled by writing the chip erase command sequence to a sector of the flash
memory which is allowed for write operations.
The chip erase operation cannot be performed from a write-protected sector, even if the chip erase
command sequence is written to the sector. Once the chip erase operation is performed from a sector that is
allowed for write operations, the contents of all of the sectors including those write-protected sectors are
erased.
■ Procedure for Chip Erase Operation
Issue the chip erase command when the flash memory is in the read/reset state. Once the chip erase
command is issued, the flash memory performs the automatic algorithm to erase the contents of all sectors
automatically.
After issuing the chip erase command to the flash memory, read the hardware sequence flag to check if the
automatic algorithm is completed. The data polling flag (DQ7) or the toggle bit flag (DQ6) can be used to
confirm if the chip erase operation is completed.
The timing limit exceeded flag (DQ5) can be checked to detect an unsuccessful chip erase operation. The
data polling flag (DQ7) may change almost at the same time as the timing limit exceeded flag (DQ5). Check
the data polling flag (DQ7) again after the timing limit exceeded flag (DQ5) indicates "1".
Similarly, the toggle bit flag (DQ6) may also stop its toggle operation almost at the same time as the timing
limit exceeded flag (DQ5). Check the toggle bit flag (DQ6) again after the timing limit exceeded flag (DQ5)
indicates "1".
40
FUJITSU MICROELECTRONICS LIMITED
CM71-10149-2ES
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
Figure 42.7-2 shows the example of the flash memory chip erase procedure using the toggle bit flag (DQ6).
Figure 42.7-2 Example of Flash Memory Chip Erase Procedure
Start
Issue chip erase command
Read hardware sequence flag
(DQ6)
temp
DQ6
Read hardware sequence flag
(DQ6, DQ5)
YES
DQ6 = temp ?
NO (Toggle)
YES
DQ5 = "0" ?
NO
temp
DQ6
Read hardware sequence flag
(DQ6)
DQ6 = temp ?
NO (Toggle)
YES
Erase error
CM71-10149-2ES
End
temp : Temporary variable for
toggle operation detection
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41
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
42.7.5 Sector Erase Operation
The contents of a sector can be erased by issuing the sector erase command to the flash memory.
■ Sector Erase Operation
The sector erase operation erases the contents of specified sectors of the flash memory. One or more
sectors can be specified. Once the contents of the specified sector(s) are erased, all bits of these sectors are
set to "1".
■ Write Protection
The sector erase operation is enabled by writing the sector erase command sequence to a sector of the
flash memory which is allowed for write operations.
■ Procedure for Sector Erase Operation
Issue the sector erase command when the flash memory is in the read/reset state. Once the sector erase
command is issued, the flash memory executes the automatic algorithm to erase the contents of the
specified sector(s) automatically.
Once the sector erase command is issued, the flash memory starts the sector erase timeout period. The
minimum sector erase timeout period is 50μs. When erasing the contents of multiple sectors, specify such
sectors by writing the sector erase code within the sector erase timeout period. Write the sector erase code
to the sectors whose contents are to be erased.
The sector erase timeout period can be checked by the sector erase timer flag (DQ3) that is one of the
hardware sequence flag. When specifying multiple sectors, make sure that the sector erase timer flag (DQ3)
is "0" every time after writing an additional sector erase code. If the sector erase timer flag (DQ3) is "1", the
last sector erase code may not have been written within the sector erase timeout period.
If the sector erase timer flag (DQ3) changes to "1" while specifying a sector whose contents are to be
erased, stop the process of specifying sectors. Reissue the sector erase command later for sectors including
the last specified sector, after the automatic algorithm is completed.
After issuing the sector erase command and the sector erase code to the flash memory, read the hardware
sequence flag to check if the automatic algorithm is completed. The data polling flag (DQ7) or the toggle bit
flag (DQ6) can be used to confirm if the sector erase operation is completed.
In this series, the data polling flag (DQ7) become "1", when the sector erase command is issued. After that, it
is changed to "0", when the sector erase timeout period is reached. And once the automatic algorithm is
completed, it is changed to "1". To confirm that the sector erase operation is completed, check that the data
polling flag (DQ7) has changed to "1" → "0" → "1". Or, check that the data polling flag (DQ7) has changed
from "0" to "1" after the sector erase timer flag (DQ3) became "1".
The timing limit exceeded flag (DQ5) can be checked to detect an unsuccessful sector erase operation. The
data polling flag (DQ7) may change almost at the same time as the timing limit exceeded flag (DQ5). Check
the data polling flag (DQ7) again after the timing limit exceeded flag (DQ5) indicates "1".
Similarly, the toggle bit flag (DQ6) may also stop its toggle operation almost at the same time as the timing
limit exceeded flag (DQ5). Check the toggle bit flag (DQ6) again after the timing limit exceeded flag (DQ5)
indicates "1".
42
FUJITSU MICROELECTRONICS LIMITED
CM71-10149-2ES
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
Figure 42.7-3 shows the example of the flash memory sector erase procedure using the toggle bit flag (DQ6).
Figure 42.7-3 Example of Flash Memory Sector Erase Procedure
Start
Issue sector erase command
YES
Another erased sector ?
NO
Write sector erase code
Read hardware sequence flag 1
(DQ6_1)
Read hardware sequence flag
(DQ3)
Read hardware sequence flag 2
(DQ6_2, DQ5)
NO
DQ3 = "1" ?
YES
DQ6_1 = DQ6_2 ?
YES
FLAG
NO (Toggle)
"1"
NO
DQ5 = "1"
YES
Read hardware sequence flag 1
(DQ6_1)
FLAG : Flag that indicates
erased sector could not
be added for sector erase
time-out period.
Read hardware sequence flag 2
(DQ6_2)
NO
DQ6_1 = DQ6_2 ?
YES
FLAG = "1" ?
YES
NO
Erase error
CM71-10149-2ES
End
FUJITSU MICROELECTRONICS LIMITED
43
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
42.7.6 Sector Erase Suspend Operation
A sector erase operation can be suspended by issuing the sector erase suspend command to
the flash memory during the sector erase operation.
■ Sector Erase Suspend Operation
During the suspension of a sector erase operation, data can be read from sectors other than erase target
sectors. In addition, data can also be written to sectors other than erase target sectors, by issuing the data
write command to them.
■ Procedure for Sector Erase Suspend Operation
The sector erase suspend command is valid only during the execution of the automatic algorithm for sector
erase operations, including the sector erase timeout period. If the sector erase suspend command is issued
during the sector erase timeout period, the sector erase timeout period is terminated immediately in order to
suspend the sector erase operation.
When the sector erase suspend command is issued during a sector erase operation after the sector erase
timeout period is reached, it takes up to 20 μs for the sector erase operation to be suspended. Before issuing
the sector erase suspend command, wait for 20 μs or more to elapse after the sector erase command or the
sector erase resume command is issued.
The hardware sequence flag can be read by read access from erase target sectors, during the suspension of
a sector erase operation. During the suspension of the sector erase operation, the read value of the data
polling flag (DQ7) is "1", and the read value of the toggle bit flag (DQ6) is also "1". After issuing the sector
erase suspend command, make sure that the sector erase operation has been suspended.
Figure 42.7-4 shows the example of the flash memory suspending sector erase procedure using the toggle
bit flag (DQ6).
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CM71-10149-2ES
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
Figure 42.7-4 Example of Flash Memory Suspending Sector Erase Procedure
Start
Confirm elapse of 20 μs
NO
Elapse of 20 μs ?
YES
Issue sector erase
suspend command
Read hardware sequence flag
(DQ6)
temp
DQ6
Read hardware sequence flag
(DQ6)
DQ6 = temp ?
NO (Toggle)
YES
temp : Temporary variable for
toggle operation detection
Suspend sector erase
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45
Chapter 42 Flash Memory
42.7 Explanation of Operations
MB91460N Series
42.7.7 Sector Erase Resume Operation
A sector erase operation can be resumed by issuing the sector erase resume command to the
flash memory during the suspension of the sector erase operation.
■ Sector Erase Resume Operation
Once the sector erase operation is resumed, the automatic algorithm for sector erase operation restarts its
execution.
■ Procedure for Resuming Sector Erase Operation
Issue the sector erase resume command when the sector erase operation is being suspended and the
automatic algorithm for the data write command is not being executed. The flash memory resumes the
automatic algorithm for sector erase operation to erase the contents of the remaining sectors automatically.
After issuing the sector erase resume command to the flash memory, read the hardware sequence flag to
check if the automatic algorithm for sector erase operations has been resumed and completed. The
procedure to confirm the completion of the sector erase operation is the same as described in "42.7.5
Sector Erase Operation".
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CM71-10149-2ES
Chapter 42 Flash Memory
42.8 Flash Memory Mode
MB91460N Series
42.8 Flash Memory Mode
When flash memory mode is set, the built-in flash memory can be controlled via external pins.
The flash memory mode is used to perform the Data Write/Erase operations using a parallel
flash programmer.
■ Setting Flash Memory Mode
The device is switched to the flash memory mode when the signal level of the mode setting pins (MD2 to
MD0) is set and the MCU is rebooted. Table 42.8-1 shows the setting the mode setting pins for the flash
memory mode.
Table 42.8-1 Setting of Mode Setting Pins for Flash Memory Mode
Mode Setting Pins
Signal level
MD2
1 (high)
MD1
1 (high)
MD0
1 (high)
Mode
Flash Memory Mode
■ Correspondence between Flash Memory Mode Control Signal and External Pin
In flash memory mode, the MCU functions stop. The built-in flash memory is associated with external pins
via which the built-in flash memory can be controlled. The automatic algorithm of the flash memory is
activated via the external pins in order to Data Write/Erase operation. Table 42.8-2 shows the
correspondence between the flash memory mode control signal and the external pin.
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Chapter 42 Flash Memory
42.8 Flash Memory Mode
MB91460N Series
Table 42.8-2 Correspondence between Flash Memory Mode Control and External Pin
Pin function in
flash memory mode
Pin function during
MCU operation
Pin number
Corresponding CPU
mode function
Corresponding pin of
single flash memory *
-
INITX
40
INITX
-
FRSTX
P22_0
21
-
RESET
MD3
MD3
36
-
-
MD2
MD2
37
-
-
MD1
MD1
38
-
-
MD0
MD0
39
-
-
RY/BYX
P21_2
56
FMCS:RDY bit
RY/BY
BYTEX
P21_5
54
Fixed to "H" internally
BYTE
WEX
P22_3
24
WE
OEX
P22_2
23
Controlled by internal
control signal + interface circuit
CEX
P22_1
22
FA0
P17_3
47
FA1 to FA4
P29_0 to P29_3
2 to 5
A0 to A3
FA5 to FA8
P29_4 to P29_7
6 to 9
A4 to A7
FA9 to FA12
P17_4 to P17_7
46 to 43
A8 to A11
FA13 to FA16
P15_2, P15_3,
P24_4, P24_5
41, 42, 14, 15
A12 to A15
FA17, FA18
P24_6, P24_7
19, 20
A16, A17
D0 to D7
P20_0 to P20_2,
P20_4 to P20_6,
P15_0, P15_1
25 to 27,
28 to 30,
31, 32
D8 to D15
P24_0 to P24_3,
P14_2, P14_3,
P21_0, P21_1
10 to 13,
60, 59
58, 57
OE
CE
Internal address bus
Internal data bus
A-1
DQ0 to DQ7
DQ8 to DQ15
* : A stand alone flash memory product is MBM29LV400TC.
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CM71-10149-2ES
Chapter 42 Flash Memory
42.8 Flash Memory Mode
MB91460N Series
■ Sector Configuration for Flash Memory Mode
The sector configuration for flash memory mode is different from the sector configuration for CPU mode.
Table 42.8-3 shows the sector configuration in the flash memory mode.
Table 42.8-3 Sector Configuration in Flash Memory Mode
Address range
FA[18:0]
Sector
adrs+3
adrs+2
adrs+1
Address range in CPU mode (reference)
adrs+0
MB91F463NC
MB91F463NA/NB
7: FFFFH to
7: E000H
SA7 (8 Kbytes)
0014: FFFFH to
0014: E000H
0014: FFFFH to
0014: C004H
7: DFFFH to
7: C000H
SA6 (8 Kbytes)
0014: DFFFH to
0014: C000H
0014: FFFBH to
0014: C000H
7: BFFFH to
7: A000H
SA5 (8 Kbytes)
0014: BFFFH to
0014: A000H
0014: BFFFH to
0014: 8004H
7: 9FFFH to
7: 8000H
SA4 (8 Kbytes)
0014: 9FFFH to
0014: 8000H
0014: BFFBH to
0014: 8000H
7: 7FFFH to
7: 0000H
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
Reserved (8 Kbytes)
-
-
6: FFFFH to
4: 0000H
Reserved (64 Kbytes)
Reserved (64 Kbytes)
Reserved (64 Kbytes)
-
-
3: FFFFH to
3: 0000H
SA19 (64 Kbytes)
000F: FFFFH to
000F: 0000H
000F: FFFFH to
000E: 0004H
2: FFFFH to
2: 0000H
SA18 (64 Kbytes)
000E: FFFFH to
000E: 0000H
000F: FFFBH to
000E: 0000H
1: FFFFH to
1: 0000H
SA17 (64 Kbytes)
000D: FFFFH to
000D: 0000H
000D: FFFFH to
000C: 0004H
0: FFFFH to
0: 0000H
SA16 (64 Kbytes)
000C: FFFFH to
000C: 0000H
000D: FFFBH to
000C: 0000H
adrs : Address that is a multiple of 4 within the address range
(Note) The reserved area
CM71-10149-2ES
cannot be used.
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49
Chapter 42 Flash Memory
42.8 Flash Memory Mode
MB91460N Series
■ Address Conversion
A formula is used to calculate the address conversion from the CPU mode to the flash memory mode.
● In case of MB91F463NA/NB
The address conversion formula for MB91F463NA/NB is shown below. While "adrs" refers to the address in CPU
mode, "FA" refers to the address in flash memory mode.
SA4, SA6 (0014:8000H ≤ adrs ≤ 0014:FFFFH; adrs[2] = 0):
FA = adrs - adrs % 0000:4000H + (adrs % 0000:4000H) / 2 - (adrs / 2) % 4 + adrs % 4 - 000D:0000H
SA5, SA7 (0014:8000H ≤ adrs ≤ 0014:FFFFH; adrs[2] = 1):
FA = adrs - adrs % 0000:4000H + (adrs % 0000:4000H) / 2 - (adrs / 2) % 4 + adrs % 4 - 000C:E000H
SA16, SA18 (000C:0000H ≤ adrs ≤ 000F:FFFFH; adrs[2] = 0):
FA = adrs - adrs % 0002:0000H + (adrs % 0002:0000H) / 2 - (adrs / 2) % 4 + adrs % 4 - 000C:0000H
SA17, SA19 (000C:0000H ≤ adrs ≤ 000F:FFFFH; adrs[2] = 1):
FA = adrs - adrs % 0002:0000H + (adrs % 0002:0000H) / 2 - (adrs / 2) % 4 + adrs % 4 - 000B:0000H
Operator definitions in the formula are as follows:
/ : Integer division
% : Reminder operation
● In case of MB91F463NC
The address conversion formula for MB91F463NC is shown below. While "adrs" refers to the address in CPU mode,
"FA" refers to the address in flash memory mode.
SA4, SA5, SA6, SA7 (0014:8000H ≤ adrs ≤ 0014:FFFFH):
FA = adrs - 000D:0000H
SA16, SA17, SA18, SA19 (000C:0000H ≤ adrs ≤ 000F:FFFFH):
FA = adrs + 000C:0000H
Operator definitions in the formula are as follows:
/ : Integer division
% : Reminder operation
50
FUJITSU MICROELECTRONICS LIMITED
CM71-10149-2ES
Chapter 42 Flash Memory
42.9 Notes
MB91460N Series
42.9 Notes
This section explains the notes of the flash memory.
■ Notes
● Writing data to bits whose value is "0"
Bits whose value is "0" cannot be changed to "1" by writing data to them. If an attempt is made to write "1" to a bit to
which "0" is written as its value, the flash memory is locked and the automatic algorithm does not complete. In rare
cases, however, it may complete normally as if "1" has been written successfully.
When the flash memory is locked, the time limit is exceeded and the timing limit exceeded flag (DQ5) indicates "1".
This state represents incorrect use of the flash memory, rather than a failure in the flash memory. If the timing limit
exceeded flag (DQ5) indicates "1", issue the reset command to the flash memory.
● Different addresses between CPU mode and flash memory mode
The flash memory has different address maps and sector layouts for CPU mode and flash memory mode. For address
conversion, see the section "■ Address Conversion" in "42.8 Flash Memory Mode".
● Issuing a command to a protected sector for writing data
Write a command sequence to sectors of the flash memory area that are allowed for writing data. Write the command
sequence correctly. The flash memory may malfunction, if a command is issued to a write protected sector, written to
an improper address or written in an incorrect order.
● Chip erase operation
When the write-protected sectors and not write-protected sectors coexist, the contents of all of the sectors, including
the write-protected sectors, will be erased, if the chip erase command is issued to a not write-protected sector.
● Resetting the MCU during the execution of the automatic algorithm
If the MCU is reset during the execution of the automatic algorithm for data-write operation, the data at the address to
which the write operation is being performed cannot be guaranteed.
● Changing access mode
Access mode must be changed via a program on the ID-RAM. Copy a program that changes the access mode to the
ID-RAM, and then run it on the ID-RAM. If the 16-bit access enable bit (FMCS:RW16) is set to "1" during the
execution of the program on the flash memory, instruction fetch is disabled; therefore, the program will hang up.
CM71-10149-2ES
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51
Chapter 42 Flash Memory
42.9 Notes
MB91460N Series
● Continuous Access of Hardware Sequence Flag
Please do not continue the instruction that reads the hardware sequence flag to read toggle bit flag (DQ6) and toggle
bit 2 flag (DQ2) correctly. For example, the toggle operation of these flags cannot be correctly read by specify the
following instructions.
LD @R4, R0 ; R4 holds the address of flash sector
LD @R4, R1
To avoid this problem, insert the NOP instruction between the instructions that read the hardware sequence flag.
LD @R4, R0 ; R4 holds the address of flash sector
NOP
LD @R4, R1
This problem is not applied to data polling flag (DQ7), timing limit exceeded flag (DQ5), and sector erase timer flag
(DQ3). This problem is independent with the frequency of CPU clock (CLKB).
● Restrictions on the data polling flag (DQ7) during the sector erase operation
In this series, when the sector erase command is issued, the value of the data polling flag (DQ7) changes differently
from the original value of the automatic algorithm. In the original specification, the flag indicates "0" when the sector
erase command is issued, and it changes to "1" when the automatic algorithm is completed. In this series, however,
the flag indicates "1" when the sector erase command is issued, it changes to "0" when the sector erase timeout period
is reached, and then, it changes back to "1" when the automatic algorithm is completed. Figure 42.9-1 shows the
difference in the value of the data polling flag (DQ7) during the sector erase operation.
52
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CM71-10149-2ES
Chapter 42 Flash Memory
42.9 Notes
MB91460N Series
Figure 42.9-1 Difference in the Value of Data Polling Flag (DQ7) during the Sector Erase Operation
Command sequence
Sector erase code
Write the command
sequence for the
sector erase
DQ7
(Original specification)
DQ7
(This series)
DQ3
Activate
automatic
algorithm
CM71-10149-2ES
End of
sector erase
timeout period
FUJITSU MICROELECTRONICS LIMITED
Complete
automatic
algorithm
53
Chapter 42 Flash Memory
42.9 Notes
54
MB91460N Series
FUJITSU MICROELECTRONICS LIMITED
CM71-10149-2ES
Chapter 43 Flash Security
43.1 Overview
MB91460N Series
Chapter 43 Flash Security
This chapter explains the flash security.
43.1 Overview
Flash security configures write protection and read protection for the flash memory.
■ Write Protection
Write protection can be set for each sector of the flash memory. The write-protected sector cannot perform
the Data Write/Erase operation.
There are two levels of write protection: the "level at which protection is released only when MCU is
activated by the internal reset vector" and the "level at which protection is applied without exceptions". A
protection level is specified for all of the sectors together.
■ Read Protection
Read protection can be set. When the read protection is enabled, no content of the flash memory can be
read via external pins. The read protection is specified for all of the sectors together.
The read protection is fixed to one protection level: the "level at which protection is released only when it is
activated by the internal reset vector".
■ Updating Security Status
Flash security is set by the flash security vector. The flash security vector is 8-byte data allocated on the
flash memory.
At a setting initialization reset (INIT), the security vector is fetched to set the security status of the flash
security. The security vector can be re-fetched by register setting to update the security status.
Code : CM71-00503-2E
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Chapter 43 Flash Security
43.2 Flash Security Vector
MB91460N Series
43.2 Flash Security Vector
The flash security vector is data allocated on the flash memory in order to configure the flash
security.
■ Flash Security Vector
The flash security vector is used to configure the write protection, read protection and protection level. The
flash security vector is one of the security vectors allocated on the flash memory. Table 43.2-1 shows the
security vector of MB91F463NC. Table 43.2-2 shows the security vector of MB91F463NA/NB.
Table 43.2-1 Security Vector of MB91F463NC
Address
Vector name
Size
Sector
0014:800CH to 0014:800FH
Boot security vector 2 (BSV2)
Word
SA4
0014:8008H to 0014:800BH
Boot security vector 1 (BSV1)
Word
SA4
0014:8004H to 0014:8007H
Flash security vector 2 (FSV2)
Word
SA4
0014:8000H to 0014:8003H
Flash security vector 1 (FSV1)
Word
SA4
Table 43.2-2 Security Vector of MB91F463NA/NB
Address
Vector name
Size
Sector
0014:800CH to 0014:800FH
Boot security vector 2 (BSV2)
Word
SA5
0014:8008H to 0014:800BH
Flash security vector 2 (FSV2)
Word
SA4
0014:8004H to 0014:8007H
Boot security vector 1 (BSV1)
Word
SA5
0014:8000H to 0014:8003H
Flash security vector 1 (FSV1)
Word
SA4
In this series, the boot security vector is not used. The address for the boot security vector is a reserved
area; therefore, do not use it for any other purpose.
Specify the sector that contains the security vector as a write-protected sector. This prevents the security
vector from being rewritten accidentally.
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Chapter 43 Flash Security
43.2 Flash Security Vector
MB91460N Series
43.2.1 Flash Security Vector 1 (FSV1)
Flash security vector 1 (FSV1) sets the read protection, write protection, protection level as well
as individual write protection for each 8-Kbyte sector.
■ Flash Security Vector 1 (FSV1)
Figure 43.2-1 shows the bit configuration of flash security vector 1 (FSV1).
Figure 43.2-1 Bit Configuration of Flash Security Vector 1 (FSV1)
bit
FSV1
31
30
29
28
27
26
25
24
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
23
22
21
20
19
18
17
16
Reserved
Reserved
Reserved
Reserved
Reserved
D18
D17
D16
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
6
5
4
3
2
1
0
SA7
SA6
SA5
SA4
Reserved
Reserved
Reserved
Reserved
bit
FSV1
bit
FSV1
bit
FSV1
[bit31 to bit19] Reserved
These bits are reserved bits. Be sure to write "0" to them.
[bit18] D18 : Protection level setting
This bit sets the protection level for write protection.
D18
Protection level setting
1
Level at which protection is released only when MCU is activated by the internal reset vector
0
Level at which protection is applied without exceptions
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Chapter 43 Flash Security
43.2 Flash Security Vector
MB91460N Series
[bit17] D17 : Write protection setting
This bit sets write protection. Setting the bit to "1" enables individual write protection for each 64-Kbyte
sector and 8-Kbyte sector.
D17
Write protection setting
1
Protects the flash memory against write operation.
0
Does not protect the flash memory against write operation.
[bit16] D16 : Read protection setting
This bit sets read protection.
D16
Read protection setting
1
Protects the flash memory against read operation.
0
Does not protect the flash memory against read operation.
[bit15 to bit0] SAx : 8-Kbyte sector individual write protection
These bits set individual write protection for each 8-Kbyte sector. When write protection is set (FSV1:D17=1),
write protection is enabled only for the sectors which are specified as to be write-protected by the SAx bit.
SAx
8-Kbyte sector individual write protection
1
Does not specify the target sector as to be write-protected.
0
Specifies the target sector as to be write-protected.
Table 43.2-3 shows 8-Kbyte sector write protection target setting bits. Bits with no target sector are reserved
bits. Be sure to write "1" to the reserved bits.
Table 43.2-3 8-Kbyte Sector Write Protection Target Setting Bits
Bit in FSV1
Target sector
15 to 8
None
7
SA7
6
SA6
5
SA5
4
SA4
3 to 0
None
Note
Reserved bits
Individual write protection is available.
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Reserved bits
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Chapter 43 Flash Security
43.2 Flash Security Vector
MB91460N Series
43.2.2 Flash Security Vector 2 (FSV2)
Flash security vector 2 (FSV2) sets individual write protection for each 64-Kbyte sector.
■ Flash Security Vector 2 (FSV2)
Figure 43.2-2 shows the bit configuration of flash security vector 2 (FSV2).
Figure 43.2-2 Bit Configuration of Flash Security Vector 2 (FSV2)
bit
FSV2
31
30
29
28
27
26
25
24
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
23
22
21
20
19
18
17
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
SA19
SA18
SA17
SA16
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
bit
FSV2
bit
FSV2
bit
FSV2
[bit31 to bit0] SAx : 64-Kbyte sector individual write protection
These bits set individual write protection for each 64-Kbyte sector. When write protection is set
(FSV1:D17=1), write protection is enabled only for the sectors which are specified as to be write-protected
by the SAx bit.
SAx
64-Kbyte sector individual write protection
1
Does not specify the target sector as to be write-protected.
0
Specifies the target sector as to be write-protected.
Table 43.2-4 shows 64-Kbyte sector write protection target setting bits. Bits with no target sector are
reserved bits. Be sure to write "1" to the reserved bits.
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Chapter 43 Flash Security
43.2 Flash Security Vector
MB91460N Series
Table 43.2-4 64K-Kbyte Sector Write Protection Target Setting Bits
Bit in FSV2
Target sector
31 to 12
None
11
SA19
10
SA18
9
SA17
8
SA16
7 to 0
None
Note
Reserved bits
Individual write protection is available.
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Reserved bits
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Chapter 43 Flash Security
43.3 Registers
MB91460N Series
43.3 Registers
Flash security has control register.
■ Register of Flash Security
Table 43.3-1 shows the register of the flash security.
Table 43.3-1
Register of Flash Security
Mnemonic
Register name
Address
Size
FSCR0
Flash security control register
0000:7100H
Byte
43.3.1 Flash Security Control Register (FSCR0)
This register activates the sequence for re-fetching the security vector.
■ Flash Security Control Register (FSCR0)
Figure 43.3-1 shows the bit Configuration of flash security control register (FSCR0).
Figure 43.3-1 Bit Configuration of Flash Security Control Register (FSCR0)
bit
7
6
5
4
3
2
1
0
S7
S6
S5
S4
S3
S2
S1
S0
Bit attribute
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
RX,W
Initial value
X
X
X
X
X
X
X
X
FSCR0
Write to the flash security control register (FSCR0) by byte access. This series does not have a CRC check
function for the flash memory. The flash security control register (FSCR0) is a write-only register.
[bit7 to bit0] S[7:0] : Sequence activation
When byte data A5H and 5AH are written to these bits continuously, the sequence for re-fetching the flash
security vector is activated. The sequence is activated immediately after 5AH is written.
S[7:0]
A5H
CM71-10149-2ES
Sequence activation
5AH
Activation of the sequence for re-fetching the flash security vector
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Chapter 43 Flash Security
43.4 Configuring Flash Security
MB91460N Series
43.4 Configuring Flash Security
Write protection and read protection are configured by setting a value to the flash security vector
through data write operation to the flash memory.
■ Setting Write Protection
Set the write protection setting bit (FSV1:D17) to "1". The protection level can be selected by the protection
level setting bit (FSV1:D18). Table 43.4-1 shows combinations of the write protection and protection level.
Table 43.4-1
Combinations of Write Protection and Protection Level
Write protection setting bit
(FSV1:D17)
Protection level setting bit
(FSV1:D18)
Protection level (operation mode
in which write protection is enabled)
0
0
0
1
1
0
Flash memory mode
1
1
Activated by internal reset vector
Flash memory mode
⎯
Write protection can be set for each sector. The target sector becomes write-protected, when the individual
write protection setting bit is "0", the write protection setting bit (FSV1:D17) is "1", and the protection level is
matched. Table 43.4-2 shows write protection for each sector.
Table 43.4-2
Write Protection for Each Sector
Individual write protection
setting bit
(FSV1:SAx/FSV2:SAx)
Write protection
setting bit
(FSV1:D17)
Protection level
setting bit
(FSV1:D18)
0
1
Match
0
1
Mismatch
0
0
Match
0
0
Mismatch
1
1
Match
1
1
Mismatch
1
0
Match
1
0
Mismatch
Write protection for sector
Disables write operation
Enables write operation
■ Setting Read Protection
Set the read protection setting bit (FSV1:D16) to "1". Only when MCU is activated by the internal reset
vector, protection is released to enable the execution of a program on the flash memory and data read
operations. In flash memory mode, protection is not released; therefore, data cannot be read from the flash
memory.
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Chapter 43 Flash Security
43.5 Re-fetching Security Vector
MB91460N Series
■ Updating Security Status
At a setting initialization reset (INIT), the security vector is fetched to set the security status of the flash
security.
43.5 Re-fetching Security Vector
The security vector can be re-fetched by register operation to update the security status.
■ Re-fetching Security Vector
When byte data A5H and 5AH are written continuously to the sequence activation bits (S[7:0]) of the flash
security control register (FSCR0), the sequence for re-fetching the flash security vector is activated. There is
no time restriction on the duration from writing A5H until writing 5AH. If, however, data other than 5AH is
written after A5H is written, the same process must be repeated, starting from writing A5H again.
The flash security vector can be re-fetched when the contents of the security vector of the flash memory
have been updated so that the security status can also be updated.
■ Notes on Sequence Activation
Once the sequence for re-fetching the flash security vector is activated, the CPU cannot read from the flash
memory. During activating the sequence if the CPU tries to execute an instruction in the flash memory or
read data from it, the operation of the CPU is locked until the sequence is completed.
It is recommended to re-fetch the flash security vector using a program on the ID-RAM. Copy a program that
activates the sequence for re-fetching the vector to the ID-RAM, and then run it on the ID-RAM.
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Chapter 43 Flash Security
43.5 Re-fetching Security Vector
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INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
65
INDEX
Index
Numerics
F
16-bit
16-bit CPU Mode ............................................... 10
32-bit
32-bit CPU Mode ............................................... 10
Features
Features .............................................................. 1
Flash Memory
Correspondence between Flash Memory Mode
Control Signal and External Pin.............. 47
Flash Memory Area ............................................. 3
Flash Memory Control Register (FMCR) ............... 9
Flash Memory Control Status Register (FMCS) ...... 7
Flash Memory Registers ....................................... 6
Resetting Flash Memory ..................................... 37
Size and Products of Flash Memory....................... 1
Flash Memory Mode
Sector Configuration for Flash Memory Mode...... 49
Setting Flash Memory Mode ............................... 47
Flash Security
Flash Security Vector ......................................... 56
Flash Security Vector 1 (FSV1)........................... 57
Flash Security Vector 2 (FSV2)........................... 59
Register of Flash Security ................................... 61
Flash Security Control Register
Flash Security Control Register (FSCR0) ............. 61
Flash Security Vector
Flash Security Vector ......................................... 56
Flash Security Vector 1 (FSV1)........................... 57
Flash Security Vector 2 (FSV2)........................... 59
FMCR
Flash Memory Control Register (FMCR) ............... 9
FMCS
Flash Memory Control Status Register (FMCS) ...... 7
FSCR
Flash Security Control Register (FSCR0) ............. 61
FSV
Flash Security Vector 1 (FSV1)........................... 57
Flash Security Vector 2 (FSV2)........................... 59
A
Access Mode
Access Mode ..................................................... 10
Changing Access Mode ...................................... 10
Address
Address Conversion............................................ 50
B
Bit Configuration
Bit Configuration of Hardware Sequence Flag ...... 20
Block Diagram
Block Diagram..................................................... 2
C
Chip Erase
Chip Erase Command ......................................... 16
Chip Erase Operation.............................. 23, 31, 40
Chip Erase/Sector Erase Operations ............... 27, 35
Data Write/Chip Erase/Sector Erase Operations .... 29
Procedure for Chip Erase Operation ..................... 40
Command Sequence
Command Sequence ........................................... 11
Control Register
Flash Memory Control Register (FMCR)................ 9
Control Status Register
Flash Memory Control Status Register (FMCS) ...... 7
CPU Mode
16-bit CPU Mode ............................................... 10
32-bit CPU Mode ............................................... 10
D
Data Write
Data Write Command ......................................... 15
Data Write Operation........................ 22, 26, 30, 34
Data Write/Chip Erase/Sector Erase Operations .... 29
E
External Pin
Correspondence between Flash Memory Mode
Control Signal and External Pin .............. 47
66
H
Hardware
Bit Configuration of Hardware Sequence Flag ...... 20
Hardware Sequence Flag .................................... 20
Reading Hardware Sequence Flag ....................... 21
M
Mode Control Signal
Correspondence between Flash Memory Mode
Control Signal and External Pin.............. 47
INDEX
N
Notes
Notes ................................................................ 51
O
Operating Clock
Operating Clock................................................... 2
Overview
Overview ............................................................ 1
P
Protection
Read Protection ................................................. 55
Setting Read Protection ...................................... 62
Setting Write Protection...................................... 62
Write Protection................................................. 55
R
Read
Read Operation.................................................. 37
Read Protection ................................................. 55
Setting Read Protection ...................................... 62
Recapturing
Recapturing Security Vector ............................... 63
Register
Register of Flash Security ................................... 61
Registers
Flash Memory Registers ....................................... 6
Reset
Reset Command................................................. 14
Resuming Sector Erase
Procedure for Resuming Sector Erase Operation ... 46
Security Vector
Recapturing Security Vector ................................63
Sequence Activation
Notes on Sequence Activation .............................63
Sequence Flag
Bit Configuration of Hardware Sequence Flag.......20
Hardware Sequence Flag .....................................20
Reading Hardware Sequence Flag ........................21
V
Vector
Flash Security Vector..........................................56
Flash Security Vector 1 (FSV1) ...........................57
Flash Security Vector 2 (FSV2) ...........................59
Recapturing Security Vector ................................63
W
Write
Setting Write Protection ......................................62
Write Protection .................................................55
Write Protection
Write Protection .....................................38, 40, 42
Writing Data
Procedure for Writing Data..................................38
Writing Data ......................................................38
S
Sector Configuration
Sector Configuration ............................................ 4
Sector Configuration for Flash Memory Mode ...... 49
Sector Erase
Chip Erase/Sector Erase Operations ............... 27, 35
Data Write/Chip Erase/Sector Erase Operations .... 29
Procedure for Sector Erase Operation................... 42
Sector Erase Command....................................... 17
Sector Erase Operation ........................... 24, 32, 42
Sector Erase Resume
Sector Erase Resume Command .......................... 19
Sector Erase Resume Operation........................... 46
Sector Erase Suspend
Procedure for Sector Erase Suspend Operation ..... 44
Sector Erase Suspend Command ......................... 18
Sector Erase Suspend Operation .. 25, 28, 33, 36, 44
Security
Updating Security Status..................................... 55
67