UT0.6uCRH ASIC Family - Aeroflex Microelectronic Solutions

Semicustom Products
UT0.6CRCommercial RadHardTM
Gate Array Family
Data Sheet
May 2014
www.aeroflex.com/RadHardASIC
FEATURES
PRODUCT DESCRIPTION
 Multiple gate array sizes up to 500,000 usable equivalent
gates
The high-performance UT0.6CRH gate array family
features densities up to 500,000 equivalent gates and is available in MIL-PRF-38535 QML Q and V product assurance levels
and is radiation-tolerant.
 Toggle rates up to 150 MHz
 Advanced 0.60.5Leffradiation-tolerant silicon gate
CMOS processed in a commercial fab
The Commercial RadHardTM silicon is fabricated at ON Semiconductor using a minimally invasive processing module,
developed by Aeroflex, that enhances the total dose radiation
hardness of the field and gate oxides while maintaining circuit
density and reliability. In addition, for both greater transient
radiation-hardness and latchup immunity, the Aeroflex 0.6
process is built on epitaxial substrate wafers.
 Operating voltage of 5V and/or 3.3V
 QML Class Q & V compliant
 Designed specifically for high reliability applications
 Commercial RadHardTM for radiation-tolerant to 300
krads(Si) to meet space requirements and SEU-immune to
less than 2.0E-10 errors/bit-day
Developed using Aeroflex’s patented architectures, the
UT0.6CRH gate array family uses a highly efficient continuous column transistor architecture for the internal cell
construction. Combined with state-of-the-art placement and
routing tools, the utilization of available transistors is maximized using three levels of metal interconnect.
 JTAG (IEEE 1149.1) boundary-scan supported
 Low noise package technology for high speed circuits
 Design support using Mentor Graphics® and SynopsysTM
in VHDL or Verilog design languages on Sun® and Linux
workstations
The UT0.6CRH family of gate arrays is supported by an extensive cell library that includes SSI, MSI, and 54XX equivalent
functions, as well as configurable RAM and cores. Aeroflex’s
core library includes the following functions:
 Supports cold sparing for power down applications
 Supports voltage translation
 Intel 80C31® equivalent
- 5V bus to 3.3V bus
 Intel 80C196® equivalent
- 3.3V bus to 5V bus
 MIL-STD-1553 functions (BRCTM, RTI, RTMP)
 MIL-STD-1750 microprocessor
 RISC microcontroller
 Configurable RAM (SRAM, DPSRAM)
 USART (82C51)
 EDAC
 Aeroflex Gaisler
We offer Aeroflex Gaisler LEON3 and other IP which can be
reviewed at www.gaisler.com/CMS
1
Table 1. Gate Densities
DEVICE PART NUMBERS
UT06MRA010
UT06MRA025
EQUIVALENT USABLE GATES1 SIGNAL I/O2
10,000
192
25,000
192
POWER & GROUND PADS3
48
48
UT06MRA050
50,000
192
48
UT06MRA075
UT06MRA100
75,000
100,000
312
312
72
72
UT06MRA150
UT06MRA200
UT06MRA250
150,000
200,000
250,000
312
432
432
72
96
96
UT06MRA300
UT06MRA350
UT06MRA400
UT06MRA450
UT06MRA500
300,000
350,000
400,000
450,000
500,000
432
432
544
544
544
96
96
144
144
144
Notes:
1. Based on NAND2 equivalents. Actual usable gate count is design-dependent. Estimates reflect a mix of functions including RAM.
2. Includes five pins that may or may not be reserved for JTAG boundary-scan, depending on user requirements.
3. Reserved for dedicated VDD/VSS and VDDQ/VSSQ.
4.Aeroflex offers four die sizes: KD (280 mils), KC (407 mils), KB (535 mils), and KM (677 mils).
Low-noise Device and Package Solutions
The UT0.6CRH array family’s output drivers feature programmable slew rate control for minimizing noise and switching
transients. This feature allows the user to optimize edge characteristics to match system requirements. Separate on-chip power
and ground buses are provided for internal cells and output drivers
which further isolate internal design circuitry from switching
noise.
er and ground paths which minimize voltage drops during periods
of heavy switching. These isolated planes also help sustain supply
voltage during dose rate events, thus preventing rail span
collapse.
Flatpacks are available with up to 352 leads; PGAs are available
with up to 299 pins and LGAs to 472 pins. Aeroflex’s flatpacks
feature a non-conductive tie bar that helps maintain lead integrity
through test and handling operations. In addition to the packages
listed in Table 2, Aeroflex offers custom package development
and package tooling modification services for individual
requirements.
In addition, Aeroflex offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring
built-in isolated power and ground planes (see Table 2). These
planes provide lower overall resistance/inductance through pow-
2
Table 2. Packages
PACKAGE
TYPE/
LEADCOUNT1
025
050
84
X
X
132
X
X
172
X
196
208
075
100
150
200
250
300
350
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
400
450
500
550
600
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Flatpack
256
304
X
X
X
352
PGA2
299
X
X
X
X
LGA
472
Notes:
1. The number of device I/O pads available may be restricted by the selected package.
2. PGA packages have one additional non-connected index pin (i.e., 84 + 1 index pin = 85 total package pins for the 85 PGA).
Contact Aeroflex for specific package drawings.
3
Clock Driver Distribution
Aeroflex design tools provide methods for balanced clock distribution that maximize drive capability and minimize relative clock
skew between clocked devices.
Extensive Cell Library
The UT0.6CRH family of gate arrays is supported by an extensive cell library that includes SSI, MSI, and 54XX-equivalent
functions, as well as RAM and other library functions. User-selectable options for cell configurations include scan for all
register elements, as well as output drive strength. Aeroflex’s core
library includes the following functions:










Speed and Performance
Aeroflex specializes in high-performance circuits designed to operate in harsh military and radiation environments. Table 3
presents a sampling of typical cell delays.
Intel® 80C31 equivalent
Intel® 80C196 equivalent
MIL-STD-1553 functions (RTI)
MIL-STD-1750 microprocessor
Standard microprocessor peripheral functions
Configurable RAM (SRAM, DPSRAM)
RISC Microcontroller
USART (82C51)
EDAC
Aeroflx Gaisler IP
Note that the propagation delay for a CMOS device is a function
of its fanout loading, input slew, supply voltage, operating temperature, and processing radiation tolerance. In a radiation
environment, additional performance variances must be considered. The UT0.6CRHarray family simulation models account
for all of these effects to accurately determine circuit performance
for its particular set of use conditions.
Power Dissipation
Each internal gate or I/O driver has an average power consumption based on its switching frequency and capacitive loading.
Radiation-tolerant processes exhibit power dissipation that is typical of CMOS processes. For a rigorous power estimating
methodology, refer to the Aeroflex UT0.6CRH Design Manual
or consult with an Aeroflex Applications Engineer.
Refer to Aeroflex’s UT0.6CRH Design Manual for complete
cell listing and details.
I/O Buffers
The UT0.6CRH gate array family offers up to 544 signal I/O
locations (note: device signal I/O availability is affected by package selection and pinout.) The I/O cells can be configured by the
user to serve as input, output, bidirectional, three-state, or additional power and ground pads. Output drive options range from
2 to 12mA. To drive larger off-chip loads, output drivers may be
combined in parallel to provide additional drive up to 24mA.
Typical Power Dissipation
1.1W/[email protected]
Other I/O buffer features and options include:





Slew rate control
Pull-up and pull-down resistors
TTL, CMOS, and Schmitt levels
Cold sparing
Voltage translation
- 5V bus to 3.3V bus
- 3.3V bus to 5V bus
JTAG Boundary-Scan
The UT0.6CRH arrays provide for a test access port and boundary-scan that conforms to the IEEE Standard 1149.1 (JTAG).
Some of the benefits of this capability are:
 Easy test of complex assembled printed circuit
boards
 Gain access to and control of internal scan paths
 Initiation of Built-In Self Test
4
0.4W/[email protected]
Aeroflex’s HDL design system lets you easily access
Aeroflex’s RadHard capabilities.
ASIC DESIGN SOFTWARE
Using a combination of state-of-the-art third-party and
proprietary design tools, Aeroflex delivers the CAE support
and capability to handle complex, high-performance ASIC
designs from design concept through design verification and
test.
ADVANTAGES OF THE AEROFLEX HDL DESIGN
SYSTEM
•
Aeroflex’s flexible circuit creation methodology supports high
level design by providing UT0.6CRH libraries for Mentor
Graphics and Synopsys synthesis tools. Design verification is
performed in any VHDL or Verilog simulator or the Mentor
Graphics environment, using Aeroflex’s robust libraries.
Aeroflex also supports Automatic Test Program Generation to
improve design testing.
•
•
•
Aeroflex HDL DESIGN SYSTEM
Aeroflex offers a Hardware Description Language (HDL)
design system supporting VHDL and Verilog. Both the VHDL
and Verilog libraries provide sign-off quality models and
robust tools.
XDTsm (eXternal Design Translation)
Through Aeroflex’s XDT services, customers can convert an
existing non-Aeroflex design to Aeroflex’s processes. The
XDT tool is particularly useful for converting an FPGA to an
Aeroflex radiation-tolerant gate array. The XDT translation
tools convert industry standard netlist formats and vendor
libraries to Aeroflex formats and libraries. Industry standard
netlist formats supported by Aeroflex include:
High Level Design Activities
Synopsys
VSS/VCS
HDL Tool
Supplier
•
•
•
•
•
Mentor
ModelSim
Cadence
NSIM
Verilog XL
VCS
Aeroflex HDL
Design System
The Aeroflex HDL Design System gives you the freedom
to use tools from Synopsys, Mentor Graphics, Cadence,
and other vendors to help you synthesize and verify a
design.
Aeroflex’s Logic Rules Checker and Tester Rules Checker
allow you to verify partial or complete designs for
compliance with Aeroflex design rules.
Aeroflex HDL Design System accepts back-annotation of
timing information through SDF.
Your design stays entirely within the language in which
you started (VHDL or Verilog) preventing conversion
headaches.
Aeroflex
Gaisler IP
Completed
ASIC Design
Aeroflex HDL Design Flow
The VHDL libraries are VITAL 3.0 compliant, and the Verilog
libraries are OVI 1.0 compliant.With the library capabilities
Aeroflex provides, you can use High Level Design methods to
synthesize your design for simulation. Aeroflex also provides
tools to verify that your HDL design will result in working
ASIC devices.
5
VHDL
Verilog HDLTM
FPGA source files (Actel, Altera, Xilinx)
EDIF
Third-party netlists supported by Synopsys
ADVANTAGES OF THE AEROFLEX MENTOR DESIGN
SYSTEM
• Aeroflex customers have successfully used the Aeroflex
Mentor Graphics Design System for over a decade.
• Aeroflex’s Logic and Tester Rules Checker tools allow you
to verify partial or complete designs for compliance with
Aeroflex manufacturing practices and procedures.
• The Design System accepts pre-and post-layout timing
information to ensure your design results in devices that
meet your specifications.
• The Design System supports Leonardo, and database
transfer between Synopsys and Mentor.
• The Design System supports powerful Mentor Graphics
ATPG capabilities.
AEROFLEX MENTOR GRAPHICS DESIGN SYSTEM
The Aeroflex Mentor Graphics Design System software is fully
integrated into the Mentor Graphics design environment,
making it familiar and easy to use. Aeroflex tools support
Mentor functions such as cross-highlighting, graphical menus,
and design navigation.
Design Idea
Convert an
FPGA
Schematic
Entry
TOOLS SUPPORTED BY AEROFLEX
Translate an
External
Design
Synthesis
Aeroflex
Mentor Design
System
Aeroflex supports libraries for:
•
•
•
•
•
•
•
•
•
•
Aeroflex
Gaisler IP
Design
Manufacturing
Mentor Graphics
ModelSim
Tessent
Synopsys
Design Compiler
PrimeTime
Formality
TetraMax
VITAL-compliant VHDL Tools
OVI-compliant Verilog Tools
Aeroflex Mentor Graphics Design Flow
TRAINING AND SUPPORT
Aeroflex personnel conduct training classes tailored to meet
individual needs. These classes can address a wide mix of
engineering backgrounds and specific customer concerns.
Applications assistance is also available through all phases of
ASIC Design.
After creating a design in the Mentor Graphics environment,
you can easily verify the design for electrical rules compliance
with the Aeroflex Logic Rules Checker. Testability can be
verified with the Aeroflex Tester Rules Checker. Both of these
tools are fully integrated into the Mentor Graphics
Environment.
When you have completed all design activities, Aeroflex’s
Design Transfer tool captures all the required files and prepares
them for easy transfer to Aeroflex. Aeroflex uses this data to
convert your design into a packaged and tested device.
6
Table 3. Typical Cell Delays
CELL
OUTPUT
TRANSITION
Internal Gates
INV1, Inverter
INV4, Inverter 4X
NAND2, 2-Input NAND
NOR2, 2-Input NOR
DFF - CLK to Q
PROPAGATION
DELAY 1
VDD = 5.0V
VDD = 3.3V
HL
.15
.16
LH
.23
.29
HL
.06
.07
LH
.10
.16
HL
.19
.25
LH
.22
.33
HL
.16
.22
LH
.32
.45
HL
.81
1.12
LH
.76
1.06
HL
.75
1.05
LH
.61
.85
HL
3.85
2.15
LH
4.66
3.76
HL
5.58
5.49
LH
2.52
2.93
HL
2.42
LH
1.29
HL
.81
1.07
LH
1.16
1.18
HL
1.39
1.12
LH
1.16
1.30
Output Buffers
OC5050N4, CMOS
OT5050N4, TTL, 4mA
OT5050N12, TTL, 12mA
Input Buffers
IC5050, CMOS
IT5050, TTL
Note:
1. All specifications in ns (typical). Output load capacitance is 50pF. Fanout loading for input buffers and gates is the equivalent of two gate input loads.
7
PHYSICAL DESIGN
Using three layers of metal interconnect, Aeroflex achieves
optimized layouts that maximize speed of critical nets, overall
chip performance, and design density up to 500,000 equivalent
gates.
PARAMETER
Total dose
Test Capability
Aeroflex supports all phases of test development from test stimulus generation through high-speed production test. This
support includes ATPG, fault simulation, and fault grading. Scan
design options are available on all UT0.6CRH storage elements. Automatic test program development capabilities handle
large vector sets for use with Aeroflex’s Teradyne Tiger tester
supporting high-speed testing (up to 1.2GHz with pin
multiplexing).
RADIATION
TOLERANCE
1.0E5 rad(SiO2)
3.0E5 rad(SiO2)
Unparalleled Quality and Reliability
Aeroflex is dedicated to meeting the stringent performance requirements of aerospace and defense systems suppliers.
Aeroflex maintains the highest level of quality and reliability
through our Quality Management Program under MIL-PRF38535 and ISO-9001. In 1988, we were the first gate array manufacturer to achieve QPL certification and qualification of our
technology families. Our product assurance program has kept
pace with the demands of certification and qualification.
NOTES
1
2
Dose rate upset
1.0E8 rad(Si)/sec
3
Dose rate
survivability
1.0E11 rad(Si)/sec
4
SEU
<2.0E-10 errors per cell-day
Projected
neutron fluence
1.0E14 n/sq cm
Latchup
Latchup-immune over specified use conditions
4, 5
Notes:
1. Total dose Co-60 testing is in accordance with MIL-STD-883,
Method 1019. Data sheet electrical characteristics guaranteed to 1.0E5
rads(SiO2). All post-radiation values measured at 25C.
2. Total dose Co-60 testing is in accordance with MIL-STD-883,
Method 1019 at dose rates <1 rad(SiO2)/s.
3. Short pulse 20ns FWHM (full width, half maximum).
4. Is design dependent; SEU limit based on standard evaluation circuit at 4.5V
worst case condition.
5. SEU-hard flip-flop cell. Non-hard flip-flop typical is 4E-8.
Our quality management plan includes the following activities
and initiatives.






Quality improvement plan
Failure analysis program
SPC plan
Corrective action plan
Change control program
Standard Evaluation Circuit (SEC) and Technology Characterization Vehicle (TCV) assessment program
 Certification and qualification program
Because of numerous product variations permitted with customer specific designs, much of the reliability testing is performed
using a Standard Evaluation Circuit (SEC) and Technology
Characterization Vehicle (TCV). The TCV utilizes test structures to evaluate hot carrier aging, electromigration, and time
dependent test samples for reliability testing. Data from the wafer-level testing can provide rapid feedback to the fabrication
process, as well as establish the reliability performance of the
product before it is packaged and shipped.
Radiation Tolerance
Aeroflex incorporates radiation-tolerance techniques in process
design, design rules, array design, power distribution, and library element design. All key radiation-tolerance process
parameters are controlled and monitored using statistical methods and in-line testing.
8
ABSOLUTE MAXIMUM RATINGS 1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
-0.3 to 6.0V
VI/O
Voltage on any pin
-0.3V to VDD + 0.3
TSTG
Storage temperature
-65 to +150C
TJ
Maximum junction temperature
+175C
ILU
Latchup immunity
150mA
DC input current
10mA
Lead temperature (soldering 5 sec)
+300C
II
TLS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VDD
Positive supply voltage
3.0 to 5.5V
TC
Case temperature range
-55 to +125C
VIN
DC input voltage
0V to VDD
9
5V DC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V 10%; -55C < TC < +125C)1,2
SYMBOL
PARAMETER
CONDITION
VIL3
Low-level input voltage
TTL inputs
CMOS
VDD = 4.5V and 5.5V
VIH3
High-level input voltage
TTL inputs
CMOS
VDD = 4.5V and 5.5V
VT + 3
Schmitt Trigger, positive going threshold
VDD = 4.5V and 5.5V
MIN
TYP
MAX
UNIT
V
0.8
.3VDD
V
2.2
.7VDD
.2.4
V
7VDD
VT-3
Schmitt Trigger, negative going threshold
VDD = 4.5V and 5.5V
0.9
V
.3VDD
VH4
Schmitt Trigger, typical range of hysteresis
0.4
V
0.6
IIN
Input leakage current
TTL, CMOS, and Schmitt inputs
Inputs with pull-down resistors
Inputs with pull-down resistors
Inputs with pull-up resistors
Inputs with pull-up resistors
Cold Spare Inputs - Normal Mode
Cold Spare Inputs - Cold Spare Mode
VOL
Low-level output voltage
TTL 2.0mA buffer
TTL 4.0mA buffer
TTL 8.0mA buffer
TTL 12.0mA buffer *
CMOS outputs
CMOS outputs (optional)
CMOS outputs (cold spare)
VOH
High-level output voltage
TTL 2.0mA buffer
TTL 4.0mA buffer
TTL 8.0mA buffer
TTL 12.0mA buffer *
CMOS outputs
CMOS outputs (optional)
CMOS outputs (cold spare)
VDD = 5.5V
VIN = VDD and VSS
VIN = VDD
VIN = VSS
VIN = VSS
VIN = VDD
A
-1
+20
-5
-225
-5
1
+225
VIN = 0 to 5.5V
-5
+5
VDD = VSS = 0V
VIN = V and 5.5V
-5
+5
VDD = 4.5V
IOL = 2.0mA
IOL = 4.0mA
IOL= 8.0mA
IOL = 12.0mA
IOL = 1.0A
IOL = 100A
IOL = 100A
VDD = 4.5V
IOH = -2.0mA
IOH = -4.0mA
IOH = -8.0mA
IOH = -12.0mA
IOH = -1.0A
IOH = -100A
IOH = -100A
10
+5
-20
+5
V
0.4
0.4
0.4
0.4
0.05
0.25
0.25
V
2.4
2.4
2.4
2.4
VDD-0.05
VDD-0.35
VDD-0.35
SYMBOL
IOZ
PARAMETER
Three-state output leakage current
TTL 2.0mA buffer
TTL 4.0mA buffer, CMOS
TTL 8.0mA buffer
TTL 12.0mA buffer *
Cold Spare Inputs - normal mode
Cold Spare Inputs - cold spare mode
CONDITION
MIN
TYP
MAX
A
VDD = 5.5V
VO = 0V and 5.5V
VDD = VSS = 0
VDD = 0 to 5.5V
IOS4,5
Short-circuit output current
TTL 2.0mA buffer
TTL 4.0mA buffer, CMOS
TTL 8.0mA buffer
TTL 12.0mA buffer *
VO = 0V and 5.5V
IDDQ
Quiescent Supply Current6
VDD = 5.5V
Group A subgroups 1,3
200K gates
400K gates
500K gates
Group A subgroup 2
VDD = 5.5V
200K gates
400K gates
500K gates
-5
-10
-20
-30
-5
5
10
20
30
-5
-5
-5
-50
-100
-200
-300
50
100
200
300
mA
A
50
100
180
mA
1
2
3
Group A, subgroup 1
VDD = 5.5V
RHA Designator: M, D, P, L, R,F
200K gates
400K gates
500K gates
4
8
12
Input capacitance

23
COUT7
Output capacitance
TTL 2.0mA buffer
TTL 4.0mA buffer, CMOS
TTL 8.0mA buffer
TTL 12.0mA buffer *

CIO7
Bidirect I/O capacitance
TTL 4.0mA buffer, CMOS
TTL 8.0mA buffer
TTL 12.0mA buffer *

CIN7
UNIT
mA
pF
pF
22
26
26
26
pF
24
26
26
Notes:
* Contact Aeroflex prior to usage.
1. These devices are capable of being configured and support dual voltage: 3.3V and/or 5.0V bus, 2.5V core/3.3V or 5.0V core/5.0V bus. The supply voltage range
shall be specified in the AID.
2. Devices are supplied to this drawing will meet all levels M, D, P, L, R and F of irradiation. However, this device is only tested at the "R" and "F" level. Pre and Post
irradiation values are identical unless otherwise specified in Table 1. When performing post irradiation electrical measurements for any RHA level, TA = +25oC.
11
3. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%;
VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage
within the above specified range, but are guaranteed to VIH(min) and VIL(max).
4. Supplied as a design limit but not guaranteed or tested.
5. Not more than one output may be shorted at a time for maximum duration of one second.
6. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low.
7. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz @0V and a signal amplitude of <50mV RMS.
12
3V DC ELECTRICAL CHARACTERISTICS
(VDD = 3.3V .3V; -55C < TC < +125C)1,2
SYMBOL
PARAMETER
CONDITION
VIL3
Low-level input voltage
CMOS
VDD = 3.0V and 3.6V
VIH3
High-level input voltage
CMOS
VDD = 3.0V and 3.6V
VT + 3
Schmitt Trigger, positive going threshold
VDD = 3.0V and 3.6V
VT-3
Schmitt Trigger, negative going threshold
VDD = 3.0V and 3.6V
VH4
Schmitt Trigger, typical range of hysteresis
IIN
Input leakage current
TTL, CMOS, and Schmitt inputs
Inputs with pull-down resistors
Inputs with pull-down resistors
Inputs with pull-up resistors
Inputs with pull-up resistors
Cold Spare Inputs - normal mode
Cold Spare Inputs - cold spare mode
VOL
Low-level output voltage
TTL 2.0mA buffer
TTL 4.0mA buffer
TTL 8.0mA buffer
CMOS outputs
CMOS outputs (optional)
CMOS outputs (cold spare)
VOH
High-level output voltage
TTL 2.0mA buffer
TTL 4.0mA buffer, CMOS
TTL 8.0mA buffer
CMOS outputs
CMOS outputs (optional)
CMOS outputs (cold spare)
VDD = 3.6V
VIN = VDD and VSS
VIN = VDD
VIN = VSS
VIN = VSS
VIN = VDD
VIN = 0 to 3.6V
VDD = VSS = 0V
VIN = V and 3.6V
MIN
13
MAX
UNIT
0.8
.3VDD
V
2.4
.7VDD
V
.7VDD
V
.3VDD
V
.6
V
A
-1
+10
-5
-225
-5
-5
1
+225
+5
-10
-5
+5
VDD = 3.0V
IOL = 2.0mA
IOL= 4.0mA
IOL= 8.0mA
IOL = 1.0A
IOL = 100A
IOL = 100A
VDD = 3.0V
IOH = 2.0mA
IOH = 2.0mA
IOH = 8.0mA
IOH = 1.0A
IOH = 100A
IOH = 100A
TYP
+5
+5
V
0.4
0.4
0.4
0.05
0.25
0.25
V
2.4
2.4
2.4
VDD-0.05
VDD-0.35
VDD-0.35
SYMBOL
IOZ
PARAMETER
CONDITION
VO = VDD and VSS
-20
20
Cold Spare Inputs - normal mode
VDD = VSS = 0V
VO = 0V and 3.6V
-5
5
-5
5
-200
200
VO = VDD and VSS
IDDQ
Quiescent Supply Current6
VDD = 5.5V
Group A subgroups 1,3
200K gates
400K gates
500K gates
Group A subgroup 2
VDD = 5.5V
200K gates
400K gates
500K gates
UNIT
A
CMOS
Short-circuit output current 5
CMOS, LVTTL
CIO7
MAX
VDD = 3.6V
IOS4,5
COUT7
TYP
Three-state output leakage current
Cold Spare Inputs - cold spare mode
CIN7
MIN
mA
A
50
100
180
mA
1
2
3
Group A, subgroup 1
VDD = 5.5V
mA
RHA designator: M, D, P, L, R
200K gates
400K gates
500K gates
4
8
12
Input capacitance

23
pF
Output capacitance
CMOS

26
pF
Bidirect I/O capacitance
CMOS

26
pF
Notes:
* Contact Aeroflex prior to usage.
1. These devices are capable of being configured and support dual voltage: 3.3V and/or 5.0V bus, 2.5V core/3.3V or 5.0V core/5.0V bus. The supply voltage range
shall be specified in the AID.
2. Devices are supplied to this drawing will meet all levels M, D, P, L, R and F of irradiation. However, this device is only tested at the "R" and "F" level. Pre and Post
irradiation values are identical unless otherwise specified in Table 1. When performing post irradiation electrical measurements for any RHA level, TA = +25oC.
3. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%;
VIL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage
within the above specified range, but are guaranteed to VIH(min) and VIL(max).
4. Supplied as a design limit but not guaranteed or tested.
5. Not more than one output may be shorted at a time for maximum duration of one second.
6. All inputs with internal pull-ups should be left floating. All other inputs should be tied high or low.
7. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz @0V and a signal amplitude of <50mV RMS.
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Intel is a registered trademark of Intel Corporation
Mentor, Mentor Graphics, AutoLogic II, QuickSim II, QuickFault II, QuickHDL, QuickGrade II, FastScan, FlexTest and DFT Advisor are registered
trademarks of Mentor Graphics Corporation
Sun is a registered trademark of Sun Microsystems, Inc.
Verilog and Leapfrog are registered trademarks of Cadence Design Systems, Inc.
Synopsys, Design Compiler, Test Compiler Plus, VHDL Compiler, Verilog HDL Compiler, TestSim and VSS are trademarks of Synopsys, Inc.
Vantage is a trademark of Viewlogic
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
This product is controlled for export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Government is required prior to the export of this product from the United States.
www.aeroflex.com
[email protected]
Aeroflex Colorado Springs, Inc., reserves the right to
make changes to any products and services described
herein at any time without notice. Consult Aeroflex or an
authorized sales representative to verify that the
information in this data sheet is current before using this
product. Aeroflex does not assume any responsibility or
liability arising out of the application or use of any product
or service described herein, except as expressly agreed to
in writing by Aeroflex; nor does the purchase, lease, or
use of a product or service from Aeroflex convey a license
under any patent rights, copyrights, trademark rights, or
any other of the intellectual rights of Aeroflex or of third
parties.
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