AND8373/D 2 Switch-Forward Current Mode Converter Prepared by: Thierry Sutto ON Semiconductor http://onsemi.com APPLICATION NOTE Introduction This application note describes the design of 120−W, 125 kHz, two−switch forward current mode converter with the NCP1252 controller. It can viewed the practical implementation of the 2−switch forward converter example described in Ref. [1]. The NCP1252 controller offers everything to build cost−effective and reliable ac−dc switching power supplies implementing the forward converter: NCP1252 detects an output overload without relying on the auxiliary Vcc, a Brown−Out input offers protection against low input voltages and improves the converter safety. Finally a SOIC8 package saves PCB space and represents a solution of choice in cost sensitive projects. The power supply described here operates from a dc input voltage, as the forward converter is usually connected after a Power Factor Correction (PFC) stage. It generates a 12−V output at 10 A. The efficiency at full load is close to 90% at the nominal output of the PFC. A major advantage of the two−switch forward converter is that the power switches only block the supply voltage instead of twice the supply voltage as in the flyback or single−switch forward converter. Here after, the complete specification, of the two switch−forward converter is described: Table 1. Specification Description Input voltage Range Value Units 350−410 Vdc Output Voltage 12 Vdc Output Power 96 W Output Peak Power during 5 sec per 1 min 120 W Minimum Output Load Current(s) 0 Adc Number of Outputs 1 Nominal Output Voltage 12 ±5% Vdc Maximum Output Current 8 Adc Maximum Output Peak Current 10 Adc Output ripple 50 mV Maximum startup time <1 s < 100 mW 90 % 20, 50 & 100 % > 50 % Maximum Transient load step of the maximum output current 50 % Maximum Output drop voltage from Iout = 5 to 10 A in 5 ms 250 mV Standby Power Target Efficiency at full load @ Vin = 390 V dc Load Conditions for Efficiency Measurements (10%, 20%,..) Min Load Efficiency (Pout = 1.2 W) Power Supply Components Calculation Transformer The following equation extracted from the buck converter running in Continuous Current Mode (CCM), turns ratio will determine the turns ratio of the transformer: V out + h @ V bulk March, 2010 − Rev. 1 (eq. 1) Where: • Vout is the output voltage • h is the targeted efficiency • Vbulkmin is the minimum operating input voltage of the forward • DCmax is the maximum duty cycle that the NCP1252 can deliver • N is the turns ratio of the transformer Extracting the turns ratio from the previous equation, we obtain: N+ © Semiconductor Components Industries, LLC, 2010 min @ DC max @ N 1 V out + 0.9 hV bulk minDC max 12 350 0.45 + 0.085 (eq. 2) Publication Order Number: AND8373/D AND8373/D Given a DIout of 5 A, the above room temperature ESR components would, generate an output voltage undershoot/ overshoot of: Using this value in Equation 1, we can estimate the minimum duty cycle at high line by changing the bulk voltage parameter: DC min + V out hV bulk maxN + 0.9 12 410 (eq. 3) 0.085 DV out + DI outR ESR,max + 5 + 38.2% max sw Ǔ + 0.45 , is 125 k V bulkmin L mag + + 350 + 13.4 mH 0.1 0.94 10%I p_pk 0.45 DC max 125 k Fsw DI L v (eq. 4) 0.25 w 318 mF 1 10 k 318 m 50 m v 2.27 A 22 m (eq. 8) V out (1 * DC min)T sw L (eq. 9) (eq. 10) V L + out (1 * DC min)T sw w 12 (1 * 0.38) 1 w 26 mH 2.27 DI L 125 k If we consider a 10% drop in the inductor value at high temperature and current, let us adopt a 29 mH output inductor. But as this value is not standard part we will stick to a 27−mH normalized value. With the selected inductor value, we can calculate the rms current in the output capacitor: (eq. 5) IC The above case assumes an ESR much lower than the capacitor impedance at the crossover frequency: 1 R ESR v v 2pf cC out 2p v Using Equation 8, we can derive a minimum inductor value for L: The crossover frequency fc will arbitrarily be selected at 10 kHz. Beyond this value, the converter would pick−up switching noise and would require a more carefull layout. Below, the stringent dropout specification would lead to the selection of a larger output capacitor. Considering a voltage drop mostly dictated by fc, the output capacitance and the step load current, we can derive a first capacitor value by using a formula already encountered: 5 10 k R ESR,max DI L + LC Output Filter: DI out w 2pf cDV out 2p V ripple To obtain the output inductor value, we can write the buck ripple expression based on the off−time duration: Based on this assumption the transformer manufacturer offered the following transformer core: E30/15/7. C out w (eq. 7) which is acceptable given a specification of 250 mV. There is a rule of thumb to select an ESR capacitor equal to the half of the calculated value with Equation 6. This rule will take into account the process variation of the capacitor plus some margin for a startup operation of the power supply at very low ambient temperature. The final check will include the circulating rms current. However, given the nonpulsating nature of the buck output, we do not expect this current to be that high. Considering the output power level and the selected capacitor, we can consider the total ripple voltage contributed by the ESR term alone. Thus, if we adopt an ESR of 22 mW (approximate value at 0°C), the maximum peak to peak output ripple current must be lower than: To ensure enough primary magnetizing current to properly reset the core (drive the stray capacitance and allow the voltage across the winding to reverse), one must usually reduce the primary inductance from the core’s ungapped value to one that will cause an adequate magnetizing current. A popular rule of thumb as to make the magnetizing current around 10% of the primary current. Since the primary current is 0.94 A peak (the calculation of this peak current is given on the following paragraph), we will let the magnetizing current rise to 0.1 A. The desired primary inductance, then, with a primary voltage of 350 Vdc and a pulse duration of 3.6 ms ǒDCF 28.5 m + 142 mV out ,rms + I out 1 * DC min Ǹ12t L (eq. 11) + 10 1 * 0.38 + 1.06 A Ǹ12 2.813 Where: v 50 mW (eq. 6) tL + L out Vout Iout We must also select a capacitor whose worst case ESR remains below the capacitor impedance at the crossover frequency, in order to limits its contribution to the transient output drop. We are going to parallel two 1000 mF FM capacitors from Panasonic. @ 1 27 m + 12 10 Fsw 1 125 k + 2.813 (eq. 12) Given the equivalent capacitor current capability (5.36 A), there is no problem here. The secondary side peak current will be: I s_pk + I out ) DI L + 10 ) 2.27 + 11.13 A 2 2 C = 2000 mF, FM series @ 16 V IC,rms = 5.36 A (2*2.38 A) @ TA = +105°C On the primary side, this current reflects to: RESR,low = 8.5 mW (19 mW/2) @ TA = +20°C I p_pk + I s_pkN ratio + 11.13 RESR,high = 28.5 mW (57 mW/2) @ TA = −10°C And the valley reaches ǒ I p_valley + I out * http://onsemi.com 2 Ǔ ǒ Ǔ DI L N ratio + 10 * 2.27 2 2 (eq. 13) 0.085 + 0.946 A (eq. 14) 0.085 + 0.75 A (eq. 15) AND8373/D Based on the following Equation 16, we are able to calculate the rms current of a pulsating waveform with linear current (see Figure 1): I rms + I ǸDC Ǹ1 ) 13 ǒDI2IǓ (eq. 16) I(t) DIL I t T DCT 0 Figure 1. Pulsating Waveform with Linear Ripple Current This waveform exactly despits the current we have with a forward converter on the primary or secondary side of the tranformer. When this current is measured on the primary side, DI represents the reflected secondary−side ripple summed with the magnetizing current. Thus if we would like to accurately I p,rms,10% + I p,rms,10% + Ǹ ǒ 0.45 (1.1 Ǹ calculate the primary rms current, the magnetizing current should be added to the Ip_pk calculated with Equation 14. The magnetizing inductance has been previously calculated (Equation 4) with 10% of the primary peak current. Therefore the primary rms current can be written has followed: ǒ DC max (1.1 @ I p_pk) 2 * 1.1 @ I p_pkDI LN ) 0.946) 2 * 1.1 0.946 Where: • DCmax is the maximum duty cycle that the NCP1252 can deliver • Ip_pk is the peak current calculated by Equation 14. • ΔIL is the maximum output peak to peak current ripple • N is the turns ratio of the transformer The mosfets are selected based on the maximum input voltage and a derating factor kM of 0.85. If we choose 500 V devices (in a two−switch forward converter, the transistor stress is limited to the input voltage), the maximum high−voltage rail must be limited to 0.85 + 425 V 0.085 ) (2.27 Ǔ (eq. 17) Ǔ 0.085) 2 + 0.63 A 3 If the PFC does not include skip cycle in light−load operation, chances are that its output voltage will reach the overvoltage protection (OVP) level. The converter thus enters a kind of autorecovery hiccup mode. It is therefore important to check that one respects Equation 18 despite the OVP detection. The FDP16N50 has been selected for this application. Its specification are as follows: • Package TO220 • BVDSS = 500 V • RDS(on) = 0.434 W at Tj = 110°C (RDS(on) = 0.31 W @ Tj = 25°C multiplied by 1.4: RDS(on) derating factor for 110°C) • QG = 45 nC • QGD = 14 nC Thanks to Equation 17, we can estimate its conduction losses as Mosfet Selection V bulk,max + BV DSSk M + 500 2.27 (DI LN) 2 3 (eq. 18) P cond + I p,rms,10% 2 R DS(on) @ T J + 110 oC + 0.632 2 As we are running a 2−switch forward application, the voltage presents on each power switch at the turn−on is equal to the half of the bulk voltage: the two following figures 0.434 + 173 mW (eq. 19) illustrate the 2−switch forward arrangement and the simulated voltage present on both power switches. http://onsemi.com 3 AND8373/D Bulk M1 DRV_hi VM1(t) D3 Lout D1 D2 DRV_lo C1 D4 M2 Vout VM2(t) Figure 2. 2−switch Forward Arrangement 400V Turn ON VDS of the power mosfets 300V 200V Turn OFF 100V 0V V(VBULK,Q5:c) 750mA Power mosfets current 500mA 250mA 0A SEL>> 860.0us −I(RSENSE2) 870.0us Time 878.1us Figure 3. Power Mosfet Curves: VDS(t) and ID(t) of the Both Power Mosfets http://onsemi.com 4 AND8373/D At the turn−on the power losses can be expressed as follow: Dt V bulk VDS(t) 2 ID(t) Ip_valley PSW,on Losses t Figure 4. Turn−on Losses (PSW,on) The average power losses at the switch on is a triangle area, the exact calculation can be done via the following integral calculation: Where the overlap (Δt) is estimated via the following equation: Dt + Dt P SW,on + F sw ŕ I (t)V D 0 + P SW,on + I p_valley Vbulk 6 2 DS(t)dt Dt I p_valleyV bulkDt 12 P SW,on + I p_valleyV bulk,maxDt 12 0.75 410 12 F sw 46.7 n (eq. 22) This overlap estimation does not take into account that the driver of the NCP1252 is a CMOS type, in that case the output driver will not deliver a constant current. Nevertheless the estimation is not so wrong. This overlap is true for a bipolar driver stage that it delivers a constant current. As we have 2 power mosfets with our application the total switch−on losses will the double of the losses from Equation 21: 358 mW. Experimental measurement: (eq. 20) F sw F sw Based on the previous equation we are able to estimate the losses at each power mosfet switch on: P SW,on + Q GD 14 n + + 46.7 ns 0.300 I DRV_pk (eq. 21) 125 k + 149 mW ID(t) 500 mA/div VDS(t) 100 V/div P(t) = ID(t) VDS(t) 30 W/div Time 20 ns/div Figure 5. Switching Losses During the Turn On of the LOW Side Mosfet http://onsemi.com 5 AND8373/D ID(t) 500 mA/div VDS(t) 100 V/div P(t) = ID(t) VDS(t) 30 W/div Time 20 ns/div Figure 6. Switching losses during the turn on of the HIGH side mosfet losses have not been well estimated. This is probably due to the wrong estimation of the driver current capability (IDRV_pk): we took the hypothesis that the driver is able to deliver a constant current as we have with a bipolar output stage (UC384X like). But as the NCP1252’s output driver stage is based on the CMOS technology, the current is varying with the voltage on the power mosfet gate, thus it is really difficult to estimate accurately the overlap. As the losses of the power MOSFET in a 2−switch forward are very low, the error introduce in these estimations does not impact to much the heat sink calculation. The losses at the turn off can be calculated using the similar method: but now the peak current is at its max value. The drain−to−source voltage of the power switch is close to zero and switches to Vbulk. Figures 5 and 6 represent the power losses of the power mosfets (high and low side mosfet). From these figures we can note that the drain to source voltage on the low and high side mosfet is not at the half of bulk voltage as expected from the theory and the simulation result. Drain to source power mosfet voltage is not equal to the half of the bulk voltage due to the parasitic element from the transformer and the power mosfet. The low side power mosfet voltage is equal to 150 V and 240 V for the high side one. Thus the measured switch−on losses are the following: • High side switch on losses: 386 mW • Low side switch on losses: 155 mW If we compare these experimental results with the theory from Equation 21 where the switch on losses has been estimated to 179 mW per switch, we can conclude that the Dt VDS(t) Ip_pk Vbulk PSW,off Losses ID(t) t Figure 7. Turn−off Losses (PSW,off) Based on the equation used for the switch on losses, we are able to estimate the losses at each power mosfet: P SW,off + I p_pkV bulk,maxDt 6 F sw + 0.95 410 6 40 n 125 k + 324 mW (eq. 23) The overlap (Δt) is estimated via the following equation: Dt + Q GD 14 n + + 40 ns 0.350 I DRV_pk http://onsemi.com 6 (eq. 24) AND8373/D We are now able to estimate the overall losses on each power mosfet: P losses + P SW,on ) P cond ) P SW,off + 0.149 ) 0.173 ) 0.324 P losses + 646 mW Tj Rqj−c Where: • Switch−on losses: PSW,on = 149 mW • Conduction losses: Pcond = 173 mW • Switch−off losses: PSW,off = 324 mW Once we have the total dissipation budget per MOSFET, a heatsink can be calculated. (eq. 25) Tc Rqc−hs Rqhs−a Ths Ta Plosses Figure 8. Thermal path between the power mosfet and the heat sink Where: • Tj is the junction temperature of the power mosfet • Tc is the case temperature of the power mosfet • Ths is the heat sink temperature • Ta is the ambient temperature • Rθj−c is the thermal resistance between the junction and the case of the power mosfet • Rθc−hs is the thermal resistance between the case of the power mosfet and the heat sink • Rθhs−a is the thermal resistance between the heat sink and the ambient temperature. The following condition has to be checked to prevent any over heating of the power mosfet during worst case operation: T jmax * T ambmax u P losses ȍ Rq As the magnetizing and demagnetizing voltage are similar (Vbulk, thanks to the 2−switch forward structure); both on and reset times are equal. t reset + I mag,pk The average current can now be derived in a snapshot: I mag_avg + + + (eq. 26) Or it can be written as follow: R qhsa t T jmax * T ambmax P losses (eq. 27) Thus the thermal resistance of the heat sink should be lower than 67.4°C/W. A KL194/25.4/SW from Seifert (ref.[2]) has been selected (14°C/W). Diodes Selection PIV + The choice of the primary freewheeling diodes depends on the transformer magnetizing inductor. The magnetizing peak current can be calculated via the following equation: V bulk,min DC max + 350 L mag F sw 13.4 m ǒ ǒ 2 Fsw Ǔ DCmax ) t reset I mag_pk Fsw 2 Fsw 0.45 ) 3.6 m 125 k Ǔ (eq. 30) 94 m 2 125 k Diode such as the MUR160 accommodates the demagnetization task easily. Usually, in off−line application as the magnetizing current remains low any 1 A high voltage diode (500 or 600 V) can do the job. Let us now take care of the secondary diodes. In the forward converter, both secondary−side diodes sustain a similar peak inverse voltage (PIV). Given a turns ratio of 0.085 and the diode’s derating factor kD, the diodes have to sustain the following PIV: R qhsa t 67.4 oCńW I mag_pk + (t on ) t reset)I mag_pk I mag_avg + 42.3 mA * ǒR qjc ) R qchsǓ t 110 * 65 * (1 ) 1.2) 0.646 L mag 13.4 m + 94 m + 3.6 ms (eq. 29) 350 V bulkmin NV bulkmax + 0.085 410 + 58 V (eq. 31) 0.60 kD Thanks to the low PIV value, we are able to select the following Schottky diode reference: MBRB30H60CT. This diode (30 A, 60 V in a TO−220) case features a maximum drop of 0.5 V at 125°C (see Figure 9) (eq. 28) 45% + 94 mA 125 k http://onsemi.com 7 AND8373/D On average these diodes would dissipate around 5.3 W or 4.4% of the total output power. In order to improve the efficiency it can be interesting to implement a synchronous rectification to replace them. For these diodes, we can re−use Equation 27 to calculate the required heat sink. IF, INSTANTANEOUS FORWARD CURRENT (A) 100 TJ = 125°C 10 TJ = 25°C 1 0.1 R qhs−a t t 125 * 65 * (2 ) 1.2) 5.33 Vf = 0.5 V @ 10 A & TJ = 125°C 0 0.2 0.4 0.6 Thus the thermal resistance of the heat sink should be lower than 8°C/W. For the demonstration board, the following heat sink has been selected KL195/25.4/SW from Seifert (ref.[2]). It provides a low thermal resistance of 6.2°C/W. 1.2 VF, INSTANTANEOUS FORWARD VOLTAGE (V) Figure 9. MBRB30H60CT, Maximum Forward Voltage versus Instaneous Current NCP1252 Component Selection The series diode would then dissipate the following power in worst case conditions (Low line and maximum duty cycle). Switching Frequency Selection A resistor connected between the Rt pin and the ground precisely sets the switching frequency between 50 kHz and a maximum of 500 kHz. The following curve helps to select the resistor according the selected switching frequency. (eq. 32) P d_on + V fI outDC max + 0.5 10 0.45 + 2.25 W The freewheeling diode would dissipate slightly more as it conducts during the off time: P d_off + V fI out(1 * DC min) 10 (eq. 33) (1 * 0.39) + 3.05 W Switching frequency, Fsw (kHz) + 0.5 (eq. 34) R qhs−a t 8.06 oCńW 1.0 0.8 T Jmax * T AMBmax * ǒR qj−c ) R qc−hsǓ P losses Switching frequency versus Rt resistor 500 450 400 350 300 250 200 150 100 50 0 0 20 40 60 Rt resistor (kOhm) 80 100 Figure 10. Switching Frequency Selection The following equation could also be used to calculate the resistor value according to the switching frequency selection: Rt + 1.95 10 9V R F sw t If we select a 33 kW resistor, this will yield: F sw + 10 9 125 k 10 9V R Rt t + 1.95 10 9 33 k (eq. 36) 2.2 + 130 kHz The measurement on the final board with a resistor equal to 33 kW gives us 130 kHz for the switching frequency. This oscillator resistor will be laid out as close as possible to the Rt pin (pin #4) of the NCP1252 and its ground (pin #5). As these pins are really close together, it will be not so difficult to take into account this requirement. The robustness of the controller against electrical noise will be improved. (eq. 35) Where: • VRt is the internal voltage reference present on the Rt pin and equal to 2.2 V. If we assume a switching frequency of 125 kHz, R t + 1.95 1.95 2.2 + 34.3 kW http://onsemi.com 8 AND8373/D Sense Resistor measurement and it will improve the robustness of the power supply. Nevertheless this time constant should not be too large compared to the switching period of the controller. It is usually recommended to select a 150−300−ns time constant for the current sense filter network. The NCP1252 provides an internal ramp compensation appearing on the CS pin. The resistor of the RC filter will play a double function: ramp compensation and time constant for filtering. Thus the ramp compensation will fix the resistor value of the RC filter and then the capacitor will be adjusted to respect the time constant previously defined. One of the following chapters describes how to calculate the ramp compensation resistor. The NCP1252 featuring a maximum peak current to 1 V, the sense resistor is computed via the following expression, where a 20% margin appears on the primary peak current (10% for the magnetizing current and 10% for general margin): R sense + F CS + 1.2 1.2I p_pk 1 + 884 mW (eq. 37) 0.946 The power dissipation of the sense resistor with a 20% margin on the primary peak current amounts to: PR sense + I p,rms,20% 2R sense + 0.695 2 (eq. 38) 0.884 + 427 mW Where: • Ip,rms,20% is the rms current of the primary peak current with 20% margin on the peak current As we are using 1206 resistor type sizes with a limited power dissipation of 250 mW, we have to place 2 resistors in parallel in order to fit the authorized power capability. Thus we select 2 resistors of 1.5 W. The new power dissipation will be 362 mW for both resistors and 180 mW for each one. Despite the presence of a Leading Edge Blanking (LEB = 130 ns), it is recommended to insert between the sense resistor and the CS pin of the controller a small RC filter in order to remove any parasitic noise from the application. This small RC network will “clean” the current sense Brown−out By monitoring the level on BO pin, the NCP1252 protects the forward converter against low input voltage conditions. When the BO pin level falls below the VBO level, the controllers stops pulsing until the input level goes back to normal and resumes the operation via a new soft start sequence. The brown−out comparator features a fixed voltage reference level (VBO). The hysteresis is implemented by using the internal current connected between the BO pin and the ground when the BO pin is below the internal voltage reference (VBO). S Q Q Vbulk RB O u p R BO − Grand Re se t + shutdown BOK RB Olo VBO UVLO reset IBO Figure 11. BO Pin Setup When BO pin voltage is below VBO (internal voltage reference), the internal current source (IBO) is activated. The following equation can be written: The following equations show how to calculate the resistors for BO pin. First of all, select the bulk voltage value at which the controller must start switching (Vbulkon) and the bulk voltage for shutdown (Vbulkoff) the controller. Where: • Vbulkon = 370 V • Vbulkoff = 350 V • VBO = 1 V (fixed internal voltage reference) • IBO = 10 mA (fixed internal current source) ǒ V bulkON + R BOup I BO ) Ǔ V BO ) V BO R BOlo (eq. 39) When BO pin voltage is higher than VBO, the internal current source is now disabled. The following equation can be written: V BO + http://onsemi.com 9 V bulkoffR BOlo R BOlo ) R BOup (eq. 40) AND8373/D From Equation 40 RBOup can be extracted: R BOup + ǒ Ǔ V bulkoff * V BO R BOlo V BO We selected the following values for the brown out resistor divider: • RBOlo = 5.1 KW + 680 W • RBOup = 1 MW + 1 MW (eq. 41) Equation 41 is substituted in Equation 39 and solved for RBOlo, yields: R BOlo + ǒ Ǔ V BO V bulkon * V BO *1 I BO V bulkoff * V BO Soft Start The soft start of the NCP1252 controls the peak current of the forward converter during the startup sequence: this prevent any over stress on the power components (primary mosfet, secondary diode and magnetic component like transformer and inductor) during this critical phase and it reduces the output overshoot. The soft start pin provides a current source connected to an internal voltage reference. Thus a capacitor connected to this current source generates a linear voltage slope that controlling the peak current of the power supply via the current sense resistor. The SS pin voltage is divided by 4 to scale down the SS pin voltage to a compatible CS pin voltage. (eq. 42) RBOup can be also written independently of RBOlo by substituting Equation 42 into Equation 41 as follow: R BOup + V bulkon * V bulkoff I BO (eq. 43) From Equation 42 and Equation 43, the resistor divider value can be calculated: ǒ Ǔ R BOlo + 1 370 * 1 * 1 + 5731 W 10 m 350 * 1 R BOup + 370 * 350 + 2.0 MW 10 m Clock Rcomp S CS LEB Rsense Iss DRV Q Soft Start Status Vdd Q R Fixe d De lay 120 ms UVLO + − SS Soft start Grand Reset Figure 12. Soft Start Principle Based on the following well known equation: I SS + C SS V SS T SS C SS + I SS (eq. 44) T SS 15 m + 10 m + 37.5 nF (eq. 45) 4.0 V SS If we select Css = 33 nF, the soft start duration measured (see Figure 13) on the demoboard is equal to 13 ms. By extracting from the previous equation the capacitor value we are able to calculate the soft start duration: if we select Tss = 15 ms, http://onsemi.com 10 AND8373/D Soft Start pin (2 V/div) T ss = 13 ms V ss = 4 V CS pin (0.5 V/div) Time (4 ms/div) Figure 13. Soft Start Duration Illustration half of the switching frequency and occur only during Continuous Conduction Mode (CCM) with a duty−cycle close or above 50%. To lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. Figure 14 depicts how internally the ramp is generated: The ramp compensation applied on CS pin is buffered from the internal oscillator ramp. A switch placed between the buffered internal oscillator ramp and Rramp disconnects the ramp compensation during the off−time DRV signal. Figure 13 illustrates that the max voltage on the soft start pin is equal to 6.6 V, but the peak current of the forward transformer linearly ramps from zero to 4.0 V. Above 4.0 V on the SS pin, the controller will clamp to the max peak current. At the beginning of the soft start the peak current variation is not linear due to the Discontinuous Mode Current (DCM) operation of the forward at low peak current and low voltage on the output. Ramp Compensation Selection Ramp compensation is a known means to cure subharmonic oscillations. These oscillations take place at Vdd FB 2R Clock R S Rcomp DRV path R Buffered Ramp Rramp Q Q − CS LEB + Rsense Figure 14. Ramp Compensation Setup In the NCP1252, the internal ramp swings with a slope of: V ramp S int + F DC max sw In a forward application the secondary−side downslope viewed on a primary side requires a projection over the sense resistor Rsense. Thus: (eq. 46) S sense + http://onsemi.com 11 (V out ) V f) N S R L out N P sense (eq. 47) AND8373/D where: • Vout is output voltage level • Vf the freewheel diode forward drop • Lout, the secondary inductor value • Ns/Np the transformer turn ratio • Rsense: the sense resistor on the primary side Assuming the selected amount of ramp compensation to be applied is δcomp, then we must calculate the division ratio to scale down Sint accordingly: Ratio + S sensed comp S int transformer magnetizing inductance. In some case illustrate here after the power supply does not need additional ramp compensation due to the high level of the natural primary ramp. The natural primary ramp is extracted from the following formula: S natural + (eq. 51) If the natural ramp compensation (δnatural_comp) is higher than the ramp compensation needed (δcomp), the power supply does not need additional ramp compensation. If not, only the difference (δcomp−δnatural_comp) should be used to calculate the accurate compensation value. Thus the new division ratio is: (eq. 49) The previous ramp compensation calculation does not take into account the natural primary ramp created by the if d natural_comp t d comp å Ratio + S sense(d comp * d natural_comp) S int (eq. 52) • Vbulk = 350 V, minimum input voltage at which the Then Rcomp can be calculated with the same equation used when the natural ramp is neglected. If we assume that our forward is based on the following information: 2 switch−Forward Power supply specification: • Regulated output: 12 V • Lout = 27 mH • Vf = 0.5 V (drop voltage on the regulated output) • Current sense resistor : 0.75 W • Switching frequency : 125 kHz S int + S natural S sense d natural_comp + (eq. 48) Ratio 1 * Ratio (eq. 50) Then the natural ramp compensation will be: A few line of algebra determined Rcomp: R comp + R ramp V bulk R L mag sense • • • • • power supply works. Duty cycle max : DCmax = 50% Vramp = 3.5 V, Internal ramp level. Rramp = 26.5 kW, Internal pull−up resistance Targeted ramp compensation level: 100% Transformer specification: − Lmag = 13 mH − Ns/Np = 0.087 Internal ramp compensation level V ramp F å S int + 3.5 125 kHz + 875 mVńms 0.50 DC max sw (eq. 53) Secondary−side downslope projected over the sense resistor is: S sense + (V out ) V f) N S (12 ) 0.5) R å S sense 0.087 L out N P sense 27 @ 10 −6 0.75 + 30.21 mVńms (eq. 54) V bulk R å S natural + 350 −3 0.75 + 20.19 mVńms L mag sense 13 @ 10 (eq. 55) S natural å d natural_comp + 20.19 + 66.8% 30.21 S sense (eq. 56) Natural primary ramp: S natural + Thus the natural ramp compensation is: d natural_comp + Here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be added to prevent sub−harmonics oscillation. Ratio + S sense(d comp * d natural_comp) S int å Ratio + 30.21(1.00 * 0.67) + 0.0114 875 (eq. 57) We can know calculate external resistor (Rcomp) to reach the correct compensation level. R comp + R ramp Ratio å R 0.0114 + 305 W 3 comp + 26.5 @ 10 1 * 0.0114 1 * Ratio Thus with Rcomp = 330 W, 100% compensation ramp is applied on the CS pin. http://onsemi.com 12 (eq. 58) AND8373/D As the ramp compensation resistor is now calculated, we are able to calculate the capacitor value of the RC network connected to the CS pin. If we assume the time constant of the RC network is equal to 220 ns, the capacitor value will be: C CS + t RC 220 n + + 666 pF 330 R Comp If we select a 680−pF normalized value for CCS we are really close to the targeted time constant of 220 ns. The following figure illustrates the behavior of the RC filtering network. (eq. 59) V Rsense (0.5 V/div) CS pin (0.5 V/div) Time (2 ms/div) Figure 15. Comparison of the Voltage on the Current Sense Resistor and After the RC Filter wire: if the original ground wire is used, the current measurement will be worse than in reality. The following figure shows a comparison of the wrong and correct current measurements over the sense resistor. After filtering the current information of the forward converter provided to the controller is free of noise. Note: The measurements done in Figure 15 have to be done by respecting a true clean ground probe connection. Usually the scope probe is delivered with a long ground Current measurement on Sense :resistor with standard probe (0.5 V/div) Short gnd connection (0.5 V/div) Time (4 ms/div) Figure 16. Current Sense Measurement on Sense Resistor with Standard and Short Ground Connection http://onsemi.com 13 AND8373/D Both following figures illustrate the different probe connection for measuring the current sense information. Figure 17 illustrates the standard probe connection: but as the probe’s ground wire is quite long, the measurement generates noise (see Figure 16 probe measurement comparison). GND connection Rsense Rsense Current sense information Figure 18. Current Sense Measurement on Sense Resistor with Short Ground Connection of the Probe Secondary diode snubber calculation: Figure 17. Current Sense Measurement on Sense Resistor with Standard Probe Connection Without snubbing elements (R2&C2, R4&C6) in parallel with the secondary diodes (D5): some oscillations appear across the secondary diode. These oscillations are the result of the leakage inductance of the secondary side of the transformer with the capacitor behavior of the diode when it blocks. Thus in the worst case condition (max input voltage) it is possible that the maximum reverse voltage of the diode has been reached; with all the consequence. Figure 18 illustrates the correct connection for measuring on a power supply the current sense information. This connection has been done just by removing the plastic tips protection of the standard probe and by soldering two short wires directly to the sense resistor pads. Figure 19. Secondary Diode Snubbing http://onsemi.com 14 AND8373/D As depicted by the following figure without snubbing element the oscillations at the nominal input voltage reach the maximum reverse voltage of the diode (60 V). 62 V with max VRRM = 60 V for the MBRB30H60!!! Voltage accross the forward diode of D5 (10 V/div) Time (2 ms/div) Figure 20. Voltage Applied to the Forward Diode of D5 will be adjusted to damp completely all the oscillations implying a quality coefficient (Q) of 1: The principle of the snubber placed in parallel of each diode is damp the oscillations. The oscillations take place at the end of the conduction of the diode and they are the consequences of the leakage inductance of the secondary winding and the parasitic diode behavior of the diode. Knowing the leakage inductance of the secondary winding of the transformer and the oscillation frequency we are able to determine the resistor to be placed in parallel of the diode to damp the oscillations. In that case the resistor R damp + L leakw r + 118 n 2p 22 M + 16 W (eq. 60) After selecting a 22−W resistor for both secondary diodes, the oscillation voltage is now limited to 36 V compared to 62 V without snubber at similar input voltage (373 Vdc). A 2.2−nF capacitor is placed in series with the resistor in order to limit the losses due to the resistor presence. 36 V with snubber on each diode Voltage accross the freewheeling diode of D5 (10 V/div) Voltage accross the forward diode of D5 (10 V/div) Time (2 ms/div) Figure 21. Voltage Applied to the Secondary Diodes (D5) with Snubber http://onsemi.com 15 AND8373/D Board Performances The following figures illustrate the general performances of this demoboard. Startup Delay As depicted by Figure 22, when the VCC voltage is rising from zero and crossing VCC(ON) level, the NCP1252 sends the first pulses on the DRV pin only when the 120−ms startup delay is elapsed. Delay: 120 ms Vcc pin (5 V/div) SS pin (5 V/div) DRV pin (10 V/div) Time (40 ms/div) Figure 22. Startup Delay Soft Start compare to the middle and the end of the soft start: this non linearity is related due to the DCM (Discontinuous Current Mode) mode of operation of the forward during the first 2 or 3 ms of the soft start when the output voltage is low (< 1 V). Figure 23 depicts a soft start sequence. The CS pin voltage is following the shape of the SS pin voltage. At the beginning of the soft start period, the peak current variation is not linear SS pin (2 V/div) CS pin (500 mV/div) 12 Vout (5 V/div) Time (4 ms/div) Figure 23. Soft Start at Full Load (10 A) http://onsemi.com 16 AND8373/D Jittering Frequency switching frequency selected by the resistor connected to Rt pin with a frequency modulation of 330 Hz. The jittering modulation can be also observed by measuring the Rt pin voltage. The Jittering frequency featured by the NCP1252 helps to spread out the switching noise and eases the filtering of the power supply. The following figure illustrates the digital jittering frequency of the NCP1252: ±5% of the centered Max: 137 kHz Center:131 kHz Min: 125 kHz Switching frequency (5 kHz/div) DRV pin (10 V/div) Time (400 ms/div) Figure 24. Jittering Frequency Measurement No Load Regulation demonstration board does not have any dummy load and ensure a correct no load regulation. This regulation is achieved by skipping some driving cycles and by forcing the NCP1252 in burst mode of operation. Thanks to the skip cycle feature implemented on the NCP1252, it is possible to achieve a real no load regulation without triggering any over voltage protection. The FB pin (200 mV/div) DRV pin (10 V/div) Time (400 ms/div) Figure 25. No Load Regulation (Real No Load to the Output) Vout = 12.096 V http://onsemi.com 17 AND8373/D Step Load Stability figures show the fast transient response without any oscillations and exhibit a low drop voltage 165 mV (1.3% of the nominal output). In order to test the close loop stability, a maximum step load of 5 A have been applied on the output. The following FB pin (2 V/div) 165 mV Ac coupling on 12−V output (0.1 V/div) Time (1 ms/div) Figure 26. Step Load Response from 5 A to 10 A FB pin (2 V/div) 165 mV Ac coupling on 12−V output (0.1 V/div) Time (1 ms/div) Figure 27. Step Load Response from 0.5 A to 5.5 A http://onsemi.com 18 AND8373/D Efficiency The efficiency measurements have been done at room temp at different load conditions and at the nominal load with different input voltage. Efficiency versus Output load at ambient temperature 95% 90% 85% Efficiency (%) 80% 75% 70% 65% 60% 55% 50% 0.0 2.0 4.0 6.0 8.0 10.0 Iout (A) Figure 28. Efficiency Measurement at Room Temperature and Nominal Input Voltage (390 V dc) versus Output Load Variation Efficiency versus Input voltage at ambient temperature 91.0% 90.5% Efficiency (%) 90.0% 89.5% 89.0% 88.5% 88.0% 360 370 380 390 400 410 Vin (V dc) Figure 29. Efficiency Measurement at Room Temperature and Nominal Output Load (10 A dc) versus Intput Voltage One possible way to improve the efficiency of the demoboard is to implement a synchronous rectification, it will improve by some percent the overall efficiency. http://onsemi.com 19 http://onsemi.com 20 Figure 30. Main Demoboard Schematic 1k 1 0 C15 220pF 0 TP 1 1 Rt R20 39k U4 NCP1252 1 2 FB SS 8 Vc c 3 BO 7 CS DRV 6 4 RT GN D 5 1 0 1nF R19 CS2 TP 8 1 C11 TP 6 SS 0 R3 47k TP 1 M1 D6 MUR160 0 TP 9 DRV 100nF DRV 0 VC C C12 NC 35V C13 33nF C10 CS D8 1SMA5931 0 D9 VC C R13 1R 5 Vc c 0 1R 5 R12 D4 BZ X84C 18/ Z TX 0 R10 47k TP 3 D R V_H _ref 0 TP 4 DRV_L M2 DRV_LO DRV_HI_ref 1 R18 10 100 1% TP CS1 6200 1% CS R21 1 1nF C14 0 FB 1 TP 7 BO 1 TP 5 FB GN D J5 0 DRV_H D3 1SMA5931 DRV_HI 1 200k 1% R16 1M 1% 0 2 2 2 2 1 1 R14 1M 1% KL195 2 1 1 KL194 1 1 F D P16N 50 R17 0 HS2 Mosfet 1 HS3 Diode 2 2 1 FDP16N50 Vbulk KL194 1 HS1 Mosfet Vbulk V12V 1 J202 Vc c 1 2 DRV 3 GN D J204 DRV_HI 1 DRV_HI_ref 2 3 DRV_LO 4 CS GN D 5 0 0 H EAD ER 3 H EAD ER 5 0 Daughter board connectors U3 TL 4 3 1 R15 4. 7k TP 2 12V SLB4−I/ 90 J3 T1 10 D5 R4 27uH TP 1 6 22R MB RB30H60 1 C5 C4 out put _power 2W 1000uF / F M 1000uF / F M TP 1 5 C6 2. 2nF 16V 16V out put _power 6 5 100V SLB4−I/ 90 XFM R1 J4 R6 2. 2nF V12V 10R C7 R9a R8 0 15k 180R J6 FB 2 1 R11 R9b 1k U2 3k GN D C9 10nF SF H 615A_4 D1N4937 SLB4−I/ 90 J1 C1 47uF D1 SLB4−I/ 90 450V J2 C2 R2 22R 2. 2nF 0 2W 100V 2306−H−RC MU R 160 1 L1 2 AND8373/D Demoboard Schematics Main Board with its Auxiliary Supply AND8373/D • Self Vcc supply: in that case the NCP1010 regulator As depicted by Figure 30, the NCP1252 feedback is implemented via a TL431 arranged in a Type 2 corrector. The power supply can be connected directly to a dc source, where the minimum startup voltage is 370 Vdc. There are 2 options for supplying the Vcc to the NCP1252: • External Vcc supply: in that case the dedicated connector for the Vcc can be used to supply the 15 Vdc to the demoboard. The NCP1010 controller for the auxiliairy supply must be removed from the board. U104 1 GN D 8 2 VC C GN D 7 NC 3 4 GND DRAIN 5 FB (see Figure 31) is used to build the 15 V output via a buck converter for stepping down the main bulk voltage to the Vcc level. This auxiliary self supply is implemented on the main board close to the bulk voltage. Vbulk NCP1010P60 + C102 47uF / 25V D101 BZ X84C 12 R101 1k C101 1n R102 1k 0 L101 1 2. 2m H 2 Vc c + C103 47uF / 25V D102 MUR1 6 0 0 Figure 31. Auxiliary Supply Based on the NCP1010 @ 65 kHz Daughter Board: Driver Stage We selected to drive also the low side power mosfet with the pulse transformer to prevent any difference on the way to drive the low and high side mosfet. The daughter board or the drivers for the high side and low side mosfet is done with a pulse transformer from PREMO. D 301 MMSD 4148 MMBT489LT1G Q301 XFM R 2 6 4 R 302 47 1 2 3 Vc c DRV GN D J 202 H EAD ER 3 Q302 MMBT589LT1G C 301 10n C 302 220nF 3 R 304 1k Q303 MMBT589LT1G 5 2 1 2 D 302 MMS D4 1 4 8 R301 47R U 301 1 D 303 R 305 47R MMS D4 1 4 8 DRV_HI 1 DRV_HI_ref 2 D R V_LO 3 DRV_LO_ref 4 5 0 J 301 GN D R 306 1k Figure 32. Daughter Board: Driver Stage http://onsemi.com 21 Q304 MMBT589LT1G J 302 H EAD ER 5 AND8373/D Demo Board Picture DCin+ DCin GND Daughter Board Drivers Out GND 12 V Out Figure 33. Top View of the Demo Board NCP1252 with its Surrounding Components Figure 34. Bottom View of the Demo Board References 1. C. Basso, “Switch Mode Power Supplies: SPICE Simulations and Practical Designs”, McGraw−Hill, 2008. 2. Heatsink manufacturer link: http://www.seifert−electronic.de/en/produkt.php?id=50 or direct link to the datasheet http://www.digtion−medien.de/seifert/Uploads/seifert_punkte/pdfs/50%5B0%5D.pdf ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 22 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AND8373/D

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