PT6311B VFD Driver/Controller IC DESCRIPTION PT6311B is a Vacuum Fluorescent Display (VFD) Controller driven on a 1/8 to 1/16 duty factor housed in 52-pin plastic LQFP Package. Twelve segment output lines, 8 grid output lines, 8 segment/grid output drive lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip micro computer. Serial data is fed to PT6311B via a three-line serial interface. APPLICATION • Microcomputer Peripheral Devices FEATURES • • • • • • • • • • CMOS Technology Low Power Consumption Key Scanning (12 x 4 matrix) Multiple Display Modes: (12 segments, 16 digits to 20 segments, 8 digits) 8-Step Dimming Circuitry LED Ports Provide (5 channels, 20mA max.) 4- Bits General Purpose Input Ports Provided Serial Interface for Clock, Data Input, Data Output, Strobe Pins No External Resistors Needed for Driver Outputs Available in 52 pins LQFP BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6311B 12-GRID X 16-SEGMENT VFD APPLICATION CIRCUIT V1.1 2 June 2010 PT6311B ORDER INFORMATION Valid Part Number PT6311B-LQ Package Type 52 Pins, LQFP Top Code PT6311B-LQ PIN CONFIGURATION V1.1 3 June 2010 PT6311B PIN DESCRIPTION Pin Name SW1 to SW4 I/O I DOUT O DIN I NC - CLK I STB I K1 to K4 I VDD - SG1/KS1 to SG12/KS12 O Description General Purpose Input Pins Data Output Pin (N-Channel, Open-Drain) This pin outputs serial data at the falling edge of the shift clock (starting from the lower bit). Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit). No Connection Clock Input Pin This pin reads serial data at the rising edge and outputs data at the falling edge. Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this in is “HIGH”, CLK is ignored. Key Data Input Pins The data inputted to these pins is latched at the end of the display cycle. Logic Power Supply High-Voltage Segment Output Pins Also acts as the Key Source. SG20/GR9 to SG19/GR10 SG18/GR11 to SG13/GR16 VEE GR1 to GR8 LED1 to LED5 GND O High-Voltage Segment/Grid Output Pins O O - OSC I Pull-Down Level High-Voltage Grid Output Pins LED Output Pin Ground Pin Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency. V1.1 4 Pin No. 1 to 4 5 6 7 8 9 10 to 13 14, 33, 45 15 to 26 36 to 35 32 to 27 34 44 to 37 50 to 46 51 52 June 2010 PT6311B INPUT/OUTPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: OUTPUT PINS: SGn/GRn INPUT PINS: DIN, CLK, STB INPUT PINS: SW1 TO SW4, K1 TO K4 OUTPUT PIN: DOUT OUTPUT PINS: LED1 TO LED5 V1.1 5 June 2010 PT6311B FUNCTION DESCRIPTION COMMANDS Commands determine the display mode and status of PT6311B. A command is the first byte (b0 to b7) inputted to PT6311B via the DIN Pin after STB Pin has changed from “HIGH” to “LOW” State. If for some reason the STB Pin is set to “HIGH” while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. COMMAND 1: DISPLAY MODE SETTING COMMANDS PT6311B provides 9 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6311B via the DIN Pin when STB is “LOW”. However, for these commands, the bits 5 to 6 (b4 to b5) are ignored, bits 7 & 8 (b6 to b7) are given a value of “0”. The Display Mode Setting Commands determine the number of segments and grids to be used (1/8 to 1/16 duty, 20 to 12 segments). When these commands are executed, the display is forcibly turned off, the key scanning stops. A display command “ON” must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned “ON”, the 16-digit, 12-segment modes is selected. MSB 0 0 - - Not Relevant V1.1 b3 b2 b1 LSB b0 Display Mode Settings: 0XXX: 8 digits, 20 segments 1000: 9 digits, 19 segments 1001: 10 digits, 18 segments 1010: 11 digits, 17 segments 1011: 12 digits, 16 segments 1100: 13 digits, 15 segments 1101: 14 digits, 14 segments 1110: 15 digits, 13 segments 1111: 16 digits, 12 segments 6 June 2010 PT6311B DISPLAY MODE AND RAM ADDRESS Data transmitted from an external device to PT6311B via the serial interface are stored in the Display RAM and are assigned addresses. The RAM Addresses of PT6311B are given below in 8 bits unit. SG1 SG4 SG5 00HL 03HL 06HL 09HL 0CHL 0FHL 12HL 15HL 18HL 1BHL 1EHL 21HL 24HL 27HL 2AHL 2DHL SG8 SG9 00HU 03HU 06HU 09HU 0CHU 0FHU 12HU 15HU 18HU 1BHU 1EHU 21HU 24HU 27HU 2AHU 2DHU SG12 SG13 01HL 04HL 07HL 0AHL 0DHL 10HL 13HL 16HL 19HL 1CHL 1FHL 22HL 25HL 28HL 2BHL 2EHL b0 SG16 SG17 SG20 01HU 04HU 07HU 0AHU 0DHU 10HU 13HU 16HU 19HU 1CHU 1FHU 22HU 25HU 28HU 2BHU 2EHU b3 b4 xxHL Lower 4 bits 02HL 05HL 08HL 0BHL 0EHL 11HL 14HL 17HL 1AHL 1DHL 20HL 23HL 26HL 29HL 2CHL 2FHL DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7 DIG8 DIG9 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 DIG16 b7 xxHU Higher 4 bits COMMAND 2: DATA SETTING COMMANDS The Data Setting Commands executes the Data Write or Data Read Modes for PT6311B. The data Setting Command, the bits 5 and 6 (b4, b5) are ignored, bit 7 (b6) is given the value of “1” while bit 8 (b7) is given the value of “0”. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of “0”. MSB 0 1 - Not Relevant - b3 b2 b1 LSB b0 Data Write & Read Mode Settings: 00: Write Data to Display Mode 01: Write Data to LED Port 10: Read Key Data 11: Read SW Data Address Increment Mode Settings (Display Mode): 0: Increment Address after Data has been Written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode V1.1 7 June 2010 PT6311B PT6311B KEY MATRIX & KEY INPUT DATA STORAGE RAM PT6311B Key Matrix consists of 12 x 4 array as shown below: Each data inputted by each key are stored as follows. They are read by a READ Command, starting from the last significant bit. When the most significant bit of the data (SG12, b7) has been read, the least significant bit of the next data (SG1, b0) is read. K1…………………K4 K1…………………K4 SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 Reading Sequence SG7/KS7 SG8/KS8 SG9/KS9 SG10/KS10 SG11/KS11 SG12/KS12 b0………………….b3 b4………………….b7 LED DISPLAY PT6311B provides 5 LED Display Terminals, namely LED1 to LED5. Data is written to the LED Port starting from the least significant bit (b0) of the port using a WRITE Command. Each bit starting from the least significant (b0) activates a specific LED Display Terminal -- b0 corresponds LED1 Display, b1 activates LED2 and so forth. Since there are only 5 LED display terminals, bits 6 to 8 (b5 ~ b7) are not used and therefore ignored. This means that b5 to b7 does NOT in anyway activate any LED Display, they are totally ignored. When a bit (b0 ~ b4) in the LED Port is “0”, the corresponding LED is ON. Conversely, when the bit is “1”, the LED Display is turned OFF. For example, Bit 1 (as designated by b0) has the value of “0”, then this means that LED1 is ON. It must be noted that when power is turned ON, bit 5 to bit 1 (b4 to b0) are given the value of “1”. Please refer to the diagrams below: MSB - Not Used V1.1 - - b3 b2 b1 LSB b0 LED1 LED2 LED3 LED4 LED5 8 June 2010 PT6311B SWITCH DATA PT6311B provides 4 Switch Inputs, namely: SW1 to SW4. SW Data is read starting from the least significant bit (b0) using a READ Command. Each bit starting from the least significant (b0) corresponds to a specific Switch Input -- b0 corresponds SW1, b1 to SW2 and so forth. Since there are only 4 Switch Inputs, Bits 5 to 8 (b4 to 7) are given the value of “0”. Please refer to the diagram below. MSB 0 0 0 0 b3 b2 b1 LSB b0 SW1 SW2 SW3 SW4 COMMAND 3: ADDRESS SETTING COMMANDS Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of “00H” to “2FH”. If the address is set to 30H or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at “00H”. Please refer to the diagram below. MSB 1 1 b5 b4 b3 b2 b1 LSB b0 Address: 00H to 2FH COMMAND 4: DISPLAY CONTROL COMMANDS The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the key scanning is stopped). MSB 1 0 - - Not Relevant b3 b2 b1 LSB b0 Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width – 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off (Key Scan Continues) 1: Display On V1.1 9 June 2010 PT6311B SCANNING AND DISPLAY TIMING The key scanning and display timing diagram is given below. One cycle of key scanning consists of 2 frames. The data of the 12 x 4 matrix is stored in the RAM. V1.1 10 June 2010 PT6311B SERIAL COMMUNICATION FORMAT The following diagram shows the PT6311B serial communication format. The DOUT Pin is an N-channel, open-drain output pin, therefore, it is highly recommended that an external pull-up resistor (1 KΩ to 10 KΩ) must be connected to DOUT. RECEPTION (DATA/COMMAND WRITE) TRANSMISSION (DATA READ) where: twait (waiting time) > 1µs It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1µs. V1.1 11 June 2010 PT6311B SWITCHING CHARACTERISTIC WAVEFORM The PT6311B Switching Characteristics Waveform is given below. where: fosc = Oscillation Frequency PWSTB (Strobe Pulse Width) ≥ 1 µs tsetup (Data Setup Time) ≥ 100 ns tTZH1 (Segment Rise Time) ≤ 2.0 µs (VDD = 5 V) tTZH2 (Grid Rise Time) ≤ 0.5 µs (VDD = 5 V) tTHZ (Segment & Grid Fall Time) ≤ 150 µs tPLZ (Propagation Delay Time) ≤ 400 ns (VDD = 5 V) V1.1 PWCLK (Clock Pulse Width) ≥ 400 ns tCLK-STB (Clock - Strobe Time) ≥ 1 µs thold (Data Hold Time) ≥ 100 ns tTZH1 (Segment Rise Time) ≤ 4.0 µs (VDD = 3.3 V) tTZH2 (Grid Rise Time) ≤ 1.2 µs (VDD = 3.3 V) tPZL (Propagation Delay Time) ≤ 100 ns tPLZ (Propagation Delay Time) ≤ 600 ns (VDD = 3.3 V) 12 June 2010 PT6311B APPLICATIONS Display memories are updated by incrementing address. Please refer to the following diagram. The following diagram shows the waveforms when updating specific addresses. V1.1 13 June 2010 PT6311B RECOMMENDED SOFTWARE FLOWCHART START Delay 200 ms SET COMMAND 2 (Write Data) SET COMMAND 3 Clear Display RAM (See Note 5) INITIAL SETTING SET COMMAND 1 SET COMMAND 4 (88H~8FH: Display ON) MAIN PROGRAM SET COMMAND 2 (Read Key & Write Data Includeed) MAIN LOOP SET COMMAND 3 SET COMMAND 1 SET COMMAND 4 END Notes: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the contents of the Display RAM are not defined; thus, it is strongly suggested that the contents of the Display RAM must be cleared during the initial setting. V1.1 14 June 2010 PT6311B ABSOLUTE MAXIMUM RATINGS (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic supply voltage Driver supply voltage Logic input voltage VFD driver output voltage LED driver output current Oscillation frequency Operating temperature Storage temperature VFD driver output current Symbol VDD VEE VI VO IOLED fosc Topr Tstg IOVFD Ratings -0.3 to +7 VDD +0.3 to VDD -40 -0.3 to VDD +0.3 VEE -0.3 to VDD +0.3 +25 3M(Max.) -40 to +85 -65 to +150 -40 (Grid) -15 (Segment) Unit V V V V mA Hz ℃ ℃ mA RECOMMENDED OPERATING RANGE (Unless otherwise stated, Ta=25℃, GND=0V) Parameter Logic supply voltage High-Level input voltage Low-Level input voltage Driver supply voltage Symbol VDD VIH VIL VEE Min. 3 0.7VDD 0 VDD -35 Typ. 5 - Max. 5.5 VDD 0.3VDD 0 Unit V V V V POWER SUPPLY SEQUENCE Note: The power on/off sequence suggestion: Applications must observe the following sequence when turning the power on or off. • At power on: First turn on the logic system power (VDD), and then turn on the driver power (VEE). • At power off: First turn off the driver power (VEE), and then turn off the logic system power (VDD). V1.1 15 June 2010 PT6311B ELECTRICAL CHARACTERISTICS (Unless otherwise stated, VDD=5V, GND=0V, VEE=VDD-35 V, Ta=25℃) Parameter Symbol Test Condition IOHLED=-1mA High-Level output voltage VOHLED LED1 to LED5 IOLLED=+20mA Low-Level output voltage VOLLED LED1 to LED5 Low-Level output voltage VOLDOUT DOUT, IOLDOUT=4mA VO=VDD -2V High-Level output current IOHSG SG1 to SG12 VO=VDD -2V, High-Level output current IOHGR GR1 to GR8, SG13/GR16 to SG20/GR9 High-Level input voltage VIH Low-Level input voltage VIL Oscillation frequency fosc R=56KΩ Input current II VI=VDD or GND Dynamic current consumption IDDdyn Under no load Display OFF (Unless otherwise stated, VDD=3.3V, GND=0V, VEE=VDD-35 V, Ta=25℃) Parameter Symbol Test Condition IOHLED = -1mA High-Level output voltage VOHLED LED1 to LED5 IOLLED = +20mA Low-Level output voltage VOLLED LED1 to LED5 Low-Level output voltage VOLDOUT DOUT, IOLDOUT = 4mA VO = VDD -2V High-Level output current IOHSG SG1 to SG12 VO = VDD -2V High-Level output current IOHGR GR1 to GR8, SG13/GR16 to SG20/GR9 High-Level input voltage VIH Low-Level input voltage VIL Oscillation frequency fosc R = 56 KΩ Input current II VI = VDD or GND Dynamic current consumption IDDdyn Under no load Display OFF V1.1 16 Min. Typ. Max. Unit 0.9VDD - - V - - 1 V - - 0.4 V -3 - - mA -15 - - mA 0.7VDD 350 - 500 - 0.3VDD 650 ±1 5 V V KHz μA mA Min. Typ. Max. Unit 0.9VDD - - V - - 1 V - - 0.4 V -1.5 - - mA -6 - - mA 0.7VDD 350 - 500 - 0.2VDD 650 ±1 3 V V KHz μA mA June 2010 PT6311B PACKAGE INFORMATION 52 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e θ L L1 Dimensions (MM) Min. 0.05 1.35 0.35 0.09 Nom. 1.40 16.60 BSC 14.00 BSC 16.60 BSC 14.00 BSC 1.00 BSC Max. 1.60 0.15 1.45 0.50 0.20 0° 3.5° 7° 0.70 0.85 1.30 REF 1.00 Note: Refer to JEDEC MS-026 V1.1 17 June 2010 PT6311B IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.1 18 June 2010