CDB42518
Evaluation Board For CS42518/16
Features
Description
Single-Ended Analog Inputs and Outputs
Integrated S/PDIF compatible Receiver
CS5361 converters supply ADCIN1 and
ADCIN2 for CS42518 One Line Modes
CS8406 S/PDIF Digital Audio Transmitter
Header for optional external configuration of
CS42518 and board
Header for external DSP serial audio I/O
3.3 or 5.0 Volt Logic Interface supply
Demonstrates recommended layout and
grounding arrangements
Windows compatible software interface to
configure CS42518 and inter-board
connections
The CDB42518 demonstration board is an excellent
means for evaluating the CS42518/16 family of highly integrated multi-channel CODEC-S/PDIF receivers.
Evaluation requires an analog/digital signal source and
analyzer, Windows compatible computer, and power
supplies.
System timing can be provided by an on-board oscillator
or phase-locked to an S/PDIF input. RCA phono jacks
are provided for the CS5361 analog inputs and CS42518
analog inputs and outputs. Digital data I/O is available
via RCA phono jacks or optical connectors to/from the
CS42518 and CS8406.
The Windows software provides a GUI to make configuration of the board easy. The software communicates
through the computer’s parallel port, and will configure
the hardware to allow all features of the CS42518 to be
evaluated. The evaluation board may also be configured
to accept external timing and data signals for operation
in a user application during system development.
ORDERING INFORMATION
CDB42518
Evaluation Board
I
+18V
-18V
+5V
GND
DSP Header
Analog Inputs
CS5361
(x2)
Analog Inputs
Analog
Filter
CS8406
CS42518
8-ch
Analog
Output
S/PDIF Output
S/PDIF Inputs
S/PDIF Output
Analog Outputs
Mux
Mute
Ext. Control
CPLD
PC Parallel Port
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
JAN ‘03
DS584DB2
1
CDB42518
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4
1.1 CS42518 ............................................................................................................................ 4
1.2 CS8406 .............................................................................................................................. 4
1.3 CS5361 .............................................................................................................................. 4
1.4 Crystal Oscillator ................................................................................................................ 4
1.5 Analog Input ....................................................................................................................... 4
1.6 Analog Outputs .................................................................................................................. 4
1.7 CPLD ................................................................................................................................. 5
1.8 DB-25 Computer Parallel Port ........................................................................................... 5
1.9 External Control Header .................................................................................................... 5
1.10 DSP Header ..................................................................................................................... 6
1.11 LED Function Indicator .................................................................................................... 6
1.12 Power ............................................................................................................................... 6
1.13 Grounding and Power Supply Decoupling ....................................................................... 6
1.14 External Control Header Signals ...................................................................................... 7
1.15 DSP Header Signals ........................................................................................................ 8
2. INITIAL BOARD SETUP ........................................................................................................... 9
2.1 Power Supplies .................................................................................................................. 9
2.2 Installing the Software ........................................................................................................ 9
3. CDB425XX.EXE USER'S GUIDE ........................................................................................... 10
3.1 Main Window ................................................................................................................... 10
3.2 CS425XX Window ........................................................................................................... 10
3.3 Preset Scripts ................................................................................................................... 10
3.4 Quick Start Preset - Analog In to Analog Out .................................................................. 10
3.5 Quick Start Preset - Analog In to Digital Out .................................................................... 10
3.6 Quick Start Guide - Digital In to Analog Out .................................................................... 11
4. BLOCK DIAGRAMS ............................................................................................................... 12
5. SCHEMATICS AND LAYOUT ................................................................................................ 16
6. BILL OF MATERIALS ............................................................................................................ 32
7. ADDENDUM ........................................................................................................................... 36
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com/en/contacts/sales
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use
those components in a standard I2C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
CDB42518
LIST OF FIGURES
Figure 1. Instrumentation Amplifier Configuration........................................................................... 5
Figure 2. MCLK and SDATA ......................................................................................................... 12
Figure 3. CX and SAI LRCK/SCLK ............................................................................................... 13
Figure 4. Output Channel Mute Select.......................................................................................... 14
Figure 5. SPDIF Routing ............................................................................................................... 15
Figure 6. CS42518 ........................................................................................................................ 16
Figure 7. Clocks, Data, and DSP Header ..................................................................................... 17
Figure 8. SPDIF ............................................................................................................................ 18
Figure 9. CS5361 External ADC #1 .............................................................................................. 19
Figure 10. CS5361 External ADC #2 ............................................................................................ 20
Figure 11. CS42518 Analog Inputs ............................................................................................... 21
Figure 12. Analog Outputs A1 and B1 .......................................................................................... 22
Figure 13. Analog Outputs A2 and B2 .......................................................................................... 23
Figure 14. Analog Outputs A3 and B3 .......................................................................................... 24
Figure 15. Analog Outputs A4 and B4 .......................................................................................... 25
Figure 16. DB-25, Ext Ctrl Header, Reset..................................................................................... 26
Figure 17. CPLD ........................................................................................................................... 27
Figure 18. Power........................................................................................................................... 28
Figure 19. Component Placement and Reference Designators.................................................... 29
Figure 20. Top Layer..................................................................................................................... 30
Figure 21. Bottom Layer................................................................................................................ 31
LIST OF TABLES
Table 1. System Connections ......................................................................................................... 6
Table 2. Jumper Settings ................................................................................................................ 7
Table 3. CS42518 External Control Header Signals....................................................................... 7
Table 4. CS42518 DSP Header Signals ......................................................................................... 8
3
CDB42518
1. SYSTEM OVERVIEW
The CDB42518 demonstration board is an excellent means for evaluating the CS42518/16 family of highly integrated CODEC-S/PDIF receivers. Analog and digital audio signal interfaces are provided, as well as a DB-25 computer
parallel port interface for use with the supplied Windows configuration software.
The CDB42518 schematic set has been partitioned into 13 pages as shown in Figures 6 through 18.
1.1
CS42518
A complete description of each member of the CS42518/16 family is included in each respective product data sheet.
1.2
CS8406
The CS8406 S/PDIF transmitter on the demonstration board (see Figure 8) allows the performance of the CS42518
to be measured digitally. Either the CS42518 CODEC (CX) port or the Serial Audio Interface (SAI) port can be multiplexed to the CS8406. The CS8406 transmitter is configured to operate in slave mode only, and will receive the
required clocks from the CS42518. The data format for the CS8406 is selectable and must match that of its source.
The CS8406 must be configured using the supplied software.
1.3
CS5361
There are two CS5361 A/D converters on the CS42518 demonstration board (see Figures 9 and 10). These converters supply the CS42518 ADCIN signals, and must operate in left-justified, 24-bit mode only. Their serial data
outputs are used when supporting the CS42518 One Line Mode of operation.
RCA analog connectors supply the inputs to each CS5361 channel through a unity gain, AC-coupled, single-todifferential circuit. Each CS5361 input circuit is biased to 1/2 VA, and a 1VRMS signal will drive the converter to full
scale. The CS5361 converters are set to operate in slave mode and will receive their clocks from the CS42518. The
SCLK and LRCK signals can be provided from either the CS42518 CX or SAI port, and must be selected using the
configuration software.
1.4
Crystal Oscillator
Oscillator Y1 (see Figure 7) provides the System Clock (OMCK) for the CS42518. The crystal oscillator on the board
is mounted in pin sockets that allow it to be removed or replaced. The board is shipped with a 24.000 MHz crystal
oscillator stuffed at Y1. Please refer to the CS42518/16 data sheet for details on OMCK operation.
The buffer on the output of the oscillator provides for signal level shifting to the proper VLS supply. This buffer can
be removed if the oscillator is powered from the same VLS voltage source as the codec.
1.5
Analog Input
RCA phono connectors supply the CS42518 analog inputs through unity gain, AC-coupled single-to-differential circuits (see Figure 11). Each input circuit is biased to match the 2.7VDC VQ, and a 1VRMS differential signal will drive
the CS42518 converter to full scale.
1.6
Analog Outputs
Each CS42518 analog output is routed through a differential to single-ended, unity-gain low pass filter, which is ACcoupled to an RCA phono jack (see Figures 12 through 15). The analog output filter on the CDB42518 has been
designed to add flexibility when evaluating the CS42518 DAC outputs. The output filter was designed in a two stage
format, with the first stage being an optional instrumentation amplifier, and the second stage a 2-pole butterworth
low pass filter.
The 2-pole low pass filter provides an example of an inexpensive circuit with good distortion and dynamic range performance. It is designed to have the in-band impedance matched between the positive and negative legs. It also
provides a balanced to single-ended conversion for standard un-balanced outputs. Evaluate this circuit by placing
the FILT jumpers (three per output channel) to position 1 (selectable by J9, J10 & J11 for OUTA1, etc.).
4
CDB42518
The instrumentation amplifier is optionally inserted before the LPF by changing the FILT jumpers to position 2. The
instrumentation amplifier incorporates a 5x gain (+14dB) which effectively lowers the noise contribution of the following 2-pole LPF. This improves the overall dynamic range of the system. The gain of this stage is determined from
the following equation:
2(R)
Gain = 1 + -----------R2
The resistor designated by R2 (see Figure 1) can be adjusted to change the gain of the instrumentation amp. The
feedback resistors on the two sides of the instrumentation amp ‘R’ must be equal.
IN+
OUT+
R
R2
R
IN-
OUT-
Figure 1. Instrumentation Amplifier Configuration
A resistor divider pad (R66 and R84 for OUTA1) has been placed after the low pass filter to bring the circuit back to
unity gain (selectable with jumper J11 for OUTA1).
The attenuation provided by the output mute transistor (Q2 for OUTA1) is determined by the resistor-divider formed
between the collector-emitter on-resistance and the output resistor of the LPF (R66 for OUTA1). The greater the
output resistor, the greater the attenuation will be for a given transistor. The trade off is that a high output impedance
is not usually desirable, and may affect the voltage transfer to the next stage based upon its input impedance.
The same resistor that affects the transistor mute level also affects the HPF formed with the output DC-block capacitor (C63 for OUTA1). For LPF configuration 2, the values for the DC-block capacitor and output resistor pad (R66
and R84 for OUTA1) were chosen to give uniform distortion performance across the audio bandwidth, particularly
at low frequency. The HPF formed by this R-C pair must be such that the voltage across the aluminum electrolytic
DC-block capacitor must be a minimum at 20Hz. This keeps the distortion due to the electrolytic's dielectric absorption properties to a minimum. For a design utilizing only LPF configuration 1, there is no post-LPF resistor-divider
pad, and a much smaller value capacitor can be used.
1.7
CPLD
The CPLD controls the on-board signal routing and configuration (see Figure 17). The CPLD interfaces with the
computer software through the DB-25 parallel port header, or can communicate with an external processor via the
External Control header.
1.8
DB-25 Computer Parallel Port
On-board clock and data routing and configuration logic, as well as the CS42518 part are configured using a computer with the supplied Windows-based software. The software communicates via the DB-25 parallel port interface
(see Figure 16) to a local CPLD that can configure all parts on the board.
1.9
External Control Header
A 26-pin dual-row header allows access to the control signals needed to configure the CS42518. The external controller has access to the CS42518 I2C/SPI signals, master mute and reset, and the CS42518 interrupt signal is available (see Figure 16). All control header signals are buffered, and are referenced to VLC levels. See Table 3 for a
complete description of External Control Header signals.
5
CDB42518
1.10
DSP Header
A 32-pin dual-row header provides access to the serial audio signals required to interface with a DSP (see Figure 7).
Either the CS42518 or the DSP header can be the master of the MCLK signal. The CS42518 can supply the DSP
header with its recovered master clock (RMCK), or pass the local oscillator-sourced OMCK. An optional configuration supported is for the DSP header to source DSP_MCLK to the OMCK input, and the RMCK of the CS42518 is
not used.
The CS42518 SAI and CX ports are individually selectable to be master or slave, and should source/receive their
clocks to/from the DSP as required. All serial port timings must be synchronous to the to RMCK or the clock source
suppling OMCK. See the data sheet for a complete description of serial port modes of operation. All DSP header
signals are buffered, and are referenced to VLS levels. DSP interface power VLS and ground are supplied to the
header. See Table 4 for a complete description of DSP Header signals.
1.11
LED Function Indicator
D1 (see Figure 16) indicates that a master reset condition has occurred on the board. D4 (see Figure 17) is sourced
from the CPLD and is currently unsupported.
1.12
Power
Power can easily be supplied to the evaluation board through three binding posts, all referenced to the single black
binding post ground connector (see Figure 18).
Supply +18.0 VDC to the green binding post to provide the positive analog rail. Supply -18.0 VDC to the yellow binding post to provide the negative analog rail. +18V and -18V supply power to the op-amps and can be +/-12 to +/-18
volts (must be +/-18 V when filter 2 is selected).
Supply +5.0VDC to the red binding post. This directly supplies the digital +5V, is regulated down to provide the digital
+3.3V, and is filtered to supply VLC, VA and VARX.
VLS and VD must be individually set with jumpers to either +3.3V or +5V.
1.13
Grounding and Power Supply Decoupling
The CS42518 requires careful attention to power supply and grounding arrangements to optimize performance.
Figures 15 and 16 detail the routing and component placement for both top and bottom layers of the demonstration
board. Power supply decoupling capacitors are located as close to the CS42518 as possible. Extensive use of
ground plane fill in the demonstration board yields large reductions in radiated noise.
CONNECTOR
INPUT/OUTPUT
SIGNAL PRESENT
+5V
Input
+ 5VDC power
-18V
Input
-18 to -12VDC negative supply for the op-amps
+18V
Input
+12 to +18VDC positive supply for the op-amps
GND
Input
Ground connection from power supply
SPDIF RX - J1
Input
Digital audio interface input via coax
SPDIF RX - OPT1
Input
SPDIF TX - J2
Output
CS8406 digital audio interface output via coax
Digital audio interface input via optical
SPDIF TX - OPT2
Output
CS8406 digital audio interface output via optical
CS42518 TXP - OPT3
Output
CS42518 digital audio interface output via optical
PC Port - J22
Input/Output
Parallel connection to computer for SPI / I2C control port signals
EXTERNAL CONTROL
HEADER - J17
Input/Output
I/O for SPI / I2C control port signals - see signal descriptions below
I/O for DSP serial port signals - see signal descriptions below
DSP HEADER - J36
Input/Output
ANALOG IN LFT/RT
Input
RCA phono jacks for analog input signal to CS42518 internal ADCs
EXT A/D #1 LEFT/RIGHT
Input
RCA phono jacks for analog input signal to CS5361 ADC #1
EXT A/D #2 LEFT/RIGHT
Input
RCA phono jacks for analog input signal to CS5361 ADC #2
OUT_A1 to OUT_B4
Output
RCA phono jacks for channels A1 to B4 analog outputs
Table 1. System Connections
6
CDB42518
JUMPER / SWITCH
PURPOSE
POSITION
FUNCTION SELECTED
J37
Selects source of voltage for the
VLS supplies
+3.3V
*+5V
Voltage source is +3.3V regulator
Voltage source is +5V binding post
J38
Selects source of voltage for the
VD supply
+3.3V
*+5V
Voltage source is +3.3V regulator
Voltage source is +5V binding post
S2
Stand-Alone Mode Select
SAM0
SAM1
Stand-Alone Modes are for debug use
and are presently unsupported
J9,J10,J11
J13,J15,J16
J18,J19,J20
J23,J25,J26
J28,J29,J30
J32,J34,J35
J39,J40,J41
J43,J45,J46
DAC Output Filter select - FILT
*1
Selects standard 2-pole LPF
2
Selects instrumentation-amp/LPF/pad
*Default Factory Settings
Table 2. Jumper Settings
1.14
External Control Header Signals
Header
Pin #
Signal Description
Source
Schematic Signal Name
Buffer
Buffer
Voltage
1
External Control Present Signal
CTRL
EXT_CONTROL_PRESENT-
-
-
2
Ground
CDB
GND
-
-
3
Address Bit 0 (I2C) / CS- (SPI)
CTRL
AD0/CS
74VHC125
VLC
4
Ground
CDB
GND
-
-
5
Address Bit 1 (I2C) / CDIN (SPI)
CTRL
AD1/CDIN
74VHC125
VLC
6
Ground
CDB
GND
-
-
7
SDA (I2C) / CDOUT (SPI)
CTRL or CS42518
SDA/CDOUT
MOSFET
VLC
8
Ground
CDB
GND
-
-
9
Serial Control Port Clock
CTRL
SCL/CCLK
74VHC125
VLC
10
Ground
CDB
GND
-
-
11
Master MUTE to all Outputs
CTRL
EXT_MUTE
74VHC125
VLC
12
Ground
CDB
GND
-
-
13
Master RESET
CTRL
EXT_RESET
Diode
-
14
Ground
CDB
GND
-
-
15
CS42518 Interrupt (Programmable)
CS42518
EXT_HDR_INT
74VHC125
VLC
16
Ground
CDB
GND
-
-
17
Enable external I2C interface
CTRL
EXT_EN_SCL
74VHC125
VLS
18
Ground
CDB
GND
-
-
19
Enable external I2C interface
CTRL
EXT_EN_SDA
74VHC125
VLS
20
Ground
CDB
GND
-
-
Table 3. CS42518 External Control Header Signals
7
CDB42518
1.15
DSP Header Signals
Header
Pin #
Signal Description
Source
Schematic
Signal Name
Buffer
Buffer
Voltage
CS42518 or DSP
DSP_MCLK
74VHC125
VLS
CDB
GND
-
-
CS42518 or DSP
DSP_CX_LRCK
74VHC125
VLS
CDB
GND
-
-
CS42518 or DSP
DSP_CX_SCLK
74VHC125
VLS
1
Master Clock
2
Ground
3
CODEC port LRCK
4
Ground
5
CODEC port SCLK
6
Ground
CDB
GND
-
-
7
CODEC port SDATA Input 1
DSP
DSP_SDAT1
74VHC125
VLS
8
Ground
CDB
GND
-
-
9
CODEC port SDATA Input 2
DSP
DSP_SDAT2
74VHC125
VLS
10
Ground
CDB
GND
-
-
11
CODEC port SDATA Input 3
DSP
DSP_SDAT3
74VHC125
VLS
12
Ground
CDB
GND
-
-
13
CODEC port SDATA Input 4
DSP
DSP_SDAT4
74VHC125
VLS
14
Ground
CDB
GND
-
-
15
no connect
-
-
-
-
16
Ground
CDB
GND
-
-
17
SAI port LRCK
CS42518 or DSP
DSP_SAI_LRCK
74VHC125
VLS
18
Ground
CDB
GND
-
-
19
SAI port SCLK
CS42518 or DSP
DSP_SAI_SCLK
74VHC125
VLS
20
Ground
CDB
GND
-
-
21
no connect
-
-
-
-
22
Ground
CDB
GND
-
-
23
CODEC port SDATA Output
CS42518
DSP_CX_SDOUT
74VHC125
VLS
24
Ground
CDB
GND
-
-
25
SAI Port SDATA Output
CS42518
DSP_SAI_SDOUT
74VHC125
VLS
26
Ground
CDB
GND
-
-
27
MCLK Direction Control
DSP
MCLK_TO_DSP-
-
-
28
Ground
CDB
GND
-
-
29
Serial Port Interface Power
CDB
VLS
-
-
30
Ground
CDB
GND
-
-
31
Serial Port Interface Power
CDB
VLS
-
-
32
Ground
CDB
GND
-
-
Table 4. CS42518 DSP Header Signals
8
CDB42518
2. INITIAL BOARD SETUP
2.1
Power Supplies
1) Verify that all power supplies are off before making connections.
2) Connect a +5.0 VDC power supply to the +5V (J47) red binding post. Select VLS and VD operating voltage by
placing a jumper on J37 and J38 to select either +5V or +3.3V.
3) Connect a +12.0 to +18.0 VDC power supply to the +18V (J49) green binding post. If using the FILT position
number 2 for the output filter stage, then supply +18.0V only.
4) Connect a -12.0 to -18.0 VDC power supply to the -18V (J50) yellow binding post. If using the FILT position
number 2 for the output filter stage, then supply -18.0V only.
5) Connect the common ground of the power supplies to the GND (J48) binding post.
6) Attach parallel port cable between board and computer.
7) Attach all required analog and digital cables to the board jacks and connectors.
8) If using the DSP Header connection, attach the required user supplied flat ribbon cable to the header with the
power supplies turned off.
9) If using the External Control Header connection, attach the required user supplied flat ribbon cable to the header
with the power supplies turned off. Note that external controller must ground the EXT_CONTROL_PRESENTsignal to gain control of the I2C/SPI signals. This can be done easily by connecting External Control Header pins
1 and 2 together.
10) With all cables and connections in place, turn on the power supplies to the board. Turn on supplies in this order:
+5 V, +18 V, -18 V.
11) Press and release the RESET switch S1. The LED, D1, will illuminate as long as S1 is depressed indicating a
reset condition. Once S1 is released, the LED should turn off. If it remains on, an error has occurred. At this
point, power off the power supplies and re-check all connections. Apply power to the board and press and
release S1. Once the LED has turned off, the board should now be ready for setup and use.
2.2
Installing the Software
1) Create a directory called CDB42518 anywhere on your system.
2) Copy CDB425XX.EXE from the included CD into this directory.
3) Copy the .LVS preset script files from the CD into this directory.
4) Run port95nt.exe from the CD. This will install a utility that will allow the CDB software to access the parallel
port. After running the program the system will need to be restarted.
5) If desired, create a shortcut to CDB425XX.EXE on your desktop. You should now be able to run
CDB425XX.EXE. Double-click on CDB425XX.EXE or its shortcut.
6) Select the LPT port you are using to connect to the CDB42518.
7) Shut down the application, reset the board, and then restart the application.
9
CDB42518
3. CDB425XX.EXE USER'S GUIDE
3.1
Main Window
The main window of the CDB42518 control application allows the user to configure the CDB42518 inter-board routing of clocks and data, as well as setup the CS5361 and CS8406 parts. To make changes to the CS5361, CS8406,
or inter-board routing, the “Configure Board” radio button must be selected.
The RESET CS425xx button will reset only the part. The MASTER RESET button will reset the CS42518, as well
as reset the board into its default state.
3.2
CS425XX Window
To configure the CS42518, the “Configure CS425xx” radio button must be selected, then press the “CS425XX” button. This will bring up the complete CS42518 configuration window.
3.3
Preset Scripts
To make configuring the board and part easier, preset scripts can be saved and recalled. A preset script is a “snapshot” of all GUI board and component settings. This can done using the File pulldown menu and choosing Load or
Save. Scripts are saved with the default .LVS extension, and when loaded, will create a .LOG file. There are several
preset scripts included with the software. The following sections represent three common setup modes with scripts
for quick evaluation of the board.
3.4
Quick Start Preset - Analog In to Analog Out
To measure analog in to analog out performance, you will need the following:
•
CS42518 Demonstration Board
•
+18 VDC, -18 VDC, and +5 VDC power supplies
•
Analog signal source and analyzer
•
Windows compatible computer with parallel port cable and CDB425xx software
Step 1 - Follow Initial Board Setup procedure as described above
Step 2 - Select Output Filter Jumpers
Set all CDB42518 analog output filter jumpers to the FILT2 settings.
Step 3 - Connect to Windows Software
Connect the computer to the board and launch the CDB425xx software.
Step 4 - Connect Signal Source
Connect the analog output from the analyzer to the Left Analog Input J7. Connect J12 analog OUTA1 RCA to the
input of the analyzer. Set the analyzer output to 1.0 VRMS, 1 kHz. Set the analyzer input to measure signal level
and apply a 22-22 kHz filter.
Step 5 - Configure the Board
Using the Windows software, load the preset script “Single Speed Analog In To Analog Out.LVS”. This preset will
configure the CS42518 to use OMCK as the master clock, CX and SAI ports will be masters, and the CX_SDOUT
(ADC) data will source all CX_SDIN (DAC) inputs. The left/right analog inputs will appear at all odd/even analog outputs. The single speed sample rate will be 46.875kHz based upon the 24.000MHz OMCK. You may load the similar
double speed or quad speed presets to investigate higher sample rates.
Step 6 - Measure Audio
You should now have audio appearing at the Analog A1 output.
3.5
Quick Start Preset - Analog In to Digital Out
To measure the analog to digital converter performance, you will need the following:
•
CS42518 Demonstration Board
•
+18 VDC, -18 VDC, and +5 VDC power supplies
10
CDB42518
•
Analog signal source and analyzer
•
Digital signal source and analyzer
•
Windows compatible computer with parallel port cable and CDB425xx software
Step 1 - Follow Initial Board Setup procedure as described above
Step 2 - Connect to Windows Software
Connect the computer to the board and launch the CDB425xx software.
Step 3 - Connect Signal Source
Connect the analog output from the analyzer to the Left Analog Input J7. Connect the CS8406 digital output (coax
J2 or optical OPT2) to the input of the analyzer. Set the analyzer output to 1.0 VRMS, 1 kHz. Set the analyzer input
to measure digital signal level and apply a 22-22 kHz filter.
Step 4 - Configure the Board
Using the Windows software, load the preset script “Single Speed Analog In To Digital Out.LVS”. This preset will
configure the CS42518 to use OMCK as the master clock, CX and SAI ports will be masters, and the CX (ADC)
clocks data will source the CS8406 inputs. The CS8406 will output the ADC digital data to both the optical and RCA
jacks. The single speed sample rate will be 46.875kHz based upon the 24.000MHz OMCK. You may load the similar
double speed or quad speed presets to investigate higher sample rates.
Step 5 - Measure Audio
You should now have digital audio appearing at the CX_SDOUT port and the CS8406 digital output.
3.6
Quick Start Guide - Digital In to Analog Out
To measure digital to analog performance, you will need the following:
•
CS42518 Demonstration Board
•
+18 VDC, -18 VDC, and +5 VDC power supplies
•
Analog signal source and analyzer
•
Digital signal source and analyzer
•
Windows compatible computer with parallel port cable and CDB425xx software
Step 1 - Follow Initial Board Setup procedure as described above
Step 2 - Select Output Filter Jumpers
Set all CDB42518 analog output filter jumpers to the FILT2 settings.
Step 3 - Connect to Windows Software
Connect the computer to the board and launch the CDB425xx software.
Step 4 - Connect Signal Source
Connect the S/PDIF digital output from the analyzer to the optical input connector OPT1. Connect the analog OUTA1
RCA phono jack J12 to the input of the analyzer. Set the analyzer output to 0 dBFS, 1 kHz, sample rate at 48 kHz.
Set the analyzer input to measure signal level and apply a 22-22 kHz filter.
Step 5 - Configure the Board
Using the Windows software, load the preset script “Single Speed Optical In to Analog Out.LVS”. This preset will
configure the CS42518 to use the recovered PLL clock as the master clock, the SAI port will be master, the CX port
will be slaved to the SAI port, the SAI_SDOUT will source all CX_SDIN inputs. The test source left/right data will
appear at all odd/even analog outputs. You may load the similar double speed or quad speed presets to investigate
higher sample rates, but you must be sure to supply an appropriate speed SPDIF signal.
Step 6 - Measure Audio
You should now have audio appearing at the Analog A1 output.
11
CDB42518
4. BLOCK DIAGRAMS
Y1
8406_MCLK
24.000 MHz
OMCK
MCLK_TO_DSP
DSP_MCLK
DSP_MCLK
MCLK_TO_DSP
5361_MCLK
RMCK
SAI_TO_CXSDIN
8406_SDIN
SAI_DATA_TO_8406
DSP_SAI_SDOUT
SAI_SDOUT
CX_TO_CXSDIN
CX_SDOUT
8406_SDIN
CX_DATA_TO_8406
DSP_CX_SDOUT
CX_SDIN1
DSP_SDAT1
CX_SDIN2
DSP_SDAT2
CX_SDIN3
DSP_SDAT3
CX_SDIN4
DSP_SDAT4
DSP_TO_CXSDIN
Figure 2. MCLK and SDATA
12
SAI LRCK
SAI SCLK
CX LRCK
CX SCLK
DSP_SAI_SLAVE
SAI_TO_8406
SLCT_SAI_5361
DSP_SCLK
DSP_SAI_MASTER
DSP_CX_MASTER
DSP_LRCK
DSP_CX_SLAVE
CX_TO_8406
SLCT_CX_5361
SAI_TO_CX
CX_TO_SAI
5361
5361
8406
8406
DSP
DSP
5361
5361
8406
8406
DSP
DSP
CDB42518
Figure 3. CX and SAI LRCK/SCLK
13
14
Figure 4. Output Channel Mute Select
MUTEC
EN_MUTE6
RXP/GPO6
MUTEC
EN_MUTE7
RXP_GPO7
MUTEC
EXT_MUTE
+V
MUTE CH 3 - 8
MUTE CH 2
MUTE CH 1
EXT_MUTE and GPO6
EXT_MUTE and MUTEC
or
EXT_MUTE and GPO7
EXT_MUTE and MUTEC
or
EXT_MUTE and MUTEC
MUTE CONTROL
3-8
2
1
CHANNEL
CDB42518
CDB42518
4053C
A0
A1
Opto-electronic
Coupler
A
RXP/GPO5
B
RXO
B0
B1
C0
RCA Jack
C
C1
RXP/GPO1
CE
ENABLE_4053C
4053B
A0
A1
A
RXP/GPO2
B
RXP/GPO3
B0
B1
C0
C
C1
RXP/GPO4
CE
ENABLE_4053B
4053A
A0
A
A1
N/C
B0
B
B1
RXP/GPO6
C0
C
C1
RXP/GPO7
CE
ENABLE_4053A
Figure 5. SPDIF Routing
15
CDB42518
Figure 6. CS42518
5. SCHEMATICS AND LAYOUT
16
Figure 7. Clocks, Data, and DSP Header
CDB42518
17
Figure 8. SPDIF
CDB42518
18
CDB42518
Figure 9. CS5361 External ADC #1
19
CDB42518
Figure 10. CS5361 External ADC #2
20
CDB42518
Figure 11. CS42518 Analog Inputs
21
Figure 12. Analog Outputs A1 and B1
CDB42518
22
Figure 13. Analog Outputs A2 and B2
CDB42518
23
Figure 14. Analog Outputs A3 and B3
CDB42518
24
Figure 15. Analog Outputs A4 and B4
CDB42518
25
Figure 16. DB-25, Ext Ctrl Header, Reset
CDB42518
26
Figure 17. CPLD
CDB42518
27
Figure 18. Power
CDB42518
28
Figure 19. Component Placement and Reference Designators
CDB42518
29
Figure 20. Top Layer
CDB42518
30
Figure 21. Bottom Layer
CDB42518
31
32
U18 U19
S2
JP1 JP2 JP3 JP4 JP5 JP6
J48
J49
J47
J50
C128 C139 C146 C147 C149 C168 C174
C5
C132 C133 C143 C154 C158 C171 C177 C178
C125
C1 C21 C22 C23 C24 C25 C27 C35 C36 C42
C43 C44 C45 C46 C47 C48 C49 C50 C58 C74
C76 C78 C80 C84 C86 C100 C101 C102 C103
C2 C3 C4 C20 C32 C37 C40 C61 C62 C69 C82
C87 C92 C93 C94 C95 C96 C104 C109 C110
C113 C114 C117 C120 C124 C127 C134 C137
C138 C144 C145 C150 C159 C160 C161 C162
C167 C173 C175 C176 C181 C187 C192 C195
C196 C197 C203 C207 C208 C209 C210 C211
C212 C213 C214 C217 C218 C219 C224 C228
C231 C233 C234 C235 C236 C248 C251 C252
C33 C39
C244
C12 C13 C15 C16 C17 C18 C163 C232 C241
C8 C10 C14 C19 C57 C71
C38 C41 C116 C123 C135 C136 C151 C155
C204
C60 C88 C119 C140 C185 C198 C223 C239
C56 C98 C112 C153 C183 C206 C221 C246
C65 C67 C105 C106 C172 C179 C180
C59 C99 C118 C157 C184 C205 C222 C247
C68 C91 C126 C148 C188 C201 C227 C242
2
1
6
1
1
1
1
7
1
8
1
29
2
1
9
6
9
8
8
8
8
7
68
Reference
U45
Qty
1
CIRRUS LOGIC
CDB42528B.sch
C1206C222J5GAC
ECE-V1CA220P
C0805C122J5GAC
C0805C182J5GAC
ECE-V1HS010SR
595D107X06R3C2T
ECE-V1CS100SR
C0805C102J5RAC
C0805C101J5GAC
ECE-V1AA101WR
C0805C104J5RAC
CS5361-KS Rev-C
76SB02
TP-102-02
111-0103-001
111-0104-001
111-0102-001
111-0107-001
C0603C103J5RAC
C0805C103J5RAC
C0805C473Z5UAC
C0805C563J5RAC
ECJ-1VB1C104K
Part Number
LP3965EMP-ADJ
KEMET
PANASONIC
KEMET
KEMET
PANASONIC
VISHAY SPRAGUE
PANASONIC
KEMET
KEMET
PANASONIC
KEMET
CAP, 1000pF, X7R, 0805, 50V, 5%
CAP, 100pF, COG, 0805, 50V, 5%
CAP, 100uF, ELEC, VS SERIES, SMT CASE-C,
10V, 20%
CAP, 100UF, TANT, 6.3V, 10%
CAP, 10uF, ELEC, VS SERIES, SMT CASE-A,
16V, 20%
CAP, 1200pF, COG, 0805, 50V, 5%
CAP, 1800PF, COG, 0805, 50V, 5%
CAP, 1uF, ELEC, VS SERIES, SMT CASE-A,
50V, 20%
CAP, 2200PF, COG, 1206, 50V, 5%
CAP, 22uF, ELEC, VA SERIES, SMT CASE-C,
16V, 20%
CAP, 0.1UF, X7R, 0805, 50V, 5%
Manufacturer
Description
National Semiconductor 1.5A Ultra Low Dropout Adjustable Linear
Regulator, SOT223-5
CRYSTAL SEMI
192 kHz AUDIO A/D CONVERTER, SO24-300
GRAYHILL
2 POSITION DIP SWITCH
CONTROL DESIGN
2-PIN JUMPER WIRE
E.F. JOHNSON
BINDING POST, BLACK
E.F. JOHNSON
BINDING POST, GREEN
E.F. JOHNSON
BINDING POST, RED
E.F. JOHNSON
BINDING POST, YELLOW
KEMET
CAP, 0.01UF, X7R, 0603, 50V, 5%
KEMET
CAP, 0.01UF, X7R, 0805, 50V, 5%
KEMET
CAP, 0.047UF, Z5U, 0805, 50V, 80-20%
KEMET
CAP, 0.056UF, X7R, 0805, 50V, 5%
PANASONIC
CAP, 0.1UF, X7R, 0603, 16V, 10%
BILL OF MATERIAL
CDB42518
6. BILL OF MATERIALS
C6 C7 C9 C11 C28 C29 C30 C31 C52 C53 C54
C55
C63 C90 C122 C142 C190 C200 C226 C243
C34 C83 C85 C115 C186 C191
C237 C238
C51
C97 C111 C152 C182 C202 C220 C245
C26
J22
U28
C156
J17
U4 U10 U13
U5
U3
U1 U2 U6 U7 U8 U9
U11 U12 U20 U24 U25 U30 U31 U32 U40 U43
U44 U46
U27
U14 U15 U16 U17 U21 U22 U26 U33 U34 U35
U36 U37 U38 U39 U41 U42
L1 L2 L3 L4 L5 L6 L7 L8 L9
D1 D4
Q5
OPT1
OPT2 OPT3
Y1
12
2
1
7
1
1
1
1
1
3
1
1
6
12
9
2
1
1
2
1
1
16
8
6
3
Reference
C75 C77 C79 C81 C129 C164 C169
C70 C89 C121 C141 C189 C199 C225 C240
C72 C73 C107 C108 C130 C131 C165 C166
C193 C194 C215 C216 C229 C230 C249 C250
C64 C66 C170
Qty
7
8
16
CIRRUS LOGIC
CDB42528B.sch
ALTERA
N/A
SAMTEC
Texas Instruments
CRYSTAL
SEMICONDUCTOR
DALLAS
SEMICONDUCTOR
NJR
PHILIPS
KEMET
KEMET
KEMET
AMP
PANASONIC
PANASONIC
PANASONIC
KEMET
PANASONIC
Manufacturer
PANASONIC
KEMET
KEMET
CIRRUS LOGIC
FAIRCHILD
SEMICONDUCTOR
ELJ-FA470KF
PANASONIC
CMD28-21SRC/TR8/T1 CHICAGO MINIATURE
BSS138ZX
Zetex
TORX173
TOSHIBA
TOTX173
TOSHIBA
ECS-2100A-240
ECS
CS4252
74VHC125MTC
NJM-2068E
NE5532D8
DS1233-10
EMP7160STC100-6
NP-CAP-0805
TSW-110-07-G-D
74HC4053
CS8406-CS
C1206C562K5GAC
C1206C562J5GAC
C0805C561J5GAC
747238-4
ECE-V1EA470UP
ECA-0JM471I
ECE-V1AA470P
C0603C471J5GAC
ECE-V1EA4R7R
Part Number
ECJ-2VC1H272J
C0603C391J5GAC
C0805C391J5GAC
BILL OF MATERIAL
IC, ELVIS, QFP64, 10X10mm, 0.5mm PITCH
IC, QUAD BUFFER WITH 3-STATE OUTPUTS,
TSSOP14-173
INDUCTOR, 47uH, 1210, TYPE FA, 10%
LED, SMT, RED
N-Channel Enhancement Mode FET, SOT23
OPTICAL TOSLINK RECEIVER
OPTICAL TOSLINK TRANSMITTER
OSCILLATOR, 24.000MHZ, HALF SIZE CASE, +/100PPM
IC, DUAL LOW NOISE OP-AMP, SO8-150
IC, DUAL LOW NOISE OP-AMP, SO8-150
CAP, 470uF, ELEC, M SERIES, 6.3V, 20%
CAP, 47uF, ELEC, VA SERIES, SMT CASE-D,
10V, 20%
CAP, 47uF, ELEC, VS SERIES, SMT CASE-D,
25V, 20%
CAP, 5600PF, COG, 1206, 50V, 10%
CAP, 5600PF, COG, 1206, 50V, 5%
CAP, 560PF, COG, 0805, 50V, 5%
CONNECTOR, D-SUB, DB25, MALE, RT.
ANGLE
CPLD
DO NOT POPULATE
HEADER, 10X2, 0.1" CTR, GOLD
HEX 2:1 Analog Switch, SOIC150-16
IC, 192kHz DIGITAL AUDIO TRANSMITTER,
SO28-300
IC, 5-VOLT ECONO RESET, TO92
CAP, 4.7uF, ELEC, VA SERIES, SMT CASE-B,
25V, 20%
CAP, 470PF, COG, 0603, 50V, 5%
Description
CAP, 2700PF, COG, 0805, 50V, 5%
CAP, 390PF, COG, 0603, 50V, 5%
CAP, 390PF, COG, 0805, 50V, 5%
CDB42518
33
34
R74 R96 R121 R145 R170 R192 R211 R229
R72 R93 R116 R142 R168 R189 R209 R226
R75 R87 R120 R135 R167 R183 R212 R220
R8 R9 R10 R11 R12 R13
R79 R179 R180 R196 R198
R35 R39 R40 R42 R44 R45 R50 R85 R98 R104
R157 R160 R163 R201 R231 R235
R133
R230
R41 R107 R108 R119 R132 R153 R155 R158
R162 R172
R66 R95 R118 R144 R164 R191 R206 R228
R51 R100 R111 R150 R156 R199 R204 R234
R125
R2 R4 R15 R16 R33 R80
R32 R78 R89 R106 R110 R124 R137 R174 R185
R215 R222
R134 R139 R146 R147 R239
R84 R99 R130 R149 R178 R197 R218 R233
R3 R5 R14 R17 R34 R81
R70 R71 R91 R92 R114 R115 R140 R141 R165
R166 R187 R188 R207 R208 R224 R225
R30 R31 R47 R52 R54 R69
R7
R159
R86 R109 R131 R154 R182 R203 R219 R238
R61 R97 R101 R102 R112 R113 R126 R127
R148 R161 R175 R176 R193 R194 R195 R205
R232 R240
R73 R94 R117 R143 R169 R190 R210 R227
R76 R90 R122 R138 R171 R186 R213 R223
R23 R24 R26 R27 R28 R29 R36 R37 R38 R43
R46 R48 R49 R53 R64 R65 R67 R68
8
8
8
6
5
16
8
8
18
6
1
1
8
18
5
8
6
16
8
8
1
6
11
1
1
10
2
Reference
U23
J1 J2 J3 J4 J5 J6 J7 J8 J12 J14 J21 J24 J31 J33
J42 J44
RN1 RN4
Qty
1
16
CIRRUS LOGIC
CDB42528B.sch
CRCW08055491F
CRCW08056191F
CRCW06036340F
CRCW06033320F
CRCW08053740F
CRCW08054421F
CRCW08054420F
CRCW08054752F
CRCW060322R1F
CRCW08052800F
CRCW08053321F
CRCW08053010F
CRCW08051001F
CRCW08052001F
CRCW08052261F
CRCW08052801F
CRCW08052941F
CRCW0805100FT
CRCW08051782F
CRCW06031001F
CRCW06031002F
CRCW0805000FT
CRCW08051651F
CRCW08051871F
CRCW08051003F
CRCW08051000F
4816P-001-472
Part Number
SN74HCT08D
ARJ-2018-1
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
DALE
BOURNS
Manufacturer
TEXAS INST
A/D ELECTRONICS
BILL OF MATERIAL
RES, 5.49K , 0805, 1/10W, 1%. 100ppm
RES, 6.19K , 0805, 1/10W, 1%. 100ppm
RES, 634 OHMS, 0603, 1/16W, 1%, 200ppm
RES, 332 OHMS, 0603, 1/16W, 1%, 200ppm
RES, 374 OHMS, 0805, 1/10W, 1%. 100ppm
RES, 4.42K , 0805, 1/10W, 1%. 100ppm
RES, 442 OHMS, 0805, 1/10W, 1%. 100ppm
RES, 47.5K , 0805, 1/10W, 1%. 100ppm
RES, 22.1 OHMS, 0603, 1/16W, 1%, 200ppm
RES, 280 OHMS, 0805, 1/10W, 1%. 100ppm
RES, 3.32K , 0805, 1/10W, 1%. 100ppm
RES, 301OHMS, 0805, 1/10W, 1%. 100ppm
RES, 1K, 0805, 1/10W, 1%. 100ppm
RES, 2.00K , 0805, 1/10W, 1%. 100ppm
RES, 2.26K , 0805, 1/10W, 1%. 100ppm
RES, 2.80K , 0805, 1/10W, 1%. 100ppm
RES, 2.94K , 0805, 1/10W, 1%. 100ppm
RES, 10-OHM, 0805, 1/10W, 1%. 100ppm
RES, 17.8K , 0805, 1/10W, 1%. 100ppm
RES, 1K, 0603, 1/16W, 1%, 200ppm
RES, 0-OHM, 0805
RES, 1.65K , 0805, 1/10W, 1%. 100ppm
RES, 1.87K , 0805, 1/10W, 1%. 100ppm
RES, 100K, 0805, 1/10W, 1%. 100ppm
RES, 100-OHM, 0805, 1/10W, 1%. 100ppm.
100ppm
RES, 10K, 0603, 1/16W, 1%, 200ppm
RES NETWORK, 4.7K, 8 ISOLATED, SO16-220
Description
QUAD 2-INPUT POS-AND GATES
RCA JACK - RIGHT ANGLE, GOLD PLATED
CDB42518
U47
T1
Z1 Z2
Z3
Q2 Q3 Q6 Q7 Q8 Q9 Q11 Q12
Q1 Q4 Q10
5361A_SDAT 5361B_SDAT CX_LRCK CX_SCLK
CX_SDIN1 CX_SDIN2 CX_SDIN3 CX_SDIN4
CX_SDOUT INT MUTEC OMCK RMCK RSTSAI_LRCK SAI_SCLK SAI_SDOUT TP1 TP2 TP3
TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11
1
1
2
1
8
3
28
1
7
1
1
1
1
2
1
26
13
Reference
R6
R22 R25
R77 R82 R83 R88 R103 R105 R123 R128 R129
R136 R151 R152 R173 R177 R181 R184 R200
R202 R214 R216 R217 R221 R236 R237
R1 R18 R19 R20 R21 R55 R56 R57 R58 R59
R60 R62 R63
RN2
RN3
D2 D3
J36
J9 J10 J11 J13 J15 J16 J18 J19 J20 J23 J25 J26
J28 J29 J30 J32 J34 J35 J37 J38 J39 J40 J41
J43 J45 J46
J27
X1 X2 X3 X4 X5 X6 X7
S1
U29
Qty
1
2
24
CIRRUS LOGIC
CDB42528B.sch
SC979-03
P6KE24A
P6KE6.8
2SC3326
MMUN2111LT1
NC7SZ126M5
TSW-105-07-G-D
313-6477-032
PTS645TL50
NC7SZ125M5
4609X-101-102
4605X-101
BAT85
TSW-116-07-G-D
TSW-103-07-G-S
CRCW060390R9F
Part Number
CRCW080575R0F
CRCW0805822J
CRCW08058870F
MOTOROLA
MOTOROLA
TOSHIBA
MOTOROLA
FAIRCHILD
SAMTEC
E.F.JOHNSON
C&K
FAIRCHILD
BOURNS
BOURNS
PHILIPS
SAMTEC
SAMTEC
DALE
Manufacturer
DALE
DALE
DALE
BILL OF MATERIAL
STAKE HEADER, 5X2, 0.1"CTR, GOLD
STANDOFF, #4-40, .25 HEX x .875 LG
SWITCH, MOMENTARY, PUSHBUTTON
TINYLOGIC UHS BUFFER W/ 3-STATE
OUTPUT, SOT23-5
TINYLOGIC UHS BUFFER W/ 3-STATE
OUTPUT, SOT23-5
Transformer, SMT, AES-192kHz Compatible
TRANSIENT SUPPRESSOR, 24V
TRANSIENT SUPPRESSOR, 6.8V
TRANSISTOR, NPN, EPITAXIAL TYPE, SC59
TRANSISTOR, PNP SILICON SMT WITH
MONOLITHIC BIAS RES NET, SOT23
RESISTOR NETWORK, 8 BUSSED, SIP9, 1K
RESISTOR NETWORK, 9 BUSSED, SIP5, 1K
SCHOTTKY DIODE, THRU-HOLE
STAKE HEADER, 16X2, 0.1: CTR, GOLD
STAKE HEADER, 3X1, 0.1" CTR, GOLD
RES, 90.9 OHMS, 0603, 1/16W, 1%, 200ppm
Description
RES, 75.0 OHMS, 0805, 1/10W, 1%. 100ppm
RES, 8.2K, 0805, 1/10W, 5%, 200ppm
RES, 887 OHMS, 0805, 1/10W, 1%. 100ppm
CDB42518
35
CDB42518
7. ADDENDUM
There are three hardware modifications to the circuit board as follows:
1) U16 pin 10 and U16 pin 13 are unterminated in the schematic set. They should have been connected to ground.
A top side modification was performed on the board by adding a wire from U16 pin 10 to U16 pin 13, then to the
ground pad at C94.
2) U17 pin 11 is grounded in the schematic set. It should have been left unterminated. A top side modification was
performed by lifting U17 pin 11.
3) The MCLK_TO_DSP- signal trace between U29 pin 1 and U47 pin 1 got merged to the ground fill beneath the
crystal oscillator Y1. A top side modification was performed on the board by cutting the trace to disconnect it
from the ground fill. A bottom side modification was performed on the board by adding a wire to reconnect the
trace.
36
• Notes •