Highly integrated CMOS RF SPDT switch with ESD and unit cell optimisation in MCM A.Y.-K. Chen Presented is the performance of a highly integrated RF single-pole double-throw (SPDT) switch fabricated in a 0.18 µm bulk CMOS process and housed in a low-cost laminated multi-chip module (MCML) package. A switch controller is also implemented and consumes ∼40 µA from a 3.4 V supply. The switch, based upon the 1.8 V thinoxide devices with resistive body-floating and unit cell layout optimisation techniques, achieves an insertion loss of 0.52/0.78 dB at 0.9/2.45 GHz, respectively. TX-to-RX isolation of > 29 dB and return loss of > 15 dB are achieved at these frequencies. The measured IP1dB of 21.7/ 21.2 dBm and IIP3 of 38.3/37.4 dBm are accomplished at 0.9/2.45 GHz, respectively. Finally, the switch achieves a RF electrostatic discharge (ESD) rating of 4 kV for the ± 2 kV human body model and 500 V for the ± 200 V machine model. Introduction: Low-cost silicon bulk CMOS technologies have been used ubiquitously for decades for modern wireless communication systems. However, the high power amplifier (PA) and transmit/receive (T/R) switch remain to be the two most critical front-end components to be ultimately integrated to realise a true system-on-chip (SOC) for wireless transceivers. Switches with reasonably low insertion loss (IL), high isolation, linearity, and moderate to high power handling capability that were once only possible in the III-V compound semiconductors such as the GaAs pHEMT have emerged in silicon bulk CMOS [1–6] and silicon- on-insulator (SOI) [7]. In this Letter, we present the performance of an area-efficient CMOS RF single-pole double-throw (SPDT) switch and consider the practical aspects of electrostatic discharge (ESD) protection, integrated switch controllers, as well as laminated packaging. Design techniques including resistive body-floating and unit cell layout optimisation are demonstrated on the 1.8 V thinoxide triple-well devices. Switch design: Illustrated in Fig. 1 are the SPDT switch and switch controller. The switch consists of two series FETs (M1 and M2) and two shunt FETs (M3 and M4). The width of the series devices (324 μm) is chosen to accommodate the IL performance over the frequency range of interest (0.9–2.45 GHz). The shunt device is ∼1/4 the size of the series devices to improve the isolation with a marginal penalty on the IL. The high precision control voltages for the switch are internally generated by an integrated switch controller, which is composed of a bandgap reference, low dropout regulator (LDO), and digital logics. The equivalent circuit of a triple-well FET with biasing for both ONand OFF-state is described in Fig. 2. During ON-state, VSB/VDB is set to 0 V for best IL (no bulk effect) for a given VG. High value unsilicided poly gate resistors (40 kH) are used to improve IL further and mitigate the degradation in power handling capability at high input power [7]. The body-floating resistor (RBF = 25 kΩ) is introduced to ensure that the bulk terminal voltage swing is in accordance with the source/ drain. This also guarantees that the source/drain-to-bulk is reversedbiased to achieve good linearity and avoid excessive capacitive coupling to the substrate. A customised unit cell technique is applied towards the device layout that improves IL by reducing the intrinsic distributed series source/drain resistances and extrinsic source/drain interconnect resistances, as illustrated in Fig. 3a. A 3 × 3 unit cell matrix layout with source/drain sharing to minimise the parasitic capacitance is used for the series switch devices, with finger width (Wf ) of 4 um and nine fingers. During OFF-state, VSB/VDB is biased at 1 V (Fig. 2b) in order to delay the onset of the junction diodes (CSB/CDB), thus improving the power handling capability. Consequently, the VG is 2.8 V for ON-state and 0 V for OFF-state while the source and drain voltages are biased at 1 V (compromise between turn-on of VGD/VGS and gate oxide breakdown for the OFF devices). The Vnwell is biased at the highest potential available (3.4 V) to keep Cpwell–nwell and Cnwell–psub reversed-biased while improving the compression characteristics at high power levels. RF ESD protection is also implemented at the Ant port which is typically exposed and most likely to encounter an ESD event. The reliability issue for a switch design is more susceptible to time-dependent dielectric breakdown (TDDB) which is a strong function of the electric field across the gate dielectric. The diode size and number of diode stacks are trade-offs among the gate oxide reliability, IL due to the diode parasitic capacitance and series resistance, and linearity. In this design, the number of series diode stacks connected anti-parallel to ground is four. The degradation in the IL due to the additional ESD diodes is ∼ 0.07 and ∼ 0.1 dB in simulation at 0.9 and 2.45 GHz, respectively. The core switch area is only 0.02 mm2 while the effective area for the switch controller is ∼ 0.04 mm2, as shown in Fig. 3b. VG VD RBias RG VDD = 3.4 V bandgap Vbg EN TX_EN RX_EN + – – + (25 k) EN Ant VG ESD VD RG CC (40 k) (15 p) Iref RBias LDO TX M1 (324/0.18) M2 (324/0.18) RG 1V 2.8 V RBias VG_TX M3 (90/0.18) M4 (90/0.18) logic and level shifters VG_RX VG V S V V Vpwell_TX S CB RBias S RBias Vpwell_RX (0.3 p) switch controller RX RG VG CB SPDT switch Fig. 1 Simplified block diagram of switch controller and SPDT RG VG RG VG (0 V) (2.8 V) RBiasCGS S (1 V) CSB CGD RBias Ron CDB bulk Cpwell-nwell RBF Cnwell-psub Rnwell Rsub (2.5 k) (25 k) Vpwell (1 V) Vnwell (3.4 V) RBiasCGS D S (1 V) (1 V) CSB RoffCoff CGDRBias bulk CDB (1 V) Cpwell-nwell Cnwell-psub Rsub a D RBF Rnwell (2.5 k) Vpwell (25 k) (0 V) Vnwell (3.4 V) b Fig. 2 Equivalent circuit model of triple-well FET with biasing scheme a ON-state b OFF-state source pwell contact bandgap drain LDO gate nwell contact SPDT CB VDD TX CC CB Ant RX Fig. 3 Customised unit cell layout and chip microphotograph a 3 × 3 unit cell matrix layout of series switch device b Chip microphotograph of SPDT and switch controller breakout Experimental results: The characterisation of the multi-chip module (MCM)-packaged switch was mounted on an evaluation board as shown in Fig. 4. Due to the symmetrical packaged switch design, the measurement data for the TX-to-Ant path and the Ant-to-RX path are nearly identical. Between 900 MHz and 3 GHz, the switch achieves a return loss (RL) > 15 dB at both the TX port and the Ant port, from −20 to 85 °C (Fig. 5a). The measured IL at 25 °C is 0.52 and 0.78 dB at 0.9 and 2.45 GHz, respectively. Under the worst-case temperature (85 °C), the measured IL (Fig. 5b) is 0.59 and 0.89 dB at 0.9 and 2.45 GHz, respectively. This increase in IL at the hot condition is mainly attributed to the mobility degradation of the FET device in strong inversion. The loss associated with the package is ∼0.05 and ∼0.14 dB at 0.9 and 2.45 GHz, respectively. The isolation from TX to RX (TX mode) illustrated in Fig. 5c is > 31 dB while that from Ant to TX (RX mode) is > 22 dB at 2.45 GHz (85 °C). Depicted in Fig. 5d, the measured IP1dB is 21.7 and 21.2 dBm at 0.9 and 2.45 GHz, respectively. The measured IIP3 (two-tone spacing of 1 MHz) is 38.3 and 37.4 dBm at 0.9 and 2.45 GHz, respectively. The switch controller draws an overall current of ∼40 µA from a 3.4 V supply. Finally, the RF ESD test was demonstrated using a handheld mini-zapper (KeyTek TPC-2A) with both human body model (HBM) and machine model (MM) inserts. The switch has successfully achieved a RF ESD rating of > 4 kV and > 500 V for the target ± 2 kV HBM and ± 200 V MM, respectively. Table 1 summarises the performance of prior published CMOS RF SPDT switches. ELECTRONICS LETTERS 11th April 2013 Vol. 49 No. 8 IP1dB of 21.7/21.2 dBm at 0.9/2.45 GHz while satisfying the target RF ESD rating of ± 2 kV HBM and ± 200 V MM. To the best of the author’s knowledge, this packaged CMOS switch has achieved the highest level of integration including the switch control and RF ESD protection among all reported to date. moulding compound Au bondwire L1 L2 L3 die attach adhesive multilayer laminate solder PCB © The Institution of Engineering and Technology 2013 4 October 2012 doi: 10.1049/el.2012.3387 One or more of the Figures in this Letter are available in colour online. A.Y.-K. Chen (Skyworks Solutions, Newbury Park, CA, USA) E-mail: austin.chen@;skyworksinc.com A.Y.-K. Chen: Was also with the Department of ECE, University of Florida, Gainesville, FL USA, and Alcatel-Lucent, Bell Laboratories, Murray Hill, NJ, USA Fig. 4 Packaged switch mounted on PCB 25 15 15 -25 °C 10 25 °C 85 °C 10 0.5 1.0 1.5 2.0 2.5 -25 °C 25 °C 85 °C insertion loss, dB 20 20 1.5 Ant port return loss, dB TX port return loss, dB 25 References 1.0 0.5 5 3.0 0 0.5 1.0 frequency, GHz –30 25 °C 25 °C 85 °C 1.5 2.0 3.0 20 0 –20 –40 IIP3 = 37.4 dBm –60 fundamental IM3 –80 frequency, GHz 2.5 IP1dB = 21.2 dBm 40 Pout, dBm –35 Ant-TX isolation, dB TX-RX isolation, dB –25 1.0 2.0 60 –20 –30 –40 0.5 1.5 frequency, GHz –25 2.5 –35 3.0 0 5 10 15 20 25 30 35 40 45 Pin, dBm Fig. 5 Measured RL, IL, and isolation at different temperatures and linearity characteristic of SPDT switch a b c d TX port RL and Ant port RL IL Isolation IP1dB and IIP3 at 2.45 GHz 1 Huang, F.-J., and O, K.K.: ‘A 0.5-μm CMOS T/R switch for 900-MHz wireless applications’, IEEE J. Solid-State Circuits, 2001, (36), (3), pp. 486–492 2 Huang, F.-J., and O, K.K.: ‘Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on P-silicon substrates’, IEEE J. Solid-State Circuits, 2004, (39), (1), pp. 35–41 3 Li, Z., Huang, F.-J., and O, K.K.: ‘5.8-GHz CMOS T/R switches with high and low substrate resistance in a 0.18-μm CMOS process’, IEEE Microw. Wirel. Compon. Lett., 2003, 13, (1), pp. 1–3 4 Talwalkar, N., Wong, N., Yue, C.P., Guan, H., and S..: ‘Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4 GHz and 5.2 GHz applications’, IEEE J. Solid-State Circuits, 2004, 39, (6), pp. 863–870 5 Yeh, M.-C., Tsai, Z.-M., Liu, R.-C., Lin, K.-Y., Chang, Y.-T., and Wang, H.: ‘Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance’, IEEE Trans. Microw. Theory Tech., 2006, 54, (1), pp. 31–39 6 Xu, H., and and O., K.K.: ‘A 31.3-dBm bulk CMOS T/R switch using stacked transistors with sub-design-rule channel length in floated p-wells’, IEEE J. Solid-State Circuits, 2007, 42, (11), pp. 577–584 7 Tinella, C., Fournier, J.M., Belot, D., and Knopik, V.: ‘A high- performance CMOS-SOI antenna switch for the 2.5–5–GHz band’, IEEE J. Solid-State Circuits, 2003, 38, (7), pp. 1279–1283 Table 1: Performance of prior published CMOS RF SPDT switches Ref. Process Technique Frequency (GHz) IL (dB) This work1,2 0.18 µm CMOS Resistive body-floating 0.9 2.45 0.52 0.78 21.7 21.2 38.3 37.4 MCM Low Rsub 0.9 0.73 18.9 38.2 SOIC Impedance transformation 0.9 2.4 0.97 1.1 26.3 22.7 37.7 29.8 SOIC [1] [2] 0.5 µm CMOS 0.18 µm CMOS IPIdB IIP3 Package (dBm) (dBm) [4]3 0.18 µm CMOS LC substrate biasing 2.4 TX: 1.5 RX: 1.6 28.5 NA Onwafer [5] 0.18 µm CMOS Resistive body-floating 2.4 0.7 21.3 30.3 Onwafer [6] 0.13 µm CMOS Body-floating and feed-forward caps 0.9 TX: 0.5 RX: 1.0 31.3 42 Onwafer 1 Denotes SPDT switch with measured HBM (4 kV) and MM (500 V) ESD ratings Denotes SPDT switch with integrated switch control Denotes SPDT switch with measured HBM (4 kV) ESD rating 2 3 Conclusion: This Letter describes a highly integrated yet area-efficient CMOS RF SPDT switch. The switch achieves an IL of 0.52/0.78 dB and ELECTRONICS LETTERS 11th April 2013 Vol. 49 No. 8