AN-401: MOSFET / IGBT Drivers Theory Applications

Application Note AN-401
INTEGRATED CIRCUITS DIVISION
MOSFET/IGBT Drivers
Theory and Applications
AN-401-R02
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1
Introduction
Modern Power Electronics makes generous use of
MOSFETs and IGBTs in most applications, and, if the
present trend is any indication, the future will see more
and more applications making use of MOSFETs and
IGBTs.
to a critical threshold voltage level VGS(th), before Drain
Current can begin to flow.
Figure 1
SOURCE
M E TA LIZ ATIO N
IGBT derives its advantages from MOSFET and BJT
topologies. It operates as a MOSFET with an injecting
region on its Drain side to provide for conductivity
modulation of the Drain drift region so that on-state
losses are reduced, especially when compared to an
equally rated high voltage MOSFET.
As far as driving the IGBT is concerned, it resembles a
MOSFET and hence all turn-on and turn-off
phenomena comments, diagrams, and Driver circuits
designed for driving MOSFET apply equally well to an
IGBT. Therefore, what follows deals only with MOSFET
models.
1.2
MOSFET Models and Critical Parameters
Figure 1 shows the internal cell structure of a DMOS
MOSFET. As shown, the Gate to Source Capacitance
consists of three components: CP , the component
created by the Gate Electrode over the
P-base region; CN+, created by the overlap of the Gate
Electrode above the N+ source region; and CO, arising
due to the proximity of the Gate Electrode to the source
metallization. In fact, all these are added to yield CGS,
which we call the Gate-to-Source Capacitance. It is this
total value of capacitance that needs to be charged first
2
CG D
N+
RB
N -D R IFT
P -BA S E
C DB
D epletion bound aries
The Gate-to-Drain capacitance, CGD is the overlap
capacitance between the Gate electrode and the
N-drift Drain region. CGD is sometimes referred to as
the “Miller” capacitance, and contributes most to the
switching speed limitation of the MOSFET. The junction
capacitance between the drain to the P-Base region is
CDS. The P-Base region of the MOSFET is shorted to
the N+ source. Figure 2 shows a curve of ID (Drain
Current) versus VGS (Gate Source Voltage). The graph
has a slope ( ID/ VGS) equal to gm, which is called
transconductance.
Figure 2 Power MOSFET Transfer Characteristics
ID
D R A IN C U R R E N T
Due to the absence of minority carrier transport,
MOSFETs can be switched at much higher
frequencies. The limit on this is imposed by two factors:
transit time of electrons across the drift region and the
time required to charge and discharge the input Gate
and “Miller” capacitances.
Cp
CN +
An attempt is made here to review this subject with
some illustrative examples, and with a view to assist
both experienced design engineers and those who are
just initiated into this discipline.
MOSFET and IGBT Technology
Co
G AT E E lectrode
Although sufficient literature is available on
characteristics of MOSFETs and IGBTs, practical
aspects of driving them in specific circuit configurations
at different power levels and at different frequencies
require that design engineers pay attention to a number
of aspects.
1.1
MOSFET Internal Structure
ID
gm =
ID
VGS
VG S
A ctua l
Lin earized
O
V G S (th)
VGS
Please note that the actual relationship between VGS
and ID is shown by the dotted line and it can be
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observed that in the vicinity of VGS(th), the relationship
between VGS and ID is parabolic in nature:
Equation 1.1
ID = K [VGS - VGS(th) ]2
Figure 5 shows another cross-sectional view of a
MOSFET with all these capacitances. In addition, It
also shows the internal body diode and the parasitic
BJT.
However, for Power MOSFETs, it is appropriate to
consider the relationship to be linear for values of VGS
above VGS(th) . The manufacturer’s data sheet value of
VGS(th) is specified at 25°C.
Figure 5 N-Channel MOSFET Internal X-Section
Figure 3 shows a symbol of a N-Channel MOSFET
and an equivalent model of the same with three interjunction parasitic capacitances, namely: CGS , CGD ,
and CDS .
PA R A S ITIC B JT
SOURCE
CGS
N+
N+
P
CDS
N-
C GD
P
N+
Figure 3 MOSFET Symbol and Equivalent Circuit
D R A IN B O D Y
D E P LE T IO N L AY E R
IN T E R N A L
B O D Y D IO D E
D R A IN
D
D
G
G ATE
1.3
G
CGD
RG
1.3.1
R D S (o n )
C DS
CGS
S
S ym b ol of
N -C hannel M O S FE T
S
These are all shown as variable, as they indeed are.
For example CGD decreases rapidly as the Drain to
Source voltage rises, as shown in Figure 4.
Figure 4 CGD Variation With Respect to VDS
CGD
CGD h
C G DI
V DS = VGS
turn-on and turn-off Phenomena
turn-on Phenomenon
To understand the turn-on and turn-off phenomena of
the Power MOSFET, we will use a clamped inductive
switching mode of operation, as it is the most
commonly used.. This is shown in Figure 6 and Figure
7. A model of the MOSFET is shown with all relevant
components, which play a role in turn-on and turn-off
events. As stated above, MOSFET’s Gate to Source
Capacitance CGS needs to be charged to a critical
voltage level to initiate conduction from Drain to
Source. A few words of explanation will help
understand Figure 6 and Figure 7. The clamped
inductive load is depicted by a current source with a
diode, D, connected antiparallel across the inductor,
and the MOSFET’s intrinsic internal Gate resistance,
RGint . As described above, the inter-junction
parametric capacitances (CGS, CGD, and CDS) are
shown, and connected at their proper points. VDD
represents the DC Bus voltage applied to the Drain of
the MOSFET through the clamped inductive load. The
Driver is supplied by VCC referenced by VP, and its
ground is connected to the common ground of VDD and
is returned to the Source of the MOSFET. The output
from the Driver is connected to the Gate of the
MOSFET through a resistor RGext.
V DS
In Figure 4, the high value of CGD is called CGDh ,
while the low value of CGD is termed CGDl.
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Figure 6 MOSFET Being Turned On by a Driver in a
Clamped Inductive Load
Figure 7 MOSFET Being Turned Off by a Driver in a
Clamped Inductive Load
+VD D
+V D D
D
VC C
t
O
i/p
VC C
IG D D
C GD
R G in t
o/p R G ext
Rd r
IG
D R IV ER
D
G
t
O
C DS
IGs
C GS
i/p
D
CG D
R G in t.
R G ext.
Rdr
G
CDS
CGS
S
S
When a positive going pulse appears at the input
terminal of the Driver, an amplified pulse appears at the
output terminal of the Driver with an amplitude VP. This
is fed to the Gate of the MOSFET through RGext . As
one can see, the rate of rise of voltage, VGS, over the
Gate and Source terminals of the MOSFET is
governed by value of the total resistance in series
(Rdr+RGext+RGint) and total effective value of
capacitance (CGS+CGD). Rdr represents the output
source impedance of the Driver. RGext is the resistance
one generally puts in series with the Gate of a
MOSFET to control the turn-on and turn-off speed of
the MOSFET.
The waveforms shown in Figure 8 depict the variation
of these different parameters with respect to time, to
help explain the entire turn-on sequence. In Figure 6
and Figure 7, the free-wheeling diode, D, is assumed
to be ideal with zero reverse recovery current. The
waveforms shown in Figure 8 are based on this
assumption:
From time zero to t1, (CGS+CGDl) is exponentially
charged with a time constant:
T1 = (Rdr + RGext + RGint) x (CGS + CGDI)
referred to as the turn-on delay. Note that between 0 to
t1, as VGS rises, IGS falls exponentially, , since it
essentially functions as an RC Circuit.
After time t1, as the gate-to-source voltage rises above
VGS(th), MOSFET enters a linear region as shown in
Figure 2. At time t1, drain current starts flowing, and
the drain to source voltage VDS, is still at VDD . From
the time t1 to t2, ID increases rapidly and as shown in
Figure 4, CGD increases from CGDl to CGDh and the
current available from the driver is diverted to charge
this increased value of CGDh . As outlined in Figure 8,
between t1 and t2, the drain current increases linearly
with respect to VGS . At time t2, the gate to source
voltage enters the Miller Plateau level and the drain
voltage begins to fall rapidly, while the MOSFET is
carrying full load current. During the time interval, t2 to
t4, VGS remains clamped to the same value as does
IGS . This is referred to as the Miller Plateau Region.
During this interval, most of the drive current available
from the driver is diverted to discharge the CGD
capacitance followed by a rapid drop of drain to source
voltage. Only the external impedance in series with
VDD limits the drain current.
until the gate-to-source voltage reaches VGS(th). In this
time period, neither the drain voltage nor the drain
current are affected, i.e. drain voltage remains at VDD
and the drain current is zero. This is also
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AN-401
Figure 8 MOSFET turn-on Sequence
Figure 9 MOSFET turn-on Sequence Showing the Effect
of Body Diode Reverse Recovery
Vp
O /P O F D R IV ER
ID
D R AIN C U R R E N T
VDS
O /P O F D R IV E R
TIM E = t
VGS
(b )
A1
V G S (th )
TIM E = t
A2
I G (t)
(c)
Ifid
TIM E = t
V D S (t)
(d )
V DS
V D S (o n)
TIM E = t
I D (t)
(0 ,0) t1 t2 t3
(e )
ID
t4
TIM E = t
Beyond t4, VGS begins to rise exponentially again with
a time constant:
T2 = (Rdr + RGext + RGint) x (CGS + CGDh)
During this time interval the MOSFET approaches its
final VGS value effectively determining it’s RDS(on). At
this point VDS attains its lowest value as determined by:
VDS = IDS x RDS(on)
In Figure 8, A1 outlines the area of the IG curve from
time t1 to t2. This represents the charge on (CGS
+CGD), as it is the integration of the gate current IG over
a time period. Similarly, A2 represents the charge on
CGDfrom t2 to t3, during which time the Miller effect is
predominant.
If one considers the diode D not to be ideal, then the
reverse recovery of the diode will influence the turn on
behavior. Thus, the waveforms would look like what is
depicted in Figure 9. As the diode undergoes reverse
recovery, you can see a hump in the waveform of VGS
as well as ID which occurs at approximately time t2.
R02
TIM E = t
G AT E -S O U R C E V O LTA G E
)
V G S (t)=V p (1 -e -t/T2 )
DRAIN SOURCE VOLTAGE
IG
-t/T1
TIM E = t
G AT E C U R R E N T
V G S (th )
V G S (t)=V p (1 -e
Ifid(t)
TIM E = t
D R A IN S O U R C E V O LTA G E
VG S
(a )
V D S (t)
V D S (on )
TIM E = t
D R A IN C U R R E N T
G AT E C U R R E N T G AT E -S O U R C E V O LTA G E
VDR
Vp
VDR
I D (t)
(0 ,0) t1
1.3.2
t2 t3
t4
TIM E = t
turn-off Phenomenon
The turn-off phenomenon is shown in Figure 10. As
can be expected, when the output from the driver drops
to zero thereby turning off the MOSFET, VGS initially
decays exponentially from time 0 to t1 at the rate
determined by time constant:
T2 = (Rdr + RGext + RGint) x (CGS + CGDh)
However, after t4, it decays exponentially at the rate
determined by:
T1 = (Rdr + RGext + RGint) x (CGS + CGDI)
Please note that the first delay in the turn off process is
required to discharge the CISS capacitance from its
initial value to the Miller Plateau level. From t = 0 to t =
t1, the gate current is flowing through the CGS and CGD
capacitances of the MOSFET. Notice that the drain
current ID remains unchanged during this time interval,
but the drain source voltage, VDS, just begins to rise.
From t1 to t2 , VDS rises from ID x RDS(on) towards its
final off state value of VDS(off), where it is clamped to
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the DC bus voltage level by the diode D. This time
interval also corresponds to the Miller effect region as
mentioned above in regards to the gate voltage, which
results in a constant VGS. During the time interval t2 to
t3, the VGS begins to fall further below VGS(th). CGS
discharges through any external impedance between
the gate and source terminals. The MOSFET is in its
linear region and the drain current ID, drops rapidly
towards a zero value. VDS was already at its off state
value, VDS(off) at the beginning of this interval therefore
at t4, the MOSFET is fully turned off.
Figure 10 MOSFET turn-off Sequence
VG S
V G S (th )
TIM E = t
e -t/T2
e -t/T1
TIM E = t
G AT E C U R R E N T
+V E
-V E
Effective COSS = 2(COSS specified)(VDS.specified/VDS.off)1/2
1.4
Power Losses In Drivers And Driven
MOSFET / IGBT
To determine the power loss in a Driver while driving a
power MOSFET, refer to equation 1.4 and the gate
charge QG vs. VGS curve for different values of VDS(off)
found in the MOSFET’s data sheet.
VCC is the Driver’s supply voltage, QG is the total gate
charge of the MOSFET being driven, and fsw is the
switching frequency. Clearly then, it is prudent then to
choose a MOSFET with lower value of QG.
As shown in Figure 8, Figure 9, and Figure 10 in
regards to MOSFET switching losses, there are some
short time-intervals during which a finite VDS and ID coexist. When this happens during turn-on, the actual
integration:
TIM E = t
Equation 1.5
VDS(t)ID(t)dt
D R A IN C U R R E N T
is defined as turn-on switching energy loss. Likewise,
during turn-off, when finite values of ID and VDS
coexist, the integration of:
Equation 1.6
VDS(t)ID(t)dt
D R A IN S O U R C E V O LTA G E
VDS
Effective CGD = 2(CRSS specified)(VDS.specified/VDS.off)1/2
Equation 1.4
IG
ID
Equation 1.3
PGATE = VCC x QG x fsw
G AT E -S O U R C E V O LTA G E
V DR
O /P O F D R IV E R
LEVEL Vp
As CGD and CDS capacitances are dependent on VDS ,
the data sheet values are valid only at specified test
conditions. Equation 1.3 can be used to calculate the
average effective values of these capacitances.
0 t1 t2
TIM E = t
t3
t4
TIM E = t
is called turn-off switching energy loss in a MOSFET.
Amongst the responsible parameters in determining
these switching energy losses, CISS, COSS, and CRSS
affect the turn-on and turn-off delays as well as the
turn-on and turn-off times.
For an IGBT, it would be similarly shown that:
The manufacturer’s Data Sheet for the MOSFET gives
values of CISS, CRSS, and COSS. The following
relationships help relate these to inter-junction parasitic
capacitances described so far:
Equation 1.2
CGD = CRSS
CGS = CISS - CRSS
CDS = COSS - CRSS
6
Equation 1.7
VCE(t)IC(t)dt
represents the switching energy loss. The time interval
for these integrals would be the appropriate time during
which finite values of ID and VDS or VCE and IC coexist
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in a MOSFET or IGBT respectively. Average switching
energy lost in the device can be computed as follows:
Equation 1.8
MOSFET: Ps = 1/2 • VDS • ID • fsw • (ton + toff)
Equation 1.9
IGBT: Ps = 1/2 • VCE • IC • fsw • (ton + toff)
The main emphasis in modern Power Electronics is to
reduce the total losses dissipated in devices and
subsystems, strive for higher operating efficiency and
achieving more compact designs, thereby reducing
volume and weight of resultant systems.Since
operation at higher and higher switching frequencies is
now a necessity, and, as a result, switching losses
predominate in the power-loss-budget in
semiconductor switches. Reducing switching losses
then becomes the single most crucial goal. Keeping
this goal in mind, the entire line of IXYS MOSFET/IGBT
Drivers are designed to facilitate the design of drive
circuits that yield fast rise and fall times.
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2
Types of Drivers
2.1
IC Drivers
2.3
Although there are many ways to drive MOSFETs and
IGBTs using hard wired electronic circuits, IC Drivers
offer convenience and features that attract designers.
The foremost advantage is compactness. IC Drivers
intrinsically offer lower propagation delay. As all
important parameters are specified in an IC Driver,
designers need not go through the time-consuming
process of defining, designing, and testing circuits to
drive MOSFET/IGBTs.
2.2
Techniques Available to Boost Current
Outputs
A totem-pole stage, with N-Channel and P-Channel
MOSFETs, can be used to boost the output from an IC
Driver. The disadvantage is that the signal is inverted,
and a “shoot-through” condition may exist when the
common gate voltage is in transition.
A totem-pole arrangement using matched NPN-PNP
transistors, on the other hand, offers many advantages,
while boosting the output currents from IC Drivers. The
shoot-through phenomenon is absent in this case. The
pair of transistors protects each other’s base-emitter
junctions and handles current surges quite well. One
such arrangement is shown in Figure 17. Here Q1 is a
NPN transistor, while Q2 is a matched PNP transistor
with appropriate collector current rating and switching
speed to satisfy the drive requirement for the highpower IGBT. Another feature added is a negative Ve
bias (-Ve) for guaranteed fast switch turn-off even in an
electrically noisy environment. This is done by utilizing
a power supply with +15 and –5 Volts outputs, whose
common ground is connected to the IGBT emitter.
IXDD609 is a very high speed IC Driver with extremely
short rise and fall times and propagation delays. Its
VCC rating is 35VDC and can actually deliver 9A peak
output current. The arrangement shown in Figure 17
does a few more things in addition to boosting the
output current still higher. It allows one to choose
different turn-on and turn-off times by selecting
different values of Rgon and Rgoff. It allows for
incorporating –Ve bias for reasons explained above. A
pair of 18V Zener diodes with their cathodes connected
together protects the gate-emitter junction of the IGBT
from voltage spikes.
8
Techniques To Generate –Ve Bias During
turn-off
The importance of –Ve bias during turn-off for
practically all semiconductor switches cannot be
overemphasized, as one may recall from the days of
Bipolar transistors. This helps to quickly remove any
charge on the CGS and CGD in the case of MOSFETs
and IGBTs, thus considerably accelerating turn-off.
It is important to understand that turn-on speed of a
MOSFET or IGBT can be increased only up to a level
matched by the reverse recovery of rectifiers or diodes
in a power supply, because in an inductive clamped
load (most common), the turn-on of a MOSFET or
IGBT coincides with the turn-off (or reverse recovery
completion) of the rectifier diode. Any turn-on faster
than this does not help. Too fast a turn-on could also
cause oscillation in the drain or collector current.
However, it is always beneficial to have a driver with an
intrinsic low turn-on time, and then being able to tailor
this with a series gate resistor.
The turn-off phenomenon, on the other hand, does not
have to wait for any other component in the subsystem.
It is here that any enhancement technique can be
utilized. Although IXYS drivers by themselves feature
extremely low turn-on and turn-off times, an
arrangement to provide –Ve bias during turn-off helps
provide for a faster turn-off, and also prevents a false
turn on even in an electrically noisy environment.
Figure 21 shows how to generate –Ve bias in a
transformer coupled drive circuit arrangement. Here a
Zener diode can be chosen of appropriate voltage for
giving that much –Ve bias (plus one diode drop) during
turn-off. Another unique feature of the circuit in Figure
21 is its ability to maintain an exact pulse waveform
across the gate and source. As shown in Figure 19, an
isolated DC to DC converter with outputs of +15V and
–5V is used to power the IXDD614. When the isolated
ground of this DC to DC Converter in connected to the
emitter of the IGBT being driven, –5V of –Ve bias
voltage during provides for a faster turn-off time.
2.4
Need for Under-Voltage Protection
Figure 2 shows depicts a typical transfer
characteristics (ID vs. VGS) of a MOSFET. As can be
seen for values of VGS below VGS(th) the drain current
is negligible, but in this vicinity, the device is in its linear
(Ohmic) region and concurrent application of large
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values of VDS could cause a considerable amount of
localized heating of the junction. In short, when a
MOSFET is being used as a switch, any operation in its
linear region could cause overheating or device failure.
Bringing the MOSFET quickly into saturation from its
off-state is the driver’s function. If VCC falls below the
minimum required value, linear operation can ensue to
the disadvantage of the MOSFET. Note, however that
most PWM ICs, controller ICs and microcomputer ICs
have this protection feature built-in, and, if sharing the
same VCC bus, the driver IC gets the benefit of this
function being implemented elsewhere in the
subsystem.
2.5
overload protection. When a short circuit/overload
occurs, the forward voltage drop of the IGBT (VCE) rises
to disproportionately high values. One must ignore the
initial turn-on rise in VCE, when output from the driver
has still not risen to a high enough value. Nevertheless,
when VCE rises to a level of, say, 7 Volts, in presence of
sufficient gate drive voltage, it means the collector
current IC has risen to a disproportionately high value,
signaling overload. When a voltage level higher than
6.5V is detected, resulting in soft turn-off of the IGBT.
Figure 19 shows how the de-sat feature can be wired
into a total driver circuit, using also other features, such
as opto-isolation and –Ve turn-off bias.
Overload / Short Circuit Protection
Any operation of the MOSFET/IGBT outside the Safe
Operating Area (SOA) could cause overheating and
eventual device failure, and should be prevented by an
electronic active monitoring and corrective
arrangement.
Load or current sensing could be done by either a Hall
Effect Sensor or by a Shunt resistor in series with
source/ emitter terminal. The voltage picked up, which
is proportional to current, is low pass filtered and then
compared to a preset limit. The comparator output
could initiate turn-off of MOSFET/IGBT. A circuit to
detect an overload/short circuit is shown in Figure 19,
where the output FAULT will go low when it occurs.
All IXDD-series drivers have an ENABLE pin, which,
when driven low, say, by the FAULT output from this
comparator, puts the final N-channel and P-channel
MOSFETs of the IXDD Driver in their TRISTATE mode.
This not only stops any output from the driver, but also
provides an environment for implementing a “soft turnoff”. To accomplish this,a resistor of sufficient value is
connected from the gate to the source/emitter of the
MOSFET. As a result, the CGS gets discharged through
this resistor and, depending on the value of the
connected resistor, a soft turn-off of any duration can
be achieved. Another way, as shown in Figure 12, is to
use a signal MOSFET, Q1, to pull down the gate when
a short circuit is detected. The resistor in series with
this signal MOSFET determines the time duration of
this soft turn-off. Soft turn-off helps protect the IGBT/
MOSFET from any voltage transients generated due to
LdIC/dt (or LdID/dt) that could otherwise bring about
avalanche breakdown. The PC board layout for this
circuit is shown in Figure 13.
For an IGBT, de-sat detection (de-sat = desaturation of
forward voltage drop) is a method used for short circuit/
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3
High Side Driving Techniques
3.1
Employing Charge-Pump and Bootstrap
Methods
The Bootstrap Technique as shown in Figure 15. The
basic bootstrap building elements are the level shift
circuit; bootstrap diode, DB; level shift transistor, Q1;
bootstrap capacitor, CB; and IXDD609 or IXDD614.
The bootstrap capacitor, IXDD609/IXDD614 driver, and
the gate resistor are the floating, source-referenced
parts of the bootstrap arrangement. The disadvantages
of this technique are longer turn-on and turn-off delays,
and 100% duty cycle is not possible. Also, the driver
has to overcome the load impedance and negative
voltage at the source of the device during turn-off.
3.2
Achieving Galvanic Isolation By Using
Optocouplers To Drive Upper MOSFET/
IGBT
For driving high-side MOSFET/IGBT in any topology,
optocouplers can be used with the following
advantages:
• Optocouplers provide a very high isolation voltage: 2500V to 5000V of isolation is achievable
with careful selection.
• Optocouplers can handle signals from DC to several MHz.
• Optocouplers are easily interfaced to controller
ICs, micro-computers, or any PWM IC.
One disadvantage is that the optocoupler adds its own
propagation delay. Another disadvantage is that a
separate, isolated power supply is required to feed the
output side of the optocoupler and the driver connected
to it. However, isolated DC to DC Converters with a few
thousand Volts of isolation are readily available. These
can be used to supply isolated and regulated +Ve 15V
and –Ve 5V to the output side of the optocoupler and
the driver IC for driving upper MOSFET/IGBT as is
shown in Figure 19 and Figure 20. As can be seen, an
identical chain of optocouplers, drivers, and DC to DC
converters are used for even lower IGBTs. This is done
to guarantee identical propagation delays for
allincoming IGBT gate signals.
3.3
Use Of Transformers To Obtain Galvanic
Isolation in Driving Upper MOSFET/IGBT
Using transformers to achieve galvanic isolation is a
very old technique. Depending on the range of
frequencies being handled and power rating (voltage
and current ratings and ratios), transformers can be
10
designed to be quite efficient. The gate drive
transformer carries very small average power, but
delivers high peak currents at turn-on and turn-off of
the MOSFET/IGBT.
While designing or choosing a gate drive transformer,
keep the following points in mind:
• The average power of the transformer can accept
should be used as a design guideline. A margin
of safety should be taken into account, keeping in
mind the maximum volt-second product and
allowing for worst case transients with maximum
duty ratio and maximum input voltage possible.
• Employing bifilar winding techniques to eliminate
any net DC current in any winding. This is to
avoid core saturation.
• If operation in any one quadrant of B-H loop is
chosen, care should be taken for resetting the
core.
Advantages of employing transformers for Gate Drive
are:
• There is no need for any isolated DC to DC Converter for driving an upper MOSFET/IGBT .
• There is practically no propagation delay time in a
transformer to carry signals from primary side to
the secondary side.
• Several thousand volts of isolation can be built-in
between windings by proper design and layouts.
The disadvantages of using transformers for Gate
Drive are:
• They can be used only for AC signals.
• Large duty ratios cannot be handled by the transformer without being saturated by net DC, unless
AC coupling capacitors are employed in series.
Two examples of gate Drive circuits, using transformers
follow. In Figure 18, a phase shift controller outputs its
signals to the IXDD604 dual drivers, which in turn, feed
the transformers. The secondary windings of these
transformers are coupled to the Gates of upper and
lower MOSFETs in an “H” Bridge topology. Figure 21
shows another transformer coupled gate drive circuit
employing a DC restore technique to maintain the
same waveshape as the original signal with the added
feature of -Ve bias offered using a Zener in series with
a fast diode across the secondary.
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4
IXYS Line of MOSFET and IGBT Drivers
IXYS offers the following MOSFET/IGBT drivers:
•
•
•
•
•
4.1
IXD_602: Dual 2A, Ultrafast Driver
IXD_604: Dual 4A, Ultrafast Driver, w/Enable
IXD_609: 9A, Ultrafast Driver, w/Enable
IXD_614: 14A, Ultrafast Driver, w/Enable
IXD_630: 30A, Ultrafast Driver, w/Enable
General Remarks About IXD_600 Series Of
Drivers
The most important strength of these drivers is their
ability to provide the high currents needed to
adequately drive today’s and tomorrow’s large size
MOSFETs and IGBTs. This is made possible by
devoting a large portion of the silicon die area to
creating a high current (NMOS and PMOS) output
stage. Another important feature of these drivers is that
there is no cross conduction, thus giving almost 33%
lower transition power dissipation.
In addition, some of these Drivers incorporate a unique
facility to disable the output by using an ENABLE pin.
When this pin is driven LOW in response to detecting
an abnormal load current, the driver output enters its
tristate (high impedance state) mode, and a soft turnoff of the MOSFET/IGBT can be achieved. This helps
prevent damage that could occur to the MOSFET/IGBT
due to a LdI/dt overvoltage transient, if it were to be
switched off abruptly, “L” representing the total
inductance in series with Drain or Collector. A
suggested circuit to accomplish this soft turn off upon
detecting overload or short circuit is shown in Figure
12. It is also possible to do this by an independent
short circuit/overload detect circuit, which could be a
part of the PWM or other controller IC. All one needs to
do is to take an output signal (FAULT) from such a
circuit, and feed it into the ENABLE pin of the driver. A
resistor, RP ,connected across gate and source or gate
and emitter (as the case may be) would ensure soft
turn-off of the MOSFET/IGBT, turn-off time being equal
to RP(CGS + CGD)
Detailed specifications of these IXD_600 series of
drivers are available on IXYS’s web site:
http://www.ixysic.com/Products/IGBT-MOSFETDvr.htm
4.1.1
IXD_604
IXD_604 is a dual 4A driver, which is useful in many
circuits employing two MOSFETs or IGBTs. It could
also be used for two MOSFETs/IGBTs connected ina
phase leg configuration. While using high voltage DC
R02
supplies for driving the phase leg, H-Bridge, or 3-phase
bridge circuits, some technique for achieving galvanic
isolation of the upper MOSFET/IGBT drivers is
required, in addition to making a provision for the
isolated power supplies.
Figure 18 shows an interesting application for
IXDD604 in a phase shift PWM controller application,
in which galvanic isolation is obtained by using ferrite
core gate drive transformers. Note that this controller
operates at a fixed frequency. Turnoff enhancement is
achieved by using local PNP transistors.
IXDD604 provides a simple answer for driving a vast
number of low and medium current MOSFETs and
IGBTs.
4.1.2
IXD_609 AND IXD_614
The IXD_609 is eminently suitable for driving higher
current MOSFETs and IGBTs, howeverthe IXD_614
can drive larger size MOSFET/IGBT Modules. Many
circuit schematics applying these in various topologies
are possible, and some of these are shown at the end
of this application note.
The 5-pin TO-263 surface mount version can be
soldered directly on to a copper pad on the printed
circuit board for better heat dissipation. It is possible
then to use these high current drivers for very high
frequency switching application, driving high current
MOSFET modules for a high power converter/inverter.
Figure 11 shows a basic low side driver configuration
using the IXDD609 or IXDD614. C1 is used as a
bypass capacitor placed very close to pins #1 and #8 of
the driver IC. Figure 16 shows a method to separately
control the turn-on and turn-off times of the MOSFET/
IGBT. turn-on time can be adjusted by Rgon, while the
turn-off time can be varied by Rgoff. The diodes in
series are fast diodes with a low forward voltage drop.
The 18V, 400mW Zener diodes protect the gate-emitter
junction of the IGBT. When laying out a PCB, the trace
length between pins #6 and #7, and the IGBT gate pins
should be as short as possible. Also, providing a
generous copper surface for a ground plane helps
achieve fast turn-on and turn-off times without creating
oscillation in the drain/collector current.
Figure 16 also shows another arrangement, and
includes a method for faster turn-off using a PNP
transistor placed very close to the MOSFET gate and
source. It is a good practice to tie the ENABLE pin of
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INTEGRATED CIRCUITS DIVISION
drivers to VCC through a 10k resistor. This ensures
that the driver always remains in its ENABLED mode,
except when driven low due to a FAULT signal. Again,
this FAULT signal puts these two drivers into their
TRISTATE output mode.
Figure 17 shows a method to boost output from
IXDD609 to a much higher level for driving a very high
power IGBT module. Here the turn-on and turn-off
times can be varied by choosing different values of
resistors, Rgon and Rgoff. To provide a –Ve bias of 5V,
the IGBT emitter is grounded to the common of +15V
and
-5V power supplies, which feeds +15V and –5V to the
IXDD609. Notice that the incoming signals must also
be level shifted.
When this happens, notice that IXDD614 offers a -Ve
bias of -5V to guarantee turn-off conditions, even in the
presence of electrical noise. -5V is applied to the gate
of each IGBT during turn-off even under normal
operating conditions. After the fault is cleared, the
microcomputer can issue a RESET signal for resuming
normal operation.
Figure 19 shows an IXDD614 driving one IGBT of a
Converter Brake Inverter (CBI) module. Here all
protection features are incorporated. For high
temperature cutoff, a bridge circuit is used with the CBI
module’s thermistor. Comparator U3 compares the
voltage drop across the thermistor to the stable voltage
from the Zener diode. P1 can be used to preset the
cutoff point at which the comparator’s output goes low.
This is fed into the microcomputer as an OVERTEMP
signal.
Short circuit protection is provided by continuously
monitoring the voltage drop across a SHUNT. Note that
one end of SHUNT is connected to the power supply
ground GND1. The voltage picked up from this SHUNT
is amplified by a low noise op-amp, and is then
compared to the stable voltage from the same Zener.
When a short circuit occurs, the comparator output
(FAULT) goes low. 1% metal film resistors are used
throughout in both these circuits to ensure precision
and stability. C3 and C4 help in offering low-pass
filtering to avoid nuisance tripping.
Principle of DESAT sensing for detecting overload on
an IGBT has been explained before, see “Overload /
Short Circuit Protection” on page 9. In the case of
an AC Motor Drive, each IGBT has to be protected
from overload using separate DESAT sensing. Figure
19 and Figure 20 show the connection for each IGBT.
DESAT sensing is done on the isolated side of each
optocoupler, while the resultant FAULT signal is
generated on the common input side with respect to
GND1. Each FAULT signal is open-collector type and
hence can be tied together with other FAULT signals
from other optocoupler or from other comparators. The
microcomputer will stop output drive signals when
either the FAULT or the OVERTEMP signal goes low.
12
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5
Practical Considerations
When designing and building driver circuits for
MOSFETs and IGBTs, several practical aspects have
to be taken into consideration to avoid prevent voltage
spikes, oscillation or ringing, and false turn-on. More
often than not, these are a result of improper or
inadequate power supply by-passing, layout and
mismatch of driver to the driven MOSFET/IGBT.
As we now understand, turning a MOSFET or an IGBT
on and off amounts to charging and discharging large
capacitive loads. Suppose we are trying to charge a
capacitive load of 10,000 pF from 0VDC to 15VDC
(assuming we are turning on a MOSFET) in 25 ns,
using the IXDD614, which is a 14A, ultra high speed
driver.
I = VxC / t
I = [(15-0)x10000x10-12 / 25x10-9] = 6A
I = 6A
Equation 5.1
What this equation tells us is that current output from
the driver is directly proportional to the voltage swing
and/or the load capacitance, and inversely proportional
to rise time. Actually the charging current would not be
steady, but would peak around 9.6A, well within the
capability of IXDD614. However, IXDD614 will have to
draw this current from its power supply in just 25 ns.
The best way to guarantee this is by putting a pair of
by-pass capacitors (of at least 10 times the load
capacitance) of complementary impedance
characteristics in parallel, very close to the VCC pin of
IXDD614. These capacitors should have the lowest
possible ESR (Equivalent Series Resistance) and ESL
(Equivalent Series Inductance). One must keep the
capacitor lead lengths to the bare minimum.
Another very crucial point is proper grounding. Drivers
need a very low impedance path for current return to
ground, to avoid ground loops. The three paths for
returning current to ground are:
• Between IXDD614 and the logic driving it.
• Between IXDD614 and its own power supply.
• Between IXDD614 and the source/emitter of the
MOSFET/IGBT being driven.
All these paths should be extremely short in length to
reduce inductance and be as wide as possible to
reduce resistance. Also, these ground paths should be
kept distinctly separate to avoid returning ground
current from the load to affect the logic line driving the
IXDD614. A good method is to dedicate one copper
plane in a multilayered PCB to provide a ground
R02
surface. All ground points in the circuit should return to
the same physical point to avoid generating differential
ground potentials.
With desired rise and fall times in the range of 25 to
50ns, extreme care is required to keep lengths of
current carrying conductors to the bare minimum.
Since every inch of length adds approximately 20 nH of
inductance, a dI/dt of 240 Amps/microsecond (used in
the example calculation for Equation 5.1) generates a
transient LdI/dt voltage of 4.8V per inch of wire length,
which subtracts from the driver’s output. The real effect
will be a significant increase in rise time for every tiny
increase in conductor length from the output pin of the
driver to the gate lead of the MOSFET/IGBT. For
example, one extra inch of conductor length could
increase rise time from 20ns to 70ns in an ultra high
speed gate drive circuit. Another detrimental effect of
longer conductor length is transmission line effect and
resultant RFI/EMI.
It is prudent to also keep in mind the fact that every
MOSFET/IGBT has some inductance depending on
the package style and design. The lower this value, the
better is the switching performance, as this inductance
is, in effect, in series with the source/emitter, and the
resulting negative feedback increases switching times.
IXYS MOSFETs and IGBTs are housed in packages
that have extremely low intrinsic inductance.
When using a driver IC for any application, it is also
necessary to compute the power dissipated in the
driver for a worst-case scenario. The total power
dissipated in the driver IC is the sum of the following:
• Capacitive load power dissipation;
• Transition power dissipation;
• Quiescent power dissipation.
For all members of the IXD_609 series of drivers,
transition power dissipation is absent due to a unique
method (patent pending) of driving the output Nchannel and P-channel MOSFETs that practically
eliminates cross conduction.
As described earlier, see “Power Losses In Drivers
And Driven MOSFET / IGBT” on page 6, a MOSFET/
IGBT driver incurs losses. The formula to calculate the
power loss in a driver is:
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Equation 5.2
PD(on) = D x ROH x VCC x Qg x fsw
ROH + RGext + RGint
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INTEGRATED CIRCUITS DIVISION
Equation 5.3
PD(off) = (1-D) x (ROL x VCC x Qg x fsw)
ROL + RGext + RGint
where:
•
•
•
•
ROH = Output resistance of driver @ output High
ROL = Output resistance of driver @ output Low
fsw = Switching frequency
RGext = resistance kept externally in series with
gate of MOSFET/IGBT
• RGint = Internal mesh resistance of MOSFET/
IGBT
• D = Duty Cycle (Value between 0.0 to 1.0)
• Qg= Gate Charge of MOSFET/IGBT
If one increases fsw to 500kHz for a DC to DC
converter application, keeping other parameters the
same as above, now the dissipation would be 569mW.
Again we are still within the dissipation limit of 231mW.
Another example: A boost converter, using IXFK55N50
at VDS=250VDC and at ID=27.5A. Assume that
fsw=500kHz and VCC=12 V. From the curve of Gate
Charge for the IXFK55N50 in its data sheet, one can
determine that Qg=370nC. Set RGext=1. We use
IXDD614YI or IXDD614CI here, both of which can
dissipate 12W. Here, the maximum value of ROH=1.5,
ROL=1.2 . Substituting the above values in the
equation, the power dissipation is computed to be:
PD = 1.5 x 12 x 370 x 10-9 x 500000
1.2 +1
Total loss PD = PD(on) + PD(off)
PD = 1.51W
Note also that, in general, RGint is small and can be
neglected, and that ROH = ROL for all IXD_600 series
drivers. Consequently, if the external turn-on and turnoff gate resistors are identical, then the total driver
power dissipation formula simplifies to:
Equation 5.4
PD = PD(on) + PD(off) = ROH x VCC x Qg x fsw
For the third example, consider driving the large size
MOSFET module, VMO 580-02F with IXD_630YI, at
fsw=250kHz. Let VCC=10V, ROH=0.17,ROL=0.16,
RGext=0. From the data sheet: Qg=2750nC at
VCC=10 V. Substituting:
PD = 0.17 x 10 x 2750 x 10-9 x 250000
0.16 + 0
PD = 7.3W
ROL + RGext
As an example:
• Assume that we are driving an IXFN200N10P for
a telecom power supply application or for a UPS/
Inverter application at a switching frequency of 20
kHz.
• RGext = 4.7 Ohms and gate supply voltage is 10V.
In the IXDD609 Data sheet, we read the value of
ROH=2(max) and ROL=1.5(max). For Qg, refer to
the data sheet for the IXFN200N10P from
www.ixys.com, and go to its Gate Charge vs. VGS
curve. Look for the value of Qg at VGS=10V. You can
read it as approximately 235nC. Substituting these
values into Equation 5.4 yields:
PD = 2 x 15 x 235 x 10-9 x 20000
1.5 + 4.7
PD = 22.74mW
IXDD630YI (TO-263) or IXDD630CI (TO-220) can
easily drive this load provided adequate heatsinking
and proper air flow are maintained. Comments above
for mounting TO-263 and TO-220 packages apply here
as well. For derating use 0.1W/°C. So for an ambient
temperature of 50°C, the answer is 2.5 W. As the limit
of IXDD630YI or IXDD630CI is 12 W, subtracting 2.5W
from this yields 9.5W; therefore, 7.3W is possible with
or without a proper heat sink. Thermal impedance
(junction to case) is 0.55°C/W for TO-263 and TO-220,
hence a rise in case temperature should be within limit.
If we increase VCC to 15V, then conduction losses in
the MOSFET could reduce due to lower RDS(on), but
obtaining the same rise and fall times will incur more
power loss in the driver due to increased VCC and Qg.
If that happens, the approach described in Figure 17
can be employed.
Assuming an ambient temperature of 50°C in the
vicinity of the IXDD609PI, the power dissipation
capability of IXDD609PI must be derated by 8mW/°C,
which is 200mW. The maximum allowable power
dissipation at this temperature becomes 1000200=800mW. However, as calculated above, we will be
dissipating only 22.74mW, so we are well within the
dissipation limit of 777.26mW.
14
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6
Conclusion
With proliferating applications of modern power
electronics worldwide, faster, more efficient and more
compact MOSFETs and IGBTs are replacing older
solid state and mechanical devices. The design of
newer and more efficient techniques to turn these solid
state devices on and off is a subject that requires
thorough study and understanding of the internal
structure and dynamic processes involved in the
working of MOSFET/IGBTs.
With the advent of IC drivers for these fast MOSFET/
IGBTs, the designer is relieved of the tedious task of
designing elaborate driver circuits. Nevertheless,
understanding these newer ICs, their strengths and
limitations, is of paramount importance. Different
configurations for particular topologies call for specific
application knowledge. Illustrations are the best way to
explain theory and applications of these IC drivers.
Practical use of these IC drivers calls for great care for
achieving near theoretical results.
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7
References:
1. B. Jayant Baliga, “Power Semiconductor Devices”,
PWS Publishing Company, Boston, MA (1996)
2. Ned Mohan, Tore M. Undeland, William P. Robbins:
“POWER ELECTRONICS: Converters, Applications
and Design”, John Wiley & Sons, New York (1994)
3. Power Supply Design Seminar - 2001 series,
Unitrode Products from Texas Instruments.
16
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INTEGRATED CIRCUITS DIVISION
Figure 11 Using IXDD609 or IXDD614 to Drive an IGBT
H .V.D C
L
O
A
D
+1 5V D C
V
R1
IN PU T
C1
TIM E
3
IC 2
CS
G
6
4
C
D1
Q
RG
5
ZD 1
ZD 2
Rp
RS
E
C 1,C 3 : 22 M FD , 25 VD C Tantalu m capacitors
C 2 : 220 0 M F D , 35V D C E lectrolytic capacitors
T1 : 2 20 VA C to 15-0-1 5 VA C , 15VA co ntrol transfo rm er
110VA C TO 1 5-0-15
Q : IX LF19 N 250
IC 1 : 7815 R egu lator
+1 5V D C
IC 2 : IX D D 609 or IXD D 614
IC 1
D 1 : IN 5817
+ C2
D 2,D 3 : IN 4002
C3
ZD 1,Z D 2 : 18V, 40 0M W Z E N E R S
R G 1 : 3 .3 ohm s to 27 ohm s
dep endin g on Turn-O N speed
R p : 2K 2, ¼ W, 5%
C s,R s : S nub ber n etw ork to redu ce IG B T sw itching
losses. Valu e depends upon fsw. Su ggest:
C s=0.1 M FD , R s=10 to 33 ohm s
R 1 : 10K , ¼ w
D2
C .T.
T1
8
7
1
2
D3
Figure 12 Soft turn-off Evaluation Circuit for IXDD609 and IXDD614
V CC : 4.5V D C to 35V D C
1
I/P
2
3
4
R5
U5
U4
Ld= 10 H
I
X
D
D
6
1
4
8
7
6
5
+
C9
U5
R9
2
U2
U5
C3
1
R02
1
781 5
+ C1 +
2
C2
D2
R s=0.005 O hm
+15V
R4
T1
M O SFET
MODULE
VM O 580 -0 2F
Q1
U2
M
A
I
N
S
R d=0.1 O hm
R7
R6
C7
D1
VDC
3
+
C2
+15V TO
ALL IC s
LM -317
2
+
U3
-
Ls=20nH
(R epresenting
stray inductance)
5
C4
4
3
R2
R3
Z1
P2
R1
P1
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INTEGRATED CIRCUITS DIVISION
Bill of Materials for Figure 12
Resistors:
Zener Diodes:
R1: 240
R2: 560
1. Z1: 1N821
Voltage Regulators:
R3: 10K
1. 7815
R4: 5K
2. LM317T
R5: 1Meg
Transistors:
1. Q1: 2N7000
R6: 1K5
R7: Rg-T.B.D.
ICs:
U1: IXDD609SI or IXDD614SI
R8: 1Meg
U2: CD4001
Capacitors:
C1: 1000mF;35VWDC
U3: LM339
C2: 22mF, 63 VWDC
U4: CD4011
C3: 1pF, silver dipped mica
U5: CD4049
C4: 100pF silver dipped mica
U6: IXDD609YI or IXDD614YI
C5: 0.1mF, 35WDC Tantalum
Note: Use either U1 or U6 but not both.
C6: 0.1mF, 35VWDC Tantalum
Trimmers:
C7: 1pF silver dipped mica
P1: 5K, 3006P Bourns or Spectrol
C8: 0.1mF, 35VWDC Tantalum
P2: 1K, 3006P Bpurns or Spectrol
C9: 0.1mF, 35VWDC Tantalum
C10: 0.1mF, 35VWDC Tantalum
Diodes:
D1: 1N4002 or BA 159
D2: 1N4002 or BA 159
18
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CN3
2
3
C9
U3
IXDD414EV-A
1
Figure 13 +VE and -VE and Component Layout with Silk-Screen Diagram
R6
C10
R2
R3
T2
U2
R5
Z1
CN2
C8
C4
Q1
U5
R9
R4
C3
R7
R8
IXDD408-EV-A
ediS redloS
R1
D2
C12
P2
P1
C1
U1
CN1
C7
D1
T1
U4
C6
C5
C11
C2
Component Side
A-VE-804DDXI
IXDD408-EV-A
IXDD414EV-A
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A-VE414DDXI
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INTEGRATED CIRCUITS DIVISION
Figure 14 Basic Charge Pump Doubler
SD2
2xV cc -V S D 2
+
+
C2
V cc
-
+
ON
SD1
Q1
18V
Ze ner
OFF
t
-
+
C1
ON
Q2
OFF
t
-
f sw ~~ 400 K H z
Figure 15 Basic Bootstrap Gate Drive Technique
V cc = + 15V
DB
V D C ~~ 50 0V D C
R5
+
R2
R1
CB
P1
V
1
R4
2
C1
3
R3
15 V
D2
4
I
I
X
X
D
D
D or D
6
6
0
1
9
4
8
7
C2
R g ext
Q4
6
L
5
CF
D1
Q1
L
O
A
D
t
0
I/P
R g e xt: 1 .0 O h m to 4 .7 O h m
Q 1 : IX T U0 1N 100
C F : G E A28 F 560 1
D B : D S EP 9 -06 C R
0.1M F D ,1 00 0 Volts
D 1 : D S E C 60 -12 A
R 1 : 1K
D 2 : 1N 5817
R 2 : 10 K
C 1 : 20 M FD ,25 V
C 2 : 20 M FD ,10 00 Volts ,C S I 1 0D C 00 20 R 3 : 2K
R 4 : 10 K
C B : 10 M FD ,2 5V D C
R 5 : 1 O hm
P 1 : 5K Trim p ot
L : 5µ H ,D A LE IH -5
20
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R02
R02
+15V
I/P
V
t
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t
V E E = -5V
I/P
+V cc=+15V
4
3
2
1
5
6
7
8
4
3
2
1
CF
+
I
X
D
D
6
0
9
R g on
5
6
7
8
D R g off
D
Z2
Z1
+
L
O
A
D
Rb
CF
I/P
H .V.D C
4
3
2
1
Q2
Q1
I
X
D
D
6
1
4
R g off
R g on
I
X
D
D or
6
0
9
5
6
7
8
Z2
Z1
LO A D
Q2
D
Z2
H .V.D C
Z1
L
O
A
D
1. Z1,Z2 : 18V,400m W
Zener diodes
2. D : 1N 5821
3. Q 1 : D 44VH 10
4. Q 2 : D 45VH 10
5. R b : 10 O hm s ,1/4w,1%
R g on
CF
IG B T
+
V cc
Figure 16 turn-off Enhancement Methods
0.0V
-5V
V
I
I
X
X
D
D
D or D
6
6
0
1
4
4
Vc c
H .V.D C
INTEGRATED CIRCUITS DIVISION
AN-401
Figure 17 Technique To Boost Current Output and
Provide -VE Bias To Achieve Faster turn-off
For High Power MOSFET And IGBT Modules
21
22
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D
C
B
4
3
2
1
4
3
2
I
X
D
D
6
0
4
R7
I
X
D
D
6
0
4
R5
+
5
6
7
8
5
6
7
8
R8
R6
T1
R G4
R4
D4
R1
D1
R G1
V c c = 16 V D C
Q4
Q1
SU G G E S TE D PAR TS :
1. U 1 : T.I. U C 3879
2. T1,T 2 : C oilcraft P art N o. SD 250-3
3. Q 1 ,Q 2,Q 3,Q 4 : 2N 29 05A
4. D 1,D 2,D 3,D 4 : D SE P 8-02 A IX Y S H iP erFR E D
5. T3 : O U TP U T Transform er
6. C F : 22M F D ,3 5 V W D C Tan talum C apacitor
7. R 1,R 2,R 3,R 4 : 560 Ohm s, ¼ w,1% M etal film
8. M 1,M 2,M 3,M 4 : IXF N 55N 50 IXY S H iP erFE T or IX F N 80N 50 IX Y S H iP erF ET
9. Z1,Z 2,...Z 8 : 18V, 400 m W Z ener diod es.
10. R G 1,R G 2,R G 3,R G 4 : 3.3 O hm s, ¼ w, 1% M eta l Film resistors.
11. R 5,R 6 ,R 7,R 8 : 10K , ¼ w, 5%
P h a se
S h ift
PW M
C o n tro lle r
IC
U1
A
1
CF
D .C .S U P P LY
COMMON
Z6
Z8
M3
Z4
Z3
Z5
M4
LO AD
T3
M2
Z7
Z2
Z1
M1
Q3
Q2
R G2
R3
R G3
D3
R2
D2
D .C . S U P P LY ~~ 3 0 0 to 3 7 5 V.D .C .
+V E
T2
INTEGRATED CIRCUITS DIVISION
AN-401
Figure 18 Transformer Coupled Gate Drive Arrangement For "H" Bridge In a Phase Shift PWM Controller at Fixed
Switching Frequency
R02
AN-401
INTEGRATED CIRCUITS DIVISION
Figure 19 3-Phase AC Motor Drive Schematic Showing How IXYS CBI (Converter-Brake-Inverter) Module Can Be Driven
By IXDD614 Using Optocouplers - All Protection Features Are Incorporated
GND1
+ 5.0 V
IS O LATE D
DC TO DC
CO NVERTER
GND1
V in-
T2
16
H C P L-31 6J
2
15
3
14
+ 15 V
VE
V L E D 2+
T6 RESET
D y na m ic
B rake
T7
13
5
12
R 5 RD
FA U LT
6
11
+
7
VLED1
O VERTEM P
- 8
VLED 1
10
RESET
Vc
VO UT
FA U LT
U1
IX D D 61 4 P I
U2
V cc 2
O /P
4
GND1
T5
C2
D E S AT
V cc
V cc 1
+
C1
T3
T4
C O M -5V
+
E N A B LE
1
I/P
V in +
T1
S in eW a ve
PW M
S ig na ls
fo r
3 -P h as e
In ve rte r
GROUND
+ 5.0 V
M IC R O C O N T R O L LE R
+ 5.0V
U6
9
VEE
R6
VEE
-5V
GND1
IX Y S 's (C B I)
CO NVERTER
BRAKE
IN V E R T E R
M O D ULE
LF
-
R1
Rg
U3
Dd
+
21
22
R4
T1
D 11
D13
D15
D15
T3
T5
D1
D3
8
D5
20
18
1
D12
2
D14
CF
3
7
15
17
D16
19
D2
14
9
D4
12
T2
13
R12
T4
SHUNT
R7
C4
-
+ 5V
R9
R10
R 11
U5
+
R8
-
U4
C3
R02
R3
T6
24
R13
GND1
Z1
D6
11
23
R2
N
T
C
16
FA U LT
+
P1
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23
24
W
V
U
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FW
FV
FU
D 12
1
G ND 1
D 14
2
D 13
D 16
3
D 15
LF
+
23
+15 V
S HU NT
T7
R
F
CF
22
24
H CP L316J
IXD D6 14
D C to D C
+5V
-5 V
Rg
D YN A M IC
B R AK E
R EG IS TO R
14
7
T7
T2
R
F
T1
R
F
+ 15 V
+ 15 V
HC PL 316 J
IX DD 614
DC to DC
T1
T2
DE S AT
-5 V R g
DE S AT
-5 V R g
+5V
HC PL 316 J
IX DD 614
DC to DC
+5V
T1
T3
RD
10
11
T2
RD
15
16
T4
T5
D2
T6
T4
R
F
Dd
T3
R
F
Dd
T7
+15V
R
F
H CP L316J
IXD D 614
D C to D C
Rg
Rg
T3
RD
12
T4
RD
17
18
O VER TE M P
D E SAT
-5V
D E SAT
-5V
+5V
H CP L316J
IXD D 614
D C to D C
M ICR OC ONT ROLLE R
6
D1
+15V
+5V
N O TE S : 1. A LL F = FAU LT S IG N A LS A RE T IED TO G ET H E R (B EIN G O P E N C O LLE C TO R) A N D F E D IN TO M IC R O C O M P U TE R .
2 . ALL R = R E SE T SIG N ALS A RE T IED TO G E T H ER A ND F E D TO H C P L-316J.
3 . O V E RT EM P AN D O V E R LO A D/S H O R T C IR C U IT FA U LT S IG N ALS AR E G E N E RAT E D AS P ER F IG (16 )
O V ERT E M P IS AL S O FE D IN M IC R O C O M P UT E R .
M CB
3 ø M AINS
D 11
21
5
D4
D3
+ 15 V
+5 V
T6
R
F
Dd
T5
R
F
Dd
+ 15 V
HC PL 316 J
IXD D 614
DC to DC
D E SAT
-5 V R g
D E SAT
-5 V R g
+5V
HC PL 316 J
IXD D 614
DC to DC
+5V
T5
T6
RD
13
RD
19
20
4
Dd
D6
Dd
M
3 A.C .
M O TO R
D5
INTEGRATED CIRCUITS DIVISION
AN-401
Figure 20 IXYS Converter, Brake Inverter (CBI) Module Being Driven By IXDD614 With Optocoupler and Desat,
Overtemp, and Short Circuit/Overload Protections
R02
AN-401
INTEGRATED CIRCUITS DIVISION
Bill of Materials for Figure 19 and Figure 20
Resistors:
Semiconductors:
R1: 10K, 1/4W, 1% MFR
U3: LM339 Comparator
R2: 560 Ohms, 1/4W, 1% MFR
U4 : LM-101 Op Amp
R3: 10K, 1/4W, 1% MFR
U5: LM339 Comparator
R4: 2.2 MegOhms, 1/4W, 5%
CBI Module: IXYS Corporation Type Nos:
R5: 10K, 1/4W, 1% MFR
MUBW 50-12A8 or any MUBW module
R6: 100 Ohms, 1/4 W, 1% MFR
from CBI 1, CBI 2 or CBI 3 series
R7: 20K, 1/4W, 1% MFR
Microcontroller: T.I. TMS320F240
R8: 61.9K, 1/4W, 1% MFR
with embedded software for AC Drive,
R9: 61.9K, 1/4W, 1% MFR
using brake feature.
R10: 10K, 1/4W, 1% MFR
IXDD614 Driver chip: 7 required to
R11: 10K, 1/4W, 1% MFR
implement A.C.Drive, using Brake feature
R12: 1.24K, 1/4W, 1% MFR
HCPL316J( Optocoupler) : 7 required to
R13: 1.24K, 1/4W, 1% MFR
implement A.C.Drive With Brake feature.
Rg: T.B.D. based on Ton , Toff , & size of IGBT
Isolated DC to DC Converter: 7 required
with specified isolation.
RD:100 Ohms,1/4 w, 5%
P1: 10K Trimpot, Bourns 3006P or Spectrol
SHUNT : 75 mV @ full load current
Capacitors:
C3, C4: 33 pF, silver dipped mica
CF: Electrolytic Filter Capacitor with very low
ESR & ESL and screw type terminals to
handle high ripple current. Voltage rating
is based on DC Bus plus AC ripple Voltage
Diodes:
Dd: General Semiconductor make,
RGP02-20E, 0.5A, 2000V, trr: 300ns
Zener Diodes:
Z1: Zener LM336, 2.5 Volt
Inductors:
LF: Gapped DC Choke
for filtering rectified power
R02
www.ixysic.com
25
AN-401
INTEGRATED CIRCUITS DIVISION
D2
Z1
C2
D2
H .V.D.C.
COMMON
Rp
Q3
Q4
D2
Rp
Z1
C2
D2
5
6
V
t
L
I/P
+
CF
4
3
2
RH
CF
+
t
I/P
H
V
26
D1
R1 C1
7
8
1
4
3
I
I
X
X
D
D
D OR D
6
6
0
1
9
4
5
6
7
RH
2
1
I
I
X
X
D
D
D OR D
6
6
1
0
4
9
8
Vcc
Vcc
D1
R1
C1
T1
C2
Z1
Rp
Q1
LO A D
T3
Q2
H .V.D.C.
Rp
Z1
C2
T2
Figure 21 IXYS Converter, Brake Inverter (CBI) Module Being Driven By IXDD614 With Optocoupler and Desat,
Overtemp, and Short Circuit/Overload Protections
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R02
AN-401
INTEGRATED CIRCUITS DIVISION
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: AN-401-R02
©Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
12/13/2012
R02
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27