IDT 9ERS3165BKILF

DATASHEET
Embedded 64-Pin Industrial Temperature
Range CK505 Compatible Clock
Recommended Application:
Industrial temperature CK505 compatible clock for embedded
systems
Output Features:
•
2 - CPU differential low power push-pull pairs
•
9 - SRC differential low power push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull
pair
•
1 - SRC/DOT selectable differential low power push-pull
pair
•
5 - PCI, 33MHz
•
1 - PCI_F, 33MHz free running
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
•
Does not require external pass transistor for voltage
regulator
•
Integrated 33ohm series resistors on differential outputs,
Zo=50Ω
• Supports spread spectrum modulation, default is 0.5%
down spread
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Selectable between one SRC differential push-pull pair
and two single-ended outputs
•
Meets PCIEX Gen2 specification on dedicated SRC
outputs. Muxed SRC outputs meet PCIEX Gen1
specification, except SRC1.
•
Meets PCIEX <85ps cycle-tocycle jitter for SRC[11:1]
•
Single-ended programmable slew rate control for RFI
reduction
ICS9ERS3165
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SEL
PCI5_F/ITP_EN
GNDPCI
VDD48
USB48M/FSLA
GND48
VDDI/O96MHz
DOT96T/SRCT_LR0
DOT96C/SRCC_LR0
GND
VDD
27FIX/LCDT/SRCT_LR1/SE1
27SS/LCDC/SRCC_LR1/SE2
GND
VDDPLL3I/O
SRCT_LR2/SATACLKT
SRCC_LR2/SATACLKC
GNDSRC
SRCT_LR3/CR#_C
SRCC_LR3/CR#_D
VDDSRCI/O
SRCT_LR4
SRCC_LR4
GNDSRC
SRCT_LR9
SRCC_LR9
SRCC_LR11/CR#_G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ICS9ERS3165
Pin Configuration
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT_LR0
CPUC_LR0
GNDCPU
CPUT_F_LR1
CPUC_F_LR1
VDDCPU_IO
NC
CPUT_ITP_LR2/SRCT8
CPUC_ITP_LR2/SRCC8
VDDSRCI/O
SRCT_LR7/CR#_F
SRCC_LR7/CR#_E
GNDSRC
SRCT_LR6
SRCC_LR6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRCI/O
SRCC_LR10
SRCT_LR10
SRCT_LR11/CR#_H
64-TSSOP
27_SEL
0 (B1b7=1)
1 (B1b7=0)
pin13
DOT96T
SRCT_LR0
pin14
DOT96C
SRCC_LR0
27_SEL
0
1
pin17
LCDT_SS
27FIX
pin18
LCDC_SS
27SS
NOTE: Pin 17/18 defaults to a different spread domain
than SRC without BIOS intervention. All pin numbers are
for TSSOP package but apply to corresponding signals
on MLF as well.
Table 1: CPU Frequency Select Table
2
FSLC
B0b7
0
0
0
0
1
1
1
1
1
FSLB
B0b6
0
0
1
1
0
0
1
1
1
FSLA
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
1
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
TSSOP Pin Description
Pin# Pin Name
1
PCI0/CR#_A
2
VDDPCI
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/27_SEL
7
PCI5_F/ITP_EN
8
9
GNDPCI
VDD48
10
USB48M/FSLA
11
12
GND48
VDDI/O96MHz
13
DOT96T/SRCT_LR0
14
DOT96C/SRCC_LR0
15
16
GND
VDD
Type DESCRIPTION
I/O
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this
pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0
of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using
the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
PWR Power supply pin for the PCI outputs, 3.3V nominal
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this
pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1
of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using
the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is
sampled on power-up as follows
I/O 0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
OUT 3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the
I/O logic value on this pin determines the power-up default of DOT_96/SRC0 and
27MHz/SRC1 output and the function table for the pin17 and pin18.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not
affected by the state of the PCI_STOP# pin. On powerup, the state of this pin
I/O determines whether pins 46 and 47 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
PWR Ground for PCI clocks.
PWR Power supply for USB clock, nominal 3.3V.
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
PWR Ground pin for the 48MHz outputs.
PWR 1.05V to 3.3V from external power supply
True clock of SRC or DOT96. The power-up default function depends on
OUT
27_Select,1= SRC0, 0=DOT96
Complement clock of SRC or DOT96. The power-up default function depends
OUT
on 27_Select,1= SRC0, 0=DOT96
PWR Ground pin for the DOT96 clocks.
PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
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1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
TSSOP Pin Description (continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
27FIX/LCDT/SRCT_LR1/SE1
Single-ended 3.3V 27MHz fix clock output / True clock of differential SRC1 or LCD
clock pair / Single ended 3.3V peripheral clock output. The default output selection
is determined by the SEL_27 default latch value. See below:
OUT 27_SEL=0: LCD100 with -0.5% down spread is selected as default. LCD100 spread
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1: Single-ended 27FIX output is selected.
18
27SS/LCDC/SRCC_LR1/SE2
Single-ended 3.3V 27MHz fix clock output / Complementary clock of differential
SRC1 or LCD clock pair / Single ended 3.3V peripheral clock output. The default
output selection is determined by the SEL_27 default latch value. See below:
27_SEL=0: LCD100 with -0.5% down spread is selected as default. LCD100 spread
OUT
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1: Single-ended 27SS output is selected with -0.5% down spread as
default. Spread percentage can be adjusted via SMBus B1b[4:1].
19
20
21
22
23
GND
VDDPLL3I/O
SRCT_LR2/SATACLKT
SRCC_LR2/SATACLKC
GNDSRC
PWR
PWR
OUT
OUT
PWR
17
24
SRCT_LR3/CR#_C
25
SRCC_LR3/CR#_D
26
27
28
29
30
31
VDDSRCI/O
SRCT_LR4
SRCC_LR4
GNDSRC
SRCT_LR9
SRCC_LR9
32
SRCC_LR11/CR#_G
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or
SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled.
Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for
either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled.
Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
PWR
I/O
I/O
PWR
OUT
OUT
I/O
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request
control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
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ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
TSSOP Pin Description (Continued)
PIN #
PIN NAME
33
SRCT_LR11/CR#_H
34
35
36
SRCT_LR10
SRCC_LR10
VDDSRCI/O
37
CPU_STOP#
38
PCI_STOP#
39
40
41
42
VDDSRC
SRCC_LR6
SRCT_LR6
GNDSRC
43
SRCC_LR7/CR#_E
TYPE
DESCRIPTION
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request
control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR 1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3
IN
bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits
IN
are shifted in from the ICH to set the FSC, FSB, FSA values
PWR VDD pin for SRC Pre-drivers, 3.3V nominal
OUT Complement clock of low power differential SRC clock pair.
OUT True clock of low power differential SRC clock pair.
PWR Ground for SRC clocks
I/O
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request
control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
. After the SRC output is disabled (high-Z), the pin can then be set to serve as a
Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
I/O
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request
control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
44
SRCT_LR7/CR#_F
45
VDDSRCI/O
PWR
46
CPUC_ITP_LR2/SRCC8
OUT
47
CPUT_ITP_LR2/SRCT8
OUT
48
49
NC
VDDCPU_IO
N/A
PWR
50
CPUC_F_LR1
OUT
51
CPUT_F_LR1
OUT
52
53
54
55
GNDCPU
CPUC_LR0
CPUT_LR0
VDDCPU
PWR
OUT
OUT
PWR
56
CK_PWRGD/PD#
57
FSLB/TEST_MODE
58
59
60
61
GNDREF
X2
X1
VDDREF
62
REF/FSLC/TEST_SEL
63
64
SDATA
SCLK
IN
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential
SRC pair. The function of this pin is determined by the latched input value on pin 7,
PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN
on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be freerunning during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running
during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
PWR Ground pin for crystal oscillator circuit
OUT Crystal output, nominally 14.318MHz.
IN Crystal input, Nominally 14.318MHz.
PWR Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/
I/O
TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification
Table.
I/O Data pin for SMBus circuitry, 5V tolerant.
IN Clock pin of SMBus circuitry, 5V tolerant.
IN
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
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1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
GNDSRC
SRCC_LR7/CR#_E
SRCT_LR7/CR#_F
VDDSRCI/O
CPUC_ITP_LR2/SRCC8
CPUT_ITP_LR2/SRCT8
NC
VDDCPU_IO
CPUC_F_LR1
CPUT_F_LR1
GNDCPU
CPUC_LR0
CPUT_LR0
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GNDREF
X2
X1
VDDREF
REF/FSLC/TEST_SEL
SDATA
SCLK
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SEL
PCI5_F/ITP_EN
GNDPCI
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ICS9ERS3165
SRCT_LR6
SRCC_LR6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRC_IO
SRCC_LR10
SRCT_LR10
SRCT_LR11/CR#_H
SRCC_LR11/CR#_G
SRCC_LR9
SRCT_LR9
GNDSRC
SRCC_LR4
SRCT_LR4
VDDSRCI/O
SRCC_LR3/CR#_D
SRCT_LR3/CR#_C
GNDSRC
SRCC_LR2/SATACLKC
SRCT_LR2/SATACLKT
VDDPLL3I/O
GND
27SS/LCDC/SRCC_LR1/SE2
27FIX/LCDT/SRCT_LR1/SE1
VDD
GND
DOT96C/SRCC_LR0
DOT96T/SRCT_LR0
VDDI/096MHz
GND48
USB48M/FSLA
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-pin MLF
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
5
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
MLF Pin Description
Pin#
1
2
3
4
Pin Name
TYPE DESCRIPTION
GNDREF
X2
X1
VDDREF
PWR
OUT
IN
PWR
5
REF/FSLC/TEST_SEL
I/O
6
7
SDATA
SCLK
I/O
IN
8
PCI0/CR#_A
9
VDDPCI
10
PCI1/CR#_B
11
PCI2/TME
12
PCI3
13
PCI4/27_SEL
14
PCI5_F/ITP_EN
15
16
GNDPCI
VDD48
17
USB48M/FSLA
18
19
GND48
VDDI/O96MHz
20
DOT96T/SRCT_LR0
21
DOT96C/SRCC_LR0
22
23
GND
VDD
I/O
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/
TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification
Table.
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin
as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of
SMBus address space . After the PCI output is disabled (high-Z), the pin can then be
set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the
CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
PWR Power supply pin for the PCI outputs, 3.3V nominal
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin
as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of
SMBus address space . After the PCI output is disabled (high-Z), the pin can then be
set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the
CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is
sampled on power-up as follows
I/O 0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
OUT 3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin24, 25 strap. On powerup, the logic
I/O value on this pin determines the power-up default of DOT_96/SRC0 and
27MHz/SRC1 output and the function table for the pin24 and pin25.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not
affected by the state of the PCI_STOP# pin. On powerup, the state of this pin
I/O determines whether pins 53 and 54 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
PWR Ground for PCI clocks.
PWR Power supply for USB clock, nominal 3.3V.
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
PWR Ground pin for the 48MHz outputs.
PWR 1.05V to 3.3V from external power supply
True clock of SRC or DOT96. The power-up default function depends on
OUT
27_Select,1= SRC0, 0=DOT96
Complement clock of SRC or DOT96. The power-up default function depends on
OUT
27_Select,1= SRC0, 0=DOT96
PWR Ground pin for the DOT96 clocks.
PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
6
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
27FIX/LCDT/SRCT_LR1/SE1
Single-ended 3.3V 27MHz fix clock output / True clock of differential SRC1 or LCD
clock pair / Single ended 3.3V peripheral clock output. The default output selection
is determined by the SEL_27 default latch value. See below:
OUT 27_SEL=0: LCD100 with -0.5% down spread is selected as default. LCD100 spread
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1: Single-ended 27FIX output is selected.
25
27SS/LCDC/SRCC_LR1/SE2
Single-ended 3.3V 27MHz fix clock output / Complementary clock of differential
SRC1 or LCD clock pair / Single ended 3.3V peripheral clock output. The default
output selection is determined by the SEL_27 default latch value. See below:
27_SEL=0: LCD100 with -0.5% down spread is selected as default. LCD100 spread
OUT
percentage can be adjusted OR output can be changed to SRC or 3.3V single-ended
peripheral clock output via SMBUs B1b[4:1].
27_SEL=1: Single-ended 27SS output is selected with -0.5% down spread as
default. Spread percentage can be adjusted via SMBus B1b[4:1].
26
27
28
29
30
GND
VDDPLL3I/O
SRCT_LR2/SATACLKT
SRCC_LR2/SATACLKC
GNDSRC
PWR
PWR
OUT
OUT
PWR
24
31
SRCT_LR3/CR#_C
32
SRCC_LR3/CR#_D
33
34
35
36
37
38
VDDSRCI/O
SRCT_LR4
SRCC_LR4
GNDSRC
SRCT_LR9
SRCC_LR9
39
SRCC_LR11/CR#_G
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or
SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled.
Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for
either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin
as a Clock Request Pin, the SRC3 output must first be disabled in byte 4, bit 7 of
SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled.
Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
PWR
I/O
I/O
PWR
OUT
OUT
I/O
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request
control of SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
7
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
MLF Pin Description (Continued)
PIN #
PIN NAME
40
SRCT_LR11/CR#_H
41
42
43
SRCT_LR10
SRCC_LR10
VDDSRCI/O
44
CPU_STOP#
45
PCI_STOP#
46
47
48
49
VDDSRC
SRCC_LR6
SRCT_LR6
GNDSRC
50
SRCC_LR7/CR#_E
TYPE
DESCRIPTION
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request
control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR 1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3
IN
bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits
IN
are shifted in from the ICH to set the FSC, FSB, FSA values
PWR VDD pin for SRC Pre-drivers, 3.3V nominal
OUT Complement clock of low power differential SRC clock pair.
OUT True clock of low power differential SRC clock pair.
PWR Ground for SRC clocks
I/O
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request
control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
. After the SRC output is disabled (high-Z), the pin can then be set to serve as a
Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
I/O
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request
control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
51
SRCT_LR7/CR#_F
52
VDDSRCI/O
PWR
53
CPUC_ITP_LR2/SRCC8
OUT
54
CPUT_ITP_LR2/SRCT8
OUT
55
56
NC
VDDCPU_IO
N/A
PWR
57
CPUC_F_LR1
OUT
58
CPUT_F_LR1
OUT
59
60
61
62
GNDCPU
CPUC_LR0
CPUT_LR0
VDDCPU
PWR
OUT
OUT
PWR
63
CK_PWRGD/PD#
64
FSLB/TEST_MODE
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential
SRC pair. The function of this pin is determined by the latched input value on pin 14,
PCIF5/ITP_EN on powerup. The function is as follows:
Pin 14 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 14, PCIF5/ITP_EN
on powerup. The function is as follows:
Pin 14 latched input Value
0 = SRC8
1 = ITP
No Connect
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be freerunning during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running
during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
8
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
General Description
ICS9ERS3165 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel
processors and Intel based systems. ICS9ERS3165 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy
output for Serial ATA and PCI-Express support.
Block Diagram
Xtal
REFCLK
SS
PLL1
SE1
1
27SS - SE2
LCD
SRC1
27SS, SE1, SE2, LCD/SRC1
0
27_SEL
SS
PLL2
IV
D
_
T
U
O
C
PCI
1
C
R
S
C
R
S
SS
PLL5
V
I
D
_
T
U
O
C
PCICLK
0
1
B1bit0
SRC_Main
SRC(11:9),(7:6),(4:3)
0
PCICLK
B0bit2
CPUCLK
CPUCLK(1:0)
0
SRC8/CPU2_ITP
Fix
PLL3
IV
D
_
T
U
O
C
V
I
D
_
T
U
O
C
SRC8
SATA
1
ITP_EN
SRC2
0
SATA
1
SRC2/SATA
B0 bit1
48MHz
48MHz
SRC0
0
DOT_96M
1
SRC0/ DOT96M
B1b7
27FIX
Power Groups
TSSOP Pin Number
VDD
GND
2
8
9
11
12
15
16
19
20
19
26,36,45
29,42
39
23
39
29,42
49
52
55
52
61
58
MLF Pin Number
VDD
GND
9
15
16
18
19
22
23
26
27
26
33,43,52
36,49
46
30
46
36,49
56
59
62
59
4
1
Description
PCICLK
USB 48 & Core, FIX PLL Analog/Digital
DOT96 Output
27FIX, 27SS, LCD, SE Outputs & Core, 27SS/LCD/SE PLLL Analog/Digital
SRC1 Output
All SRC Outputs except SRC1
SATA Output, FIX PLL Analog/Digital
SRC Outputs, CPU/PCIEX PLL Analog/Digital
CPU Outputs
CPU Outputs & Core
Crystal, REF Output & Core
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
9
Description
PCICLK
USB 48 & Core, FIX PLL Analog/Digital
DOT96 Output
27FIX, 27SS, LCD, SE Outputs & Core, 27SS/LCD/SE PLLL Analog/Digital
SRC1 Output
All SRC Outputs except SRC1
SATA Output, FIX PLL Analog/Digital
SRC Outputs, CPU/PCIEX PLL Analog/Digital
CPU Outputs
CPU Outputs & Core
Crystal, REF Output & Core
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
MAX
UNITS
Maximum Supply Voltage
VDDxxx
Supply Voltage
4.6
V
1,7
Maximum Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
3.8
V
1,7
Maximum Input Voltage
VIH
3.3V LVCMOS Inputs
Minimum Input Voltage
VIL
Any Input
Storage Temperature
Ts
Case Temperature
Tcase
Input ESD protection
ESD prot
MIN
4.6
V
1,7,8
V
1,7
150
°
1,7
115
°C
1
V
1,7
GND - 0.5
-
-65
Human Body Model
Notes
C
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Ambient Operating Temp
Tambient
-
-40
TYPICAL
85
°C
Notes
1
Supply Voltage
VDDxxx
Supply Voltage
3.135
3.465
V
1
Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
1
3.465
V
1
Input High Voltage
VIHSE
Single-ended inputs
2
VDD + 0.3
V
1
Input Low Voltage
VILSE
Single-ended inputs
VSS - 0.3
0.8
V
1
Input Leakage Current
IIN
-5
5
uA
1
Input Leakage Current
IINRES
VIN = VDD , VIN = GND
Inputs with pull or pull down
resistors
VIN = VDD , VIN = GND
-200
200
uA
1
Output High Voltage
VOHSE
Single-ended outputs, IOH = -1mA
V
1
0.4
V
1
0.9
V
1
0.4
V
1
2.4
Output Low Voltage
VOLSE
Single-ended outputs, IOL = 1 mA
Output High Voltage
VOHDIF
Differential Outputs
Output Low Voltage
Low Threshold InputHigh Voltage (Test Mode)
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
VOLDIF
Differential Outputs
VIH_FS_TEST
3.3 V +/-5%
2
VDD + 0.3
V
1
VIH_FS
3.3 V +/-5%
0.7
1.5
V
1
VIL_FS
3.3 V +/-5%
VSS - 0.3
0.35
V
1
0.7
IDD_DEFAULT
3.3V supply, PLL1,2 off
95
125
mA
1
IDD_PLL3DIF
3.3V supply, PLL1,2 Differential Out
106
125
mA
1
101
125
mA
1
32
50
mA
1
26
30
mA
1
IDD_PD3.3
3.3V supply, PLL1,2 Single-ended
Out
0.8V supply, Differential IO current,
all outputs enabled
3.3V supply, Power Down Mode
IDD_PDIO
0.8V IO supply, Power Down Mode
0.23
0.5
mA
1
IDD_iAMT3.3
3.3V supply, iAMT Mode
47
60
mA
1
IDD_iAMT0.8
0.8V IO supply, iAMTMode
5
10
mA
1
Input Frequency
Fi
VDD = 3.3 V
14.318
MHz
2
Pin Inductance
Lpin
7
nH
1
CIN
Logic Inputs
5
pF
1
Input Capacitance
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
fSSMOD
Triangular Modulation
33
kHz
1
Operating Supply Current
IDD_PLL3SE
IDD_IO
Power Down Current
iAMT Mode Current
Spread Spectrum Modulation
Frequency
25
1.5
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
10
30
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
SMBus Voltage
VDD
CONDITIONS
Low-level Output Voltage
Current sinking at
VOLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Maximum SMBus Operating
Frequency
VOLSMB
@ IPULLUP
IPULLUP
SMB Data Pin
TFI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
FSMBUS
Block Mode
TRI2C
MIN
MAX
UNITS
Notes
2.7
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
100
kHz
1
MAX
UNITS
Notes
1.8
ms
1
15
ns
1
300
us
1
10
ns
1
5
ns
1
5
ns
1
4
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
Clk Stabilization
TSTAB
Tdrive_SRC
TDRSRC
Tdrive_PD#
TDRPD
Tdrive_CPU
TDRSRC
Tfall_PD#
TFALL
Trise_PD#
TRISE
CONDITIONS
From VDD Power-Up or deassertion of PD# to 1st clock
SRC output enable after
PCI_STOP# de-assertion
Differential output enable after
PD# de-assertion
CPU output enable after
CPU_STOP# de-assertion
MIN
Fall/rise time of PD#, PCI_STOP#
and CPU_STOP# inputs
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
NOTES
Rising Edge Slew Rate
tSLR
Differential Measurement
2.5
8
V/ns
1,2
Falling Edge Slew Rate
tFLR
Differential Measurement
2.5
8
V/ns
1,2
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
VHIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
VLOW
Includes undershoot
mV
1
Differential Voltage Swing
VSWING
Differential Measurement
300
Crossing Point Voltage
VXABS
Single-ended Measurement
300
Crossing Point Variation
VXABSVAR
Single-ended Measurement
Duty Cycle
DCYC
Differential Measurement
CPU Jitter - Cycle to Cycle
CPUJ C2C
Differential Measurement
85
ps
1
SRC0 Jitter - Cycle to Cycle
SRC[11:1] Jitter - Cycle to
Cycle
SATA Jitter - Cycle to Cycle
SRCJ C2C
Differential Measurement
125
ps
1
SRCJ C2C
Differential Measurement
85
ps
1
SATAJ C2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJ C2C
Differential Measurement
250
ps
1
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[11,7,4,2,0] Skew
SRCSKEW
Differential Measurement
SRC[10,9,8,6,3] Skew
SRCSKEW
Differential Measurement
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
11
-300
mV
1
550
mV
1,3,4
140
mV
1,3,5
55
%
1
45
0 nominal
3
ps
1
ns
1
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,6
30.00900
ns
6
30.15980
ns
6
30.65980
ns
6
V
1
33.33MHz output nominal
Clock period
T period
Absolute min/max period
Tabs
33.33MHz output nominal/spread
29.49100
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
33.33MHz output spread
0.4
V OH @MIN = 1.0 V
IOH
29.99100
-33
-33
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
Output Low Current
IOL
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
Duty Cycle
dt1
VT = 1.5 V
30
Skew
tskew
VT = 1.5 V
tdelay
VT = 1.5 V
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
1
mA
1
mA
1
mA
1
38
mA
1
4
V/ns
1
1
4
V/ns
1
45
55
%
1
250
ps
1
ps
1,9
500
ps
1
VOL @ MAX = 0.4 V
Intentional PCI-PCI delay
V
1
200 nominal
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
Electrical Characteristics - USB48MHz
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
MIN
-100
MAX
100
UNITS
ppm
NOTES
6
1,6
Clock period
T period
48.00MHz output nominal
20.83125
20.83542
ns
Absolute min/max period
T abs
48.00MHz output nominal
20.48130
21.18540
ns
6
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
V
1
Output High Current
IOH
mA
1
0.4
V OH @MIN = 1.0 V
-29
-23
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
29
mA
1
mA
1
Output Low Current
IOL
27
mA
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
2
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
2
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
350
ps
1
VOL @ MAX = 0.4 V
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
12
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
ppm
see Tperiod min-max values
TYP
-15
15
37.0376
Clock period
Tperiod
27.000MHz output nominal
37.0365
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
Output Low Current
IOL
Edge Rate
tslewr/f
Rising/Falling edge rate
Rise Time
tr1
Fall Time
tf1
Duty Cycle
Jitter
tjcyc-cyc
VT = 1.5 V
Notes
1,6
ppm
6
6
ns
V
1
0.55
V
1
mA
1
-23
mA
1
mA
1
-29
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
UNITS
50
Output High Voltage
V OH @MIN = 1.0 V
MAX
-50
29
27
mA
1
1
4
V/ns
1
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
dt1
VT = 1.5 V
45
55
%
1
tltj
Long Term (10us), VT = 1.5 V
800
ps
1
tjpk-pk
VT = 1.5 V
-200
200
ps
1
200
ps
1
VOL @ MAX = 0.4 V
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,6
Clock period
Tperiod
14.318MHz output nominal
69.8203
69.8622
ns
6
Absolute min/max period
Tabs
14.318MHz output nominal
69.8203
70.86224
ns
6
Output High Voltage
VOH
IOH = -1 mA
2.4
Output Low Voltage
VOL
IOL = 1 mA
Output High Current
IOH
Output Low Current
IOL
VOH @MIN = 1.0 V,
[email protected] = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
V
1
0.4
V
1
-33
-33
mA
1
30
38
mA
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
4
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
4
V/ns
1
45
Duty Cycle
dt1
VT = 1.5 V
Jitter
tjcyc-cyc
VT = 1.5 V
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
13
55
%
1
1000
ps
1
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Electrical Characteristics - Differential Jitter Parameters
PARAMETER
Symbol
Conditions
PCIe Gen 1
PCIe Gen 2
tjphaseLo
Jitter, Phase
10kHz < f < 1.5MHz
PCIe Gen 2
tjphaseHigh
1.5MHz < f < Nyquist (50MHz)
*TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%, Rs= 0Ω, CL = 2pF
tjphasePLL
Min
TYP
Max
Units
Notes
86
ps (p-p)
ps
(RMS)
ps
(RMS)
1,11
3
3.1
1,11
1,11
Notes on Electrical Characteristics:
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing centered around differential zero
3
Vxabs is defined as the voltage where CLK = CLK#
4
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The
average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
5
6
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
7
Operation under these conditions is neither implied, nor guaranteed.
8
Maximum input voltage is not to exceed maximum VDD
9
See PCI Clock-to-Clock Delay Figure
10
At nominal voltage and temperature
11
See http://www.pcisig.com for complete specs
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
14
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Table 1: CPU Frequency Select Table
2
FSLC
B0b7
0
0
0
0
1
1
1
1
1
FSLB
B0b6
0
0
1
1
0
0
1
1
1
FSLA
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 2: 27FIX/LCDT/SRCT_LR1/SE1, 27SS/LCDC/SRCC_LR1/SE2 Configuration
27FIX/LCDT/SRCT_LR1/SE1 27SS/LCDC/SRCC_LR1/SE2
B1b3
B1b2
B1b1
27_SEL B1b4
Spread
MHz
%
PLL1 & PLL2 disabled
100.00
100.00
-0.50%
100.00
-1%
100.00
-1.50%
100.00
+/-0.25%
100.00
+/-0.5%
N/A
N/A
24.576
None
98.304
None
98.304
None
27.000
None
25.000
None
MHz
0
0
0
0
0
0
0
0
1
100.00
0
0
0
1
0
100.00
0
0
0
1
1
100.00
0
0
1
0
0
100.00
0
0
1
0
1
100.00
0
0
1
1
0
100.00
0
0
1
1
1
N/A
0
1
0
0
0
24.576
0
1
0
0
1
24.576
0
1
0
1
0
98.304
0
1
0
1
1
27.000
0
1
1
0
0
25.000
0
1
1
0
1
0
1
1
1
0
N/A
N/A
0
1
1
1
1
N/A
N/A
0
0
0
0
0
N/A
N/A
1
0
0
0
1
N/A
N/A
1
0
0
1
0
27MHz_nonSS
1
27MHz_SS
0
0
1
1
27MHz_nonSS
1
27MHz_SS
0
1
0
0
27MHz_nonSS
1
27MHz_SS
0
1
0
1
27MHz_nonSS
1
27MHz_SS
27MHz_nonSS
0
1
1
0
27MHz_SS
1
27MHz_nonSS
0
1
1
1
1
27MHz_SS
27MHz_nonSS
1
0
0
0
27MHz_SS
1
1
0
0
1
27MHz_nonSS
1
27MHz_SS
1
0
1
0
27MHz_nonSS
27MHz_SS
1
1
0
1
1
N/A
N/A
1
1
1
0
0
N/A
N/A
1
1
1
0
1
N/A
N/A
1
1
1
1
0
N/A
N/A
1
1
1
1
1
N/A
N/A
1
Note: Mode 00000 ~ 00110 on Table 2 only applies when SRC_MAIN source is from PLL5.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
15
N/A
N/A
N/A
N/A
Comment
SRCCLK1 from SRC_MAIN
LCDCLK from PLL1
LCDCLK from PLL1
LCDCLK from PLL1
LCDCLK from PLL1
LCDCLK from PLL1
N/A
24.576Mhz on SE1 and SE2
24.576Mhz on SE1, 98.304Mhz on SE2
98.304Mhz on SE1 and SE2
27Mhz on SE1 and SE2
25Mhz on SE1 and SE2
N/A
N/A
N/A
-0.5%
-1%
-1.5%
-2%
-0.75%
-1.25%
-1.75%
+-0.5%
+-0.75%
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Table 3: IO_Vout select table
B9b2
0
0
0
0
1
1
1
1
B9b1
0
0
1
1
0
0
1
1
B9b0
0
1
0
1
0
1
0
1
IO_Vout
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1.0V
Table 4: Device ID table
B8b7
B8b6
B8b5
B8b4
Comment
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
64 pin MLF
64 pin TSSOP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
16
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
CPU Power Management Table
PD#
CPU_STOP#
PCI_STOP#
PEREQ#
SMBus
Register
OE
1
0
1
1
1
X
0
X
1
X
X
X
X
X
X
X
Enable
Enable
Enable
Disable
M1
CPU0
CPU0#
CPU1
CPU1#
CPU2
CPU2#
Running
Low/20K
High
Low/20K
Low/20K
Running
Low
Low
Low
Low
Running
Low/20K
High
Low/20K
Running
Running
Low
Low
Low
Running
Running
Low/20K
High
Low/20K
Low/20K
Running
Low
Low
Low
Low
PCIEX, LCD Power Management Table
PD#
CPU_STOP#
1
0
1
1
1
PCI_STOP#
X
X
X
X
X
1
X
0
X
X
PEREQ#
SMBus
Register
OE
0
X
0
1
X
Enable
Enable
Enable
Enable
Disable
M1
PCIeT
PCIeC
Free-Run
Running
Running
Low/20K
Low
Running
Running
Running
Running
Low/20K
Low
Low/20K
Low
PCIeT
PCIeC
Stoppable
Running
Running
Low/20K
Low
High
Low
Low/20K
Low
Low/20K
Low
Low/20K
Low
LCD
LCD #
Free-Run
Running
Running
Low/20K
Low
Running
Running
Running
Running
Low/20K
Low
Low/20K
Low
LCD
LCD #
Stoppable
Running
Running
Low/20K
Low
High
Low
Running
Running
Low/20K
Low
Low/20K
Low
SATA
SATA#
Free-Run
Running Running
Low/20K
Low
Running Running
Running Running
Low/20K
Low
Low/20K
Low
SATA
SATA#
Stoppable
Running Running
Low/20K
Low
High
Low
Running Running
Low/20K
Low
Low/20K
Low
DOT, SATA Power Management Table
PD#
CPU_STOP#
PCI_STOP#
PEREQ#
1
0
1
1
1
X
X
X
X
X
1
X
0
X
X
X
X
X
X
X
SMBus
Register
OE
Enable
Enable
Enable
Enable
Disable
M1
DOT
DOT#
Running
Low/20K
Running
Running
Low/20K
Low/20K
Running
Low
Running
Running
Low
Low
Singled-Ended Power Management Table
PD#
CPU_STOP#
PCI_STOP#
PEREQ#
SMBus
Register
OE
1
0
1
1
X
X
X
X
1
X
0
X
X
X
X
X
Enable
Enable
Enable
Disable
M1
PCIF/PCI
PCIF/PCI
Free-Run Stoppable
Running Running
Low
Low
Running
Low
Low
Low
Low
Low
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
17
USB48
REF
27M
SE
Running
Low
Running
Low
Low
Running
Low
Running
Low
Low
Running
Low
Running
Low
Low
Running
Low
Running
Low
Low
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
General SMBus Serial Interface Information for the ICS9ERS3165
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
18
Not acknowledge
stoP bit
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 0 FS Readback & PLL Selection Register
Bit
7
6
5
Name
FSLC
FSLB
FSLA
Description
CPU Freq. Sel. Bit (Most Significant)
CPU Freq. Sel. Bit
CPU Freq. Sel. Bit (Least Significant)
Type
R
R
R
0
1
4
iAMT_EN
Set via SMBus or dynamically by CK505 if detects dynamic M1
R
Legacy Mode
iAMT Enabled
3
2
1
Reserved
SRC_Main_SEL
SATA_SEL
Reserved
Select source for SRC Main
Select source for SATA clock
RW
RW
RW
SRC Main = PLL5
SATA = SRC_Main
SRC Main = PLL2
SATA = PLL3
Default
Latch
Latch
Latch
iAMT power on
status
0
0
0
0
PD_Restore
1 = on Power Down de-assert return to last known state
0 = clear all SMBus configurations as if cold power-on and go to
latches open state
This bit is ignored and treated at '1' if device is in iAMT mode.
RW
Configuration Not Saved
Configuration Saved
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
SRC0
Down spread
Down
1
DOT96
Center spread
Center
See Table 1 : CPU Frequency Select Table
Byte 1 PLL1 Quick Config Register
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1; When 27_Select pin = 1, PWD = 0
Bit
Name
Description
7
SRC0_SEL
Select SRC0 or DOT96
6
PLL5_SSC_SEL
Select 0.5% down or center SSC
5
PLL2_SSC SEL
Select 0.5% center or down SSC
4
PLL1_CF3
PLL1 Quick Config Bit 3
3
PLL1_CF2
PLL1 Quick Config Bit 2
2
PLL1_CF1
PLL1 Quick Config Bit 1
1
PLL1_CF0
PLL1 Quick Config Bit 0
0
PCI_SEL
PCI_SEL
PCI from PLL5
PCI from SRC_MAIN
Default
Note 1
0
0
0
0
1
0
1
See Table 2: pin 27FIX/LCDT/SRCT_LR1/SE1,
27SS/LCDC/SRCC_LR1/SE2 Configuration
Only applies if Byte 0, bit 2 = 0.
Byte 2 Single Ended Output Enable Register
Bit
7
6
5
4
3
2
1
0
Name
REF_OE
USB_OE
PCIF5_OE
PCI4_OE
PCI3_OE
PCI2_OE
PCI1_OE
PCI0_OE
Description
Output enable for REF
Output enable for USB
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Description
Output enable for SRC11
Output enable for SRC10
Output enable for SRC9
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Reserved
Output enable for SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Default
1
1
1
1
1
1
1
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable CR#_A
CR#_A -> SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
1
Enable CR#_A
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
Default
0
0
0
0
0
0
0
0
Byte 3 SRC Output Enable Register
Bit
7
6
5
4
3
2
1
0
Name
SRC11_OE
SRC10_OE
SRC9_OE
SRC8/ITP_OE
SRC7_OE
SRC6_OE
Reserved
SRC4_OE
Byte 4 SRC/CPU/DOT Output Enable & Spread Spectrum Disable Register
Bit
7
6
5
4
3
2
1
0
Name
SRC3_OE
SATA/SRC2_OE
SRC1_OE
SRC0/DOT96_OE
CPU1_OE
CPU0_OE
PLL5_SSC_ON
PLL2_SSC_ON
Description
Output enable for SRC3
Output enable for SATA/SRC2
Output enable for SRC1
Output enable for SRC0/DOT96
Output enable for CPU1
Output enable for CPU0
Enable PLL5's spread modulation
Enable PLL2's spread modulation
Byte 5 Clock Request Enable/Configuration Register
Bit
7
6
5
4
3
2
1
0
Name
CR#_A_EN
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
CR#_D_EN
CR#_D_SEL
Description
Enable CR#_A (clk req) for SRC0 or SRC2
Sets CR#_A to control either SRC0 or SRC2
Enable CR#_B (clk req) for SRC1 or SRC4
Sets CR#_B to control either SRC1 or SRC4
Enable CR#_C (clk req) for SRC0 or SRC2
Sets CR#_C to control either SRC0 or SRC2
Enable CR#_D (clk req) for SRC1 or SRC4
Sets CR#_D to control either SRC1 or SRC4
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
19
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 6 Clock Request Enable/Configuration Register
Bit
7
6
5
4
3
2
Name
CR#_E_EN
CR#_F_EN
CR#_G_EN
CR#_H_EN
Description
Enable CR#_E (clk req) for SRC6
Enable CR#_F (clk req) for SRC8
Enable CR#_G (clk req) for SRC9
Enable CR#_H (clk req) for SRC10
Type
RW
RW
RW
RW
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Disable CR#_H
Reserved
Reserved
Reserved
Reserved
RW
RW
-
1
Enable CR#_E
Enable CR#_F
Enable CR#_G
Enable CR#_H
-
1
LCD/SRC1_STP_CRTL•
If set, LCD_SS/SRC1 stops with PCI_STOP#
RW
Free Running
0
SRC0_STP_CRTL
If set, SRC0 stop with PCI_STOP#
RW
Free Running
Description
Type
R
R
R
R
R
R
R
R
0
0
Reserved
Reserved
Output enable for SE1
Output enable for SE2
Type
R
R
R
R
RW
RW
RW
RW
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Default
0
0
0
0
0
0
0
0
Byte 7 Vendor ID/ Revision ID Register
Bit
7
6
5
4
3
2
1
0
Name
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
Revision ID
Vendor ID
ICS is 0001, binary
1
Default
0
0
0
1
0
0
0
1
1
Default (TSSOP)
0
0
0
1
0
0
1
1
Vendor specific
Byte 8 Device ID & Output Enable Register
Bit
7
6
5
4
3
2
1
0
Name
Device_ID3
Device_ID2
Device_ID1
Device_ID0
Reserved
Reserved
27MHz_nonSS/SE1_OE
27MHz_SS/SE2_OE
Description
Table of Device identifier codes, used for differentiating between
CK505 package options, etc.
See Device ID Table 4
Disabled
Disabled
Enabled
Enabled
1
Stops with PCI_STOP#
assertion
no overclocking
Outputs = REF/N
Test mode
Default (MLF)
0
0
0
0
0
0
1
1
Byte 9 Test and Output Control Register
Bit
Name
Description
Type
0
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of PCI_STOP#
RW
Free running
6
5
4
3
2
1
0
TME_Readback
Reserved
Test Mode Select
Test Mode Entry
CPU IO_VOUT2
CPU IO_VOUT1
CPU IO_VOUT0
Truested Mode Enable (TME) strap status
Reserved
Allows test select, ignores REF/FSC/TestSel
Allows entry into test mode, ignores FSB/TestMode
CPU IO Output Voltage Select (Most Significant Bit)
CPU IO Output Voltage Select
CPU IO Output Voltage Select (Least Significant Bit)
R
RW
RW
RW
RW
RW
RW
normal operation
Outputs HI-Z
Normal operation
Description
Readback of 27_Select latch
Type
R
0
Dot96/ LCD_SS /SE
See Table 3: V_IO Selection
(Default is 0.8V)
Default
0
TME latch
1
0
0
1
0
1
Byte 10 Output Control Register
Bit
7
Name
27_SEL Latch Readback
6
PCI4 STOP EN
Allows control of PCI4 with assertion of PCI_STOP#
RW
Free running
5
PCI3 STOP EN
Allows control of PCI3 with assertion of PCI_STOP#
RW
Free running
4
PCI2 STOP EN
Allows control of PCI2 with assertion of PCI_STOP#
RW
Free running
3
PCI1 STOP EN
Allows control of PCI1 with assertion of PCI_STOP#
RW
Free running
2
PCI0 STOP EN
Allows control of PCI0 with assertion of PCI_STOP#
RW
Free running
1
0
CPU1 Stop Enable
CPU0 Stop Enable
Enables control of CPU1 with CPU_STOP#
Enables control of CPU0 with CPU_STOP#
RW
RW
Free Running
Free Running
1
SRC0/ 27MHz
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stoppable
Stoppable
Description
Reserved
Reserved
Reserved
Reserved
M1 mode clk enable, only if ITP_EN=1
M1 mode clk enable
Reserved
Enables control of CPU2 with CPU_STOP#
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Free Running
1
Enable
Enable
Stoppable
Default
27_SEL latch
Default
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
Byte 11 iAMT/CPU2 Control Register
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
CPU2_AMT_EN
CPU1_AMT_EN
Reserved
CPU2 Stop Enable
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
20
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 12 Byte Count Register
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
BC5
BC4
BC3
BC2
BC1
BC0
Description
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Read Back byte count register,
max bytes = 32
0
-
1
-
Default
0
0
0
0
1
1
0
1
Byte 13 Single Ended Output Slew Rate Control Register
Bit
7
6
5
4
3
2
1
0
Name
REF
REF
27M_FIX
27M_FIX
27M_SS
27M_SS
Reserved
Reserved
Description
RW
0
1
Default
RW
RW
RW
RW
RW
RW
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
0
1
0
1
0
1
Reserved
Reserved
RW
RW
-
-
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
Default
X
X
X
X
X
X
X
X
1
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Default
Slew Rate Control
Slew Rate Control
Slew Rate Control
Byte 14 Reserved
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 15 Reserved
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 16 Reserved
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 17 SRC Output Control Register
Bit
7
6
5
4
3
2
1
0
Name
Description
RW
0
SATA/SRC2_STP_CRTL
If set, SATA/SRC2 stops with PCI_STOP#
RW
Free Running
SRC3_STP_CRTL
If set, SRC3 stops with PCI_STOP#
RW
Free Running
SRC4_STP_CRTL
If set, SRC4 stops with PCI_STOP#
RW
Free Running
SRC6_STP_CRTL
If set, SRC6 stops with PCI_STOP#
RW
Free Running
SRC7_STP_CRTL
If set, SRC7 stops with PCI_STOP#
RW
Free Running
Reserved
Reserved
RW
-
SRC8_STP_CRTL
If set, SRC8 stops with PCI_STOP#
RW
Free Running
SRC9_STP_CRTL
If set, SRC9 stops with PCI_STOP#
RW
Free Running
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
21
0
0
0
0
0
0
0
0
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 18 Differential Output Control Register
Bit
7
6
5
4
3
2
1
0
Name
Description
RW
0
SRC10_STP_CRTL
If set, SRC10 stops with PCI_STOP#
RW
Free Running
RW
Free Running
SRC11_STP_CRTL
SRC/CPUITP_SRC8 IO_VOUT2
SRC/CPUITP_SRC8 IO_VOUT1
SRC/CPUITP_SRC8 IO_VOUT0
SATA/SRC2 IO_VOUT2
SATA/SRC2 IO_VOUT1
SATA/SRC2 IO_VOUT0
If set, SRC11 stops with PCI_STOP#
SRC & CPUITP_SRC8 IO Output Voltage Select (Most Significant
Bit)
SRC IO & CPUITP_SRC8 Output Voltage Select
SRC & CPUITP_SRC8 IO Output Voltage Select (Least
Significant Bit)
SATA_SRC2 IO Output Voltage Select (Most Significant Bit)
SATA_SRC2 IO Output Voltage Select
SATA_SRC2 IO Output Voltage Select (Least Significant Bit)
1
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
RW
RW
0
0
1
See Table 3: V_IO Selection
(Default is 0.8V)
RW
RW
RW
RW
Default
0
1
See Table 3: V_IO Selection
(Default is 0.8V)
1
0
1
Byte 19 Differential Output Control Register
Bit
7
6
5
4
3
2
1
0
Name
LCD_SS (SRC1) IO_VOUT2
LCD_SS (SRC1) IO_VOUT1
LCD_SS (SRC1) IO_VOUT0
Description
LCD_SS IO Output Voltage Select (Most Significant Bit)
LCD_SS IO Output Voltage Select
LCD_SS IO Output Voltage Select (Least Significant Bit)
RW
RW
RW
RW
SRC0/DOT96 IO_VOUT2
SRC0_DOT96 IO Output Voltage Select (Most Significant Bit)
RW
SRC0/DOT96 IO_VOUT1
SRC0_DOT96 IO Output Voltage Select
RW
SRC0/DOT96 IO_VOUT0
SRC0_DOT96 IO Output Voltage Select (Least Significant Bit)
RW
Reserved
Reserved
Reserved
Reserved
RW
RW
Description
Type
RW
RW
RW
RW
0
1
See Table 3: V_IO Selection
(Default is 0.8V)
Default
1
0
1
1
See Table 3: V_IO Selection
(Default is 0.8V)
0
1
-
-
0
0
0
1
Default
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
0
1
0
1
0
Byte 20 Single Ended Slew Rate Control Register
Bit
7
6
5
4
3
2
1
0
Name
48MHz
48MHz
PCIF5
PCIF5
PCI4
PCI4
PCI3
PCI3
Slew Rate Control
Slew Rate Control
Slew Rate Control
RW
RW
Slew Rate Control
RW
RW
1
0
1
Byte 21 Single Ended Slew Rate & M/N Enable Control Register
Bit
7
6
5
4
3
2
1
0
Name
PCI2
PCI2
PCI1
PCI1
PCI0
PCI0
Reserved
Reserved
Description
Slew Rate Control
Slew Rate Control
Slew Rate Control
Reserved
Reserved
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
22
Type
0
1
Default
RW
RW
RW
RW
RW
RW
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
00 = Hi-Z
10 = 2.0 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
01 = 1.4 V/ns
11 = 2.4 V/ns
0
1
0
1
0
1
RW
RW
-
-
0
0
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Test Clarification Table
Comments
CK_PWRG=1 w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If CK_PWRG=1 w/ V>2.0V then use TEST_SEL
If CK_PWRG=1 w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 after CK_PWRG=1,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
HW
SW
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MODE
HW PIN
TEST ENTRY
BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V
>2.0V
>2.0V
>2.0V
X
0
0
1
0
X
X
X
0
0
1
0
NORMAL
HI-Z
REF/N
REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
1
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
23
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
24
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
25
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
c
N
L
E1
E
INDEX
AREA
1 2
a
D
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
-1.20
-.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.17
0.27
.007
.011
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
-0.10
-.004
A
A2
VARIATIONS
A1
N
-C-
64
e
b
SEATING
PLANE
D mm.
MIN
16.90
D (inch)
MAX
17.10
MIN
.665
MAX
.673
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0039
Ordering Information
Part/Order Number
9ERS3165BKILF
9ERS3165BKILFT
9ERS3165BGILF
9ERS3165BGILFT
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
64-pin MLF
64-pin MLF
64-pin TSSOP
64-pin TSSOP
Temperature
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
Parts that are ordered w ith a “LF” suffix to the part num ber are the Pb-Free configuration and are RoHS com pliant.
Due to package size constraints, actual top-side m arking m ay differ from the full orderable part num ber.
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
26
1613C—02/08/12
ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Revision History
Rev.
0.1
0.2
Issue Date
04/29/09
04/30/09
Description
Initial Release
Updates to electrical tables.
Page #
Various
Various
0.3
06/29/09
Updated TSSOP/MLF pinout and descriptions, table 2, and Byte 1.
A
B
C
08/19/09
01/25/10
02/08/12
Released to final
Updated document template
Updated MLF package drawing and footrint
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
408-284-6578
[email protected]
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
TM
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
27