IDT 954226AGLF

DATASHEET
Programmable Timing Control HubTM for Mobile P4TM
Systems
Recommended Application:
CK410M Compatible Main Clock
Output Features:
•
2 - 0.7V current-mode differential CPU pairs
•
4 - 0.7V current-mode differential PCI Express* pairs
•
1 - 0.7V current-mode differential CPU/PCI Express
selectable pair
•
1 - 0.7V current-mode differential SATA pair
•
1 - 0.7V current-mode differential LCDCLK/PCI Express
selectable pair
•
4 - PCI (33MHz)
•
2 - PCICLK_F, (33MHz) free-running
•
1 - USB, 48MHz
•
1 - DOT, 96MHz, 0.7V current differential pair
•
2 - REF, 14.318MHz
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Supports undriven differential CPU, PCI Express pair
in PD for power management.
•
PEREQ# pins to support PCI Express and SATA power
management.
X2
X1
GND
REF0
REF1/FSLC/TEST_SEL
CPU_STOP#
PCI/SRC_STOP#
PCICLK2/REQ_SEL**
VDDPCI
GND
PCICLK3
54 53 52 51 50 49 48 47 46 45 44 43
VDDPCI 1
42 VDDREF
ITP_EN/PCICLK_F0 2
41 SDATA
**SELPCIEX_LCDCLK#/PCICLK_F1 3
40 SCLK
Vtt_PwrGd#/PD 4
39 GND
VDD48 5
38 CPUCLKT0
FSLA/USB_48MHz 6
37 CPUCLKC0
GND 7
36 VDDCPU
ICS 954226AKLF
DOTT_96MHz 8
35 CPUCLKT1
DOTC_96MHz 9
34 CPUCLKC1
FSLB/TEST_MODE 10
33 IREF
LCDCLK_SS/PCIEXT0 11
32 GNDA
LCDCLK_SS/PCIEXC0 12
31 VDDA
PCIEXT1 13
30 CPUCLKT2_ITP/PCIEXT6
PCIEXC1 14
29 CPUCLKC2_ITP/PCIEXC6
VDDPCIEX
PEREQ1#*/PCIEXT5
PEREQ2#*/PCIEXC5
PCIEXT4
PCIEXC4
GND
VDDPCIEX
SATACLKC
SATACLKT
PCIEXC3
PCIEXT3
PCIEXC2
17 18 19 20 21 22 23 24 25 26 27 28
PCIEXT2
15 16
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
ITP_EN/PCICLK_F0
**SELPCIEX_LCDCLK#/PCICLK_F1
Vtt_PwrGd#/PD
VDD48
FSLA/USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
FSLB/TEST_MODE
LCDCLK_SS/PCIEX0T
LCDCLK_SS/PCIEX0C
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS954226
56 55
PCICLK4
TSSOP Pin Configuration
PCICLK5
GND
MLF Pin Configuration
VDDPCIEX
954226
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
PCI Express outputs cycle-cycle jitter < 125ps
•
SATA outputs cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 500ps
•
+/- 300ppm frequency accuracy on CPU, PCI Express
and SATA clocks
•
+/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCI Express
•
Supports programmable spread percentage and
frequency
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCICLK2/REQ_SEL**
PCI/SRC_STOP#
CPU_STOP#
REF1/FSLC/TEST_SEL
REF0
GND
X1
X2
VDDREF
SDATA
SCLK
GND
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
IREF
GNDA
VDDA
CPUCLKT2_ITP/PCIEXT6
CPUCLKC2_ITP/PCIEXC6
VDDPCIEX
PEREQ1#*/PCIEXT5
PEREQ2#*/PCIEXC5
PCIEXT4
PCIEXC4
GND
56-TSSOP
56-MLF
* Internal Pull-Up Resistor
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
** Internal Pull-Down Resistor
Table 1: Frequency Selection Table
FSLC B6b2 FS LB B6b1 FS LA B6b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
PCIEX
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
REF
MHz
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
USB
MHz
48.00
48.00
48.00
48.00
48.00
48.00
48.00
48.00
DOT
MHz
96.00
96.00
96.00
96.00
96.00
96.00
96.00
96.00
Spread %
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
1
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
TSSOP Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
PWR
PWR
OUT
OUT
OUT
PWR
PWR
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
1
2
3
4
5
6
7
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
8
ITP_EN/PCICLK_F0
I/O
9
**SELPCIEX_LCDCLK#/PCICLK_F1
I/O
10
Vtt_PwrGd#/PD
IN
11
VDD48
12
FSLA/USB_48MHz
13
14
15
GND
DOTT_96MHz
DOTC_96MHz
16
FSLB/TEST_MODE
17
LCDCLK_SS/PCIEX0T
OUT
18
LCDCLK_SS/PCIEX0C
OUT
19
20
21
22
23
24
25
26
27
28
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
I/O
PWR
OUT
OUT
IN
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
2
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
TSSOP Pin Description (cont.)
PIN #
PIN NAME
TYPE
29
30
31
GND
PCIEXC4
PCIEXT4
PWR
OUT
OUT
32
PEREQ2#*/PCIEXC5
I/O
33
PEREQ1#*/PCIEXT5
I/O
34
VDDPCIEX
PWR
35
CPUCLKC2_ITP/PCIEXC6
OUT
36
CPUCLKT2_ITP/PCIEXT6
OUT
37
38
VDDA
GNDA
PWR
PWR
39
IREF
OUT
40
CPUCLKC1
OUT
41
CPUCLKT1
OUT
42
VDDCPU
PWR
43
CPUCLKC0
OUT
44
CPUCLKT0
OUT
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REF0
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
REF1/FSLC/TEST_SEL
I/O
54
CPU_STOP#
IN
55
PCI/SRC_STOP#
IN
56
PCICLK2/REQ_SEL**
I/O
DESCRIPTION
Ground pin.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
Power supply for PCI Express clocks, nominal 3.3V
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
3
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
MLF Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
PWR
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX /
Free running 3.3V PCI clock output.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin used
to put the device into a low power state. The internal clocks, PLLs and the
crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin.
Free running PCI clock not affected by PCI_STOP# through I2C .
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCIEX_6 pair
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
True clock of LCDCLK_SS output / True clock of PCI Express differential
pair. Selected by SELPCIEX_LCDCLK#
Complementary clock of LCDCLK_SS output / Complementary clock of PCI
Express differential pair. Selected by SELPCIEX_LCDCLK#
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply for PCI Express clocks, nominal 3.3V
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
True clock of differential SATA pair.
Complement clock of differential SATA pair.
Power supply for PCI Express clocks, nominal 3.3V
Ground pin.
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / Complement clock of
differential PCI Express output.
Real-time input pin that controls SATACLK and PCIEXCLK outputs that are
selected through the I2c. 1 = disabled, 0 = enabled. / True clock of
differential PCI Express output.
Power supply for PCI Express clocks, nominal 3.3V
1
VDDPCI
2
ITP_EN/PCICLK_F0
I/O
3
**SELPCIEX_LCDCLK#/PCICLK_F1
I/O
4
Vtt_PwrGd#/PD
IN
5
VDD48
6
FSLA/USB_48MHz
7
GND
PWR
8
DOTT_96MHz
OUT
9
DOTC_96MHz
OUT
10
FSLB/TEST_MODE
11
LCDCLK_SS/PCIEXT0
OUT
12
LCDCLK_SS/PCIEXC0
OUT
13
14
15
16
17
18
19
20
21
22
23
24
25
PCIEXT1
PCIEXC1
VDDPCIEX
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
SATACLKT
SATACLKC
VDDPCIEX
GND
PCIEXC4
PCIEXT4
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
26
PEREQ2#*/PCIEXC5
I/O
27
PEREQ1#*/PCIEXT5
I/O
28
VDDPCIEX
PWR
I/O
IN
PWR
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
4
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
29
CPUCLKC2_ITP/PCIEXC6
OUT
30
CPUCLKT2_ITP/PCIEXT6
OUT
31
32
VDDA
GNDA
PWR
PWR
33
IREF
OUT
34
CPUCLKC1
OUT
35
CPUCLKT1
OUT
36
VDDCPU
PWR
37
CPUCLKC0
OUT
38
CPUCLKT0
OUT
39
40
41
42
43
44
45
46
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REF0
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
47
REF1/FSLC/TEST_SEL
I/O
48
CPU_STOP#
IN
49
PCI/SRC_STOP#
IN
50
PCICLK2/REQ_SEL**
I/O
51
52
53
54
55
56
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
PWR
PWR
OUT
OUT
OUT
PWR
DESCRIPTION
Complementary clock of CPU_ITP/PCIEX differential pair CPU_ITP/PCIEX
output. These are current mode outputs. External resistors are required
for voltage bias. Selected by ITP_EN input.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
3.3V power for the PLL core.
Ground pin for the PLL core.
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test
Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
5
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
General Description
The ICS954226 is a CK410M compatible clock synthesizer. It provides a single-chip solution for mobile systems built with
Intel P4-M processors and Intel mobile chipsets. The device is driven with a 14.318MHz crystal and generates CPU outputs
up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI Express.
Block Diagram
REF(1:0)
USB_48MHz
X1
X2
XTAL
OSC.
FIXED PLL
DIVIDER
DOT_96MHz
PCICLK(5:2)
PCICLK_F(1:0)
PROG.
SPREAD
MAIN PLL
PCI/SRC_STOP#
CPU_STOP#
FSL(C:A)
ITP_EN
TEST_MODE
TEST_SEL
VTT_PWRGD#/PD
PEREQ#(2:1)
SDATA
SCLK
SELPCIEX_LCDCLK#
REQ_SEL
PCIEX(5:1)
PROG.
DIVIDERS
CPUCLK2/PCIEX6
CPUCLK(1:0)
LCDCLK_SS/PCIEX0
CONTROL
LOGIC
SATACLK
IREF
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
6
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Table2: LCDCLK Spread and Frequency Selection Table
Byte 6b7
Byte 6b6
Byte 6b5
0
0
0
0
0
Pin
17/18
MHz
96.00
0
0
0
0
1
96.00
0
0
0
1
0
96.00
0
0
0
1
1
96.00
0
0
1
0
0
96.00
0
0
1
0
1
96.00
0
0
1
1
0
96.00
0
0
1
1
1
96.00
0
1
0
0
0
96.00
0
1
0
0
1
96.00
0
1
0
1
0
96.00
0
1
0
1
1
96.00
0
1
1
0
0
96.00
0
1
1
0
1
96.00
0
1
1
1
0
96.00
0
1
1
1
1
96.00
1
0
0
0
0
100.00
1
0
0
0
1
100.00
1
0
0
1
0
100.00
1
0
0
1
1
100.00
1
0
1
0
0
100.00
1
0
1
0
1
100.00
1
0
1
1
0
100.00
1
0
1
1
1
100.00
1
1
0
0
0
100.00
1
1
0
0
1
100.00
1
1
0
1
0
100.00
1
1
0
1
1
100.00
1
1
1
0
0
100.00
1
1
1
0
1
100.00
1
1
1
1
1
1
1
1
0
1
100.00
Byte 6b4 Byte 6b3
100.00
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
Spread
%
0.8 Down
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
3 Down
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
0.8 Down
1 Down
1.25 Down
1.5 Down
1.75 Down
2 Down
2.5 Down
3 Down
+/-0.3 Center
+/-0.4 Center
+/-0.5 Center
+/-0.6 Center
+/-0.8 Center
+/-1.0 Center
+/-1.25 Center
+/-1.5 Center
0930A—04/13/10
7
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
General SMBus serial interface information for the 954226
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 1.
N
P
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
Not acknowledge
stoP bit
0930A—04/13/10
8
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: Output Control Register
Byte 0
Pin #
Name
Control
Type
0
1
PWD
Output Enable
RW
Disable
Enable
1
Function
Bit 7
-
CPUCLK2_ITP/PCIEX6
Enable
Bit 6
-
PCIEX5 Enable
Output Enable
RW
Disable
Enable
1
Bit 5
-
PCIEX4 Enable
Output Enable
RW
Disable
Enable
1
Bit 4
-
SATACLK Enable
Output Enable
RW
Disable
Enable
1
Bit 3
-
PCIEX3 Enable
Output Enable
RW
Disable
Enable
1
Bit 2
-
PCIEX2 Enable
Output Enable
RW
Disable
Enable
1
Bit 1
Bit 0
-
PCIEX1 Enable
Output Enable
RW
Output Enable
RW
Enable
Enable
1
LCDCLK/PCIEX0 Enable
Disable
Disable
Type
0
1
PWD
0
1
SMBus Table: Spread and Output Control Register
Bit 7
-
Test Clock Mode Entry
Control
Function
Test Mode
RW
Disable
Enable
Bit 6
-
DOT_96MHz Enable
Output Enable
RW
Disable
Enable
1
Bit 5
-
USB_48MHz Enable
Output Enable
RW
Disable
Enable
1
Bit 4
-
Output Enable
RW
Disable
Enable
1
Bit 3
-
Spread Control
RW
OFF
ON
1
Bit 2
-
RW
RW
Enable
-
Output Enable
Output Enable
Disable
Bit 1
REF_0 Enable
LCDCLK/PCIEX0 Spectrum
Mode
CPUCLK1
CPUCLK0
Disable
Enable
1
1
Bit 0
-
Spread Spectrum Mode
Spread Control for PLL1
RW
OFF
ON
0
Type
0
1
PWD
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Hi-Z
Enable
Enable
Enable
Enable
REF/N
1
1
1
1
0
RW
Enable
Disable
1
RW
RW
Disable
Disable
Enable
Enable
1
1
Type
0
1
PWD
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
RW
Free Running
Stoppable
0
Byte 1
Pin #
Name
SMBus Table: Output Control Register
Byte 2
Pin #
Name
PCICLK5
PCICLK4
PCICLK3
PCICLK2
Test Mode Selection
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
-
Bit 2
-
PCI_STOP
Bit 1
Bit 0
-
PCI_F0 Enable
PCI_F1 Enable
Control
Function
Output Enable
Output Enable
Output Enable
Output Enable
Test Mode Selection
Stop all PCI, PCIEX and
SATA clocks
Output Enable
Output Enable
SMBus Table: Output Control Register
Byte 3
Pin #
Name
Control
Function
Bit 7
-
PCIEX6
Bit 6
-
PCIEX5
Bit 5
-
PCIEX4
Bit 4
-
SATACLK
Bit 3
-
PCIEX3
Bit 2
-
PCIEX2
Bit 1
-
PCIEX1
RW
Free Running
Stoppable
0
Bit 0
-
PCIEX0
RW
Free Running
Stoppable
0
Allow assertion of
PCI_STOP# or setting of
PCI_STOP control bit in
SMBus register to stop
PCIEX clocks
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
9
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: Output Control Register
Bit 7
Bit 6
-
REF_1 Enable
96MHz
Control
Function
Output Enable
Driven in PD
Bit 5
-
REF_0 STRENGTH
Strength Programming
RW
1X
2X
1
Bit 4
Bit 3
Bit 2
-
PCI_F1
PCI_F0
CPUCLK2_ITP
Allow assertion of
PCI_STOP# or setting of
RW
RW
RW
Free Running
Free Running
Free Running
Stoppable
Stoppable
Stoppable
0
0
1
Bit 1
-
CPUCLK1
RW
Free Running
Stoppable
1
Bit 0
-
CPUCLK0
RW
Free Running
Stoppable
1
Byte 4
Pin #
Name
Allow assertion of
CPU_STOP# to stop
CPUCLK outputs
Type
0
1
PWD
RW
RW
Disable
Driven
Enable
Hi-Z
1
1
SMBus Table: Output Control Register
Byte 5
Name
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
PCI_STOP Drive Mode
CPUCLK2_ITP_STOP Drive
Mode
CPUCLK1_STOP Drive
Mode
CPUCLK0_STOP Drive
Mode
Control
Function
Driven in PCI_STOP#
Driven in CPU_STOP#
PCIEX (6:0) Drive Mode
Type
0
1
PWD
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
RW
Driven
Hi-Z
0
CPUCLK2_ITP_PD Drive
Mode
CPUCLK[1:0] PD Drive
Mode
Driven in Powerdown (PD)
ITP_EN
PCIEX/CPU_ITP select
RW
PCIEX
CPU_ITP
latch
Name
Control
Function
Type
0
1
PWD
96Mhz
100Mhz
0
SMBus Table: Output Control Register
Byte 6
Pin #
Bit 7
-
SS4
LCDCLK Spread Prog Bit 4
RW
Bit 6
-
SS3
LCDCLK Spread Prog Bit 3
RW
Bit 5
-
SS2
LCDCLK Spread Prog Bit 2
RW
Bit 4
-
SS1
LCDCLK Spread Prog Bit 1
RW
0
Bit 3
Bit 2
-
SS0
FSLC
LCDCLK Spread Prog Bit 0
Freq Select Bit 2
RW
RW
0
Latched
Bit 1
-
FSLB
Freq Select Bit 1
RW
Bit 0
-
FSLA
Freq Select Bit 0
RW
Control
Function
Type
0
1
PWD
R
R
R
R
R
R
R
R
-
-
x
x
x
x
0
0
0
1
1
See Table 2: LCDCLK Freq Sel
See Table 1: PLL1 Frequency Selection
Table
0
Latched
Latched
SMBus Table: Vendor & Revision ID Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
REVISION ID
VENDOR ID
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
10
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: Byte Count Register
Byte 8
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control
Function
Type
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Byte Count Programming
b(7:0)
RW
RW
RW
RW
RW
RW
RW
RW
Name
Control
Function
Type
0
1
Name
Pin #
0
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
PWD
0
0
0
0
1
1
1
1
SMBus Table: Watchdog Timer Register
Byte 9
Pin #
PWD
Bit 7
-
WDH_EN
Watchdog Hard Alarm Enable
RW
Disable
Enable
0
Bit 6
Bit 5
Bit 4
-
WDS_EN
WD Hard Status
WD Soft Status
RW
R
R
Disable
Normal
Normal
Enable
Alarm
Alarm
0
X
X
Bit 3
-
WDTCtrl
RW
290ms Base
1160ms Base
0
Bit 2
Bit 1
Bit 0
-
WD2
WD1
WD0
Watchdog Soft Alarm Enable
WD Hard Alarm Status
WD Soft Alarm Status
Watch Dog Time base
Control
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
RW
RW
RW
These bits represent X*290ms (or 1.16S)
the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
1
1
1
SMBus Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
M/N_EN
PLLM/N Programming Enable
RW
Disable
Enable
0
Bit 6
-
LCDCLK/PCIEX0 SEL
SELPCIEX0/LCDCLK#
RW
LCDCLK
PCIEX0
latch
Bit 5
-
REQ_SEL
REQ_SEL
RW
PCIEX5
PEREQ
latch
Bit 4
-
LCDCLK/PCIEX0
Driven in PD
RW
Driven
Hi-Z
0
Bit 3
-
WD Safe Freq Source
WD Safe Freq Source
RW
Latch
Inputs/Byte6[2:0]
B10b(2:0)
0
Bit 2
-
WD SFC
Bit 1
-
WD SFB
Bit 0
-
WD SFA
Watch Dog Safe Freq
Programming bits
RW
RW
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
RW
0
0
0
SMBus Table: VCO Frequency Control Register
Bit 7
-
N Div8
Control
Function
N Divider Prog bit 8
Bit 6
-
N Div 9
N Divider Prog bit 9
Bit 5
-
M Div5
Bit 4
-
M Div4
Bit 3
-
M Div3
Bit 2
-
M Div2
RW
Bit 1
-
M Div1
RW
X
Bit 0
-
M Div0
RW
X
Byte 11
Pin #
Name
Type
PWD
RW
X
X
RW
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
1
RW
RW
M Divider Programming bits
0
RW
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
X
X
X
X
0930A—04/13/10
11
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: VCO Frequency Control Register
Pin #
Byte 12
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
-
Control
Function
0
Type
N Divider Programming
b(8:0)
N Div0
RW
RW
RW
RW
RW
RW
RW
1
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: Spread Spectrum Control Register
Byte 13
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
-
Control
Function
Type
Spread Spectrum
Programming b(7:0)
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
PWD
X
X
X
X
X
X
X
X
SMBus Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Control
Function
Reserved
Type
0
1
PWD
R
-
-
0
Bit 7
-
Reserved
Bit 6
-
SSP14
RW
Bit 5
-
SSP13
RW
Bit 4
-
SSP12
RW
Bit 3
-
SSP11
Bit 2
-
SSP10
RW
Bit 1
-
SSP9
RW
X
Bit 0
-
SSP8
RW
X
Spread Spectrum
Programming b(14:8)
RW
X
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
X
X
X
X
SMBus Table: Output Divider Control Register
Byte 15
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
Name
PCIEX Div3
PCIEX Div2
PCIEX Div1
PCIEX Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
Control
Function
Type
PCIEX Divider Ratio
Programming Bits
CPUDivider Ratio
Programming Bits
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0000:/2
0001:/3
0010:/5
0011:/15
0000:/2
0001:/3
0010:/5
0011:/15
0100:/4
0101:/6
0110:/10
0111:/30
0100:/4
0101:/6
0110:/10
0111:/30
1000:/8
1001:/12
1010:/20
1011:/60
1000:/8
1001:/12
1010:/20
1011:/60
1100:/16
1101:/24
1110:/40
1111:/120
1100:/16
1101:/24
1110:/40
1111:/120
PWD
X
X
X
X
X
X
X
X
0930A—04/13/10
12
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: PEREQ# Control Register
Control
Byte 16
Pin #
Name
Function
Type
0
1
PWD
Bit 7
-
Reserved
Reserved
RW
-
-
0
Bit 6
-
PCIEX4 is controlled
RW
Not Controlled
Controlled
0
Bit 5
-
PCIEX3 is controlled
RW
Not Controlled
Controlled
0
Bit 4
-
PEREQ2# controls selected
outputs. Outputs controlled
by this pin will be Hi-Z when
PEREQ2# is high.
PCIEX1 is controlled
RW
Not Controlled
Controlled
0
Bit 3
-
Reserved
Reserved
RW
-
-
0
Bit 2
-
SATACLK is controlled
RW
Not Controlled
Controlled
0
Bit 1
-
PCIEX2 is controlled
RW
Not Controlled
Controlled
0
Bit 0
-
PEREQ1# controls selected
outputs. Outputs controlled
by this pin will be Hi-Z when
PEREQ1# is high.
PCIEX0 is controlled
RW
Not Controlled
Controlled
0
Type
0
1
PWD
SMBus Table: PLL 2 VCO Frequency Control Register
Pin #
Byte 17
Name
Control
Function
N Divider Prog bit 8
N Divider Prog bit 9
Bit 7
Bit 6
-
N Div8
N Div9
Bit 5
-
M Div5
Bit 4
-
M Div4
Bit 3
-
M Div3
Bit 2
-
M Div2
RW
Bit 1
-
M Div1
RW
X
Bit 0
-
M Div0
RW
X
RW
RW
RW
RW
M Divider Programming bits
RW
X
X
The decimal representation of M and N
Divier in Byte 17 and 18 will configure the
VCO frequency. Default at power up =
Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
X
X
X
X
SMBus Table: PLL 2 VCO Frequency Control Register
Byte 18
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control
Function
Type
N Divider Programming
b(8:0)
RW
RW
RW
RW
RW
RW
RW
RW
Control
Function
Type
0
1
The decimal representation of M and N
Divier in Byte 17 and 18 will configure the
VCO frequency. Default at power up =
Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL 2 Spread Spectrum Control Register
Byte 19
Pin #
Name
Bit 7
-
SSP7
RW
Bit 6
Bit 5
Bit 4
Bit 3
-
SSP6
SSP5
SSP4
SSP3
RW
RW
RW
RW
Bit 2
Bit 1
Bit 0
-
SSP2
SSP1
SSP0
Spread Spectrum
Programming b(7:0)
RW
RW
RW
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0
1
PWD
X
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
X
X
X
X
X
X
X
0930A—04/13/10
13
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
SMBus Table: PLL2 Spread Spectrum Control Register
Byte 20
Pin #
Name
Control
Function
Reserved
Type
0
1
PWD
R
-
-
0
Bit 7
-
Reserved
Bit 6
Bit 5
Bit 4
-
SSP14
SSP13
SSP12
Bit 3
-
SSP11
Bit 2
-
SSP10
Bit 1
-
SSP9
RW
Bit 0
-
SSP8
RW
RW
RW
RW
Spread Spectrum
Programming b(14:8)
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
RW
RW
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
X
X
X
X
X
X
X
0930A—04/13/10
14
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Absolute Maximum Rating
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage
VDDA
MIN
MAX
UNITS
Notes
-
4.6
V
1
-
4.6
V
1
150
70
125
°
C
°C
°C
1
1
1
V
1
UNITS
Notes
V
1
V
uA
1
1
-5
uA
1
-200
uA
1
3.3V Logic Input Supply
VDD
Voltage
Storage Temperature
Ts
Ambient Operating Temp Tambient
Junction Temperature
Tj
-
-65
0
Input ESD protection HBM ESD prot
-
2000
1
TYP
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
Input High Voltage
V IH
3.3 V +/-5%
2
Input Low Voltage
Input High Current
V IL
I IH
VSS - 0.3
-5
I IL2
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up resistors
VIH_FSL
3.3 V +/-5%
0.7
1.7
V
1
VSS - 0.3
0.35
V
1
400
70
12
7
5
6
5
mA
mA
mA
MHz
nH
pF
pF
pF
1
1
1
2
1
1
1
1
1.8
ms
1
33
kHz
1
300
us
1
5
5
5.5
0.4
ns
ns
V
V
1
1
1
1
mA
1
1000
ns
1
300
ns
1
Input Low Current
I IL1
Low Threshold InputHigh Voltage
Low Threshold InputLow Voltage
Operating Supply Current
VIL_FSL
3.3 V +/-5%
IDD3.3OP
Powerdown Current
IDD3.3PD
Input Frequency
Pin Inductance
Fi
Lpin
CIN
COUT
CINX
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
Input Capacitance
Clk Stabilization
TSTAB
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion of
PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
VDD
VOL
TFI2C
MAX
VDD +
0.3
0.8
5
14.31818
30
2.7
@ IPULLUP
4
IPULLUP
TRI2C
TYP
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
15
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Zo
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Vx(abs)
d-Vx
ppm
Statistical measurement on single
ended signal
Measurement on single ended signal
using absolute value.
660
-150
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Rise/Fall Matching
tr
tf
d-tr
d-tf
trfm
Duty Cycle
dt3
Skew
tsk3
Skew
Jitter, Cycle to cycle
Jitter, Cycle to cycle
Variation of crossing over all edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Measurement from differential wavefrom
TYP
-300
250
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
45
CPU(1:0), VT = 50%
CPU(1:0) to CPU2_ITP,
tsk4
VT = 50%
Measurement from differential wavefrom
tjcyc-cyc
(CPU2_ITP)
Measurement from differential
tjcyc-cyc
wavefrom, (CPU(1:0))
MAX
UNITS
Notes
Ω
1
700
700
125
125
20
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
%
1,3
1,3
1
1
1
1
1,2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
55
%
1
100
ps
1
150
ps
1
125
ps
1
85
ps
1
850
150
1150
550
140
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
*T A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
16
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Electrical Characteristics - SATA/PCIEX/[email protected] 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Zo
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Vx(abs)
d-Vx
ppm
Statistical measurement on single
ended signal
Measurement on single ended signal
using absolute value.
660
-150
Average period
Tperiod
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Rise/Fall Matching
Tabsmin
tr
tf
d-tr
d-tf
trfm
Duty Cycle
dt3
Measurement from differential wavefrom
Skew
tsk3
VT = 50%
Jitter, Cycle to cycle
TYP
UNITS
Notes
Ω
1
700
700
125
125
20
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ns
ps
ps
ps
ps
%
1,3
1,3
1
1
1
1
1,2
2
2
1,2
1
1
1
1
1
55
%
1
250
ps
1
125
ps
1
850
150
1150
-300
250
Variation of crossing over all edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
MAX
550
140
300
10.0030
10.0533
-300
9.9970
9.9970
9.8720
175
175
45
tjcyc-cyc Measurement from differential wavefrom
*TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9ΩΒIREF = 475Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ Z O=50Ω.
Electrical Characteristics - DOT_96MHz/[email protected] 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
MIN
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Average period
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Rise/Fall Matching
Zo
VO = Vx
3000
VHigh
VLow
Vovs
Vuds
Vx(abs)
d-Vcross
ppm
Tperiod
Tabsmin
tr
tf
d-tr
d-tf
trfm
Statistical measurement on single
ended signal
Measurement on single ended signal
using absolute value.
660
-150
Duty Cycle
dt3
Measurement from differential wavefrom
Jitter, Cycle to cycle
Variation of crossing over all edges
see Tperiod min-max values
96.00MHz nominal
96.00MHz nominal
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
-300
250
-100
10.4135
10.1635
175
175
45
tjcyc-cyc Measurement from differential wavefrom
MAX
UNITS
Notes
Ω
1
700
700
125
125
20
mV
mV
mV
mV
mV
mV
ppm
ns
ns
ps
ps
ps
ps
%
1,3
1,3
1
1
1
1
1,2
2
1,2
1
1
1
1
1
55
%
1
250
ps
1
850
150
1150
550
140
100
10.4198
*T A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS =33.2Ω, RP =49.9ΩΤIREF = 475Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ Z O=50Ω.
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
17
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
RDSP
VOH
VOL
Output High Current
I OH
Output Low Current
IOL
Edge Rate
tslewr/f
Duty Cycle
Group Skew
Jitter, Cycle to cycle
dt1
tskew
CONDITIONS*
VO = VDD*(0.5)
I OH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
tjcyc-cyc
MIN
12
2.4
TYP
MAX
55
38
V
V
mA
mA
mA
mA
Notes
1
1
1
1
1
1
1
1
4
V/ns
1
45
55
500
250
%
ps
ps
1
1
1
MAX
100
20.8354
55
UNITS
ppm
ns
Ω
Notes
1
0.55
-33
-33
30
UNITS
Ω
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - 48MHz
PARAMETER
Long Accuracy
Clock period
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
ppm
Tperiod
RDSP
VOH
VOL
Output High Current
I OH
Output Low Current
IOL
Edge Rate
t slewr/f_48
Duty Cycle
Jitter, Cycle to cycle
dt1
tjcyc-cyc
CONDITIONS*
see Tperiod min-max values
48.00MHz output nominal
VO = VDD*(0.5)
I OH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
48M Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
VT = 1.5 V
MIN
-100
20.8313
12
2.4
TYP
38
V
V
mA
mA
mA
mA
1
1
1
1
1
1
1
1
2
V/ns
1
45
55
500
%
ps
1
1
MAX
UNITS
Notes
300
69.8550
0.4
ppm
ns
V
V
1,2
2
1
1
-29
-23
mA
1
29
27
mA
1
1
4
V/ns
1
45
55
1000
%
ps
1
1
0.55
-33
-33
30
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 33Ω
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
Long Accuracy
Clock period
Output High Voltage
Output Low Voltage
ppm
Tperiod
VOH
VOL
-300
69.8270
2.4
Output High Current
IOH
Output Low Current
IOL
Edge Rate
tslewr/f
Duty Cycle
Jitter
dt1
tjcyc-cyc
see Tperiod min-max values
14.318MHz output nominal
IOH = -1 mA
IOL = 1 mA
VOH @MIN = 1.0 V,
[email protected] = 3.135 V
VOL @MIN = 1.95 V,
VOL
@MAX = 0.4 V
Rising/Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VT = 1.5 V
VT = 1.5 V
TYP
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 39Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
18
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Test Clarification Table
Comments
SW
HW
T_SEL
T_MODE
HW PIN
0
1
1
1
HW PIN
X
0
0
1
TEST
ENTRY
BIT
W1b7
0
X
X
X
1
1
X
1
REF/N
0
X
1
0
HI-Z
0
X
1
1
REF/N
FSLC/TES FSLB/TES
· FS_C/TEST_SEL is a 3-level latched input.
o Power-up w/ V >= 2.0V to select TEST
o Power-up w/ V < 2.0V to have pin function as
FS_C.
· When pin is FS_C, VIH_FS and VIL_FS levels
apply.
· FS_B/TEST_MODE is a low-threshold input
o VIH_FS and VIL_FS levels apply.
o TEST_MODE is a real time input
· TEST_SEL can be invoked after power up
through SMBus B1b7.
o If TEST is selected by B1b7, only B2b3 controls
TEST_MODE. The FS_B/TEST_Mode pin is not
used.
· Power must be cycled to exit TEST.
REF/N or
HI-Z
W2b3
OUTPUT
X
NORMAL
0
HI-Z
1
REF/N
0
REF/N
W1b7: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
W2b3: 1= REF/N, Default = 0 (HI-Z)
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
19
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
c
N
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
A1
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
aaa
-0.10
-.004
-Ce
b
SEATING
PLANE
aaa C
VARIATIONS
N
56
D mm.
MIN
MAX
13.90
14.10
D (inch)
MIN
.547
MAX
.555
Reference Doc.: JEDEC Publicat ion 95, M O-153
10-0039
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
20
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
(Ref.)
Seating Plane
(N D -1)x e
(Ref.)
A1
Index Area
L
A3
N
N
1
Anvil
Singulation
E2
(N -1)x e
(Ref.)
2
b
(Re f.)
A
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
are Even
E2
Sawn
Singulation
D
(T yp.)
e
2 If N & N
D
2
OR
Top V iew
ND & N
Even
e
D2
2
ND & N
Odd
Thermal
Base
D2
0. 08
C
C
THERMALLY ENHANCED, VERY THIN, FINE PITCH
QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS
SYMBOL
A
A1
A3
b
e
DIMENSIONS
MIN.
MAX.
0.8
1.0
0
0.05
0.25 Reference
0.18
0.3
0.50 BASIC
ICS 56L
SYMBOL
VLLD-2 / -5 TOLERANCE
N
56
56
ND
14
14
NE
14
14
D x E BASIC
8.00 x 8.00 8.00 x 8.00
D2 MIN. / MAX. 2.75 / 6.80
4.35 / 4.65
E2 MIN. / MAX. 2.75 / 6.80
5.05 / 5.35
L MIN. / MAX. 0.30 / 0.50
0.30 / 0.50
Ordering Information
Part / Order Number
954226AGLF
954226AGLFT
954226AKLF
954226AKLFT
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
56-pin TSSOP
56-pin TSSOP
56-pin MLF
56-pin MLF
Temperature
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
“LF” to the suffix are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
IDT® Programmable Timing Control HubTM for Mobile P4TM Systems
0930A—04/13/10
21
954226
Programmable Timing Control HubTM for Mobile P4TM Systems
Revision History
Rev.
0.1
Issue Date
3/29/2005
Who
JC
0.2
7/14/2006
DC
A
4/12/2010
RDW
Description
Updated Ordering Information from "Lead Free" to "Annealed Lead Free"
Added MLF Pinout, Pin Description and Ordering Information.
1. Clean up Electrical Tables
2. Corrected Test Clarification Table
3. Move to final
Page #
18
1, 4, 5, 21
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