DG721, DG722, DG723 Datasheet

DG721, DG722, DG723
Vishay Siliconix
1.8 V to 5.5 V, 4  Dual SPST Switches
DESCRIPTION
FEATURES
The DG721, DG722 and DG723 are precision dual SPST
switches designed to operate from single 1.8 V to 5.5 V
power supply with low power dissipation. The DG721,
DG722 and DG723 can switch both analog and digital
signals within the power supply rail, and conduct well in both
directions.
Fabricated with advance submicron CMOS process, these
switches provide high precision low and flat ON resistance,
low leakage current, low parasitic capacitance, and low
charge injection.
The DG721, DG722 and DG723 contain two independent
Single Pole Single Throw (SPST) switches. Switch-1 and
switch-2 are normally open for the DG721 and normally
closed for the DG722. For the DG723, switch-1 is normally
open and switch-2 is normally closed with a Break-BeforeMake switching timing.
The DG721, DG722 and DG723 are the ideal switches for
use in low voltage instruments and healthcare devices, fitting
the circuits of low voltage ADC and DAC, analog front end
gain control, and signal path control.
As a committed partner to the community and the
environment, Vishay Siliconix manufactures this product with
lead (Pb)-free device termination. The TDFN8 package has
a nickel-palladium-gold device termination and is
represented by the lead (Pb)-free “-E4” suffix to the ordering
part number. The MSOP-8 package has tin device
termination and is represented by “-E3”. Both device
terminations meet all JEDEC standards for reflow and MSL
rating.
As a further sign of Vishay Siliconix's commitment, the
DG721, DG722 and D723 are fully RoHS compliant and
Halogen-free.
• Halogen-free according to IEC 61249-2-21
definition
• 1.8 V to 5.5 V single power supply
• Low and flat switch on resistance, 2.5 /typ.
• Low leakage and parasitic capacitance
• 366 MHz, - 3 dB bandwidth
• Latch-up current > 300 mA (JESD78)
• Space saving packages
2 mm x 2 mm TDFN8
MSOP8
• Over voltage tolerant TTL/CMOS compatible
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
•
•
•
•
•
•
•
•
•
Healthcare and medical devices
Test instruments
Portable meters
Data acquisitions
Control and automation
PDAs and modems
Communication systems
Audio, video systems
Mechanical reed relay replacement
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG721, MSOP-8
DG721, TDFN-8
NO1
1
8
V+
COM1
2
7
IN1
IN2
3
6
COM2
GND
4
5
NO2
Top View
NO1 1
8 V+
V+
8
1
NO1
COM1 2
7 IN1
IN1
7
2
COM1
6 COM2 COM2 6
3
IN2
5 NO2
4 GND
IN2 3
GND 4
Top View
NO2 5
Bottom View
ADX
Pin 1
Device Marking for TDFN-8: for DG721
x = Date/Lot Traceability Code
Device Marking for MSOP-8: 721
Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG721, DG722, DG723
Vishay Siliconix
DG722, MSOP-8
DG722, TDFN-8
NC 1
1
8
V+
COM1
2
7
IN1
IN2
3
6
COM2
GND
4
5
NC2
NC 1 1
8 V+
V+
8
1
NC 1
COM1 2
7 IN1
IN1
7
2
COM1
6 COM2 COM2 6
3
IN2
5 NC2
4 GND
IN2 3
GND 4
Top View
NC 2 5
Top View
AEX
Pin 1
Device Marking for TDFN-8: for DG722
x = Date/Lot Traceability Code
Bottom View
Device Marking for MSOP-8: 722
DG723, MSOP-8
DG723, TDFN-8
NO1
1
8
V+
COM1
2
7
IN1
IN2
3
6
COM2
GND
4
5
NC2
NO1 1
8 V+
V+
8
1
NO1
COM1 2
7 IN1
IN1
7
2
COM1
6 COM2 COM2 6
3
IN2
IN2 3
5 NC2
GND 4
Top View
Top View
NC 2 5
AFX
4 GND Pin 1
Bottom View
Device Marking for TDFN-8: for DG723
x = Date/Lot Traceability Code
Device Marking for MSOP-8: 723
TRUTH TABLE (DG721, DG722)
Logic
TRUTH TABLE (DG723)
DG721
DG722
Switches
Logic
Switch-1
Switch-2
0
1
Off
0
Off
On
1
0
On
1
On
Off
ORDERING INFORMATION
Temperature Range
Package
Part Number
DG721DQ-T1-GE3
MSOP-8
DG722DQ-T1-GE3
DG723DQ-T1-GE3
- 40 °C to 85 °C
DG721DN-T1-GE4
TDFN-8
DG722DN-T1-GE4
DG723DN-T1-GE4
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Referenced V+ to GND
- 0.3 to 6
IN, COM, NC, NOa
- 0.3 to (V+ + 0.3)
Continuous Current (Any Terminal)
± 50
Peak Current (Pulsed at 1 ms, 10 % duty cycle)
± 200
Storage Temperature (D Suffix)
Power Dissipation (Packages)b
Unit
mA
- 65 to 150
c
MSOP-8
320
TDFN-8d
842
V
°C
mW
Notes:
a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 4 mW/°C above 70 °C.
d. Derate 10.53 mW/°C above 70 °C.
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Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG721, DG722, DG723
Vishay Siliconix
SPECIFICATIONS (V+ = 3 V)
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 3 V, ± 10 %, VIN = 0.4 or 1.5 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
Full
0
Typ.c
Max.b
Unit
V+
V
Analog Switch
VNO, VNC
VCOM
Analog Signal Ranged
On-Resistance
RON
V+ = 2.7 V, VCOM = 0 V to V+, INO, INC = - 10 mA
Room
Full
6.5
RON Flatnessd
RON
Flatness
V+ = 2.7 V, VCOM = 1.1 V to 1.6 V,
INO, INC = - 10 mA
Room
0.4
RON
Match
V+ = 2.7 V, VD = 1.1 V to 1.6 V, ID = - 10 mA
Room
Full
0.3
RON Matchd
Switch Off Leakage Current
INO(off)
INC(off)
ICOM(off)
Channel-On Leakage Current
ICOM(on)
V+ = 3.3 V
VNO, VNC = 1 V/3 V, VCOM = 3 V/1 V
V+ = 3.3 V, VNO, VNC = VCOM = 1 V/3 V
10

0.9
Room
Full
- 0.25
- 0.35
0.25
0.35
Room
Full
- 0.25
- 0.35
0.25
0.35
Room
Full
- 0.25
- 0.35
0.25
0.35
2
nA
Digital Control
Input High Voltage
VINH
Full
Input Low Voltage
VINL
Full
Input Capacitanced
Input Current
Cin
f = 1 MHz
Full
IINL or IINH
VIN = 0 or V+
Full
tON
VNO or VNC = 2 V, RL = 300 , CL = 35 pF
figures 1 and 2
0.4
2.4
-1
V
pF
1
µA
Dynamic Characteristics
Turn-On Time
tOFF
Turn-Off Time
Charge
Injectiond
Bandwidth
d
Off-Isolation
d
QINJ
CL = 1 nF, VGEN = 0 V, RGEN = 0 , figure 3
BW
V+ = 3 V, RL = 50 , CL = 5 pF, - 3dB
OIRR
Crosstalkd
XTALK
Off-Isolationd
OIRR
Crosstalkd
Source-Off Capacitance
XTALK
d
RL = 50 , CL = 5 pF, f = 1 MHz
RL = 50 , CL = 5 pF, f = 10 MHz
CNC/NO(off)
Drain-Off Capacitanced
CCOM(off)
d
Channel-On Capacitance
VIN = 0 or V+, f = 1 MHz
CON
Room
Full
16
Room
Full
7
Room
1.8
pC
MHz
55
ns
40
Room
319
Room
- 67
Room
- 92
Room
- 47
Room
- 90
Room
8
Room
9
Room
22
dB
pF
Power Supply
Power Supply Current
Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
I+
VIN = 0 or V+, V+ = 3.3 V
1
µA
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG721, DG722, DG723
Vishay Siliconix
SPECIFICATIONS (V+ = 5 V)
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 5 V, ± 10 %, VIN = 0.8 or 2.4 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
Full
0
Typ.c
Max.b
Unit
V+
V
Analog Switch
VNO, VNC
VCOM
Analog Signal Ranged
On-Resistance
RON
V+ = 4.5 V, VCOM = 0 V to V+, INO, INC = 10 mA
Room
Full
2.5
4.5
5
RON Flatnessd
RON
Flatness
V+ = 4.5 V, VCOM = 1.3 V to 3 V, INO, INC = 10 mA
Room
0.75
1.5
RON
Match
V+ = 4.5 V, ID = 10 mA, VCOM = 1.3 V to 3 V
Room
0.2
0.9
RON Matchd
Switch Off Leakage Current
INO(off)
INC(off)
ICOM(off)
Channel-On Leakage Current
ICOM(on)
V+ = 5.5 V
VNO, VNC = 1 V/4.5 V, VCOM = 4.5 V/1 V
V+ = 5.5 V
VNO, VNC = VCOM = 1 V/4.5 V
Room
Full
- 0.25
- 0.35
0.25
0.35
Room
Full
- 0.25
- 0.35
0.25
0.35
Room
Full
- 0.25
- 0.35
0.25
0.35
2.4

nA
Digital Control
Input High Voltage
VINH
Full
Input Low Voltage
VINL
Full
Cin
f = 1 MHz
Full
IINL or IINH
VIN = 0 or V+
Full
Turn-On Timed
tON
Turn-Off Timed
tOFF
VNO or VNC = 3 V, RL = 300 , CL = 35 pF
figures 1 and 2
Charge Injectiond
QINJ
CL = 1 nF, VGEN = 0 V, RGEN = 0 , figure 3
BW
V+ = 5 V, RL = 50 , CL = 5 pF, - 3 dB
Input Capacitance
Input Current
V
0.8
2.2
- 0.1
pF
0.005
0.1
µA
Room
Full
17
30
40
Room
Full
9
Room
2.2
pC
MHz
Dynamic Characteristics
d
Bandwidth
Off-Isolationd
OIRR
Crosstalkd
XTALK
Off-Isolationd
OIRR
Crosstalkd
XTALK
Source-Off Capacitance
Drain-Off
d
RL = 50 , CL = 5 pF, f = 10 MHz
CNC/NO(off)
Capacitanced
Channel-On Capacitance
RL = 50 , CL = 5 pF, f = 1 MHz
CCOM(off)
d
VIN = 0 or V+, f = 1 MHz
CON
ns
35
Room
366
Room
- 67
Room
- 90
Room
- 47
Room
- 90
Room
8
Room
9
Room
22
dB
pF
Power Supply
Power Supply Range
V+
Power Supply Current
I+
1.8
VIN = 0 or V+, V+ = 5.5 V
Full
5.5
V
2
µA
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Not production tested.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG721, DG722, DG723
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
35
T = 25 °C
INO/NC = - 10 mA
30
RON - On-Resistance (Ω)
RON - On-Resistance (Ω)
V+ = 1.8 V
25
20
V+ = 2.4 V
15
V+ = 2.7 V
V+ = 3.0 V
V+ = 3.3 V
V+ = 4.5 V
V+ = 5.0 V
V+ = 5.5 V
10
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V+ = 2.7 V
INO/NC = - 10 mA
+ 25 °C
+ 85 °C
- 40 °C
5.5
VD - Analog Voltage (V)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
VD - Analog Voltage (V)
RON vs. VD and Single Supply Voltage
RON vs. Analog Voltage and Temperature
5.0
10 mA
V+ = 4.5 V
INO/NC = - 10 mA
4.5
1 mA
+ 25 °C
+ 85 °C
3.5
V+ = 5.5 V
I+ - Supply Current (A)
4.0
RON - On-Resistance (Ω)
10
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
- 40 °C
3.0
2.5
2.0
1.5
100 µA
10 µA
1 µA
V+ = 5.0 V
V+ = 3.3 V
100 nA
10 nA
V+ = 3.0 V
1.0
V+ = 1.8 V
1 nA
0.5
0.0
0.0
100 pA
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10
4.5
100
VD - Analog Voltage (V)
RON vs. Analog Voltage and Temperature
VT - Switching Threshold (V)
Leakage Current (pA)
V+ = 5.5 V
10
ICOM(ON)
ICOM(OFF)
INO(OFF)
0.1
- 60
- 40
- 20
0
20
40
60
Temperature (°C)
80
100
Leakage Current vs. Temperature
Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
10 M
Supply Current vs. Input Switching Frequency
100
1
1K
10 K
100 K
1M
Input Switching Frequency (Hz)
120
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
1.5
VIH
VIL
2.0
2.5
3.0
3.5
4.0
4.5
V+ - Supply Voltage (V)
5.0
5.5
Switching Threshold vs. Supply Voltage
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG721, DG722, DG723
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
0
0
-1
- 10
- 20
-2
Off Isolation (dB)
- 30
Loss (dB)
-3
-4
-5
- 40
- 50
- 60
- 70
-6
- 80
-7
- 90
-8
1
10
100
1000
Frequency (MHz)
- 100
10 000
10
100
Frequency (MHz)
1
Off Isolation vs. Frequency
0
5
- 10
4
- 20
3
- 30
2
- 40
1
Charge (PC)
Crosstalk (dB)
Insertion Loss vs. Frequency
- 50
- 60
- 80
-3
- 90
-4
10
100
Frequency (MHz)
V+ = 2.7 V
V+ = 5.5 V
V+ = 4.5 V
-1
-2
1
V+ = 3 V
0
- 70
- 100
1000
CL = 1 nF
-5
1000
0
Crosstalk vs. Frequency
1
2
3
4
Source Volts
5
6
Charge Injection vs. Analog Voltage
TEST CIRCUITS
V+
Logic
Input
Switch
Input
tr < 5 ns
tf < 5 ns
Switch Output
COM
VOUT
0.9 x VOUT
IN
Logic
Input
50 %
VINL
V+
NO or NC
VINH
RL
300 Ω
GND
CL
35 pF
Switch
Output
0V
tON
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
CL (includes fixture and stray capacitance)
VOUT = VCOM
tOFF
RL
R L + R ON
Figure 1. Switching Time
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Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG721, DG722, DG723
Vishay Siliconix
TEST CIRCUITS
V+
ΔVOUT
V+
Rgen
COM
VOUT
NC or NO
VOUT
+
IN
Vgen
IN
CL = 1 nF
On
On
Off
GND
Q = ΔVOUT x CL
VIN = 0 - V+
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 2. Charge Injection
V+
V+
10 nF
10 nF
V+
V+
NC or NO
COM
0 V, 2.4 V
IN
Meter
COM
IN
0 V, 2.4 V
RL
NC or NO
GND
HP4192A
Impedance
Analyzer
or Equivalent
GND
f = 1 MHz
Analyzer
V COM
Off Isolation = 20 log V
NO/ NC
Figure 4. Channel Off/On Capacitance
Figure 3. Off-Isolation
V+
10 nF
V+
COM 1
RL
NC 1
VIN 1
NO 2
COM 2
VIN 2
Analyzer
GND
RL
Figure 5. Channel to Channel Crosstalk
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66586.
Document Number: 66586
S11-1799-Rev. F, 12-Sep-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
Case Outline for TDFN8 2 x 2
Index Area
(D/2 x E/2)
MILLIMETERS
A
A3
A1 (6)
D
7
E
2
DIM.
MIN.
NOM.
MAX.
MIN.
NOM.
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0.00
-
0.05
0.000
-
0.002
A3
8
1
INCHES
0.152 REF
MAX.
0.006 REF
b
0.18
0.23
0.28
0.007
0.009
0.011
D
1.95
2.00
2.05
0.077
0.079
0.081
D2
0.75
0.80
0.85
0.030
0.031
0.033
3
6
e
E
1.95
2.00
2.05
0.077
0.079
0.081
4
5
E2
1.40
1.45
1.50
0.055
0.057
0.059
K
-
0.25
-
-
0.010
-
L
0.30
0.35
0.40
0.012
0.014
0.016
Top View
0.05 C
(7)
Side View
D2
Note
(1) All dimensions are in millimeters which will govern.
(2) Max. package warpage is 0.05 mm.
(3) Max. allowable burrs is 0.076 mm in all directions.
(4) Pin #1 ID on top will be laser/ink marked.
(5) Dimension applies to meatlized terminal and is measured
between 0.20 mm and 0.25 mm from terminal tip.
(6) Applied only for terminals.
(7) Applied for exposed pad and terminals.
b (5)
1
7
2
6
3
5
4
e
E2
8
0.020 BSC
ECN: T15-0301-Rev. B, 29-Jun-15
DWG: 5997
L
Pin 1 Indicator
(Optional)
0.50 BSC
K
K
Bottom View
Revison: 29-Jun-15
1
Document Number: 67493
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
MSOP:
8−LEADS
JEDEC Part Number: MO-187, (Variation AA and BA)
(N/2) Tips)
2X
5
A B C 0.20
N N-1
0.60
0.48 Max
Detail “B”
(Scale: 30/1)
Dambar Protrusion
E
1 2
0.50
N/2
0.60
0.08 M C B S
b
A S
7
Top View
b1
e1
With Plating
e
A
See Detail “B”
c1
0.10 C
-H-
A1
D
6
Seating Plane
c
Section “C-C”
Scale: 100/1
(See Note 8)
Base Metal
-A-
3
See Detail “A”
Side View
0.25
BSC
C
Parting Line
0.07 R. Min
2 Places
Seating Plane
ς
A2
0.05 S
C
E1
-B-
L 4
T
-C-
3
0.95
End View
Detail “A”
(Scale: 30/1)
N = 8L
NOTES:
1.
Die thickness allowable is 0.203"0.0127.
2.
Dimensioning and tolerances per ANSI.Y14.5M-1994.
3.
Dimensions “D” and “E1” do not include mold flash or protrusions, and are
measured at Datum plane -H- , mold flash or protrusions shall not exceed
0.15 mm per side.
4.
Dimension is the length of terminal for soldering to a substrate.
5.
Terminal positions are shown for reference only.
6.
Formed leads shall be planar with respect to one another within 0.10 mm at
seating plane.
7.
The lead width dimension does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the lead width
dimension at maximum material condition. Dambar cannot be located on the
lower radius or the lead foot. Minimum space between protrusions and an
adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”.
8.
Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip.
9.
Controlling dimension: millimeters.
10. This part is compliant with JEDEC registration MO-187, variation AA and BA.
11. Datums -A- and -B- to be determined Datum plane -H- .
MILLIMETERS
Dim
Min
Nom
Max
A
A1
A2
b
b1
c
c1
D
E
E1
e
e1
L
N
T
-
-
1.10
0.05
0.10
0.15
0.75
0.85
0.95
0.25
-
0.38
8
0.25
0.30
0.33
8
0.13
-
0.23
0.15
0.18
0.13
3.00 BSC
Note
3
4.90 BSC
2.90
3.00
3.10
3
0.70
4
0.65 BSC
1.95 BSC
0.40
0.55
8
0_
4_
5
6_
ECN: T-02080—Rev. C, 15-Jul-02
DWG: 5867
12. Exposed pad area in bottom side is the same as teh leadframe pad size.
Document Number: 71244
12-Jul-02
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Revision: 02-Oct-12
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Document Number: 91000