ALTERA Datasheet

2016
DHDLC IP Core
HDLC/SDLC Controller v. 1.00
COMPANY OVERVIEW
Digital Core Design is a leading IP Core provider
and a System-on-Chip design house. The company
was founded in 1999 and since the very beginning
has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers
and with more than 500 hundred licenses sold to
companies like Intel, Siemens, Philips, General
Electric, Sony and Toyota. Based on more than 70
different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we
are designing solutions tailored to your needs.
APPLICATIONS
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KEY FEATURES
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The DHDLC IP core is used for controlling
HDLC/SDLC transmission frame, no matter if it’s 8-,
16- or 32-bit microcontroller. It allows saving MCU
time wasted for handling HDLC/SDLC features, like
bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer for
both the receiver and transmitter.
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PINS DESCRIPTION
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IP CORE OVERVIEW
PIN
clk
rst
addr(3:0)
datai(7:0)
rd
wr
cs
rxd
rxclk
cxd
txclk
rxdatai(7:0)
txdatai(7:0)
irq
datao(7:0)
txd
txclko
txclken
rxdatao(7:0)
rxraddr(3:0)*
rxwaddr(3:0)*
rxrd
rxwr
txdatao(7:0)
txraddr(3:0)*
txwaddr(3:0)*
txrd
txwr
txdmareq
txdmaclr
rxdmareq
rxdmaclr
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
input
output
input
DESCRIPTION
Master clock
Reset
CPU interface address input
CPU interface data input bus
CPU interface read control input
CPU interface write control input
CPU interface chip select input
Receiver data input
Receiver clock input
Collision detect input
Transmitter clock input
Rx FIFO data input
Tx FIFO data input
Interrupt request output
CPU interface data output bus
Transmitter data output
Transmitter clock output
Transmitter clock output enable
Rx FIFO data output bus
Rx FIFO read address output bus
Rx FIFO write address output bus
Rx FIFO read control
Rx FIFO write control
Tx FIFO data output bus
Tx FIFO read address output bus
Tx FIFO write address output bus
Tx FIFO read control
Tx FIFO write control
TX DMA service request
TX DMA request clear
RX DMA service request
RX DMA request clear
CPU based applications with serial interface based
on HDLC/SDLC protocol
Telecommunication
Two separate receiver and transmitter interfaces.
Two separate, configurable FIFO buffers for receiver
and transmitter
Bit stuffing and unstuffing
Address recognition for receiver and address insertion for transmitter
Two or one byte address field
CRC-16 and CRC-32 computation and checking
Collision detect
Byte alignment error detection
Programmable number of bits for idle detection
NRZI coding support
Shared flags, shared zeroes support
Pad fill with flags option
Transmitter clock generation
8-bit, 16-bit, 32-bit CPU interface
Interrupt output for handling control flags and
FIFOs’ filling
Configurable core parameters
LICENSING
Comprehensible and clearly defined licensing
methods without royalty-per-chip fees make use
of our IP Cores easy and simple.
Single-Site license option – dedicated to small and
middle sized companies, which run their business
in one place.
Multi-Site license option – dedicated to corporate
customers, who operate at several locations. The
licensed product can be used in selected company
branches.
In all cases the number of IP Core instantiations
within a project and the number of manufactured
chips are unlimited. The license is royalty-per-chip
free. There are no restrictions regarding the time
of use. There are two formats of the delivered IP
Core:
VHDL or Verilog RTL synthesizable source code
FPGA EDIF/NGO/NGD/QXP/VQM called (Netlist)
UNITS SUMMARY
CPU Interface – it performs operations of reading and
writing internal registers of module.
Serial Interface – it performs bit stuffing and unstuffing, NRZI coding, collision detection, CRC calculation,
flags and abort detection, idle detection and synchronizes serial inputs with main clock domain
1
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
FIFO control – it manages access to FIFO buffers of
receive and transmitter.
Control Unit – it controls HDLC frame and services
request from CPU interface module
BLOCK DIAGRAM
Clock Divider – it generates divided clock signal for
TXCLKO output.
DELIVERABLES
♦
Source code:
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VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment
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Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
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Installation notes
HDL core specification
Datasheet
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IP Core implementation support
3 months maintenance
● Delivery of the IP Core and documentation updates, minor
●
and major versions changes
Phone & email support
clk
datai(7:0)
addr(3:0)
rd
wr
cs
cxd
txclk
rxd
rxclk
rxdatai(7:0)
txdatai(7:0)
rxdmaclr
txdmaclr
irq
rxwaddr(3:0)
rxrd
rxwr
FIFO
Control
txdatai(7:0)
txdatao(7:0)
txraddr(3:0)
irq
datao(7:0
)
txdmareq
rxdmareq
txd
txclko
txclke
n
rxdatao(7:0)
rxraddr(3:0)
rxwaddr(3:0
) rxrd
rxwr
txdatao(7:0)
txraddr(3:0)
txwaddr(3:0
) txrd
txwr
rxd
rxclk
txd
Serial
Interface
txclk
txclko
Control
Unit
txdmareq
txdmaclr
rxdmareq
rxdmaclr
SYMBOL
rst
CPU
Interface
rxdatai(7:0)
rxdatao(7:0)
rxraddr(3:0)
txwaddr(3:0)
txrd
txwr
Synthesis scripts
Example application
Technical support
addr(3:0)
datai(7:0)
datao(7:0)
wr
rd
cs
Clock
Divider
txclken
clk
reset
PERFORMANCE
The following table gives a survey about the Core
area and performance in ALTERA® devices after
Place & Route:
Device
ARIA
ARIA II
ARIA V
CYCLONE
CYCLONE II
CYCLONE III
CYCLONE IV
CYCLONE V
STRATIX
STRATIX II
STRATIX III
STRATIX IV
STRATIX V
Memory
Bits
517/363
256
510/360
256
507/443
256
767
256
787
256
785/359
256
789/359
256
507/359
256
767/336
256
511/359
256
507/391
256
510/392
256
511/440
256
Core performance in ALTERA® devices
Logic Cells
Fmax
179 MHz
260 MHz
204 MHz
140 MHz
160 MHz
188 MHz
199 MHz
183 MHz
169 MHz
260 MHz
383 MHz
384 MHz
385 MHz
CONTACT
Digital Core Design Headquarters:
Wroclawska 94, 41-902 Bytom, POLAND
e-mail:
tel.:
fax:
[email protected]
0048 32 282 82 66
0048 32 282 74 37
Distributors:
Please check:
http://dcd.pl/sales
2
Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved.
All trademarks mentioned in this document are the property
of their respective owners.
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