DP8051 Core performance improvement

Application note v4.04 DP8051 performance improvement 1.
PERFORMANCE IMPROVEMENT This document present a speed comparison of DP8051 Core vs. standard 8051 devices. In presented tables are compared numbers of CLK cycles needed to execute selected arithmetic operations. A 1 cycle is equal to 1 CLK period. a) 8‐bit addition ‐ immediate data The following code performs immediate data (constant) addition to an 8‐bit register. Rx = Rx + #n Mnemonic MOV ADD MOV Sum: A, Rx A, #n Rx, A Opcode Bytes 80C51 cycles DP8051 cycles E8h‐EFh 24h F8h‐FFh 1 2 1 12 12 12 36 1 2 1 4 DP8051 Performance Improvement: 9,0 b) 8‐bit subtraction ‐ direct addressing The following code performs direct addressing subtraction from an 8‐bit register. Rx = Rx ‐ (dir) Mnemonic MOV SUBB MOV Sum: A, Rx A, dir Rx, A Opcode Bytes 80C51 cycles DP8051 cycles E8h‐EFh 25h F8h‐FFh 1 2 1 12 12 12 36 1 2 1 4 9,0 DP8051 Performance Improvement: c) 8‐bit multiplication The following code performs the 8‐bit registers multiplication. Rx = Rx * Ry Mnemonic Opcode Bytes 80C51 cycles MOV MOV MUL MOV A, Rx B, Ry AB Rx, A Sum: DP8051 cycles E8h‐EFh 88h‐8Fh A4h F8h‐FFh 1 2 1 1 12 24 48 12 1 2 2 1 96 6 Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -1- All trademarks mentioned in this document are trademarks of their respective owners. Application note v4.04 16 DP8051 Performance Improvement: d) 8 – bit division The following code performs the 8‐bit registers division. Rx = Rx / Ry Mnemonic MOV MOV DIV MOV Sum: A, Rx B, Ry AB Rx, A Opcode Bytes 80C51 cycles DP8051 cycles E8h‐EFh 88h‐8Fh 84h F8h‐FFh 1 2 1 1 12 24 48 12 96 1 2 6 1 10 DP8051 Performance Improvement: 9,6 e) 16 ‐ bit addition The following code performs 16‐bit addition. The first operand and result are located in registers pair RaRb. Second operand is located in registers pair RxRy. RaRb = RaRb + RxRy Mnemonic Opcode Bytes 80C51 cycles DP8051 cycles MOV ADD MOV MOV ADDC MOV Sum: A, Rb A, Ry Rb, A A, Ra A, Rx Ra, A E8h‐EFh 28h‐2Fh F8h‐FFh E8h‐EFh 38h‐3Fh F8h‐FFh 1 1 1 1 1 1 DP8051 Performance Improvement: 12 12 12 12 12 12 72 1 1 1 1 1 1 6 12,0 Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -2- All trademarks mentioned in this document are trademarks of their respective owners. Application note v4.04 Performance improvement summary Total performance improvement of DP8051 vs. standard 8051 devices has been summarized in the table below. It shows the most common used multi‐precision arithmetic operation. 80C51 cycle DP8051 cycle Improvement Function 8‐bit addition (immediate data) 8‐bit addition (direct addressing) 8‐bit addition (indirect addressing) 8‐bit addition (register addressing) 8‐bit subtraction (immediate data) 8‐bit subtraction (direct addressing) 8‐bit subtraction (indirect addressing) 8‐bit subtraction (register addressing) 8‐bit multiplication 8‐bit division 16‐bit addition 16‐bit subtraction 16‐bit multiplication 32‐bit addition 32‐bit subtraction 32‐bit multiplication Average speed improvement: 36 36 36 36 36 36 36 36 96 96 72 84 312 144 156 1248 5 6 6 5 5 6 6 5 9 10 10 11 32 20 21 142 9,0 9,0 9,0 12,0 9,0 9,0 9,0 12,0 16,0 9,6 12,0 12,0 13,6 12,0 12,0 12,6 11,12 Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -3- All trademarks mentioned in this document are trademarks of their respective owners. 
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