2016 DSDRAM IP Core Configurable SDRAM controller v. 1.00 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. DELIVERABLES ♦ ● ● ● ♦ VHDL & VERILOG test bench environment ♦ Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support KEY FEATURES ● ● ● ● Supports any SDRAM discrete devices PC 66/100/133 SDRAM SDRAM from 16 Mbit to 1024 Mbit sizes Programmable data size ○ 8, 16, and 32 bits ● Supports all burst lengths ○ 1, 2, 4, 8 and full page ● CAS latency ○ LICENSING VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF ● ● ● IP CORE OVERVIEW The DSDRAM is a soft Core of a configurable SDRAM controller. It is fully compliant to the JEDEC PC100/133 standards. The DSDRAM can operate with any SDRAM memory device, in terms of size and required timing parameters. All access timing parameters, such as CAS latency, refresh interval, etc., are programmable, to support different speed grades of SDRAM devices and different operating frequencies. The timing parameters can be set to proper default values during synthesis time. It is very small, efficient, static, fully synchronous design, with no internal tri-state buffers and signals. Source code: 1, 2, and 3 ● Programmable access timing parameters ● Supports multiple external SDRAM banks ● Automatic refresh generation with program- mable refresh intervals ● Self-refreshing mode ● Fully synthesizable, static design with no inter- nal tri-states UNITS SUMMARY Processor Interface - manages communication between processor and internal SDRAM controller module. Control commands are issued to SDRAM interface, based on state of read/write and chip select signals. SDRAM Interface - unit translating internal states of SDRAM controller to SDRAM chip signal formats. It manages data flow between Processor Interface and SDRAM chip SDRAM Controller - main unit, responsible for proper control of SDRAM chip. It issues automatically refreshing commands, to preserve valid data inside SDRAM chip. It also issues NOP, LOAD MODE REGISTER, READ, WRITE, (AUTO) PRECHARGE, ACTIVE commands. 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. TYPICAL DSDRAM CONNECTION Typical connection of DSDRAM Controller to microprocessor and SDRAM memory has been shown below. datao datai(31:0) datai datao(31:0) address( s CPU addr(24:0) sddq(31:0) dq(31:0) sddqm(3:0) dqm(3:0) be(3:0) busy read y rd rd wr wr DSDRAM controller rst cs clk sda(12:0) a(12:0) sdba(1:0) ba(1:0) sdcke cke sdcs cs sdras ras sdcas cas sdwe SDRAM we clk clk PLL PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock rst input Global reset datai(31:0)1 input Processor data bus (input) be(3:0)3 input Processor byte enable addr(24:0)2 input Processor address bus rd input Processor data read wr input Processor data write sdqi(31:0)1 output SDRAM data bus (input) datao(31:0)1 output Processor data bus (output) busy output Processor data busy indicator sdqo(31:0)1 output SDRAM data bus (output) sdqm(3:0)3 output SDRAM byte mask lines sda(14:0)4 output SDRAM address bus sdba(1:0)5 output SDRAM bank address lines sdras output SDRAM RAS line sdcas output SDRAM CAS line sdwe output SDRAM write enable line sdcs output SDRAM chip select line sdcke output SDRAM clock enable line 1 - bus size is configurable as 8, 16, 32, 64 bits of wide 2 - address size is automatically adjusted based on number of ROWS, COLUMNS, and BANKS of SDRAM chip (byte count) 3 - number of byte enable lines is automatically adjusted depend on data bus size and can have 1, 2, 4 or 8 lines 4 - SDRAM address size depends on number of memory's ROWS 5 - BANKS bus size is user configurable, and can have 1 or 2 bits BLOCK DIAGRAM clk rst addr(24:0) be(3:0) wr rd busy cs sdqo(31:0) sdqi(31:0) sdqm(3:0) Processor Interface SDRAM Interface sda(14:0) sdba(1:0) sdras sdcas sdwe sdcs sdcke datai(31:0) datao(31:0) SDRAM Controller CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: email@example.com 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.