APW7262 3MHz Synchronous Switch-Mode Battery Charger with Full USB Compliance and USB-OTG Boost Regulator Features General Description • Charge Faster Than Linear Charger The APW7262 combine switch-mode battery charger and • 3MHz with 0% to 99.5% Duty Cycle Synchronous a boost regulator with fixed 3MHz switching frequency, which drives two integrated N-channel power MOSFETs. Switch-Mode Charger with 1.5A Integrated N- In battery charging, the high-efficiency step-down DC/DC converter is capable of delivering 1.5A output current over MOSFETs • 4V-6V Input Operating Range • 20V Absolute Maximum Input Voltage • Safety a wide input voltage range from 4V to 6V for APW7262, the step-down DC/DC converter is ideally suited for portable -Reverse leakage protection to prevent battery electronic devices that are powered from 1-cell Li-ion battery. The Charging parameters and operating modes drainage -Thermal regulation and protection can be programmed through an I 2C interface. The APW7262 has high accuracy regulation of input current, -Input/output over-voltage protection charge current and charge voltage. It equipped with charge termination, and charge status monitoring for battery -Cycle-by-cycle current limit • Accuracy -+1% charge voltage regulation (0 to 85oC) detection. The APW7262 charge the battery in three phases: -+5% charge current regulation -+5% input current regulation (100mA and conditioning, constant current and constant voltage. The APW7262 features Dynamic Power Management (DPM) 500mA) mode to accomplish input power limiting. The input current is limited to the value set by the I2C host. This feature • Built-In Input Current Sensing and Limiting • Automatic Charging • Programmable Through High-Speed I2C reduces battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger simultaneously. The charge termination is based on battery voltage, a Interface(3.4Mb/s) -Input Current Limit -Fast-Charge and Termination Current programmed minimum current level and charge current termination bit set by the I2C host. -Charge Regulation Voltage -Weak Battery Voltage Threshold If the battery voltage falls below an internal threshold, the APW7262 automatically restarts the charge cycle, and -VIN DPM Threshold -Termination Enable/Disable when the input voltage falls below the battery voltage, it will enter a low-quiescent current sleep mode. The -OTG Enable/Disable -Reset All Parameter Control APW7262 supports the thermal regulation and over temperature protection to maintain the junction temperature -Safety Timer with Reset Control • of 120oC by reducing charge current. The APW7262 can operate as a boost regulator. To sup- 5V, 500mA Boost Mode for USB OTG for 2.5V to 4.5V Battery Input • port USB OTG device, APW7262 can provide VBUS (5.05V) by boosting the battery voltage. Available in 1.7mmx2.1mm WLCSP-20 and TQFN4x4-20A Packages The APW7262 is available in1.7mmx2.1mm WLCSP-20 and TQFN4x4-20A packages. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 1 www.anpec.com.tw APW7262 Applications • Cell Phones, Smart Phones and PDAs • Tablet PC • Portable Media Players, Handheld Device Simplified Application Circuit APW7262 To SYSTEM ADAPTER or USB VBUS CVBUS LOUT VBAT RSNS SW PMID CSNS VAUX REGN BOOT COUT1 10k COUT2 PACK- CSIN CPMID 10k PACK+ CBOOT CPMID 10k CSIN SDA CSOUT SCL CSOUT STAT OTG CD PGND Ordering and Marking Information Package Code HA : WLCSP1.7x2.1-20 QB : TQFN4x4-20A APW7262 Assembly Material Operating Ambient Temperature Range I : -40 to 85oC Handling Code Temperature Range Handling Code TR : Tape & Reel Package Code Assembly Material G : Halogen and Lead Free Device APW7262HA: 7262 • X X - Date Code APW7262QB: APW 7262 •XXXXX X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 2 www.anpec.com.tw APW7262 Pin Configuration PGND SCL (A4) SW BOOT (A3) SW VBUS (A2) PMID VBUS (A1) PMID APW7262 Top View 20 19 18 17 16 15 CSIN VBUS 1 PMID (B3) SDA (B4) VBUS 2 14 GND 21 GND BOOT 3 STAT (C4) PGND (D1) PGND (D2) PGND (D3) OTG (D4) CSIN (E1) CD (E2) REGN (E3) CSOUT (E4) 12 REGN NC 5 11 NC 6 7 8 STAT SW (C3) SDA SW (C2) SCL SW (C1) 13 CD NC 4 9 10 OTG PMID (B2) CSOUT PMID (B1) TQFN4x4-20 (Top View) = Thermal Pad (connected to GND plane for better heat dissipation) 1.7X2.1mm 20-pin WLCSP-20 Absolute Maximum Ratings (Note 1,2) Symbol VI/O VBOOT TJ Parameter Rating Unit VBUS, PMID and STAT to PGND Voltage -0.3 to 20 V BOOT and SW to PGND Voltage -0.3 to 20 V SCL, SDA, OTG, REGN, CSIN, CSOUT and CD to PGND Voltage -0.3 to 7 V BOOT Supply Voltage (BOOT to SW) -0.3 ~ 7 Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature (10 Seconds) V 150 o -65 to 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2: The device is ESD sensitive. Handling precautions are recommended. Thermal Characteristics (Note 3) Symbol Parameter θJA Junction-to-Ambient Resistance in free air θJC Junction-to-Case Resistance in free air Typical Value WLCSP1.7x2.1-20 85 TQFN4x4-20A 41 WLCSP1.7x2.1-20 25 TQFN4x4-20A 9 Unit o C/W o C/W Note 3: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 3 www.anpec.com.tw APW7262 Recommended Operating Conditions (Note 4) S ymbol Parameter Range Unit 4 to 6 V VBUS Supply Voltage (VBUS to GND) VOUT Converter Output Voltage 3.5 to 4.44 V I OUT Output Curren t (R SNS=68mΩ) 0.55~1.55 A TA Ambient Temperatu re TJ Junction Temperature -40 to 85 o -40 to 125 o C C Note 4: Refer to the typical application circuit. Electrical Characteristics Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7262 Test Conditions Min Typ Max Unit VBUS > VBUS(min), PWM switching - 10 - mA VBUS > VBUS(min), PWM no switching - - 5 mA - 140 260 µA - 0.2 5 µA - - 20 µA 3.5 - 4.44 V -0.5 - 0.5 -1 - 1 INPUT CURRENT IVBUS VBUS supply current control o o 0 C < TJ < 85 C, CD=1 or HZ_MODE=1 ILKG Leakage current from battery to 0oC < TJ < 85oC, VCSOUT=4.2V, High VBUS pin Impedance Mode, VBUS=0V o o Battery discharge current in High 0 C < TJ < 85 C, VCSOUT=4.2V, High Impedance Mode, (CSIN, CSOUT, Impedance Mode, SCL, SDA, OTG=0V or SW pins) 1.8V VOLTAGE REGULATION VOREG Output Regulation voltage programmable range Voltage regulation accuracy Operating in voltage regulation TA = 25oC TA = -40 ~ 85oC % CURRENT REGULATION (FAST CHARGE) IO(CHARGE) Output charge current programmable range VLOWV≦VCSOUT<VOREG, VBUS>VSLP, RSNS=68mΩ, LOW_CHG=0 550 - 1500 mA Low charge current VLOWV≦VCSOUT<VOREG, VBUS>VSLP, RSNS=68mΩ, LOW_CHG=1 - 325 350 mA 20mV < VIREG < 40mV -8 - 2 % 40mV < VIREG -6 - 0 % -3.5 - 3.5 -3 - 3 3.4 - 3.7 V -5 - 5 % Charge Current Accuracy Across RSNS Regulation accuracy of the voltage 37.4mV≦VIREG<44.2mV across RSNS (for charge current regulation) 44.2mV≦VIREG VIREG = IO(CHARGE) x RSNS % WEAK BATTERY DETECTION VLOWV Weak battery voltage threshold programmable range Adjustable using I2C control Weak battery voltage accuracy Hysteresis for VLOWV Battery voltage falling - 100 - mV Deglitch time for weak battery threshold Rising voltage, 2mV overdrive, tRISE=100ns - 30 - ms Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 4 www.anpec.com.tw APW7262 Electrical Characteristics Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7262 Test Conditions Min Typ Max Unit CD and OTG PIN LOGIC LEVEL Input low threshold level - - 0.4 V VIH VIL Input high threshold level 1.5 - - V Ibias Input bias current - - 1 µA Voltage on control pin is 5V CHARGE TERMINATION DETECTION ITERM Termination charge current programmable range VCSOUT>VOREG-VREGH, VBUS>VSLP, RSNS=68mΩ 50 - 400 mA Deglitch time for charge termination Both rising and falling, 2mV overdrive, tRISE, tFALL=100ns - 30 - ms Regulation accuracy for termination current across RSNS VIREG_TERM=IOTERM x RSNS 3.4mV≦VIREG_TERM≦6.8mV -25 - 25 6.8mV≦VIREG_TERM≦17mV -25 - 25 17mV≦VIREG_TERM≦27.2mV -5 - 5 Input voltage DPM threshold programmable range 4.2 - 4.76 V VIN DPM threshold accuracy -3 - 3 % TJ=0oC~125oC 88 93 98 TJ=-40oC ~125oC 86 93 98 TJ=0 C ~125 C 450 475 500 TJ=-40oC ~125oC 440 475 500 - - 6.5 V - 30 - mA 100 120 150 mV - 130 - ms % INPUT BASED DYNAMIC POWER MANAGEMENT VIN_DPM INPUT CURRENT LIMIT IIN=100mA IIN_LIMIT Input current limiting threshold o IIN=500mA o mA VREF BIAS REGULATOR VREGN Input bias regulator voltage VBUS>VIN(min) or VCSOUT>VBUS(min), IREGN=1mA, CREGN=1µF VREGN output short current limit BATTERY RECHARGE THRESHOLD VRCH Recharge threshold voltage Below VOREG Deglitch time VCSOUT decreasing below tFALL=100ns, 10mV overdrive Low-level output saturation voltage, STAT pin IO=10mA, sink current - - 0.55 V High-level leakage current for STAT Voltage on STAT pin is 5V - - 1 µA - - 0.4 V threshold, STAT OUTPUT VOL(STAT) I2C BUS LOGIC LEVELS AND TIMING CHARACTERISTIC VOL Output low threshold level IO=10mA, sink current VIL Input low threshold level VPULL_UP=1.8V, SDA and SCL - 0.4 V - - V VIH Input high threshold level VPULL_UP=1.8V, SDA and SCL 1.2 IBIAS Input bias current VPULL_UP=1.8V, SDA and SCL - - 1 µA fSCL SCL clock frequency VPULL_UP=1.8V, SDA and SCL - - 3.4 MHz Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 5 www.anpec.com.tw APW7262 Electrical Characteristics Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7262 Test Conditions Unit Min Typ Max BATTERY DETECTION (In Termination) IDETECT Battery detection current before Begins after termination detected, charge done (sink current) VCSOUT≦VOREG - -0.8 - mA tDETECT Battery detection time - 262 - ms 0 40 100 mV 140 200 260 mV - 30 - ms 3.6 3.8 4 V mV SLEEP COMPARATOR VSLP VSLP_EXIT SLEEP mode entry threshold, VBUS-VCSOUT 2.3V≦VCSOUT≦VOREG, VBUS falling Sleep mode exit hysteresis 2.3V≦VCSOUT≦VOREG Deglitch time for VBUS rising above Rising voltage, 2mV overdrive, tRISE=100ns VSLP+VSLP_EXIT UNDERVOLTAGE LOCKOUT (UVLO) UVLO UVLO_HYS IC active threshold voltage VBUS rising, Exit UVLO IC active hysteresis VBUS falling below UVLO, Enter UVLO - 150 - IIN_LIMIT=500mA, Measured from VBUS to PMID (for WLCSP-20) - 180 250 IIN_LIMIT=500mA, Measured from VBUS to PMID (for TQFN-20A) - 220 290 Measured from PMID to SW, VBOOT-VSW =4V (for WLCSP-20) - 130 225 Measured from PMID to SW, VBOOT-VSW =4V (for TQFN-20A) - 170 265 - 130 225 PWM Internal top reverse blocking MOSFET on-resistance Internal top N-Channel Switching MOSFET on-resistance Internal bottom N-Channel Measured from SW to PGND (for WLCSP-20) MOSFET on-resistance fOSC Measured from SW to PGND (for TQFN-20A) Oscillator frequency mΩ - 170 265 2.7 3 3.3 MHz 6.3 6.5 6.7 V - CHARGE MODE PROTECTION VOVP_IN_USB VOVP IILIMIT VSHORT Input VBUS OVP threshold voltage VBUS threshold to turn off converter during charge VOVP_IN_USB VOVP_IN_USB hysteresis VBUS falling from above VOVP_IN_USB 170 - mV Output OVP threshold voltage VCSOUT threshold over VOREG to turn off charger 110 during charge 117 121 % VOVP hysteresis Lower limit for VCSOUT falling from above VOVP - 11 - % Cycle-by-cycle current limit for charge Charge mode operation 2.4 3 3.5 A Trickle to fast charge threshold VCSOUT rising 1.9 2.1 2.3 V VSHORT hysteresis VCSOUT falling below VSHORT - 100 - mV Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 6 www.anpec.com.tw APW7262 Electrical Characteristics Unless otherwise specified, these specifications apply over VBUS=5V, CD=0, HZ_MODE=0, OPA_MODE=0 and TA= -40 to 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7262 Test Conditions Unit Min Typ Max 25 35 45 Boost output voltage (to VBUS pin) 2.5V<VCSOUT<4.5V 4.9 5.05 5.2 V Boost output voltage accuracy -3 - 3 % 500 - - mA - 1.59 - A 5.8 6 6.2 V - 162 - mV 4.75 4.9 5.05 V - 200 - mV - 2.5 - V - 2.9 3.05 V 220 - - kΩ Thermal trip - 165 - Thermal hysteresis - 10 - - 120 - 35 40 45 CHARGE MODE PROTECTION ISHORT Trickle charge charging current VCSOUT≦VSHORT mA BOOST MODE OPERATION FOR VBUS (OPA_MODE=1, HZ_MODE=0) VBUS_B IBO IBLIMIT VBUSOVP Cycle by cycle current VBUS falling from above VBUSOVP Maximum battery voltage for boost (CSOUT pin) VCSOUT rising edge during boost VBATMAX hysteresis VBATMIN VBUS_B=5.05V, 2.5V<VCSOUT<4.5V Overvoltage protection threshold fo Threshold over VBUS to turn off converter during boost boost (VBUS pin) VBUSOVP hysteresis VBATMAX Including line and load regulation Maximum output current for boost VBUS_B=5.05V, 2.5V<VCSOUT<4.5V VCSOUT falling from above VBATMAX Minimum battery voltage for boost During boosting (CSOUT pin) Before boost starts Boost output resistance at high-impedance mode (From VBUS to PGND) CD=1 or HZ_MODE=1 PROTECTION TSHUTDOWN TCF Thermal regulation threshold Charge current begins to reduce t40M 40 minute timer 40 minute mode Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 7 o C Min www.anpec.com.tw APW7262 I2C Serial Control Port Operation Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) Symbol Parameter Test Conditions APW7262 Min. Typ. Max. fSCL Frequency, SCL - - 400 tW(H) Pulse Duration, SCL High 0.6 - - tW(L) Pulse Duration, SCL Low 1.3 - - tr Rise Time, SCL and SDA - - 300 ns tf Fall Time, SCL and SDA - - 300 ns tsetup1 Setup Time, SCL to SDA 100 - - ns thold1 Hold Time, SCL to SDA 0 - - ns t(buf) Bus Free Time Between Stop and Start Condition 1.3 - - tsetup2 Setup Time, SCL to Start Condition 0.6 - - thold2 Hold Time, Start condition to SCL 0.6 - - tsetup3 Setup Time, SCL to Stop Condition 0.6 - - - - 400 CL No Wait States Unit µs µs Load Capacitance for Each Bus Line tw(H) kHz tf tw(L) pF tr SCL tsu1 th1 SDA Figure1. SCL and SDA Timing SCL tsu2 th2 t (buf) tsu3 SDA Stop Condition Start Condition Figure 2. Start and Stop Conditions Timing Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 8 www.anpec.com.tw APW7262 Reset Timing Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Recommended Use Model” section on usage of all terminals. Symbol tp(/RST) td(I2C_Ready) Parameter Pulse Duration, RESET Active. Test Conditions No Load Time to Enable I2C APW7262 Unit Min. Typ. Max. 100 - - µs - - 13.5 ms RESET t w(RESET) I2 C Active I2 C Active t d(I2C_Ready) Figure 3. Reset Timing Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 9 www.anpec.com.tw APW7262 Pin Description PIN NAME A1, A2 VBUS Charge Input Voltage. A3 BOOT Supply Input for the Internal high-side gate driver and an internal level-shift circuit. Connect to an external ceramic capacitor and internal diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. A4 SCL I2C Interface Clock. This pin should not be left floating. B1, B2, B3 PMID Converter Input Voltage. Connect at least 4.7? µF ceramic capacitor from PVCC to PGND and place it as close as possible to IC. B4 SDA I2C Interface Data. This pin should not be left floating. C1, C2, C3 SW Junction point of the Internal high-side MOSFET Source, output filter inductor and internal the low-side MOSFET Drain. Connect the 0.01µF bootstrap capacitor from SW to BOOT. C4 STAT STAT is an open drain output used to indicate the status of the various charger operations. Low when charge in progress. STAT can be used to drive a LED or communicate with a host processor. D1, D2, D3 PGND Power ground. Ground connection for high current power converter node. This pin is used as sink for internal low-side gate drivers. D4 OTG Boost Mode Enable Control or Input Current Limit Selection Pin. When OTG actives, the device operates in boost mode. E1 CSIN Positive Input of current sensing Amplifier for charge terminal. A 0.1µF ceramic capacitor is placed from CSIN to CSOUT to provide differential-mode filtering. An optional 0.1µF ceramic capacitor is placed from CSIN pin to PGND for common-mode filtering. E2 CD E3 REGN E4 CSOUT Description Charge Disable. CD=Low, charge is enabled, CD=High, charge is disabled. Supply Voltage. This pin provides bias supply, low-side gate drivers and the bootstrap circuit for high-side drivers. Ensure that this pin is bypassed by a 1µF ceramic capacitor next to the pin. Battery Output and Negative Input of current sensing Amplifier for charge terminal. A 0.1µF ceramic capacitor is placed from CSOUT to CSIN to provide differential-mode filtering. An optional 0.1µF ceramic capacitor is placed from CSOUT pin to PGND for common-mode filtering. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 10 www.anpec.com.tw APW7262 Typical Operating Characteristics Battery Charge Current vs. VBAT, VOREG=4.2V, IIN_LIMIT=500mA Battery Charge Current vs. VBAT, VOREG=4.2V, IIN_LIMIT=100mA 1000 Battery Charge Current (mA) Battery Charge Current (mA) 250 200 150 100 50 800 600 400 200 0 0 2.7 3 3.3 3.6 3.9 4.2 2.7 3.3 3.6 3.9 4.2 Battery Voltage, VBAT (V) OTG, Load Regulation, VBUS vs. IVBUS HZ_Mode Current IVBUS vs. Input Voltage VBUS with Temperature 5.2 250 200 Hz_Mode Current, IVBUS (uA) Output Voltage, VBUS (V) 3 Battery Voltage, VBAT (V) 5.1 5 150 100 85°C 4.9 25°C 50 -30°C 4.8 0 0 100 200 300 400 500 4 4.4 Load Current, IVBUS (mA) 5.2 5.6 6 Boost Mode, No Switching Quiescent Current IBAT vs. Battery Voltage VBAT with Temperature No Switching Quiescent IVBUS vs. Input Voltage VBUS with Temperature 400 3.2 No Switching Current, IBAT (uA) No Switching Current, IVBUS (mA) 4.8 Input Voltage, VBUS (V) 3 2.8 2.6 2.4 85°C 25°C 2.2 -30°C 2 350 300 250 85°C 25°C -30°C 200 150 100 50 0 4 4.4 4.8 5.2 5.6 6 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Input Voltage, VBUS (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 Battery Voltage, VBAT (V) 11 www.anpec.com.tw APW7262 Typical Operating Characteristics 40 Boost Mode, Quiescent Current IBAT vs. Battery Voltage VBAT in HZ_Mode with Temperature Hz_Mode Current, IBAT (uA) 35 30 25 20 85°C 15 10 25°C -30°C 5 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 Battery Voltage, VBAT (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 12 www.anpec.com.tw APW7262 Operating Waveforms Charge Mode start-up VBUS, VOREG=4.2V, VBAT=3.8 Charge Mode start-up VBUS, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=100mA 1 1 2 3 3 4 2 4 CH1: VBUS (5V/div) CH2: IVBUS (200mA/div) CH3: VBAT (2V/div) CH4: IL (500mA/div) Time: 1s/div CH1: VBUS (5V/div) CH2: VBAT (1V/div) CH3: VSTAT (5V/div) CH4: IBAT (500mA/div) Time: 1s/div Charge Mode start-up VBUS, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=500mA Charge Mode start-up VBUS, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=800mA 1 1 2 2 3 3 4 4 CH1: VBUS (5V/div) CH2: IVBUS (500mA/div) CH3: VBAT (2V/div) CH4: IL (500mA/div) Time: 500ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 CH1: VBUS (5V/div) CH2: IVBUS (500mA/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 500ms/div 13 www.anpec.com.tw APW7262 Operating Waveforms Charge Shutdown with HZ_MODE Bit Set, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit Charge Mode start-up VBUS, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit 1 1 2 2 3 3 4 4 CH1: VSTAT (5V/div) CH2: IVBUS (1A/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 100ms/div CH1: VBUS (5V/div) CH2: IVBUS (500mA/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 500ms/div Charge Start-up with HZ _MODE Bit Reset, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit Charge Shutdown with CD Pin Pulled High, VOREG=4.2V, VBAT=Float, IIN_LIMIT=NO Limit 1 1 2 2 3 3 4 4 CH1: VCD (2V/div) CH2: VSTAT (5V/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 100ms/div CH1: VSTAT (5V/div) CH2: IVBUS (1A/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 200µs/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 14 www.anpec.com.tw APW7262 Operating Waveforms Charge Start-up with CD Pin Pulled Low, VOREG=4.2V, VBAT=Float, IIN_LIMIT=NO Limit Battery Remove/Insertion during Charging, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit, TE=0 1 1 2 2 3 3 4 CH1: IVBUS (1A/div) CH2: VBAT (2V/div) CH3: IL (1A/div) Time: 50ms/div CH1: VCD (2V/div) CH2: VSTAT (5V/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 1s/div DPM, VSP=4.533V, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit, TE=1 Battery Remove during Charging, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit, TE=1 1 2 1 2 3 3 4 CH1: VBUS (1V/div) CH2: IVBUS (1A/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 5ms/div CH1: IVBUS (1A/div) CH2: VBAT (2V/div) CH3: IL (1A/div) Time: 500ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 15 www.anpec.com.tw APW7262 Operating Waveforms DPM, VSP=4.533V, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit , TE=1 (Cont.) Charge Mode, VBUS OVP/Released OVP, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit 2 2 1 1 3 3 4 4 CH1: VBUS (1V/div) CH2: IVBUS (1A/div) CH3: VBAT (2V/div) CH4: IL (1A/div) Time: 20µs/div CH1: VBUS (2V/div) CH2: VSTAT (5V/div) CH3: VBAT (2V/div) CH4: IL (500mA/div) Time: 1s/div Charge Mode, Battery OVP/Released OVP, VOREG=4.2V, IIN_LIMIT=NO Limit Battery Overload, VOREG=4.2V, VBAT=Float, IIN_LIMIT=NO Limit 1 1 2 2 3 3 4 4 CH1: VBUS (2V/div) CH2: VBAT (2V/div) CH3: VSTAT (5V/div) CH4: IL (1A/div) Time: 200µs/div CH1: VBUS (5V/div) CH2: VSTAT (5V/div) CH3: VBAT (2V/div) CH4: IL (500mA/div) Time: 1s/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 16 www.anpec.com.tw APW7262 Operating Waveforms Boost Mode, VBAT=3.8V, IVBUS= No Load, In PFM Operation OTP, VOREG=4.2V, VBAT=3.8, IIN_LIMIT=NO Limit, TE=1 1 1 2 2 3 3 4 CH1: IL (500mA/div) CH2: VLX (5V/div) CH3: VBUS (5V/div) Time: 500ns/div CH1: VSTAT (5V/div) CH2: IVBUS (1A/div) CH3: VBAT (2V/div) CH4: IBAT (1A/div) Time: 500ms/div Boost Mode, VBAT=3.8V, IVBUS= 500mA, In CCM Operation 1 2 3 4 CH1: IL (500mA/div) CH2: VLX (5V/div) CH3: VBUS (5V/div) CH4: IVBUS (500mA/div) Time: 200ns/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 17 www.anpec.com.tw APW7262 Block Diagram PMID VREG VBUS N VBUS VBUS REFERENCE AND BIAS VCSOUT Q1 REGN BOOT CHARGE PUMP VPMID UGATE VBUS OVP CSIN IIN_LIMIT Gate Driver Q2 SW VIN_DPM VCSOUT PWM Signal Controller VOREG REGN CSOUT LGATE Gate Driver IOCHARGE 3.8V Q3 PGND UVLO VBUS CD LOGIC CONTROL AND CHARGE CONTROL TIMER VCSOUT+40mV OTG SLEEP MODE VCSOUT VBUS I2C INTERFACE VBUS OVP VBUS_OVP 2V VCSOUT BAT OVP VBAT_OVP SCL BAT SHORT VBUS PROTECTION BEHAVIOR CONTROLLER TSHUT IC Tj TSHUT STAT SDA Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 18 www.anpec.com.tw APW7262 Typical Application Circuit APW7262 To SYSTEM ADAPTER or USB VBUS 1uF 1uH VBAT 68m SW PMID 0.1uF VAUX REGN 10k 22uF BOOT 22uF PACK- 0.1uF 1uF 10k PACK+ 0.01uF 4.7uF 10k CSIN SDA CSOUT SCL 0.1uF STAT OTG CD Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 PGND 19 www.anpec.com.tw APW7262 Typical Application Circuit Charger VBUS POR Power On VBUS N VBUS > UVLO Y Y VBAT > VLOWV HZ, CE or CD Pin=1 N Y HZ State N Charge Configuration State N 40 Min Timer Y HZ, CE or CD Pin=1 HZ, CE or CD Pin=1 Y N Y N HZ State Charge State Reset All Resisters, Starts 40 Min Figure 4. Charger VBUS POR Flow Chart Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 20 www.anpec.com.tw APW7262 Typical Application Circuit HZ State HZ State N Y HZ, CD Pin, CE =1 VBAT > VLOWV Y N Y CD Pin = High N Charge State Figure 5. HZ State Flow Chart Charge Configuration State Charge Configuration State N Y 40 Min and CE=0 Charge State Figure 6. Charge Configuration Flow Chart Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 21 www.anpec.com.tw APW7262 Typical Application Circuit Charge State Charge State N VBAT < VSHORT Y Enable ISHORT 30mA, PreCharging 40 Min Timeout Y Timer Fault, Set CE=1 Charge Configuration State N Fast Charge 40 Min Timeout Y N TE Bit=1 IOUT < ITERM VBAT > VRECH N Battery Absent, Reset Charge Parameters Delay TINT Y Y Stop Charging, Enable IDET Sink Cuurent for TDETECT to Monitor Battery Status VBAT < VRECH N Charge Complete, HZ Mode VBAT < VRECH Y N Figure 7. Operational Flow Chart in Charge Mode In Charge State=>Charge Start Charge Start N I2C Writing N 40 Min Mode 40 Min Timeout Y Time Fault, Set CE=1 Y Figure 8. Charger Timer Flow Chart Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 22 www.anpec.com.tw APW7262 Function Description The APW7262 is a switch-mode battery charger with fixed 3MHz switching frequency, which drives two integrated The input current limit, I IN_LIMIT, fast charge current, I O(CHARGE), and the battery regulation voltage, VOREG, can be N-channel power MOSFETs. The step-down DC/DC converter is ideally suited for portable electronic devices. In set by the host. Once the battery voltage reaches VOREG, the charge current is decreased as shown in Figure 9. addition, the APW7262 can supply 5V to USB On-The-Go (OTG) peripherals through I2C programmable. The APW7262 has three operation states in substance: 1.Charge State - charges a single-cell Li-ion or Li-poly- VOREG IO_CHARGE mer battery with an integrated synchronous rectification buck regulator. ICHARGE V BA 2.Boost State - supply 5V power to USB-OTG with an integrated synchronous rectification boost regulator us- T ITERM VSHORT ISHORT ing battery terminal as input. 3.High-Impedance State - Both the charging and boost Voltage PreFast Charge-Current Regulation Charge Regulation circuits are off. This state consumes low quiescent current from VBUS or the battery. (a) Charging Process, Not Limited by IIN_LIMIT CHARGEMODE Battery Current Regulation VOREG ICHARGE Limits the maximum charging current. Using the resistor RSNS connected between CSIN and CSOUT as the bat- T V BA VSHORT tery sensing. ITERM ISHORT Input Current Regulation The total input current is a function of the system supply current and the battery charging current. When the sum- Voltage PreFast Charge-Current Regulation Charge Regulation mation of system power and charge power exceeds the maximum VBUS input power, the device will reduce input (b) Charge Curve, IIN_LIMIT Limits ICHARGE current by using Dynamic Power Management (DPM). Using the internal MOSFET RDS(on) from VBUS to PMID Figure 9. Typical Charge Process The APW7262 monitors the battery-pack voltage between terminal as the input current sensing. the CSOUT and PGND pins as voltage regulation feedback. The regulation voltage is adjustable from 3.5V Charge Voltage Regulation to 4.44V and is programmed through I2C interface. The IC monitors the charging current during the whole The regulator is restricted from exceeding this voltage. When the voltage which is across RSNS drops below the voltage regulation phase. The termination current level is programmable by I2C interface. The host can set the termination current threshold (ITERM), programmed by TE bit (REG1[3]) the battery charging is completed. Battery Charging Process charge termination bit (REG1[3]) of charge control register to 0 to disable the charge current termination behavior. While battery voltage is below the VSHORT threshold, the IC applies a constant short-circuit current I SHORT, to the battery. When one of the following conditions is occurred, a new charge cycle is initiated. The charge current ramps up to fast charge current, IO(CHARGE), or a charge current is limited by the input current - The battery voltage falls below the VOREG - VRECH threshold when TE bit is set to 0. of IIN_LIMIT when the battery voltage is above VSHORT and below VOREG. - VBUS Power-on reset (POR), if battery voltage is below the VLOWV threshold. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 23 www.anpec.com.tw APW7262 Function Description Safety Timer At the beginning of charging process, the IC starts a 40- Thermal Regulation To prevent overheating of the chip during the charging minute timer that can be only disabled by VBUS POR Toggle. When the 40-minute timer times out, the IC turns process, the IC monitors the junction temperature, TJ, of the die. Once TJ reaches the thermal regulation threshold, off the charging operation, set CE bit to 1 (REG1[2]) and indicates a timer fault (110) on the FAULT bit (REG[2:0]). TCF, the IC begins to taper down the charge current. When the junction temperature increases approximately 10oC Toggle POR or write CE bit to 0 can restart charging process. Fault condition is cleared by POR and fault sta- above TCF, the charge current is reduced to zero. In any state, The IC suspends charging if TJ exceeds TSHTDWN. tus bits can only be updated after the STAT bit are read by the host. In thermal shutdown mode, PWM is turned off and all timers are frozen. When TJ falls below TSHTDWN by approxi- In default operation condition, 32-second timer is disabled and it can be programmable through 32sec timer mately 10oC, the APW7262 resumes charging process. bit (REG6[7]). If 32-second timer is enabled, it can be reset by any write-action performed by host through I2C Sleep Mode If the V BUS voltage falls below the sleep mode entry interface. Writing “1” to reset the TMR_RST bit (REG0[7]) will reset the 32-second timer and TMR_RST is auto- threshold, VCSOUT+VSLP, the IC enters to the sleep mode. This feature prevents draining the battery during the ab- matically set to “0” after the 32-second timer is reset. The charge is terminated and charge parameters are reset to sence of VBUS. During sleep mode, the internal reverse blocking switch and PWM controller are turned off. default values when the 32-second timer expires. Then the 40-minute timer starts and the charge resumes. VBUS Low Voltage Detection (UVLO) During charging process, the APW7262 continuously Special Charger The APW7262 has additional functionality to limit Input monitors VBUS voltage. If VBUS falls below UVLO threshold, the IC stops to charge and sets STAT bits to “11”, the current in case a current-limited “special charger” is supplying VBUS. If VBUS voltage is equal to the programmable FAULT bits to “011” off. If VBUS rises above UVLO rising threshold, the charging VSP (REG5[4]), the PWM controller starts to decrease the operation frequency and limits the charge process is repeated. VBUS Over-Voltage Protection The IC provides a built-in input over voltage protection (OVP) to protect the device and other components against current to keep VBUS=VSP. Safety Settings The APW7262 provides a SAFETY register (REG6) damage if the VBUS voltage goes too high. When the VBUS OVP condition is detected, the IC turns off the PWM To avoid the value of the IO_CHARGE exceeding from the value of the ISAFE (REG4[6:4]). converter, sets the STAT bit to “11” and FAULT bits to “001”. Once VBUS drops below the VBUS OVP exit threshold, The ISAFE register establishes value that limit the maximum value of IO_CHARGE used by the control logic. If the host the fault is cleared and charge process resumes. attempts to write a value higher than ISAFE to IO_CHARGE, the ISAFE value as the IO_CHARGE register value. Battery Over-Voltage Protection The IC provides a built-in over voltage protection to pro- Input Current Limit The APW7262 integrated the input current sensing circuit tect the device and other components against damage if the battery voltage goes too high, as when the battery is and control loop. When operating in boost mode, the input current limit is default 500mA. In charge mode, the suddenly removed. When the battery OVP condition is detected, the IC turns off the PWM converter, sets the input current limit is set by the programmed control bits in register 01H. STAT bit to “11” and FAULT bits to “100”. Once VBAT drops to the battery OVP threshold, the fault is cleared and charge process resumes. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 24 www.anpec.com.tw APW7262 Function Description Battery Short Circuit Protection If the battery voltage VBAT is below the short circuit threshold VSHORT, a constant current source ISHORT supplies VBAT PFM Mode at Light Load In boost mode, under light load conditions, the IC operates in PFM mode (power saving) to reduce the power until VBAT > VSHORT. loss and improve the converter efficiency. In PFM Mode, the on-time pulse width is constant and Cycle-by-Cycle Charge Mode Current Limit The APW7262 monitors internal high-side MOSFET for regulates off-time by zero crossing sensing. current sensing. If the peak current exceeds the highside MOSFET limit threshold, it will turn off the high-side VBUS Over-Voltage Protection The IC provides a built-in over voltage protection to pro- MOSFET until the next cycle. When the current is below the over-current threshold, the high-side driver automati- tect the device and other components against damage if the VBUS voltage goes too high. When the VBUS OVP con- cally resumes. dition is detected, the IC turns off the PWM converter, sets the STAT bit to “11”, FAULT bits to “001” and resets BOOST MODE BOOST mode can be enabled if OTG pin and OPA_MODE bits as indicated in below table. OTG_EN OTG PIN HZ_MODE OPA_MODE BOOST 1 HIGH LOW X ENABLE X X LOW 1 ENABLE 1 LOW LOW 0 DISABLE 0 HIGH LOW 0 DISABLE X X LOW X DISABLE OPA_MODE bit to 0. And then, APW7262 will return to charge mode. Battery Over-Voltage Protection In Boost mode, the IC provides a built-in input over voltage protection to protect the device and other components against damage if the VBAT voltage goes too high. When the VBAT OVP condition is detected, the IC turns off the PWM converter, sets the STAT bit to “11” and resets OPA_MODE bit to 0. And then, APW7262 will return to charge mode. The APW7262 operates in boost mode and delivers power to VBUS from the battery. In normal boost mode, the APW7262 converts the battery voltage (2.5V to 4.5V) to VBUS (5V) and delivers a current IBO 500mA at lowest to support other USB OTG devices connected to the USB connector. PWM Controller in BOOST Mode In boost mode, the APW7262 provides an integrated, fixed 3-MHz frequency voltage-mode controller to regulate output voltage VBUS as the same as charge mode operation. In boost mode, cycle-by-cycle current limit is sensed through the RSNS from CSIN to CSOUT. The peak current limit threshold is equal to (0.12V/RSNS). For Example, if RSNS=68mΩ, the peak current limit is about 1.76A. When current limit event is triggered, IC will turn off Q3 driver. If current limit event is released, it will re-back normal operation. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 25 www.anpec.com.tw APW7262 I2C Introduction I2C SERIAL CONTROL INTERFACE The APW7262 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports standard mode (100-kHz), fast mode (400-kHz) and the high-speed mode (up to 3.4Mbps in wire mode) data transfer rates for single byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status. The DAP supports the standard-mode I2C bus operation (100 kHz maximum), the fast I2C bus operation (400 kHz maximum) and the high-speed mode (up to 3.4Mbps in wire mode). The DAP performs all I2C operations without I2C wait cycles. General I2C Operation The I2C bus uses two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A highto-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 10. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The APW7262 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the high level for the bus. SDA 7-Bit Slave Address R/ A W 7 6 5 4 3 2 1 0 8-Bit Register Address (N) A 7 6 5 4 3 2 1 0 8-Bit Register Data for Address (N) 7 6 5 4 3 2 1 0 A 8-Bit Register Data for Address (N) A 7 6 5 4 3 2 1 0 SCL Start Stop 2 Figure 10. Typical I C sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 10. Pin A_SEL defines the I2C device address. The device 7-bit address is defined as “1101010” (6AH) for APW7262. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 26 www.anpec.com.tw APW7262 I2C Introduction Single-Byte Transfer The serial control interface supports single-byte read/write operations for sub-addresses 0x00 to 0xFF. Supplying a sub-address for each sub-address transaction is referred to as random I2C addressing. The APW7262 also supports sequential I2C addressing. For write transactions, if a sub-address is issued followed by data for that sub-address and the 15 sub-addresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 sub-addresses is successfully received by the APW7262. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many sub-addresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last sub-address is discarded. However, all other data written is accepted; only the incomplete data is discarded. Single-Byte Write As shown in Figure 11, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the APW7262 internal memory address being accessed. After receiving the address byte, the APW7262 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the APW7262 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Start Condition Acknowledge A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 I2C Device Address and Read/ Write Bit Acknowledge A6 A5 A4 A3 A2 A1 A0 ACK D7 Sub-address Acknowledge D6 D5 D4 D3 Data Byte D2 D1 D0 ACK Stop Condition Figure 11. Single-Byte Write Transfer Single-Byte Read As shown in Figure 12, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the APW7262 address and the read/write bit, APW7262 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the APW7262 address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the APW7262 again responds with an acknowledge bit. Next, the APW7262 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 27 www.anpec.com.tw APW7262 I2C Introduction Single-Byte Read (Cont.) Start Condition Acknowledge A6 A5 A1 Acknowledge Acknowledge A0 R/W ACK A7 A6 I2C Device Address and Read/ Write Bit A1 A0 ACK Sub-address A6 Repeat Start Condition A5 A1 A0 R/W ACK D7 I2C Device Address and Read/ Write Bit Not Acknowledge D6 D1 D0 ACK Stop Condition Data Byte Figure 12. Single-Byte Read Transfer Register Description The APW7262 has seven user-accessible registers. It is as defined as below table. Register Address Name Read/Write/Read Only State Default Value 00 Control/Status Read/Write X1XX 0XXX 01 Control/Input Current Limit Read/Write 0011 0000 02 Control/Battery Voltage Read/Write 0000 1010 03 Vender/Part/Revision Read Only 100X XXXX 04 Termination/Fast Charge Current Read/Write 1000 1001 05 Enable/Special Charger Voltage Read/Write/Read Only 001X X100 06 Safety Limit Read/Write 0100 0000 The below tables define the operation of each register bit. Default values are in bold text. Table1. Register Address: 00 Bit Name 7 TMR_RST/OTG 6 [5:4] 3 [2:0] EN_STAT STAT BOOST Data Read/Write Description Write Write “0” or “1” has no effect Read OTG pin status. “0”=> OTG=Low; “1”=> OTG=High 0 Read/Write Disable STAT pin function Enable STAT pin function 1 Read/Write 00 Read Ready 01 Read Charge in process 10 Read Charge done 11 Read Fault 0 Read Not in boost mode 1 Read In boost mode 000 Read Charge mode : Normal Boost mode : Normal 001 Read Charge mode : VBUS OVP Boost mode : VBUS OVP 010 Read Charge mode : Sleep mode Boost mode : Over load 011 Read Charge mode : VBUS < UVLO Boost mode : VBAT < UVLOBST FAULT Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 28 www.anpec.com.tw APW7262 Register Description Bit [2:0] Name Data Read/Write 100 Read Charge mode : Battery OVP Boost mode : N/A 101 Read Charge mode : Thermal Shutdown Boost mode : Thermal Shutdown 110 Read Charge mode : Timer fault Boost mode : Timer fault 111 Read Charge mode : No battery Boost mode : N/A FAULT Description Table2. Register Address: 01 Bit [7:6] [5:4] 3 2 1 0 Name IIN_LIMIT VLOWV TE CE HZ_MODE OPA_MODE Data Read/Write Description 00 Read/Write 100mA 01 Read/Write 500mA 10 Read/Write 800mA 11 Read/Write No Current Limit 00 Read/Write 3.4V 01 Read/Write 3.5V 10 Read/Write 3.6V 11 Read/Write 3.7V 0 Read/Write Disable charge current termination 1 Read/Write Enable charge current termination 0 Read/Write Charge enabled 1 Read/Write Charge disabled 0 Read/Write Not High-Impedance Mode 1 Read/Write High-Impedance Mode 0 Read/Write Charge Mode 1 Read/Write Boost Mode Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 29 www.anpec.com.tw APW7262 Register Description Table3. Register Address: 02 Bit [7:2] Name OREG Data Read/Write Description 000000 Read/Write 3.5V 000001 Read/Write 3.52V 000010 Read/Write 3.54V 000011 Read/Write 3.56V 000100 Read/Write 3.58V 000101 Read/Write 3.6V 000110 Read/Write 3.62V 000111 Read/Write 3.64V 001000 Read/Write 3.66V 001001 Read/Write 3.68V 001010 Read/Write 3.7V 001011 Read/Write 3.72V 001100 Read/Write 3.74V 001101 Read/Write 3.76V 001110 Read/Write 3.78V 001111 Read/Write 3.8V 010000 Read/Write 3.82V 010001 Read/Write 3.84V 010010 Read/Write 3.86V 010011 Read/Write 3.88V 010100 Read/Write 3.9V 010101 Read/Write 3.92V 010110 Read/Write 3.94V 010111 Read/Write 3.96V 011000 Read/Write 3.98V 011001 Read/Write 4V 011010 Read/Write 4.02V 011011 Read/Write 4.04V 011100 Read/Write 4.06V 011101 Read/Write 4.08V 011110 Read/Write 4.1V 011111 Read/Write 4.12V 100000 Read/Write 4.14V 100001 Read/Write 4.16V 100010 Read/Write 4.18V 100011 Read/Write 4.2V 100100 Read/Write 4.22V Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 30 www.anpec.com.tw APW7262 Register Description Table3. Register Address: 02 Bit [7:2] 1 0 Name OREG OTG_PL OTG_EN Data Read/Write Description 100100 Read/Write 4.22V 100101 Read/Write 4.24V 100110 Read/Write 4.26V 100111 Read/Write 4.28V 101000 Read/Write 4.3V 101001 Read/Write 4.32V 101010 Read/Write 4.34V 101011 Read/Write 4.36V 101100 Read/Write 4.38V 101101 Read/Write 4.4V 101110 Read/Write 4.42V 101111 Read/Write 4.44V 110000 Read/Write 4.44V 110001 Read/Write 4.44V 110010 Read/Write 4.44V 110011 Read/Write 4.44V 110100 Read/Write 4.44V 110101 Read/Write 4.44V 110110 Read/Write 4.44V 110111 Read/Write 4.44V 111000 Read/Write 4.44V 111001 Read/Write 4.44V 111010 Read/Write 4.44V 111011 Read/Write 4.44V 111100 Read/Write 4.44V 111101 Read/Write 4.44V 111110 Read/Write 4.44V 0 Read/Write OTG pin active Low 1 Read/Write OTG pin active High 0 Read/Write OTG pin is disabled 1 Read/Write OTG pin is enabled Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 31 www.anpec.com.tw APW7262 Register Description Table4. Register Address: 03 Name Data Read/Write [7:5] Vender code 010 Read Only [4:3] PN 01 Read Only For I2C Add ress [2:0] REV 010 Read Only IC Revision Bit Description Table5. Register Address: 04 Read/Write Description Bit Name Data 7 Reserved 0 Read Only Unused 000 Read/Write RSNS: 56mΩ=>668mA; RSNS: 68mΩ=>550mA ; RSNS: 100mΩ=>374mA 001 Read/Write RSNS: 56mΩ=>789mA; RSNS: 68mΩ=>650mA ; RSNS: 100mΩ=>442mA 010 Read/Write RSNS: 56mΩ=>911mA; RSNS: 68mΩ=>750mA ; RSNS: 100mΩ=>510mA 011 Read/Write RSNS: 56mΩ=>1032mA; RSNS: 68mΩ=>850mA ; RSNS: 100mΩ=>578mA 100 Read/Write RSNS:56mΩ=>1275mA; RSNS: 68mΩ=>1050mA ; RSNS: 100mΩ=>714mA 101 Read/Write RSNS: 56mΩ=>1396mA; RSNS: 68mΩ=>1150mA ; RSNS: 100mΩ=>782mA 110 Read/Write RSNS: 56mΩ=>1639mA; RSNS: 68mΩ=>1350mA ; RSNS: 100mΩ=>918mA 111 Read/Write RSNS:56mΩ=>1882mA; RSNS: 68mΩ=>1550mA ; RSNS: 100mΩ=>1054mA 1 Read Only Unused 000 Read/Write RSNS: 56mΩ=>118mA; RSNS: 68mΩ=>97mA; RSNS: 100mΩ=>33mA 001 Read/Write RSNS: 56mΩ=>118mA; RSNS: 68mΩ=>97mA; RSNS: 100mΩ=>66mA 010 Read/Write RSNS: 56mΩ=>277mA; RSNS: 68mΩ=>146mA; RSNS: 100mΩ=>99mA 011 Read/Write RSNS: 56mΩ=>236mA; RSNS: 68mΩ=>194mA; RSNS: 100mΩ=>132mA 100 Read/Write RSNS: 56mΩ=>295mA; RSNS: 68mΩ=>243mA; RSNS: 100mΩ=>165mA 101 Read/Write RSNS: 56mΩ=>353mA; RSNS: 68mΩ=>291mA; RSNS: 100mΩ=>198mA 110 Read/Write RSNS: 56mΩ=>412mA; RSNS: 68mΩ=>340mA; RSNS: 100mΩ=>231mA 111 Read/Write RSNS: 56mΩ=>421mA; RSNS: 68mΩ=>388mA; RSNS: 100mΩ=>264mA [6:4] 3 [2:0] IOCHARGE Reserved ITERM Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 32 www.anpec.com.tw APW7262 Register Description Table6. Register Address: 05 Read/Write Description Bit Name Data 7 Reserved 0 Read Only Unused 6 Reserved 0 Read/Write Unused 0 Read/Write Charge current is controlled by IOCHARGE bits 5 IO_LEVEL 1 Read/Write Charge current is set to 395mA for RSNS: 56mΩ, 325mA for RSNS: 68mΩ, 221mA for RSNS: 100mΩ 0 Read Only Special charger is not active 1 Read Only Special charger is active and VBUS is being regulated to VSP 0 Read Only CD pin is Low 1 Read Only CD pin is High 000 Read/Write VSP=4.213V 001 Read/Write VSP=4.29V 010 Read/Write VSP=4.373V 011 Read/Write VSP=4.453V 100 Read/Write VSP=4.533V 101 Read/Write VSP=4.613V 110 Read/Write VSP=4.693V 111 Read/Write VSP=4.773V 4 3 [2:0] SP EN_LEVEL VSP Table7. Register Address: 06 Bit Name 7 Timer Data 0 Read/Write Call out 32sec timer function Read/Write 1 [6:4] ISAFE Description No 32sec timer function 000 Read/Write RSNS: 56mΩ=>668mA; RSNS: 68mΩ=>550mA ; RSNS: 100mΩ=>374mA 001 Read/Write RSNS: 56mΩ=>789mA; RSNS: 68mΩ=>650mA ; RSNS: 100mΩ=>442mA 010 Read/Write RSNS: 56mΩ=>911mA; RSNS: 68mΩ=>750mA ; RSNS: 100mΩ=>510mA 011 Read/Write RSNS: 56mΩ=>1032mA; RSNS: 68mΩ=>850mA ; RSNS: 100mΩ=>578mA 100 Read/Write RSNS: 56mΩ=>1275mA; RSNS: 68mΩ=>1050mA ; RSNS: 100mΩ=>714mA 101 Read/Write RSNS: 56mΩ=>1396mA; RSNS: 68mΩ=>1150mA ; RSNS: 100mΩ=>782mA 110 Read/Write RSNS: 56mΩ=>1639mA; RSNS: 68mΩ=>1350mA ; RSNS: 100mΩ=>918mA 111 Read/Write Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 RSNS: 56mΩ=>1882mA; RSNS: 68mΩ=>1550mA ; RSNS: 100mΩ=>1054mA 33 www.anpec.com.tw APW7262 Register Description Table6. Register Address: 06 (cont.) [3:0] VSAFE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 4.2V 4.22V 4.24V 4.26V 4.28V 4.3V 4.32V 4.34V 4.36V 4.38V 4.4V 4.42V 4.44V 4.44V 4.44V 4.44V 34 www.anpec.com.tw APW7262 Package Information E WLCSP1.7x2.1-20 Pin 1 A2 D A1 A NX aaa c e e/2 SEATING PLANE b e S Y M B O L WLCSP1.7x2.1-20 MILLIMETERS MIN. INCHES MAX. MIN. MAX. A 0.63 A1 0.19 0.23 0.007 0.009 A2 0.32 0.40 0.013 0.016 b 0.20 0.30 0.008 0.012 D 2.10 2.22 0.083 0.087 E 1.70 1.98 0.067 0.078 e aaa Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 0.025 0.40 BSC 0.016 BSC 0.05 0.002 35 www.anpec.com.tw APW7262 Package Information TQFN4x4-20A A e E D Pin 1 A1 D2 A3 NX aaa c L K E2 Pin 1 Corner e S Y M B O L A TQFN4x4-20A MILLIMETERS MAX. 0.80 MIN. 0.028 MAX. 0.031 0.05 0.000 0.002 0.18 0.30 0.008 REF 0.008 0.012 3.90 4.10 0.154 2.50 0.079 0.098 4.10 0.154 0.161 2.50 0.079 0.098 MIN. 0.70 A1 A3 0.00 0.20 REF b D D2 E E2 INCHES 2.00 3.90 2.00 0.161 e L 0.50 BSC 0.35 0.45 0.020 BSC 0.014 0.018 K 0.20 0.008 aaa 0.08 0.003 Note : 1. Followed from JEDEC MO-220 VGGD-5. Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 36 www.anpec.com.tw APW7262 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application WLCSP 1.7x2.1-20 A H 178.0±2.00 50 MIN. P0 P1 T1 8.4+2.00 -0.00 P2 4.0±0.10 4.0±0.10 2.0±0.05 A H 330.0±2.00 50 MIN. P0 P1 T1 12.4+2.00 -0.00 P2 4.0±0.10 8.0±0.10 2.0±0.05 TQFN4x4-20A C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00 d D W E1 F 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 D1 A0 B0 K0 2.15±0.05 2.32±0.05 0.81±0.05 d T 0.6+0.00 -0.40 D W E1 F 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 D1 T 0.6+0.00 -0.40 A0 B0 K0 4.30±0.20 4.30±0.20 1.00±0.20 1.5 MIN. 1.5 MIN. (mm) Devices Per Unit Package Type WLCSP1.7x2.1-20 TQFN4x4-20A Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 Unit Tape & Reel Tape & Reel Quantity 3000 3000 37 www.anpec.com.tw APW7262 Taping Direction Information WLCSP1.7x2.1-20 USER DIRECTION OF FEED TQFN4x4-20A USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 38 www.anpec.com.tw APW7262 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 39 www.anpec.com.tw APW7262 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 40 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7262 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Jul., 2014 41 www.anpec.com.tw