IDT 72V11071L15TFI

3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
FIFOs in a single package with all associated control, data, and flag lines
assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) has a 8-bit input
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and a Write Enable pin (WENA, WENB). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate Write Enable pin is asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and Read Enable pin (RENA, RENB). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual clock operation. An Output Enable pin
(OEA, OEB) is provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has two fixed flags, Empty (EFA, EFB) and Full (FFA,
FFB).
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FEATURES
•
•
•
•
•
•
•
•
•
IDT72V10071, IDT72V11071
IDT72V12071, IDT72V13071
IDT72V14071
Memory organization:
IDT72V10071  Dual 256 x 8
IDT72V11071  Dual 512 x 8
IDT72V12071  Dual 1,024 x 8
IDT72V13071  Dual 2,048 x 8
IDT72V14071  Dual 4,096 x 8
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
15 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty and Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)
Industrial temperature range (–40°°C to +85°° C)
DESCRIPTION
The IDT72V10071/72V11071/72V12071/72V13071/72V14071 are dual
Multimedia FIFOs. The device is functionally equivalent to two independent
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
READ
CONTROL
WRITE
CONTROL
RCLKA
RENA
OEA
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
DA0 - DA7
Data In
x8
RESET LOGIC
WENB
x8
FLAG OUTPUTS
RSA
WCLKB
QA0 - QA7
Data Out
EFA
FFA
READ
CONTROL
WRITE
CONTROL
RCLKB
RENB
OEB
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
DB0 - DB7
Data In
x8
RESET LOGIC
QB0 - QB7
Data Out
x8
FLAG OUTPUTS
RSB
EFB
FFB
6360 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
NOVEMBER 2003
INDUSTRIAL TEMPERATURE RANGE
1
 2003 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
DSC-6360/1
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
QA7
FFA
EFA
OEA
GND
RCLKA
RENA
GND
QB0
QB1
QB2
QB3
DNC
QB4
QB5
QB6
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DA3
GND
DA4
DA5
DA6
DA7
DNC(1)
DNC(1)
VCC
WCLKB
WENB
RSB
DB0
DB1
DB2
DB3
QA6
QA5
QA4
DNC(1)
QA3
QA2
QA1
QA0
VCC
VCC
WCLKA
WENA
RSA
DA0
DA1
DA2
NOTE:
1. DNC = Do Not Connect.
STQFP (PP64-1, order code: TF)
TOP VIEW
2
QB7
FFB
EFB
OEB
GND
RCLKB
RENB
GND
Vcc
DNC(1)
DNC(1)
DB7
DB6
DB5
DB4
GND
6360 drw02
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
The IDT72V10071/72V11071/72V12071/72V13071/72V14071's two
FIFOs, referred to as FIFO A and FIFO B, are identical in every respect.
FIFO A and FIFO B operate completely independent from each other.
Symbol
Name
I/O
Description
DA0-DA7
DB0-DB7
A Data Inputs
B Data Inputs
I
I
8-bit data inputs to FIFO array A.
8-bit data inputs to FIFO array B.
RSA, RSB
Reset
I
WCLKA
WCLKB
Write Clock
I
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) go as HIGH and EFA (EFB) go as LOW. After power-up, a reset of both FIFOs A and B
is required before an initial WRITE.
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable
is asserted.
WENA
WENB
QA0-QA7
Write Enable
When WENA (WENB) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA
(WCLKB). Data will not be written into the FIFO if FFA (FFB) is LOW.
O 8-bit data outputs from FIFO array A.
QB0-QB7
RCLKA
RCLKB
B Data Outputs
Read Clock
O 8-bit data outputs from FIFO array B.
I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA (RENB) is
asserted.
RENA
RENB
OEA
OEB
Read Enable
I
Output Enable
I
EFA
EFB
FFA
FFB
Empty Flag
O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When
EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA
(FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
V CC
GND
Power
Ground
A Data Outputs
Full Flag
I
When RENA (RENB) is LOW, data is read from FIFO A (B) on every LOW-to-HIGH transition of RCLKA
(RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
When OEA (OEB) is LOW, outputs DA0-DA7 (DB0-DB7) are active. If OEA (OEB) is HIGH, outputs
DA0-DA7 (DB0-DB7) will be in a high-impedance state.
+3.3V power supply pin.
0V ground pin.
3
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
RECOMMENDED OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
Rating
Terminal Voltage with
TSTG
IOUT
Respect to GND
Storage Temperature
DC Output Current
Industrial
–0.5 to +5
–55 to +125
–50 to +50
INDUSTRIAL TEMPERATURE RANGE
Unit
V
°C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol
Parameter
Min
Typ.
Max
Unit
VCC
Supply Voltage(Industrial)
3.0
3.3
3.6
V
GND
Supply Voltage(Industrial)
0
0
—
V
VIH
Input High Voltage (Industrial)
2.0
—
5.0
V
VIL
Input Low Voltage (Industrial)
—
—
0.8
V
TA
Operating Temperature
Industrial
-40

85
°C
NOTE:
1. Outputs are not 5V tolerant.
DC ELECTRICAL CHARACTERISTICS
(Industrial :VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Industrial
tCLK = 15 ns
Symbol
Min.
Typ.
Max.
Unit
Input Leakage Current (Any Input)
–1
—
–1
µA
Output Leakage Current
–10
—
10
µA
VOH
Output Logic “1” Voltage, IOH = –2 mA
2.4
—
—
V
VOL
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
V
Active Power Supply Current (both FIFOs)
—
—
40
mA
Standby Current
—
—
10
mA
ILI
(1)
ILO
(2)
ICC1(3,4,5)
(2,6)
ICC2
Parameter
NOTES:
1. Measurements with 0.4 ≤ V IN ≤ VCC.
2. OEA, OEB ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs disabled (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 2[0.17 + 0.48*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
V CC = 3.3V, T A = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
6. All Inputs = V CC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
(2)
CIN
COUT
Parameter
Input Capacitance
(1,2)
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
NOTE:
1. With output deselected (OEA, OEB ≥ VIH).
2. Characterized values, not currently tested.
4
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS(1)
(Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
Industrial
IDT72V10071L15
IDT72V11071L15
IDT72V12071L15
IDT72V13071L15
IDT72V14071L15
Symbol
Parameter
Min.
Max.
Unit
fS
Clock Cycle Frequency
—
66.7
MHz
tA
Data Access Time
2
10
ns
tCLK
Clock Cycle Time
15
—
ns
tCLKH
Clock High Time
6
—
ns
tCLKL
Clock Low Time
6
—
ns
tDS
Data Set-up Time
4
—
ns
tDH
Data Hold Time
1
—
ns
tENS
Enable Set-up Time
4
—
ns
tENH
Enable Hold Time
1
—
ns
tRS
Reset Pulse Width(1)
15
—
ns
tRSS
Reset Set-up Time
10
—
ns
tRSR
Reset Recovery Time
10
—
ns
tRSF
Reset to Flag Time and Output Time
—
15
ns
tOLZ
Output Enable to Output in Low-Z(2)
0
—
ns
tOE
Output Enable to Output Valid
3
8
ns
tOHZ
Output Enable to Output in High-Z(2)
3
8
ns
tWFF
Write Clock to Full Flag
—
10
ns
tREF
Read Clock to Empty Flag
—
10
ns
tSKEW1
Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag
6
—
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
510Ω
GND to 3.0V
30pF*
6360 drw03
or equivalent circuit
Figure 1. Output Load
See Figure 1
*Includes jig and scope capacitances.
5
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
Read Enable (RENA, RENB) — When Read Enable, RENA, (RENB) is
LOW, data is read from Array A (B) to the output register on the LOW-to-HIGH
transition of the Read Clock, RCLKA (RCLKB).
When Read Enable, RENA, (RENB) for FIFO A (B) is HIGH, the output
register holds the previous data and no new data is allowed to be loaded into
the register.
When all the data has been read from FIFO A (B), the Empty Flag, EFA
(EFB) will go LOW, inhibiting further read operations. Once a valid write
operation has been accomplished, EFA (EFB) will go HIGH after tREF and a
valid read can begin. The Read Enable, RENA, (RENB) is ignored when FIFO
A (B) is empty.
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The following description
explains the interaction of input and output signals for FIFO A. The corresponding signal names for FIFO B are provided in parentheses.
INPUTS
Data In (DA0 – DA7, DB0 – DB7) — DA0 - DA7 are the eight data inputs
for memory array A. DB0 - DB7 are the eight data inputs for memory array B.
CONTROLS
Reset (RSA, RSB) — Reset of FIFO A (B) is accomplished whenever RSA
(RSB) input is taken to a LOW state. During reset, the internal read and write
pointers associated with the FIFO are set to the first location. A reset is required
after power-up before a write operation can take place. The Full Flag, FFA
(FFB) will be reset to HIGH after tRSF. The Empty Flag, EFA (EFB) will be reset
to LOW after tRSF. During reset, the output register is initialized to all zeros.
Output Enable (OEA, OEB) — When Output Enable, OEA (OEB) is
enabled (LOW), the parallel output buffers of FIFO A (B) receive data from their
respective output register. When Output Enable, OEA (OEB) is disabled
(HIGH), the QA (QB) output data bus is in a high-impedance state.
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is initiated
on the LOW-to-HIGH transition of WCLKA (WCLKB). Data set-up and hold
times must be met with respect to the LOW-to-HIGH transition of WCLKA
(WCLKB). The Full Flag, FFA (FFB) is synchronized with respect to the
LOW-to-HIGH transition of the Write Clock, WCLKA (WCLKB).
The Write and Read clock can be asynchronous or coincident.
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA (FFB) will go LOW after 256 writes to the IDT72V10071's FIFO A (B), 512
writes to the IDT72V11071's FIFO A (B), 1,024 writes to the IDT72V12071's
FIFO A (B), 2,048 writes to the IDT72V13071's FIFO A (B), and 4,096 writes
to the IDT72V14071's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of
the Write Clock WCLKA (WCLKB).
OUTPUTS
Write Enable (WENA, WENB) — When WENA (WENB) is LOW, data can
be loaded into the input register of RAM Array A (B) on the LOW-to-HIGH
transition of every Write Clock, WCLKA (WCLKB). Data is stored in Array A
(B) sequentially and independently of any on-going read operation.
When WENA (WENB) is HIGH, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write
operations. Upon the completion of a valid read cycle, the FFA (FFB) will go
HIGH after tWFF, allowing a valid write to begin. WENA (WENB) is ignored when
FIFO A (B) is full.
Empty Flag (EFA, EFB) — EFA (EFB) will go LOW, inhibiting further read
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
EFA (EFB) is synchronized with respect to the LOW-to-HIGH transition of
the Read Clock RCLKA (RCLKB).
Data Outputs (QA0 – QA7, QB0 – QB7 ) — QA0 - QA7 are the eight data
outputs for memory array A, QB0 - QB7 are the eight data outputs for memory
array B.
Read Clock (RCLKA, RCLKB) —
Data can be read from Array A (B) on the LOW-to-HIGH transition of
RCLKA (RCLKB). The Empty Flag, EFA (EFB) is synchronized with respect
to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clock can be asynchronous or coincident.
6
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
tRS
RSA (RSB)
tRSS
tRSR
tRSS
tRSR
RENA(RENB)
WENA (WENB)
tRSF
EF A
(EF B)
tRSF
FFA
(F F B)
tRSF
(1)
OEA (OEB) = 1
QA0 - QA7
(QB0 - QB7)
OEA (OEB) = 0
6360 drw04
NOTES:
1. After reset, QA0 - QA7 (QB0 - QB7) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
2. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 2. Reset Timing
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tDH
tDS
(DA0 - DA7
DB0 - DB7)
DATA IN VALID
tENS
tENH
WENA (WENB)
NO OPERATION
tWFF
tWFF
F F A (F F B)
tSKEW1(1)
RCLKA (RCLKB)
RENA (RENB)
6360 drw05
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
Figure 3. Write Cycle Timing
7
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENH
tENS
NO OPERATION
RENA (RENB)
tREF
tREF
EF A (EF B)
tA
QA0 - QA7
(QB0 - QB7)
VALID DATA
tOLZ
tOHZ
tOE
OEA (OEB)
(1)
tSKEW1
WCLKA, WCLKB
WENA (WENB)
6360 drw06
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
Figure 4. Read Cycle Timing
WCLKA (WCLKB)
tDS
DA0 - DA7
(DB0 - DB7)
D1
tENS
D2
D3
D0 (First Valid Write)
WENA (WENB)
tSKEW1
tFRL(1)
RCLKA (RCLKB)
tREF
EF A (EF B)
tENS
RENA (RENB)
tA
QA0 - QA7
(QB0 - QB7)
tA
D0
D1
tOLZ
tOE
OEA (OEB)
6360 drw07
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 5. First Data Word Latency Timing
8
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
NO WRITE
NO WRITE
WCLKA
(WCLKB)
INDUSTRIAL TEMPERATURE RANGE
tSKEW1
tDS
NO WRITE
tSKEW1
tDH
DA0 - DA7
(DB0 - DB7)
tWFF
tWFF
tWFF
FFA (FFB)
tENS
tENS
tENH
WENA
(WENB)
RCLKA
(RCLKB)
tENS
tENH
tENS
tENH
RENA
(RENB)
tA
OEA LOW
(OEB)
QA0 - QA7
(QB0 - QB7)
tA
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
6360 drw08
Figure 6. Full Flag Timing
WCLKA (WCLKB)
tDS
tDS
DA0 - DA7
(DB0 - DB7)
DATA WRITE 1
tENS
DATA WRITE 2
tENH
WENA, (WENB)
tENS
tENH
(1)
(1)
tSKEW1
tFRL
tSKEW1
tFRL
RCLKA (RLCKB)
tREF
tREF
tREF
EFA (EFB)
RENA
(RENB)
OEA (OEB)
LOW
tA
QA0 - QA7
(QB0 - QB7)
DATA READ
DATA IN OUTPUT REGISTER
6360 drw09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. Empty Flag Timing
9
ORDERING INFORMATION
IDT
XXXXX
Device Type
X
Power
XX
Speed
XX
Package
X
Process/
Temperature
Range
I
Industrial (-40°C to +85°C)
TF
Plastic Quad Flatpack (STQFP, PP64-1)
15
Industrial
L
Low Power
72V10071
72V11071
72V12071
72V13071
72V14071
256 x 8  3.3 Volt DUAL Multimedia FIFO
512 x 8  3.3 Volt DUAL Multimedia FIFO
1,024 x 8  3.3 Volt DUAL Multimedia FIFO
2,048 x 8  3.3 Volt DUAL Multimedia FIFO
4,096 x 8  3.3 Volt DUAL Multimedia FIFO
Clock Cycle Time (tCLK),
speed in Nanoseconds
6360 drw10
DATASHEET DOCUMENT HISTORY
11/17/2003
pg. 1.
CORPORATE HEADQUARTERS
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Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
10
for TECH SUPPORT:
(408) 330-1753
FIFOhelp@idt.com