Datasheet

THCS132_Rev.1.02_E
THCS132
I/OSpreader
General Description
Features
The THCS132 provides a function to serialize
multiple parallel signals into single-ended serial
line at least or to deserialize the data stream over
single-ended serial line or single differential pair
into multiple parallel signals.
This small number of transmission line simplifies
system configuration and reduces system cost
including cable width, connector size and pins
and PCB layout area.
The THCS132 is offered in 8bit/16bit parallel
IOs as host MPU interface. It can transfer 16bit
independent parallel signals to remote side by
only 1-line or 1-pair cable.
Transmitter, receiver or transceiver function can
be selected by pin options.
- No External Clock Required.
-8bit/16bit Parallel IOs to MPU.
- Uni-directional/Bi-directional Mode Selectable
- Single-ended/Differential Mode (noise tolerant)
Selectable
- AC Coupling Supported with Differential Mode
- Transmission Status Error Indicator Supported
(Line Cut Detection and Packet Error
Detection)
- Digital Filter Function.
- Power supply : 3.0 to 5.5V
- QFN 32-pin Package
- EU RoHS Compliant
Block Diagram
THCS132
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BID
FAULTN
RSTN
DATA0
DATA1
DATA2
DATA3
DATA4
25
26
27
28
29
30
31
32
DIR
TEST
GND
NC
NC
VDD
WIDTH
FILT
Pin Diagram
1
24
2
23
3
4
5
6
22
Exposed Pad
(Top View)
33 GND EXP
21
20
19
7
18
8
17
SIG
IOP
ION
DATA15
DATA14
DATA13
DATA12
GND
GND
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
9 10 11 12 13 14 15 16
Pin Description
Pin No.
Pin Name
Internal Processing
1
BID
Input, Pull-down
2
FAULTN
Output, Open-drain
3
RSTN
Input, Pull-down
4-8
10-16
18-21
DATA0-15
Input/Output,
Pull-up
9,17,30
GND
-
22
ION
Input/Output
Serial data differential mode(-) I/O
23
IOP
Input/Output
Serial data CMOS/differential mode(+) I/O
24
SIG
Input, Pull-down
Serial data I/O mode select
Low : CMOS High : Differential
25
FILT
Input, Pull-down
Digital filter enable pin
Low : OFF High : ON
26
WIDTH
Input, Pull-down
Data bit width select
Low : 8bit High : 16bit
27
VDD
-
Power Supply
28,29
NC
-
Non-connection pin. Please set it being opened.
31
TEST
Input, Pull-down
Test pin. Please connect to GND.
Transmitter/receiver select
Low : Transmitter (Uni-direction) / Master (Bi-direction)
High : Receiver (Uni-direction) / Slave (Bi-direction)
32
DIR
Input, Pull-down
33
GND EXP
-
Description
Uni-direction/Bi-direction mode select
Low : Uni-direction High : Bi-direction
Transmitter status error indicator
Low : Abnormal operation detected
Reset input
Low : Reset
High : Normal operation
Parallel data I/O bit : 0-15
Refer to the tables of “Parallel I/O Pin Function”
Ground
GND EXP should be soldered to GND.
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Absolute Maximum Rating
Parameter
Condition
Min
Typ
Max
Unit
-
-0.4
-
6
V
-0.4
-
6
V
-
-0.4
-
6
V
Ta=25℃
-
-
2
W
Storage Temperature
-
-55
-
150
℃
Junction Temperature
-
-
-
125
℃
Condition
Min
Typ
Max
Unit
Power Supply Voltage VDD
-
3.0
-
5.5
V
Ambient Operating Temperature
-
-40
-
85
℃
Power Supply Voltage VDD
Digital Input Voltage
(DATA0-DATA15,WIDTH,BID,FILT,DIR,SI
G,RSTN)
Open-drain Output Pin(FAULTN)
Allowable Power Dissipation
-
Recommended Operating Condition
Parameter
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Electrical Characteristic DC Characteristics (at VDD=5.0V, Ta=25℃, unless otherwise noted)
Parameter
Condition
Min
Typ
Max
Unit
-
20
30
mA
Mode E
Power Supply Current
LVDS mode
(Note)
UVLO Threshold Voltage (VDD Rising)
-
-
2.6
2.8
V
UVLO Hysteresis Voltage
-
-
0.15
-
V
Digital Input High-level Voltage (VIH)
-
0.7VDD
-
-
V
Digital Input Low level Voltage (VIL)
-
-
-
0.3VDD
V
Digital Input Leakage Current 1
-
-
-
+/-50
uA
Digital Input Hysteresis Voltage
VDD=3.0V
-
0.11VDD
-
V
Tj=125℃
VDD-0.6
-
-
V
Digital Output High-level Voltage
(VOH)
Iout=-4mA
Digital Output High-level ON Resistance
VDD=3.3V
-
56
-

(RonH)
VDD=5.0V
-
46
-

-
-
0.4
V
VDD=3.0V
Digital Output Low-level Voltage (VOL)
Tj=125℃
Iout=4mA
Digital Output Low-level ON Resistance
VDD=3.3V
-
44
-

(RonL)
VDD=5.0V
-
36
-

-
-
0.4
V
Open Drain Output Low-level Voltage
Iout=1mA
FAULTN
LVDS Differential Input Voltage (VID)
IOP/ION
200
-
-
mV
LVDS Input Leakage Current
IOP/ION
-
-
+/-50
uA
350
-
-
mV
-
600
-
mV
-
-
750
mV
IOP/ION
1.0
1.25
1.4
V
-
-
250
-
k
VDD=3.0V
IOP/ION
LVDS Differential Output Voltage
(VOD)
VDD=5.0V
IOP/ION
VDD=5.5V
IOP/ION
LVDS Output Common-mode Voltage
(VOC)
Pull-down Resistance
Pull-up Resistance
500
k
Note: The power supply current is maximum in this condition.
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LVDS Input Output Differential Voltage
ION
ION
VOC
VID
VOD
IOP
IOP
Electrical Characteristic AC Characteristics (Reset Section)
Mark
tRST
tWRST
Parameter
Time from Reset (RSTN) Release to
Valid Input
Reset (RSTN) Low Pulse Width
Condition
Min
Typ
-
-
-
-
50
-
Max
100
(Note)
-
Unit
us
ns
Note : In AC coupling, tRST changes with the capacity to connect.
Timing Chart (Reset Section)
Rese t(RSTN) signal
tWRST
Input Reset(RSTN)
tRST
Input data/Bi-direction
(DATA)
Valid data
Output data(DATA)
500kΩpull up
Output Low
Vaild data output
In the case of the mode F, output is controlled by signal of
output enable (OEN_L/OEN_U), a pull-up state is continued
until it sets signal of output enable to LOW.
Electrical Characteristic AC Characteristics (Serial Communication)
Mark
fPSPLa
fPSPLb
Item
Serializer Input Sampling Frequency
(Uni-direction)
Serializer Input Sampling Frequency
(Bi-direction)
Condition
Min
Typ
Max
Unit
BID=L
50
-
-
kHz
BID=H
30
-
-
kHz
tPSa
Time of Serializer Transmission (Uni-direction)
BID=L
-
-
18
us
tSPa
Deserializer Output Renewal Time (Uni-direction)
BID=L
-
-
2
us
tPSb
Time of Serializer Transmission (Bi-direction)
BID=H
-
-
14
us
tSPb
Deserializer Output Renewal Time (Bi-direction)
BID=H
-
-
2
us
fSTR
Serial Data Transmission Rate
-
-
2.5
-
MHz
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Timing Chart (Uni-direction Mode)
Transmitter Mode
Internal Register
Input (DATA[15:0])
Parallel Input[15:0]
1/fPSPLa
Internal Sampling Clock
tPSa
Serial Data Output
Receiver Mode
Serial Data Input
Serial Output
Serial Output
Serial Input
Serial Input
Internal Register
Output (DATA[15:0])
Parallel Output[15:0]
tSPa
Timing Chart (Bi-direction Mode)
Master device
Input data(DATA[7:0])
Parallel input [7:0]
Output data(DATA[7:0])
Parallel output [7:0]
1/fPSPLb
Internal sampling clock
tPSb
Input/Output Serial data
Serial output
Serial input
Slave device
Input/Output Serial data
Serial input
Serial output
tSPb
Serial output
Serial input
Internal sampling clock
tPSb
Output data(DATA[7:0])
Parallel output [7:0]
tSPb
Input data (DATA[7:0])
Parallel input [7:0]
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Electrical Characteristic AC Characteristics (Latch Enable, Output Enable)
Symbol
tWLE
tSULE
tHLE
tCLLEa
tCLLEb1
Parameter
Condition
Min
Typ
Max
Unit
-
130
-
-
ns
-
133
-
-
ns
-
20
-
-
ns
-
100
-
-
ns
-
20
-
-
us
Latch Enable(LEN_U/LEN_L/LEN)Pulse
Width
Latch Enable (LEN_U/LEN_L/LEN)Rise
Edge Setup Time
Latch Enable (LEN_U/LEN_L/LEN)Rise
Edge Hold Time
Latch Enable (LEN_U/LEN_L/LEN)
Clearance1
Latch Enable (LEN_U/LEN_L/LEN)
Clearance2 (Uni-direction)
tCLLEb2
Latch Enable (LEN)Clearance2(Bi-direction)
-
40
-
-
us
tWOE
Output Enable (OEN_U/OEN_L)Pulse Width
-
50
-
-
ns
tCLOE
Output Enable (OEN_U/OEN_L)Clearance
-
50
-
-
ns
tPZO
Output Enable (OEN_U/OEN_L)Delay Time
CL=25pF
-
-
50
ns
tPOZ
Output Disable (OEN_U/OEN_L)Delay Time
CL=25pF
-
-
38
ns
Timing Chart (Latch Enable, Output Enable)
8bit Input + Latch Enable
Upper Latch Enable
(LEN_U)
Lower Latch Enable
(LEN_L)
Data Input
(DATA[7:0])
tWLE
tCLLEb1
tCLLEa
tSULE
tHLE
Upper 8bit data
Lower 8bit data
Upper 8bit data
8bit Output+ Output Enable
Upper Output Enable
(OEN_U)
Lower Output Enable
(OEN_L)
Data Output
(DATA[7:0])
tCLOE
tWOE
tPZO
tPOZ
Upper 8bit data
Lower 8bit data
When receiving new incoming data during OEN_U or OEN_L = Low, output data is updated to this new data .
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8bit Input/Output + Latch enable・Output enable
tWLE
Input latch enable
(LEN)
output enable
(OEN)
tCLLEb2
tWOE
tSULE
Input/Output data
(DATA[7:0])
tHLE
tPZO
Transmitter data
tPOZ
Receive r data
Transmitter data
When receiving new incoming data during OEN = Low, output data is updated to this new data
Functional Description
・Functional Description List for Mode Pin
Pin Name
Mode
Name
WIDTH
BID
A
L
B
H
C
H
D
E
F
DATA11
L
-
-
16bit / Bi-direction / Transmitter
H
-
-
16bit / Bi-direction / Receiver
L
-
-
8bit / Bi-direction / Transmitter・Receiver Master
H
-
-
8bit / Bi-direction / Transmitter・Receiver Slave
8bit(Upper・Lower)/ Uni-direction / Transmitter
H
L
G
DATA10
L
L
H
Operating Mode
DIR
L
L
L
8bit(Upper・Lower)/ Uni-direction / Receiver
8bit(Upper・Lower)/ Bi-direction / Transmitter・
Receiver Master
・Mode Connectable Table
Mode Name
A
A
B
B
C
F
G
v
v
16bit / Uni-direction / Receiver
v
8bit / Bi-direction / Transmitter・Receiver Master
v
E
v
v
v
v
Operating Mode
16bit / Uni-direction / Transmitter
v
D
G
E
v
C
F
D
v
v
8bit / Bi-direction / Transmitter・Receiver Master
8bit(Upper・Lower)/ Uni-direction / Transmitter
8bit(Upper・Lower)/ Uni-direction / Receiver
8bit(Upper・Lower)/ Bi-direction / Transmitter・
Receiver Master
・「v」mark indicates a possible connection mode.
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・Parallel I/O Pin Function (Mode A, B, C, D)
WIDTH
High (16bit)
BID
Low (Uni-direction)
Low (Uni-direction)
High (Bi-direction)
High (Bi-direction)
DIR
Low (Transmitter)
High (Receiver)
Low (Master)
High (Slave)
Mode
A
B
C
D
I/O
Function Name
I/O
Function Name
I/O
Function Name
I/O
Function Name
DATA0
I
DIN0
O
DOUT0
I
DIN0
I
DIN0
DATA1
I
DIN1
O
DOUT1
I
DIN1
I
DIN1
DATA2
I
DIN2
O
DOUT2
I
DIN2
I
DIN2
DATA3
I
DIN3
O
DOUT3
I
DIN3
I
DIN3
DATA4
I
DIN4
O
DOUT4
I
DIN4
I
DIN4
DATA5
I
DIN5
O
DOUT5
I
DIN5
I
DIN5
DATA6
I
DIN6
O
DOUT6
I
DIN6
I
DIN6
DATA7
I
DIN7
O
DOUT7
I
DIN7
I
DIN7
DATA8
I
DIN8
O
DOUT8
O
DOUT0
O
DOUT0
DATA9
I
DIN9
O
DOUT9
O
DOUT1
O
DOUT1
DATA10
I
DIN10
O
DOUT10
O
DOUT2
O
DOUT2
DATA11
I
DIN11
O
DOUT11
O
DOUT3
O
DOUT3
DATA12
I
DIN12
O
DOUT12
O
DOUT4
O
DOUT4
DATA13
I
DIN13
O
DOUT13
O
DOUT5
O
DOUT5
DATA14
I
DIN14
O
DOUT14
O
DOUT6
O
DOUT6
DATA15
I
DIN15
O
DOUT15
O
DOUT7
O
DOUT7
Connection Examples (Mode A, B, C, D)
Mode A
DIN[15:0]
Mode B
Serialize
Deserialize
Mode C
DOUT[15:0]
Mode D
DOUT[7:0]
DIN[7:0]
Serialize
&
Deserialize
Serialize
&
Deserialize
DIN[7:0]
DOUT[7:0]
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Parallel I/O Pin Function (Mode E, F, G)
WIDTH
Low (8bit Upper・Lower)
BID
Low (Uni-direction)
Low (Uni-direction)
High (Bi-direction)
DIR
Low (Transmitter)
High (Transmitter)
Low (Master)
Mode
E
F
G
I/O
Function Name
I/O
Function Name
I/O
Function Name
DATA0
I
DIN0
O
DOUT0
IO
DIO0
DATA1
-
-
-
-
-
-
DATA2
I
DIN1
O
DOUT1
IO
DIO1
DATA3
-
-
-
-
-
-
DATA4
I
DIN2
O
DOUT2
IO
DIO2
DATA5
-
-
-
-
-
-
DATA6
I
DIN3
O
DOUT3
IO
DIO3
DATA7
-
-
-
-
-
-
DATA8
I
LEN_L
I
OEN_L
I
LEN
DATA9
I
LEN_U
I
OEN_U
I
OEN
DATA10
I
Low
I
Low
I
Low
DATA11
I
Low
I
Low
I
Low
DATA12
I
DIN4
O
DOUT4
IO
DIO4
DATA13
I
DIN5
O
DOUT5
IO
DIO5
DATA14
I
DIN6
O
DOUT6
IO
DIO6
DATA15
I
DIN7
O
DOUT7
IO
DIO7
*Non-functional pins marked as “-” are pulled up by 500kΩ internally
Connection Example (Mode E, F, G)
Mode E
DIN[7:0]
Latch
circuit
Mode F
Serialize
Deserialize
Selector
DOUT[7:0]
LEN_U
OEN_U
LEN_L
OEN_L
Mode G
Mode D
DOUT[7:0]
DIO[7:0]
Latch
Circuit
&
I/O
conversion
Serialize
&
Deserialize
Serialize
&
Deserialize
DIN[7:0]
LEN
OEN
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・Latch Enable, Output Enable Truth Table
Mode E
LEN_U
LEN_L
Latch Enable Input
L
L
↑
H
Upper 8bit input latch
H
↑
Lower 8bit input latch and 16bit data reception
H
H
Keep data
Lower 8bit is transmitted by sampling frequency
(8bit through mode)
The rising edge of LEN_L is the trigger for sampling of upper and lower data.
Mode F
OEN_U
OEN_L
Output Enable Input
L
L
L
H
Upper 8bit Output enable
H
L
Lower 8bit Output enable
H
H
Output disable
(DATA pins are pulled up by 500k internally)
Output disable
(DATA pins are pulled up by 500k internally)
Mode G
LEN
OEN
L
L
Prohibition
↑
H
8bit Input Latch
H
L
8bit Output enable
H
H
Latch Enable、Output Enable Input
Output disable
(DATA pins are pulled up by 500k internally)
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
Function Setup for Serial I/O Pins
IOP and ION pins are set as 1 line CMOS I/O or 2-lane LVDS I/O with a SIG pin.
Pin Setup
Pin Function
Description
SIG
IOP
ION
L
CMOS I/O
*
H
Differential mode I/O+
Differential mode I/O
CMOS I/O
Differential mode I/O
*: Please keep pin being opened(No connection)

Function of Transmission Status Error Indicator, FAULTN (Receiver mode)
FAULTN is the output pin. When the protocol of received data is not correct or serial data more than
50usec (typ) is not received, FAULTN pin will be changed into low level. The received data is
canceled when a FAULTN pin outputs Low. When normal serial data is received, a FAULTN pin
outputs High in case of pulled up externally.

Digital Filter Function
When FILT pin is set to high level, the digital filter function is active.
If the transmitter matches the 3
sampling frequency content with the deserialized parallel data, it is updated as the correct data.
Electrical Characteristic AC Characteristics (3-wire Serial I/O Unit)
Mark
Parameter
Condition
Min
Typ
Max
Unit
fSCK
tCH
SCK Frequency
SCK High period
-
50
-
10
-
MHz
ns
tCL
SCK Low period
-
50
-
-
ns
tDVCH
SI Setup time
-
10
-
-
ns
tCHDX
SI Hold time
-
15
-
-
ns
tCHSL
CSN Not Active Hold time
-
10
-
-
ns
tSLCH
CSN Active Setup time
-
200
-
-
ns
tCHSH
CSN Active Hold time
-
50
-
-
ns
tSHCH
CSN Not Active Set up time
-
50
-
-
ns
tSHSL
CSN Not Active period
-
2
-
-
us
tSLSO
Delay time From CSN Fall to SO Output
CL=25pF
-
-
190
ns
tCLSO
Delay time From SCK Fall to SO Output
CL=25pF
-
-
40
ns
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Timing Chart (3-wire Serial I/O Unit)
CSN
tSHSL
tCHSL
tSLCH
tCL
tCHSH
tCH
tSHCH
SCK
tDVCH
tCHDX
SI
tSLSO
tCLSO
SO
Function Description

Mode Pin Function Setting List
Pin Name
Mode
Name
WIDTH
A serial
B serial
C serial
L
BID
DIR
L
L
L
H
H
L
Etc
DATA10:H
DATA11:L
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Operating Mode
Serial / Uni-direction / Transmitter
Serial / Uni-direction / Receiver
Serial / Bi-direction / Master
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
Parallel I/O Pin Function (Mode A serial, B serial, C serial)
WIDTH
Low(3 lines serial)
BID
Low(Uni-direction)
Low(Uni-direction)
High(Bi-direction)
DIR
Low(Transmitter)
High(Transmitter)
Low(Master)
Mode
A Serial
B Serial
C Serial
I/O
Function name
I/O
Function name
I/O
Function name
I
CSN
I
CSN
I
CSN
DATA1
I
SCK
I
SCK
I
SCK
DATA2
I
SI
-
-
I
SI
DATA3
-
-
O
SO
O
SO
DATA4
-
-
-
-
-
-
DATA5
-
-
-
-
-
-
DATA6
-
-
-
-
-
-
DATA7
-
-
-
-
-
-
DATA8
-
-
-
-
-
-
DATA9
-
-
-
-
-
-
DATA10
I
High
I
High
I
High
DATA11
I
Low
I
Low
I
Low
DATA12
-
-
-
-
-
-
DATA13
-
-
-
-
-
-
DATA14
-
-
-
-
-
-
DATA15
-
-
-
-
-
-
DATA0
* Unnamed pin is pulled up by 500k internally.

Connection Examples (Mode A serial, B serial, C serial)
Mode A serial
CSN
SCK
SI
Serial
I/F
Mode B serial
Serialize
Deserialize
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Serial
I/F
CSN
SCK
SO
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Mode C Serial
CSN
SCK
SI
SO
Mode D
DOUT[7:0]
Serial
I/F
Serialize
&
Deserialize
Serialize
&
Deserialize
DIN[7:0]
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THCS132_Rev.1.02_E
Package
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THCS132_Rev.1.02_E
Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always
apply to the customer's design. We are not responsible for possible errors and omissions in this material.
Please note if errors or omissions should be found in this material, we may not be able to correct them
immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third
parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we
will be exempted from the responsibility unless it directly relates to the production process or functions of
the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications : audio-video
device, office automation device, communication device, consumer electronics, smartphone, feature
phone, and amusement machine device. This product must not be used
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a
product conforming to the demands and specifications of ISO/TS16949 ("the Specified Product") in this
data sheet. THine Electronics, Inc. (“THine”) accepts no liability whatsoever for any product other than
the Specified Product for it not conforming to the aforementioned demands and specifications.
5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that
the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a
certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged
to have sufficiently redundant or error preventive design applied to the use of the product so as not to
have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary
to support warranty for performance of this product. Except where mandated by applicable law or deemed
necessary by THine based on the user’s request, testing of all functions and performance of the product is
not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of
strategic goods under the Foreign Exchange and Foreign Trade Control Law.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings
or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a
smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection
devices, such as fuses.
THine Electronics, Inc.
sales@thine.co.jp
Copyright©2016 THine Electronics, Inc.
17/17
THine Electronics, Inc.
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