®
ispLSI 1000EA Family
Architectural Description
October 2001
Introduction
The ispLSI 1000EA Family of High Density Programmable Logic devices includes the 1016EA, 1024EA, 1032EA
and 1048EA devices. Each family member offers internal registers, input registers, Universal I/O pins, dedicated
input pins, dedicated clock inputs and a Global Routing Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1000EA Family features 5V JTAG In-System Programmability (ISP™)
and in-system diagnostic capabilities via the IEEE 1149.1 Test Access Port. The devices offer non-volatile reprogrammability of the logic, as well as the interconnects, to provide truly reconfigurable systems. Each output pin has
optional slow slew and open-drain configurations.
The basic unit of logic for the ispLSI families is the Generic Logic Block (GLB). Figure 1 illustrates the ispLSI
1032EA with its 32 GLBs labeled A0, A1 .. D7. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and
four outputs, which can be configured to be either combinatorial or registered. Inputs to the GLB come from the
Global Routing Pool (GRP) and dedicated inputs. All of the GLB outputs are brought back into the GRP so they can
be connected to the inputs of any other GLB on the device.
IN 7
IN 6
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 59
I/O 58
I/O 57
I/O 56
I/O 63
I/O 62
I/O 61
I/O 60
Figure 1. ispLSI 1032EA Functional Block Diagram
RESET
Input Bus
VCCIO
Generic
Logic Blocks
(GLBs)
Output Routing Pool (ORP)
D7
D6
D5
D4
D3
D2
D1
GOE 1/IN 5
GOE 0/IN 4
D0
I/O 47
I/O 46
I/O 45
I/O 44
C7
C5
A2
A3
A4
C3
C2
A5
C1
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
A6
I/O 12
I/O 13
I/O 14
I/O 15
C0
B1
B2
B3
B4
B5
B6
Output Routing Pool (ORP)
TMS
Input Bus
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
0139B/1032EA
B7
Megablock
TDO
Clock
Distribution
Network
Y0
Y1
Y2
Y3
A7
B0
TDI
C4
Global
Routing
Pool
(GRP)
lnput Bus
Output Routing Pool (ORP)
I/O 8
I/O 9
I/O 10
I/O 11
C6
A1
lnput Bus
I/O 4
I/O 5
I/O 6
I/O 7
A0
Output Routing Pool (ORP)
I/O 0
I/O 1
I/O 2
I/O 3
www.latticesemi.com
1
I/O 28
I/O 29
I/O 30
I/O 31
I/O 24
I/O 25
I/O 26
I/O 27
I/O 20
I/O 21
I/O 22
I/O 23
I/O 16
I/O 17
I/O 18
I/O 19
TCK
1karch_07
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
As an example, the ispLSI 1032EA has 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell
can be individually programmed to be a combinatorial input, registered input, latched input, output or bidirectional
I/O pin with tristate control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages.
The I/O cells are grouped into sets of 16 as shown in Figure 1. Each of these I/O groups is associated with a
Megablock through the use of the Output Routing Pool (ORP).
Eight GLBs, 16 I/O cells, one ORP and two dedicated inputs are connected together to make a Megablock. The
outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each Megablock can generate one common Product Term Output Enable (PTOE) signal. The ispLSI 1032EA device, shown in Figure 1, contains four Megablocks.
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bidirectional I/O cells. All
of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the devices are selected using the Clock Distribution Network. The dedicated clock pins (Y0, Y1, Y2 and
Y3) are brought into the distribution network, and five outputs (CLK 0, CLK1, CLK 2, IOCLK 0 and IOCLK 1) are
provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special GLB (C0 on the ispLSI 1032EA devices). The logic of this GLB allows the user to create an internal clock from
a combination of internal signals within the device.
All ispLSI 1000EA family members are 100% IEEE 1149.1 Boundary Scan Testable through the Boundary Scan
Test Access Port (TAP).
Generic Logic Block
The Generic Logic Block (GLB) is the standard logic block of Lattice’s high density ispLSI devices. A GLB has 18
inputs, four outputs and the logic necessary to implement most standard logic functions. The internal logic of the
GLB is divided into four separate sections: the AND Array, the Product Term Sharing Array (PTSA), the Reconfigurable Registers and the Control Functions (see Figure 2).
Figure 2. GLB: Product Term Sharing Array Example
Inputs From
Global Routing Pool
0
1
2
3
4
5
6
7
8
Dedicated
Inputs
Product Term
Sharing Array
9 10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4
Reconfigurable
Registers
D, J-K, and T
DQ
M
U
X
DQ
M
U
X
DQ
M
U
X
O2 To
Global
Routing
Pool and
Output
Routing
O1
Pool
DQ
M
U
X
O0
4
5
7
O3
AND Array
PT Reset
Global RESET
Control
Functions
CLK 0
CLK 1
CLK 2
PT Clock
MUX
PT Output
Enable
MUX
To Output
Enable Mux
2
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
The AND array consists of 20 product terms, which can produce the logical product of any of the 18 GLB inputs. 16
of the inputs come from the Global Routing Pool, and are either feedback signals from any of the GLBs or inputs
from the external I/O cells. The two remaining inputs come directly from two dedicated input pins. These signals
are available to the product terms in both the logical true and the complemented forms which makes Boolean logic
reduction more efficient.
The PTSA takes the 20 product terms and routes them to the four GLB outputs. There are four OR gates, with four,
four, five and seven product terms each (Figure 2). The output of any of these OR gates can be routed to any of the
four GLB outputs, and if more product terms are needed, the PTSA can combine them as necessary. In addition,
the PTSA can share product terms similar to an FPLA device. If the user's main concern is speed, the PTSA can
use a bypass circuit which provides four product terms to each output, to increase the performance of the cell
(Figure 3). This can be done to any or all of the four outputs from the GLB.
Figure 3. GLB: Four Product Term Bypass Example
Inputs From
Global Routing Pool
0
1
2
3
4
5
6
7
8
Dedicated
Inputs
9 10 11 12 13 14 15 16 17
Product Term Sharing
Array (Four Product Term
Bypass Shown)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
AND Array
D Registers
4
DQ
M
U
X
O3
DQ
M
U
X
O2
DQ
M
U
X
To
Global
Routing
Pool and
Output
Routing
O1 Pool
DQ
M
U
X
O0
4
4
4
PT Reset
Global RESET
Control
Functions
CLK 0
CLK 1
CLK 2
PT Clock
PT Output
Enable
MUX
MUX
To Output
Enable Mux
0131A/1K
The Reconfigurable Registers consist of four D-type flip-flops with an XOR gate on the input. The XOR gate in the
GLB can be used either as a logic element or to reconfigure the D-type flip-flop to emulate a J-K or T-type flip-flop
(see Figure 4). This greatly simplifies the design of counters, comparators and ALU type functions. The registers
can be bypassed if the user needs a combinatorial output. Each register output is brought back into the Global
Routing Pool and is also brought to the I/O cells via the Output Routing Pool. Reconfigurable registers are not available when the four product term bypass is used.
The PTSA is flexible enough to allow these features to be used in virtually any combination that the user desires. In
the GLB shown in Figure 5, Output Three (O3) is configured using the XOR gate while Output Two (O2) is configured using the four Product Term Bypass. Output One (O1) uses one of the inputs from the five Product Term OR
gate while Output Zero (O0) combines the remaining four product terms with all of the product terms from the
seven Product Term OR gate for a total of 11 (7+4).
3
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Figure 4. GLB: XOR Gate Example
Inputs From
Global Routing Pool
0
1
2
3
4
5
6
7
8
Dedicated
Inputs
Product Term Sharing
Array (XOR
Configuration Shown)
9 10 11 12 13 14 15 16 17
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
D Registers
3
3
DQ
M
U
X
DQ
M
U
X
DQ
M
U
X
DQ
M
U
X
4
6
O3
To
O2 Global
Routing
Pool and
Output
Routing
O1
Pool
O0
AND Array
PT Reset
Global RESET
Control
Functions
CLK 0
CLK 1
CLK 2
PT Clock
MUX
MUX
PT Output
Enable
To Output
Enable Mux
Figure 5. GLB: Mixed Mode Configuration Example
Inputs From
Global Routing Pool
0
1
2
3
4
5
6
7
8
Dedicated
Inputs
Product Term
Sharing Array
9 10 11 12 13 14 15 16 17
D Registers
3 + 4 (Shared)
PTs and XOR
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
3
4
4 PT Bypass
M
U
X
D Q
M
U
X
D Q
M
U
X
To
O2 Global
Routing
Pool and
Output
Routing
O1 Pool
D Q
M
U
X
O0
Single PT
4
7
D Q
7 + 4 (Shared)
PTs
O3
AND Array
PT Reset
Global RESET
Control
Functions
CLK 0
CLK 1
CLK 2
PT Clock
MUX
PT Output
Enable
MUX
To Output
Enable Mux
Various signals that control the operation of the GLB outputs are driven from the Control Functions (Figure 5). The
clock for the registers can come from any of three sources developed in the Clock Distribution Network (see Clock
Distribution Network section) or from a product term within the GLB. The Reset Signal for the GLB can come from
the Global Reset pin (RESET) or from a product term within the GLB. The global reset pin is always connected and
is logically "ORed" with the PT reset (if used). An active reset signal always sets the Q of the registers to a logic 0
state. The Output Enable for the I/O cells associated with the GLB comes from a product term within the block. Use
4
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
of a product term for a control function makes that product term unavailable for use as a logic term. Refer to the
Product Term Sharing Matrix (Table 1) to determine which logic functions are affected.
There are many additional features in a GLB that allow implementation of logic intensive functions. These features
are accessible using the hard macros from the software and require no intervention on the part of the user.
Table 1. Product Term Sharing Matrix
Product Standard Configuration
Four Product Term
Single Product Term
Term #
Output Number
Bypass Output Number
Output Number
3
2
1
0
3
2
1
0
3
2
1
0
XOR Function
Output Number
3
3
2
2
1
1
Alternate
Function
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK/Reset
13
14
15
16
17
18
19
OE/Reset
Product Term Sharing Matrix
This matrix describes how each of the product terms are used in the various modes. For example, Product Term 12
can be used as an input to the five input OR gate in the standard configuration. This OR gate under standard configuration can be routed to any of the four GLB outputs. Product Term 12 is not used in the four product term
bypass mode. When GLB output one is used in the XOR mode, Product Term 12 becomes one of the inputs to the
four input OR Gate. If Product Term 12 is not used in the logic, then it is available for use as either the Asynchronous Clock signal or the GLB Reset signal.
The Megablock
A Megablock consists of eight GLBs, an ORP, 16 I/O cells, two dedicated inputs and a common product term OE.
These elements are coupled together as shown in Figure 6. The various members of the ispLSI 1000EA family
combine from one to six Megablocks on a single device (Table 2).
For the ispLSI 1000EA family, the eight GLBs within the Megablock share two dedicated input pins. These dedicated input pins are not available to GLBs in any other Megablock. The pins are dedicated (non-registered) inputs
only. The product term OE signal is generated within the Megablock. The OE signal can be generated using a product term (PT19) in any of eight GLBs within the Megablock. See Output Enable Control section for further details.
Because of the shared logic within the Megablock, signals that share a common function (counters, busses, etc.)
should be grouped within a Megablock. This will allow the user to obtain the best utilization of the logic within the
device and eliminate routing bottlenecks.
5
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Table 2. Device Resources
ispLSI Device
Megablocks
GLBs
I/O Cells
Dedicated Inputs
1010EA
2
16
32
1
1024EA
3
24
48
2
1032EA
4
32
64
4
1048EA
6
48
96
8
Input Routing
Signal inputs are handled in two ways within the device. First, each I/O cell within the device has its input routed
directly to the GRP. This gives every GLB within the device access to each I/O cell input. Second, each Megablock
has two dedicated inputs which are directly routed to the eight GLBs within the Megablock. Both input paths are
shown in Figure 6.
Figure 6. The Megablock Block Diagram
Global Routing Pool
16
16
GLB
D0
16
GLB
D1
16
GLB
D2
16
GLB
D3
16
GLB
D4
16
GLB
D5
16
GLB
D6
16
GLB
D7
Output Routing Pool
I/O Cell Inputs to GRP
IN
6
IN
7
I/O
Cell
0
I/O
Cell
1
I/O
Cell
2
I/O
Cell
3
I/O
Cell
4
I/O
Cell
5
I/O
Cell
6
I/O
Cell
7
I/O
Cell
8
I/O
Cell
9
I/O
Cell
10
I/O
Cell
11
I/O
Cell
12
I/O
Cell
13
I/O
Cell
14
I/O
Cell
15
The Output Routing Pool
The ORP routes signals from the GLB outputs to I/O cells configured as outputs or bidirectional pins (Figure 7).
The purpose of the ORP is to allow greater flexibility when assigning I/O pins. It also simplifies the job for the routing software which results in a higher degree of utilization.
Figure 7. Output Routing Pool
A0
0 1 2 3
A1
0 1 2 3
A2
0 1 2 3
A3
0 1 2 3
A4
0 1 2 3
A5
0 1 2 3
A6
0 1 2 3
A7
0 1 2 3
I/O Cell Inputs
to GRP
16
ORP
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
6
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
By examining the ORP in Figure 7, it can be seen that a GLB output can be connected to one of four I/O cells. Further flexibility is provided by using the PTSA (Figures 2 through 5) which makes the GLB outputs completely interchangeable. This allows the routing program to freely interchange the outputs to achieve the best routability. This is
an automatic process and requires no intervention on the part of the user.
The ORP bypass connections (Figure 8) further increase the flexibility of the device. The ORP bypass connects
specific GLB outputs to specific I/O cells at a faster speed. The bypass path tends to restrict the routability of the
device and should only be used for critical signals.
Figure 8. Output Routing Pool Showing Bypass
A0
0 1 2 3
A1
0 1 2 3
A2
0 1 2 3
A3
0 1 2 3
A4
0 1 2 3
A5
0 1 2 3
A6
0 1 2 3
A7
0 1 2 3
I/O Cell Inputs
to GRP
16
ORP
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O Cell
The I/O cell (Figure 9) is used to route input, output or bidirectional signals connected to the I/O pin. One logic input
comes from the ORP, and the other comes from the faster ORP bypass. A pair of multiplexers select which signal
will be used, and its polarity.
Figure 9. I/O Cell Architecture
GOE0
GOE1*
MUX
MUX
Product Term OE
VCCIO
Output
Enable
Active
Pull Up
From Output
Routing Pool
From Output
Routing Pool
Bypass
MUX
MUX
Slow
Slew
Open
Drain
I/O Pin
5V/3.3V
VCCIO
To Global
Routing Pool
MUX
D Q
IOCLK 0
MUX
MUX
R/L
Reset
IOCLK 1
Notes:
From Global
RESET
Represents an E2CMOS Cell.
* Not Available on ispLSI 1016EA
7
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Figure 10. Examples of I/O Cell Configurations
Pin
Bi-Directional
I/O Pin
Pin
Input Buffer
I/O Pin
Output Buffer
D Q
Pin
I/O Cell
Clock
Pin
LE
Bi-Directional
I/O Pin With
Registered Input
Inverting Output Buffer
Latch Input
I/O Pin
D Q
Pin
D Q
Pin
I/O Cell
Clock
Output Buffer with
3-State Enable
I/O Cell
Clock
Registered Input
Input Cells
Output Cells
Bi-Directional Cells
The Output Enable can be set to a logic high (enabled) when an output pin is desired, or logic low (disabled) when
an input pin is needed. The Global Reset (RESET) signal is driven by the active low chip reset pin. The Global
Reset pin is always connected to all GLB and I/O registers. Each I/O cell can individually select one of the two clock
signals (IOCLK 0 or IOCLK 1). The clock signals are generated by the Clock Distribution Network.
Using the multiplexers, the I/O cell can be configured as an input, an output, a tristated output or a bidirectional I/O.
The D-type register can be configured as a level sensitive transparent latch or an edge triggered flip-flop to store
the incoming data. Figure 10 illustrates some of the various I/O cell configurations possible.
In addition to the standard totem-pole output configuration, each output can be programmed as an open-drain output. The totem-pole output drives the specified VOH and VOL levels, whereas the open-drain output drives only the
specified VOL. The VOH level on the open-drain output depends on the external loading and pull-up resistance. The
default configuration for the output driver is the totem-pole configuration.
Each output can be programmed independently with a slow or fast slew rate. In order to minimize output switching
noise, the slow slew option should be used. The default slew rate for all output pins is fast slew.
A VCCIO pin is available which must be connected to a common 5V or 3.3V power supply so the output levels can
be matched to 5V or 3.3V compatible voltages. VCCIO is common to all the I/O cells and the user applied VCCIO
voltage on the pin determines the I/O voltage reference for the entire device. When VCCIO is set to 3.3V, the output
can source 2mA and sink 8mA. When VCCIO is set to 5V, the outputs can source 4mA and sink 8mA.
An active pull-up resistor is available on all the I/O pins connected to VCCIO. If an I/O pin is not being used in a functional design, the pull-up will automatically be used in order to hold the I/O cell at VCCIO. Noise immunity can be
improved by having all the active pull-ups on the I/O pins being programmed on. Each I/O pin that is used functionally in the design can be configured with the pull-up on or off.
Output Enable Control
The product term OE signal produced in each Megablock is available to all I/O cells in the Megablock that produced
the signal. This product term OE bus allows more flexibility for bi-directional or tri-state control. An optional Global
Output Enable (GOE) is provided on each of the 1000EA devices. The GOE provides minimum delay output enable
control and additional OE signal choices to the OE MUX. On the 1016EA and 1032EA devices, the GOE is multiplexed with dedicated inputs.
8
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Figure 11. Output Enable Control for a Megablock
GLB
A0
GLB
A1
GLB
A2
GLB
A3
GLB
A4
GLB
A5
GLB
A6
GLB
A7
8:1 OE MUX
PTOEs
From Other
Megablocks
GOE0
To Other
I/O Cells
GOE1*
MUX
MUX
MUX
MUX
MUX
•
Portion
of I/O
Cell 0
•
MUX
•
MUX
Portion
of I/O
Cell 1
MUX
Portion
of I/O
Cell 14
Portion
of I/O
Cell 15
I/O Pin
I/O Pin
I/O Pin
I/O Pin
0134/1K
*Not available on ispLSI 1016E.
Global Routing Pool
The GRP is a proprietary interconnect structure that offers fast predictable speeds with complete connectivity. The
GRP allows the outputs from the GLBs or the I/O cell inputs to be connected to the inputs of the GLBs. Any GLB
output is available to the input of all other GLBs, and similarly an input from an I/O pin is available as an input to all
of the GLBs. Because of the uniform architecture of the ispLSI devices, the delays through the GRP are both consistent and predictable. However, they are slightly affected by GLB loading. See individual ispLSI 1000EA device
data sheets for specific GLB loading delays. Delays through the GRP have been equalized to minimize timing
skew.
Clock Distribution Network
The Clock Distribution Networks are shown in Figure 12. They generate five global clock signals CLK 0, CLK 1,
CLK 2 , IOCLK 0 and IOCLK 1. The first three, CLK 0, CLK 1 and CLK 2 may be used for clocking all the GLBs in
the device. Similarly, IOCLK 0 and IOCLK 1 signals are used for clocking all of the I/O cells in the device. There are
four dedicated system clock pins (Y0, Y1, Y2, Y3) (two for the ispLSI 1016EA (Y0, Y1)), which can be directed to
any GLB or any I/O cell using the Clock Distribution Network. The other inputs to the Clock Distribution Network are
the four outputs of a dedicated clock GLB ("C0" for the ispLSI 1032EA is shown in Figure 1). These clock GLB outputs can be used to create a user-defined internal clocking scheme.
9
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Figure 12. Clock Distribution Networks
ispLSI 1024EA,
1032EA and 1048EA
Generic Logic
Block "C0"
O0 O1 O2 O3
ispLSI 1016EA
Generic Logic
Block “B0”
O0 O1 O2 O3
Clock Distribution
Network
Clock Distribution
Network
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Y0 Y1*
CLK/
Reset
Y0 Y1 Y2 Y3
Dedicated Clock
Input Pins
Dedicated Clock
Input Pins
*Note: Pin Y1 has the Clock and
Reset functions multiplexed
on the ispLSI 1016EA;
selection is controlled in
the software tools.
For example, the clock GLB can be clocked using the external main clock pin Y0 connected to global clock signal
CLK 0. The outputs of the clock GLB in turn can generate a "divide by" signal of the CLK 0 which can be connected
to the CLK 1, CLK 2, IOCLK 0 or IOCLK 1 global clock lines.
All GLBs have the capability of generating their own asynchronous clocks using the clock Product Term (PT12).
CLK 0, CLK 1 and CLK 2 feed to their corresponding clock MUX inputs on all the GLBs (Figure 2).
The two I/O clocks generated in the Clock Distribution Network IOCLK 0 and IOCLK 1, are brought to all the I/O
cells and the user programs the I/O cell to use one of the two.
Boundary Scan and ISP
ISP programming of the device is performed via IEEE1149.1 compliant JTAG state machine. The programming signals are driven on the standard Test Access Port (TAP) interface. The four wire interface includes Test Data In
(TDI), Test Clock (TCK), Test Mode Select (TMS), and Test Data Out (TDO). ISP program enable and disable is
controlled by the private programming instruction set.
In addition to ISP programming, the JTAG state machine also provides standard boundary scan test capability.
Standard boundary scan instructions supported are Sample/Preload, Extest, Bypass and High-Z instructions. The
boundary scan test registers associated with each of the I/O pins control the state of the I/O pin when the device is
not in normal functional mode. This feature allows users to define the state of the I/O pins during test and ISP programming modes.
10
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Figure 13. Boundary Scan Register for I/O Pins
HIGHZ
SCANIN
(from previous
cell)
BSCAN
Registers
D
BSCAN
Latches
Q
D
Normal
Function
OE
Q
0
1
EXTEST
PROG_MODE
Normal
Function
Shift DR
D
Q
D
Q
Clock DR
D
Q
0
I/O Pin
1
SCANOUT
(to next cell)
Update DR
Reset
Figure 14. Boundary Scan Register for Dedicated Input Pins
Input Pin
SCANIN
(from previous
cell)
D
Q
SCANOUT
(to next cell)
Shift DR
Clock DR
Timing Model
The task of determining the timing through the device is simple and straightforward. A device timing model is
shown in Figure 15. To determine the time that it takes for data to propagate through the device, simply determine
the path the data is expected to follow, and add the various delays together (Figure 16). Critical timing paths are
shown in Figure 16, using data sheet parameters. Note that the internal timing parameters are given for reference
only, and are not tested. External timing parameters are tested and guaranteed on every device.
11
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Figure 15. ispLSI 1000EA Timing Model
I/O Cell
GRP
GLB
#47
Ded. In
I/O Pin
(Input)
#60
ORP
I/O Cell
Feedback
#34
#28
Comb 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#22
#30
#35
#39
#49
Input
D Register Q
RST
#23 - 27
GRP Loading
Delay
20 PT
XOR Delays
GLB Reg
Delay
ORP
Delay
#29, 31 - 33
#36 - 38
I/O Reg Bypass
GRP4
Reg 4 PT Bypass
D
Q
#50, 51
#52, 53
#48
RST
#60
Reset
Clock
Distribution
Y1,2,3*
#40 - 43
Control RE
PTs
OE
#44 - 46 CK
#56 - 59
0491/1KEA
#55
Y0
#54
GOE 0,1*
*Note: Y1, Y2 and GOE0 only for the ispLSI 1016EA.
Figure 16. ispLSI Timing Model Examples*
Combinatorial Paths
+
+
tgrp4
+
+
tgrp4
tsu = Logic
+
th = Clock(max) +
tco = Clock(max) +
Regsu
Regh
Regco
- Clock(min)
Logic
+
Output
tgrp4
+
+
t4ptbp )
+
(tiobp
+
+
(torpbp
+
+
txoradj)
+
(tiobp
+
+
(torp
tpd1
#1
=
=
tiobp
#22
= tiobp
#2
=
#22
Registered Paths
tpd2
#30
#30
+
+
t4ptbp
#35
+
#39
+
+
txoradj
+
+
t20ptxor
+
+
tgsu
+
+
tgrp4
+
+
tob)
+
+
tgsu
+
+
tgrp4
+
+
tob)
#50,51
#38
+ t20ptxor
#39
+
+
torpbp
+
+
torp
+
tgy0(min)
+
+
t4ptbp)
+
+
tgy0(min)
+
+
txoradj)
#49
#48
General Form:
Specific Examples:
tsu1 = (tiobp
#6
=
#22
+
+
#30
th1 = tgy0(max) +
tgh
#8
+
#41
tco1 = tgy0(max) +
tgco
#7
+
#42
+
+
tgrp4
=
=
#55
#55
tsu2 = (tiobp
#9
=
#22
#30
th2 = tgy0(max) +
tgh
#11 =
+
#41
tco2 = tgy0(max) +
tgco
#10 =
#42
#55
#55
+
#35
#22
#49
#38
#22
#48
#40
#30
#55
#35
#50
#40
#30
#55
#38
*The timing parameter reference numbers refer to the internal timing parameters contained in
the individual data sheets.
12
tob
+
+
#50,51
+
+
tob
#50,51
I/O Pin
(Output)
Lattice Semiconductor
ispLSI 1000EA Family Architectural Description
Circuit Timing Example
A design requires one logic level (using the 20PTXOR path). The design then uses a GLB register before exiting
the device using the ORP bypass. Calculate tSU, tH and tCO.
Figure 17. Timing Calculation Example
Logic Level
20PTXOR
IN
GLB Reg
ORP
Bypass
Out
Clock GLB
Reg
Y0
tsu
=
=
=
0.8 ns =
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #57)
(0.3 + 1.5 + 1.9) + (0.2) – (0.9 + 1.4 + 0.8)
th
=
=
=
1.4 ns =
Clock (max) + Reg h - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#55 + #42 + #57) + (#41) – (#22 + #30 + #37)
(0.9 + 1.4 + 1.8) + (1.0) – (0.3 + 1.5 + 1.9)
tco
7.2 ns
=
=
=
=
Clock (max) + Reg co + ut put
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)
Note: Calculations are based upon timing specifications for the ispLSI 1032EA-200 device.
13