E X P A N D E D Non-Volatile Instant-On Infinitely Reconfigurable P R O G R A M M A B L E L O G I C D E V I C E S ispXPLD 5000MX Ultimate ispXP™ Flexibility The ispXPLD™ 5000MX family represents a new class of devices from Lattice Semiconductor called eXpanded Programmable Logic Devices (XPLDs). These devices are built around a new building block, the Multi-Function Block (MFB). These blocks can be configured as SuperWIDE™ (136-input) logic, single- or dual-port memory, FIFO, or CAM depending on the user’s application. This unparalleled PLD flexibility is combined with sysIO™ interfaces for support of leading edge standards such as LVDS, HSTL, and SSTL, along with the more familiar LVCMOS standards. sysCLOCK™ PLLs allow easy clock management. ispXPLD 5000MX devices provide expanded in-system programming referred to as ispXP. As such, ispXPLD devices are non-volatile and infinitely reconfigurable. They can be programmed through an industry standard IEEE 1532 interface or reconfigured through the Lattice sysCONFIG™ interface. Devices are available to support 3.3, 2.5, and 1.8-volt power supply operation. Key Features and Benefits ■ Flexible MFB Architecture • SuperWIDE Logic • Arithmetic support • Single- or Dual-Port RAM • Asynchronous FIFO • Ternary CAM Flexibility ispXPLD 5256MX Block Diagram Multi Function Blocks (MFBs) are independently programmable as logic, single- or dual-port memory, FIFO, or CAM Global Routing Pool (GRP) provides flexible, deterministic routing I/O Bank 0 sysIO sysIO sysIO sysCLOCK PLLs • Multiply & divide • Clock shifting ■ sysIO Interfaces • LVTTL, LVCMOS 1.8, 2.5, 3.3: Programmable drive strength; Flexible bus-maintenance; Hot-socketing • SSTL, HSTL • GTL+, PCI-X, PCI 3.3, AGP-1X • LVDS • LVPECL ■ Expanded In-System Programming (ispXP) • Instant-on capability • Single chip convenience • ISP™ via IEEE 1532 Interface • Infinitely reconfigurable via IEEE 1532 or sysCONFIG interface • Security scheme ■ High Speed Operation • 4.0ns pin-to-pin delays • 300 MHz fMAX • Deterministic timing ■ Low Power Consumption • Static power as low as 20mA • 1.8-volt core for low dynamic power ■ Easy System Integration • 3.3, 2.5 and 1.8-volt power supply operation • IEEE 1149.1 boundary scan testing • Lead-free package options I/O Bank 3 MFB MFB MFB MFB sysCLOCK PLL sysIO ■ Global Routing Pool sysIO sysCLOCK PLL MFB MFB MFB I/O Bank an a n 1 sysIO MFB ISP Port sysIO sysIO I/O Bank 2 sysCLOCK PLLs sysIO for ultra high speed I/Os ISP Port offers non-volatile, In-system programmability, and reconfigurability via sysCONFIG interface ispXPLD 5000MX Architecture Multi-Function Block MFB • Highly Flexible Architecture – Each MFB can be independently configured as SuperWIDE Logic, single- or dual-port RAM, FIFO, or CAM sysIO Interfaces sysCLOCK PLL for Timing Control •On-board sysIO Banks allow ispXPLD 5000MX devices to support a wide range of I/O standards • Each sysIO Bank has its own separate I/O supply voltage and reference voltage • 2 sysCLOCK PLLs per device • 10 to 320 MHz PLL operation • ±100ps cycle-to-cycle jitter • ±150ps period jitter • ±300ps input jitter Synchronous DRAM PLL_Lock Clock Chip CLK_Out GCLK_IN PLL_RST Input Clock (M) Divider ÷ 1 to 32 Programmable +Delay PLL (n) Programmable –Delay Feedback Divider (N) X 1 to 32 Post-scalar (V) Divider ÷ 1,2,4,8,16,32 Clock Net Secondary (K) Divider ÷ Clock Net 2,4,8,16,32 SEC_Out Logic CTT LVTTL LVCMOS LVDS LVPECL LVTTL LVCMOS SSTL LVTTL LVCMOS (Logic, ASICs, CPU, DSP) ispXPLD 5000MX PLL_FBK with sysIO High-Speed Backplane LVDS LVPECL GTL+ PCI PCI-X AGP HSTL LVTTL LVCMOS High-Speed SRAM ispXPLD 5000MX Features Low Power SuperWIDE Architecture • 70% reduction in power consumption (@ 100MHz) • Low static power – zero power E2 cells, full CMOS design • Low power benefits: improved reliability, smaller power supplies, less cooling required • 68-input logic block implements complex functions in one logic level • Two MFBs (Multi-Function Blocks) can be combined to support up to 136 inputs! Traditional Complex Functions in 2 Logic Levels Lattice SuperWIDE Complex Functions in 1 Logic Level 750 mA Traditional 2.5V CPLD 36-Input Logic Block 500 mA 70% Lower Power Current Lattice 68-Input Logic Block 250 mA 36-Input Logic Block 36-Input Logic Block Lattice 2.5V ispXPLD 5000MB 0 100 MHz 200 MHz 300 MHz Frequency 1X Delay 2X Delay Note: Power consumption of 512 macrocell device ispXPLD 5000MX Applications ispXP, sysIO, sysCLOCK, SINGLE- OR D U A L - P O RT R A M , FIFO , C AM , AND P R O G R A M M A B L E LO G IC AL L I N O N E P A C K A G E . THE ispXPLD 5000MX OFFERS The ispXPLD 5000MX Family is an excellent solution for bus bridging applications. ispXPLD 5000MX features include: • Instant-on • High performance – 4.0ns pin-to-pin delay • sysIO interfaces for high-speed I/Os • sysCLOCK PLLs for easy timing control • Memory for buffering SONET Link Layer to PHY SONET PHY Layer (Internal) Switch Fabric Interface Memory Interface ispXPLD 5000MX Storage Area Network Interfaces PDH ATM Ethernet T HE U LT I M AT E I N L O G I C DE S I G N F L E X I B I L I T Y. ispXPLD 5000MV, 5000MB and 5000MC Family Attributes* Family Member ispXPLD 5256MV ispXPLD 5512MV ispXPLD 5768MV ispXPLD 51024MV ispXPLD 5256MB ispXPLD 5512MB ispXPLD 5768MB ispXPLD 51024MB ispXPLD 5256MC ispXPLD 5512MC ispXPLD 5768MC ispXPLD 51024MC System Gates Macrocells Memory kbit CAM kbit PLLs tPD tS tCO FMAX Vcc 75K 256 128 48 2 4.0ns 2.2ns 2.8ns 300MHz 3.3V 150K 512 256 96 2 4.5ns 2.8ns 3.0ns 270MHz 3.3V 225K 768 384 144 2 5.0ns 2.8ns 3.2ns 250MHz 3.3V 300K 1024 512 192 2 5.2ns 3.0ns 3.7ns 250MHz 3.3V 75K 256 128 48 2 4.0ns 2.2ns 2.8ns 300MHz 2.5V 150K 512 256 96 2 4.5ns 2.8ns 3.0ns 270MHz 2.5V 225K 768 384 144 2 5.0ns 2.8ns 3.2ns 250MHz 2.5V 300K 1024 512 192 2 5.2ns 3.0ns 3.7ns 250MHz 2.5V 75K 256 128 48 2 4.0ns 2.2ns 2.8ns 300MHz 1.8V 150K 512 256 96 2 4.5ns 2.8ns 3.0ns 270MHz 1.8V 225K 768 384 144 2 5.0ns 2.8ns 3.2ns 250MHz 1.8V 300K 1024 512 192 2 5.2ns 3.0ns 3.7ns 250MHz 1.8V ispXPLD 5000MX Family Package Options and Available I/Os Family Member ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX ispXPLD 51024MX 208 PQFP 256 fpBGA* 484 fpBGA* 672 fpBGA* – – 141 – 149 193 253 – – 193 317 – – – 317 381 * fpBGA = Fine Pitch BGA (1.0mm ball pitch) ispXPLD 5000MX Advanced Packaging Packages are shown actual size. Dimensions refer to package body size. Applications Support 1-800-LATTICE (528-8423) (408) 826-6002 [email protected] www.latticesemi.com Copyright © 2004 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ISP, sysCONFIG, sysIO, sysCLOCK, SuperWIDE, ispXP, and ispXPLD are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. January 2004 Order #: I0140B