Si2308BDS-DS

SPICE Device Model Si2308BDS
www.vishay.com
Vishay Siliconix
N-Channel 60 V (D-S) MOSFET
DESCRIPTION
CHARACTERISTICS
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
subcircuit model is extracted and optimized over the -55 °C
to +125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used
to model the gate charge characteristics while avoiding
convergence difficulties of the switched Cgd model. All
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the -55 °C to +125 °C Temperature Range
• Model the Gate Charge
SUBCIRCUIT MODEL SCHEMATIC
D
R1
3
M2
Gx
G
RG
CGS
DBD
M1
S
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
S14-1396-Rev. B, 14-Jul-14
Document Number: 68124
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPICE Device Model Si2308BDS
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SIMULATED MEASURED
DATA
DATA
SYMBOL
TEST CONDITIONS
VGS(th)
VDS = VGS, ID = 250 μA
1.9
-
VGS = 10 V, ID = 1.9 A
0.126
0.130
VGS = 4.5 V, ID = 1.7 A
0.159
0.160
UNIT
Static
Gate Threshold Voltage
Drain-Source On-State Resistance a
RDS(on)
V
Ω
Forward Transconductance a
gfs
VDS = 15 V, ID = 1.9 A
4.2
5
S
Body Diode Voltage
VSD
IS = 1.5 A
0.78
0.80
V
189
190
27
26
11
15
3.6
4.5
Dynamic b
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
VDS = 30 V, VGS = 0 V, f = 1 MHz
VDS = 30 V, VGS = 10 V, ID = 1.9 A
VDS = 30 V, VGS = 4.5 V, ID = 1.9 A
2
2.3
0.80
0.80
1.1
1
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
S14-1396-Rev. B, 14-Jul-14
Document Number: 68124
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SPICE Device Model Si2308BDS
www.vishay.com
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted)
Note
• Dots and squares represent measured data.
Copyright: Vishay Intertechnology, Inc.
S14-1396-Rev. B, 14-Jul-14
Document Number: 68124
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Revision: 02-Oct-12
1
Document Number: 91000