ISL6420A ® Data Sheet October 13, 2005 FN9169.1 Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller Features The ISL6420A simplifies the implementation of a complete control and protection scheme for a high-performance DC/DC buck converter. It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology, the ISL6420A integrates control, output adjustment, monitoring and protection functions into a single package. Additionally, the IC features an external reference voltage tracking mode for externally referenced buck converter applications and DDR termination supplies, as well as a voltage margining mode for system testing in networking DC/DC converter applications. • Excellent Output Voltage Regulation - 0.6V Internal Reference - ±1.0% Reference Accuracy Over Line and Temperature The ISL6420A provides simple, single feedback loop, voltage mode control with fast transient response. The output voltage of the converter can be precisely regulated to as low as 0.6V, with a maximum tolerance of ±1.0% over temperature and line voltage variations. The operating frequency is fully adjustable from 100kHz to 1.4MHz. High frequency operation offers cost and space savings. The error amplifier features a 15MHz gain-bandwidth product and 6V/µs slew rate that enables high converter bandwidth for fast transient response. The PWM duty cycle ranges from 0% to 100% in transient conditions. Selecting the capacitor value from the ENSS pin to ground sets a fully adjustable PWM soft-start. Pulling the ENSS pin LOW disables the controller. The ISL6420A monitors the output voltage and generates a PGOOD (power good) signal when soft-start sequence is complete and the output is within regulation. A built-in overvoltage protection circuit prevents the output voltage from going above typically 115% of the set point. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit the PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sensing resistor. • Operates from 4.5V to 28V Input • Resistor-Selectable Switching Frequency - 100kHz to 1.4MHz • Voltage Margining and External Reference Tracking Modes • Output Can Sink or Source Current • Lossless, Programmable Overcurrent Protection - Uses Upper MOSFET’s rDS(ON) • Programmable Soft-Start • Drives N-Channel MOSFETs • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle • Extensive Circuit Protection Functions - PGOOD, Overvoltage, Overcurrent, Shutdown • Diode Emulation during Startup for Pre-Biased Load Applications • Offered in 20 Ld QFN and QSOP Packages • QFN (4x4) Package - QFN compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - QFN Near Chip Scale Package Footprint; Improves PCB Efficiency, Thinner in Profile • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Power Supplies for Microprocessors/ASICs - Embedded Controllers - DSP and Core Processors - DDR SDRAM Bus Termination • Ethernet Routers and Switchers • High-Power DC/DC Regulators • Distributed DC/DC Power Architecture • Personal Computer Peripherals • Externally Referenced Buck Converters 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL6420A Ordering Information PART MARKING PART NUMBER TEMP. RANGE (°C) PKG. DWG. # PACKAGE ISL6420AIAZ (Note) 6420AIAZ -40 to +85 20 Ld QSOP (Pb-free) M20.15 ISL6420AIAZ-TK (Note) 6420AIAZ -40 to +85 20 Ld QSOP (Pb-free) Tape and Reel M20.15 ISL6420AIRZ (Note) 6420AIRZ -40 to +85 20 Ld 4x4 QFN (Pb-free) L20.4x4 ISL6420AIRZ-TK (Note) 6420AIRZ -40 to +85 20 Ld 4x4 QFN (Pb-free) Tape and Reel L20.4x4 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts GPIO2 UGATE PHASE PVCC LGATE ISL6420A (QSOP) TOP VIEW BOOT ISL6420A (QFN) TOP VIEW 20 19 18 17 16 1 15 PGND GPIO1/REFIN 2 14 CDEL OCSET 3 13 PGOOD REFOUT 4 12 ENSS 6 7 8 9 10 SGND RT FB 11 COMP VIN 5 VCC5 VMSET/MODE 2 CDEL 1 PGND 2 19 ENSS LGATE 3 18 COMP 20 PGOOD PVCC 4 17 FB PHASE 5 16 RT UGATE 6 15 SGND BOOT 7 14 VIN GPIO2 8 13 VCC5 GPIO1/REFIN 9 12 VMSET/MODE OCSET 10 11 REFOUT FN9169.1 October 13, 2005 ISL6420A Functional Block Diagram VIN VCC5 OCSET SGND LDO OVERCURRENT COMP + OCFLT PHASE REFERENCE 0.6V SS + OVFLT UVFLT UGATE FAULT LOGIC PHASE ERROR AMP - FB BOOT + - COMP PHASE LOGIC PWM LOGIC PWM COMP PVCC GPIO1/REFIN LGATE RAMP GENERATOR GPIO2 REFOUT VOLTAGE MARGINING VMSET/MODE OV/UV VOLTAGE MONITOR FB PGND OVFLT PGOOD UVFLT OSC EN/SS RT ENSS CDEL Typical 5V Input DC/DC Application Schematic 5V C6 C1 C3 C2 PVCC VIN VCC5 D1 OCSET MONITOR AND PROTECTION ENSS Q1 PGOOD C8 C9 UGATE OSC R2 CDEL R1 BOOT RT C7 0.1µF C5 C4 L1 PHASE REF 3.3V SGND ++ -- FB R3 C11 COMP Q2 C10 PGND GPIO1/REFIN R6 R5 LGATE -+ + C12 REFOUT GPIO2 C13 R4 VMSET/MODE 3 FN9169.1 October 13, 2005 ISL6420A Typical 12V Input DC/DC Application Schematic 12V C6 C1 C3 C2 PVCC VIN VCC5 D1 OCSET MONITOR AND PROTECTION ENSS Q1 PGOOD R2 C9 UGATE OSC L1 PHASE CDEL C8 R1 BOOT RT C7 C5 C4 REF 3.3V SGND R3 C11 C10 PGND COMP GPIO1/REFIN R6 C12 R5 Q2 LGATE -+ + ++ -- FB REFOUT GPIO2 C13 R4 VMSET/MODE Typical 5V Input DC/DC Application Schematic 5V C6 C1 C3 C2 VIN PVCC C4 D1 VCC5 OCSET MONITOR AND PROTECTION SS/EN Q1 CDEL R2 R1 BOOT RT C7 C5 C8 UGATE OSC L1 PHASE PGOOD REF 2.5V/1.25V SGND R3 C10 C11 LGATE -+ + ++ -- FB C9 PGND COMP R5 Q2 GPIO1/REFIN <-- VREF = VDDQ/2 GPIO2 REFOUT C12 1.25V VREF TO REFIN OF VTT SUPPLY VMSET/MODE VCC5 R4 CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS 4 FN9169.1 October 13, 2005 ISL6420A Typical 12V Input DC/DC Application Schematic 12V C6 C1 C2 C3 VIN PVCC VCC5 MONITOR AND PROTECTION SS/EN RT C7 D1 OCSET R1 BOOT Q1 CDEL R2 C5 C4 UGATE OSC C8 L1 PHASE PGOOD REF 2.5V/1.25V VDDQ/VTT SGND R3 -+ + ++ -- FB C10 LGATE Q2 C9 PGND COMP GPIO1/REFIN <-- VREF = VDDQ/2 GPIO2 C11 R5 REFOUT C12 1.25V VREF TO REFIN OF VTT SUPPLY VMSET/MODE VCC5 R4 CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS 5 FN9169.1 October 13, 2005 ISL6420A Absolute Maximum Ratings (Note 1) Thermal Information Bias Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V BOOT and Ugate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36V ESD Classification Human Body Model (JESD22 - A114) . . . . . . . . . . . . . . . . . 2000V Charged Device Model (JESD22 - C101) . . . . . . . . . . . . . . 1000V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) QFN Package (Notes 2, 3). . . . . . . . . . 47 8.5 QSOP Package (Note 2) . . . . . . . . . . . 90 NA Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Ambient Temperature Range. . . . . . . . . -40°C to 85°C (for “I” suffix) Junction Temperature Range. . . . . . . . . . . . . . . . . . . -40°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. All voltages are with respect to GND. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Operating Conditions, Unless Otherwise Noted: VIN = 12V, PVCC shorted with VCC5, TA = 25°C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 5.6 12 28 V - 1.4 - mA - 2.0 3.0 mA VIN SUPPLY Input Voltage Range VIN SUPPLY CURRENT Shutdown Current (Note 4) ENSS = GND Operating Current (Notes 4, 5) VCC5 SUPPLY (Notes 5, 6) Input Voltage Range VIN = VCC5 for 5V configuration 4.5 5.0 5.5 V Output Voltage VIN = 5.6V to 28V, IL = 3mA to 50mA 4.5 5.0 5.5 V Maximum Output Current VIN = 12V 50 - - mA 4.310 4.400 4.475 V Falling VCC5 Threshold 4.090 4.100 4.250 V UVLO Threshold Hysteresis 0.16 - - V Min Output Voltage (Note 7) - 0.6 - V Max Output Voltage (Note 7) - VIN - 0.5 - V POWER-ON RESET Rising VCC5 Threshold VIN connected to VCC5, 5V input operation PWM CONVERTERS Maximum Duty Cycle F = 300kHz 90 96 - % Minimum Duty Cycle F = 300kHz - - 0 % - 80 - nA FB Pin Bias Current Undervoltage Protection VUV1 Fraction of the set point; ~3µs noise filter 75 - 85 % Overvoltage Protection VOVP1 Fraction of the set point; ~1µs noise filter 112 - 120 % Free Running Frequency RT = VCC5, TA = -40°C to 85°C 270 300 330 kHz Total Variation TA = -40°C to 85°C, with frequency set by external resistor at RT - ±10% - % Frequency Range (Set by RT) VIN = 12V 100 - 1400 kHz - 1.25 - VP-P OSCILLATOR ∆VOSC Ramp Amplitude (Note 7) 6 FN9169.1 October 13, 2005 ISL6420A Electrical Specifications Operating Conditions, Unless Otherwise Noted: VIN = 12V, PVCC shorted with VCC5, TA = 25°C (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 0.600 - V -1.0 - +1.0 % ISS - 10 - µA VSOFT 1.0 - - V - - 1.0 V - 0.7 - A REFERENCE AND SOFT-START/ENABLE Internal Reference Voltage VREF Reference Voltage Accuracy TA = -40°C to 85°C, VIN = 5.6V to 28V Soft-Start Current Soft-Start Threshold Enable Low (Converter disabled) PWM CONTROLLER GATE DRIVERS Gate Drive Peak Current Rise Time Co = 1000pF - 20 - ns Fall Time Co = 1000pF - 20 - ns - 20 - ns - 88 - dB GBW - 15 - MHz SR - 6 - V/µs 80 100 120 µA Dead Time Between Drivers ERROR AMPLIFIER DC Gain (Note 7) Gain-Bandwidth Product (Note 7) Slew Rate (Note 7) OVERCURRENT PROTECTION OCSET Current Source IOCSET VOCSET = 4.5V Dynamic Current Limit ON time TOCON Frequency = 300kHz - 20 - ms Dynamic Current Limit OFF time TOCOFF Frequency = 300kHz - 128 - ms POWER GOOD AND CONTROL FUNCTIONS Power-Good Lower Threshold VPG- Fraction of the set point; ~3µs noise filter -14 -10 -8 % Power-Good Higher Threshold VPG+ Fraction of the set point; ~3µs noise filter 9 - 16 % VPULLUP = 5.5V - - 1 µA PGOOD Voltage Low IPGOOD = 4mA - - 0.5 V PGOOD Delay CDEL = 0.1µF - 125 - ms CDEL Current for PGOOD CDEL threshold = 2.5V - 2 - µA - 2.5 - V PGOOD Leakage Current IPGLKG CDEL Threshold EXTERNAL REFERENCE MIn External Reference Input at GPIO1/REFIN. VMSET/MODE = H, CREFOUT = 2.2µF - 0.600 - V Max External Reference Input at GPIO1/REFIN. VMSET/MODE = H, CREFOUT = 2.2µF - - 1.250 V REFERENCE BUFFER Buffered Output Voltage - Internal Reference VREFOUT IREFOUT = 1mA, VMSET/MODE = High, CREFOUT = 2.2µF, TA = -40°C to 85°C 0.583 0.595 0.607 V Buffered Output Voltage - Internal Reference VREFOUT IREFOUT = 20mA, VMSET/MODE = High, CREFOUT = 2.2µF, TA = -40°C to 85°C 0.575 0.587 0.599 V Buffered Output Voltage - External Reference VREFOUT VREFIN = 1.25V, IREFOUT = 1mA, VMSET2/MODE = High, CREFOUT = 2.2µF 1.227 1.246 1.265 V 7 FN9169.1 October 13, 2005 ISL6420A Electrical Specifications Operating Conditions, Unless Otherwise Noted: VIN = 12V, PVCC shorted with VCC5, TA = 25°C (Continued) PARAMETER SYMBOL Buffered Output Voltage - External Reference VREFOUT TEST CONDITIONS VREFIN = 1.25V, IREFOUT = 20mA, VMSET2/MODE = High, CREFOUT = 2.2µF CREFOUT = 2.2µF Current Drive Capability MIN TYP MAX UNITS 1.219 1.238 1.257 V 20 - - mA -10 - +10 % - 100 - µA VOLTAGE MARGINING Voltage Margining Range (Note 7) CDEL Current for Voltage Margining Slew Time CDEL = 0.1µF, VMSET = 330kΩ - 2.5 - ms ISET1 on FB Pin VMSET = 330K, GPIO1 = L GPIO2 = H - 7.48 - µA ISET2 on FB Pin VMSET = 330K, GPIO1 = H GPIO2 = L - 7.48 - µA Shutdown Temperature (Note 7) - 150 - °C Thermal Shutdown Hysteresis (Note 7) - 20 - °C THERMAL SHUTDOWN NOTES: 4. The operating supply current and shutdown current specifications for 5V input are the same as VIN supply current specifications, i.e., 5.6V to 28V input conditions. These should also be tested with part configured for 5V input configuration, i.e., VIN = VCC5 = PVCC = 5V. 5. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current. 6. When the input voltage is 5.6V to 28V at VIN pin, the VCC5 pin provides a 5V output capable of 50mA (max) total from the internal LDO. When the input voltage is 5V, VCC5 pin will be used as a 5V input, the internal LDO regulator is disabled and the VIN must be connected to the VCC5. In both cases the PVCC pin should always be connected to VCC5 pin. (Refer to the Pin Descriptions sections for more details.) 7. Guaranteed by design. Not production tested. 0.604 320 0.602 310 VSW (kHz) VREF (V) Typical Performance Curves 0.600 0.598 0.596 0.594 -40 300 290 280 -15 10 35 TEMPERATURE (°C) FIGURE 1. VREF vs TEMPERATURE 8 60 85 270 -40 -15 10 35 TEMPERATURE (°C) 60 85 FIGURE 2. VSW vs TEMPERATURE FN9169.1 October 13, 2005 ISL6420A Typical Performance Curves (Continued) 94.00 92.00 EFFICIENCY (%) 1.05 0.95 IOUT = 5A 90.00 88.00 86.00 84.00 82.00 0.85 -40 80.00 -15 10 35 TEMPERATURE (°C) 60 85 0 10 5 15 20 25 30 VIN (V) FIGURE 3. IOCSET vs TEMPERATURE FIGURE 4. EFFICIENCY vs VIN 25°C, VIN = 28V, IIN = 1.367, IOUT = 10A FIGURE 5. FIGURE 6. 98 VIN = 5V 96 94 EFFICIENCY (%) IOCSET NORMALIZED 1.15 VIN = 12V 92 90 88 86 84 82 80 0 1 2 3 4 5 6 LOAD (A) 7 8 9 10 FIGURE 7. EFFICIENCY vs LOAD CURRENT (VOUT = 3.3V) 9 FN9169.1 October 13, 2005 ISL6420A VIN - This pin powers the controller and must be decoupled to ground using a ceramic capacitor as close as possible to the VIN pin. TABLE 1. INPUT SUPPLY CONFIGURATION INPUT PIN CONFIGURATION 5.6V to 28V Connect the input to the VIN pin. The VCC5 pin will provide a 5V output from the internal LDO. Connect PVCC to VCC5. 5V ±10% Connect the input to the VCC5 pin. Connect the PVCC and VIN pins to VCC5. SGND - This pin provides the signal ground for the IC. Tie this pin to the ground plane through the lowest impedance connection. LGATE - This pin provides the PWM-controlled gate drive for the lower MOSFET. PHASE - This pin is the junction point of the output filter inductor, the upper MOSFET source and the lower MOSFET drain. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection. This pin also provides a return path for the upper gate drive. UGATE - This pin provides the PWM-controlled gate drive for the upper MOSFET. BOOT - This pin powers the upper MOSFET driver. Connect this pin to the junction of the bootstrap capacitor and the cathode of the bootstrap diode. The anode of the bootstrap diode is connected to the VCC5 pin. FB - This pin is connected to the feedback resistor divider and provides the voltage feedback signal for the controller. This pin sets the output voltage of the converter. COMP - This pin is the error amplifier output pin. It is used as the compensation point for the PWM error amplifier. PGOOD - This pin provides a power good status. It is an open collector output used to indicate the status of the output voltage. RT - This is the oscillator frequency selection pin. Connecting this pin directly to VCC5 will select the oscillator free running frequency of 300kHz. By placing a resistor from this pin to GND, the oscillator frequency can be programmed from 100kHz to 1.4MHz. Figure 8 shows the oscillator frequency vs the RT resistance. CDEL - The PGOOD signal can be delayed by a time proportional to a CDEL current of 2µA & the value of the capacitor connected between this pin and ground. A 0.1µF will typically provide 125ms delay. When in the Voltage margining mode the CDEL current is 100µA typical and provides the delay for the output voltage slew rate, 2.5ms typical for the 0.1µF capacitor. 10 FREQUENCY (kHz) Pin Descriptions 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 25 50 75 RT (kΩ) 100 125 150 FIGURE 8. OSCILLATOR FREQUENCY vs RT PGND - This pin provides the power ground for the IC. Tie this pin to the ground plane through the lowest impedance connection. PVCC - This pin is the power connection for the gate drivers. Connect this pin to the VCC5 pin. VCC5 – This pin is the output of the internal 5V LDO. Connect a minimum of 4.7µF ceramic decoupling capacitor as close to the IC as possible at this pin. Refer to Table 1. ENSS - This pin provides enable/disable function and softstart for the PWM output. The output drivers are turned off when this pin is held below 1V. OCSET - Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 100µA current source (IOCS), and the upper MOSFET on resistance rDS(ON) set the converter overcurrent (OC) trip point according to the following equation: I OCSSET • R OCSET I OC = -----------------------------------------------------R DS ( ON ) (EQ. 1) An overcurrent trip cycles the soft-start function with an ON time of 20ms and an OFF time of 128ms. GPIO1/REFIN - This is a dual function pin. If VMSET/MODE is not connected to VCC5 then this pin serves as GPIO1. Refer to Table 2 for GPIO commands interpretation. If VMSET/MODE is connected to VCC5 then this pin will serve as REFIN. As REFIN, this pin is the non-inverting input to the error amplifier. Connect the desired reference voltage to this pin in the range of 0.6V to 1.25V. Connect this pin to VCC5 to use internal reference. REFOUT - If VMSET/MODE pin is connected to VCC5, then this pin serves as REFOUT. It provides buffered reference output for REFIN. Connect 2.2µF capacitor to this pin when used as REFOUT. If not used to source current, connect a 1µF bypass capacitor to this pin. FN9169.1 October 13, 2005 ISL6420A VMSET/MODE - This pin is a dual function pin. Tie this pin to VCC5 to disable voltage margining. When not tied to VCC5, this pin serves as VMSET. Connect a resistor from this pin to ground to set delta for voltage margining. If voltage margining and external reference tracking mode are not needed, this pin can be tied directly to ground. TABLE 2. VOLTAGE MARGINING CONTROLLED BY GPIO1 AND GPIO2 GPIO1 GPIO2 VOUT L L No Change L H + Delta VOUT H L - Delta VOUT H H Ignored GPIO2 - This is general purpose IO pin for voltage margining. Refer to Table 2. TABLE 3. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION PIN CONFIGURATIONS FUNCTION/MODES VMSET/MODE Enable Voltage Margining Pin Connected to GND with resistor. It is used as VMSET. REFOUT GPIO1/REFIN Serves as a general Connect a 1µF purpose I/O. Refer to capacitor for bypass of external Table 2 reference. GPIO2 COMMENTS Serves as a general purpose I/O. Refer to Table 2 REFIN or REFOUT functions will not be available in this mode. The internal 0.6V reference is used. Pin Connected No Voltage Margining. Normal operation using internal reference. to GND with resistor. It is REFOUT not used. used as VMSET Connect a 1µF capacitor for bypass of external reference. L L No Voltage Margining. Normal operation with internal reference. Buffered VREFOUT = 0.6V. H Connect a 2.2µF capacitor to GND. H L No Voltage Margining. External reference. Buffered VREFOUT = VREFIN H Connect a 2.2µF Connect to an external capacitor to GND. reference voltage source (0.6V to 1.25V) L NOTES: 1. The GPIO1/REFIN and GPIO2 pins cannot be left floating. 2. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE. Functional Description Initialization The ISL6420A automatically initializes upon receipt of power. The Power-On Reset (POR) function monitors the internal bias voltage generated from LDO output (VCC5) and the ENSS pin. The POR function initiates the soft-start operation after the VCC5 exceeds the POR threshold. The POR function inhibits operation with the chip disabled (ENSS pin <1V). When the ENSS pin voltage reaches 1V typically, the internal 0.6V reference begins to charge following the dv/dt of the ENSS voltage. As the soft-start pin charges from 1V to 1.6V, the reference voltage charges from 0V to 0.6V. Figure 9 shows a typical soft-start sequence. VIN = 28V, VOUT = 3.3V, IOUT = 10A The device can operate from an input supply voltage of 5.6V to 28V connected directly to the VIN pin using the internal 5V linear regulator to bias the chip and supply the gate drivers. For 5V ±10% applications, connect VIN to VCC5 to bypass the linear regulator. Soft-Start/Enable The ISL6420A soft-start function uses an internal current source and an external capacitor to reduce stresses and surge current during startup. When the output of the internal linear regulator reaches the POR threshold, the POR function initiates the soft-start sequence. An internal 10µA current source charges an external capacitor on the ENSS pin linearly from 0V to 3.3V. 11 FIGURE 9. TYPICAL SOFT-START WAVEFORM FN9169.1 October 13, 2005 ISL6420A Overcurrent Protection Voltage Margining The overcurrent function protects the converter from a shorted output by using the upper MOSFET’s on-resistance, rDS(ON) to monitor the current. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor. The ISL6420A has a voltage margining mode that can be used for system testing. The voltage margining percentage is resistor selectable up to ±10%. The voltage margining mode can be enabled by connecting a margining set resistor from VMSET pin to ground and using the control pins GPIO1/2 to toggle between positive and negative margining (Refer to Table 2). With voltage margining enabled, the VMSET resistor to ground will set a current, which is switched to the FB pin. The current will be equal to 2.468V divided by the value of the external resistor tied to the VMSET pin. The overcurrent function cycles the soft-start function in a hiccup mode with an ON time of 20ms and an OFF time of 128ms to provide fault protection. On detecting an overcurrent condition, the IC waits for four soft-start cycles before the output drivers are turned ON again, this process is repeated till the overcurrent condition is removed. A resistor connected to the drain of the upper FET and the OCSET pin programs the overcurrent trip level. The PHASE node voltage will be compared against the voltage on the OCSET pin, while the upper FET is on. A current (100µA typically) is pulled from the OCSET pin to establish the OCSET voltage. If PHASE is lower than OCSET while the upper FET is on then an overcurrent condition is detected for that clock cycle. The upper gate pulse is immediately terminated, and a counter is incremented. If an overcurrent condition is detected for 8 consecutive clock cycles, and the circuit is not in soft-start, the ISL6420A enters into the softstart hiccup mode. During hiccup, the external capacitor on the ENSS pin is discharged. After the cap is discharged, it is released and a soft-start cycle is initiated. During soft-start, pulse termination current limiting is enabled, but the 8-cycle hiccup counter is held in reset until soft-start is completed. 2.468V I VM = -----------------------R VMSET (EQ. 2) R FB ∆V VM = 2.468V -----------------------R VMSET (EQ. 3) The power supply output increases when GPIO2 is HIGH and decreases when GPIO1 is HIGH. The amount that the output voltage of the power supply changes with voltage margining, will be equal to 2.468V times the ratio of the external feedback resistor and the external resistor tied to VMSET. Figure 10 shows the positive and negative margining for a 3.3V output, using a 20.5kΩ feedback resistor and using various VMSET resistor values. 3.7 The overcurrent function will trip at a peak inductor current (IOC) determined from Equation 1, where IOCSET is the internal OCSET current source. 1. The maximum rDS(ON) at the highest junction temperature. 2. Determine I OC for I OC > I OUT ( MAX ) + ( ∆I ) ⁄ 2 , where ∆I is the output inductor ripple current. A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage. 12 3.5 3.4 VOUT (V) The OC trip point varies mainly due to the upper MOSFETs rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 3.6 3.3 3.2 3.1 3.0 2.9 2.8 150 175 200 225 250 275 300 325 350 375 400 RVMSET (kΩ) FIGURE 10. VOLTAGE MARGINING vs VMSET RESISTANCE FN9169.1 October 13, 2005 ISL6420A VIN = 12V, VOUT = 3.3V, NO LOAD 20mA and sinking up to 50µA current with a 2.2µF capacitor connected to the REFOUT pin. If VMSET/MODE pin is tied to high but GPIO1/REFIN is connected to an external voltage source between 0.6V to 1.25V, then this external voltage is used as the reference voltage at the positive input of the error amplifier. The buffered reference output on REFOUT will be Vrefin ±0.01V, capable of sourcing 20mA and sinking up to 50µA current with a 2.2µF capacitor on the REFOUT pin. Power Good The PGOOD pin can be used to monitor the status of the output voltage. PGOOD will be true (open drain) when the FB pin is within ±10% of the reference and the ENSS pin has completed its soft-start ramp. FIGURE 11A. VIN = 12V, VOUT = 3.3V, NO LOAD Additionally, a capacitor on the CDEL pin will set a delay for the PGOOD signal. After the ENSS pin completes its softstart ramp, a 2µA current begins charging the CDEL capacitor to 2.5V. The capacitor will be quickly discharged before PGOOD goes high. The programmable delay can be used to sequence multiple converters or as a LOW-true reset signal. VIN = 12V, VOUT = 3.3V, IOUT = 10A FIGURE 11B. The slew time of the current is set by an external capacitor on the CDEL pin, which is charged and discharged with a 100µA current source. The change in voltage on the capacitor is 2.5V. This same capacitor is used to set the PGOOD active delay after soft-start. When PGOOD is low, the internal PGOOD circuitry uses the capacitor and when PGOOD is high, the voltage margining circuit uses the capacitor. The slew time for voltage margining can be in the range of 300µs to 2ms. If the voltage on the FB pin exceeds ±10% of the reference, then PGOOD will go low after 1µs of noise filtering. External Reference/DDR Supply Over-Temperature Protection The voltage margining can be disabled by connecting the VMSET/MODE to VCC5. In this mode the chip can be configured to work with an external reference input and provide a buffered reference output. The IC is protected against over-temperature conditions. When the junction temperature exceeds 150°C, the PWM shuts off. Normal operation is resumed when the junction temperature is cooled down to 130°C. If VMSET/MODE pin and the GPIO1/REFIN pin are both tied to VCC5, then the internal 0.6V reference is used as the error amplifier non-inverting input. The buffered reference output on REFOUT will be 0.6V ±0.01V, capable of sourcing Shutdown 13 FIGURE 12. PGOOD DELAY When ENSS pin is below 1V, the regulator is disabled with the PWM output drivers three-stated. When disabled, the IC power will be reduced. FN9169.1 October 13, 2005 ISL6420A Undervoltage If the voltage on the FB pin is less than 15% of the reference voltage for 8 consecutive PWM cycles, then the circuit enters into soft-start hiccup mode. This mode is identical to the overcurrent hiccup mode. VIN = 12V, VOUT = 3.3V at 25mA LOAD Overvoltage Protection If the voltage on the FB pin exceeds the reference voltage by 15%, the lower gate driver is turned on continuously to discharge the output voltage. If the overvoltage condition continues for 32 consecutive PWM cycles, then the chip is turned off with the gate drivers three-stated. The voltage on the FB pin will fall and reach the 15% undervoltage threshold. After 8 clock cycles, the chip will enter soft-start hiccup mode. This mode is identical to the overcurrent hiccup mode. FIGURE 13. PREBIASED OUTPUT AT 25mA LOAD The gate control logic translates generated PWM control signals into the MOSFET gate drive signals providing necessary amplification, level shifting and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operational conditions. Since MOSFET switching time can vary dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring the gate-tosource voltages of both upper and lower MOSFETs. The lower MOSFET is not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the upper MOSFET is not turned on until the gate-to-source voltage of the lower MOSFET has decreased to less than approximately 1V. This allows a wide variety of upper and lower MOSFETs to be used without a concern for simultaneous conduction, or shoot-through. Startup into Pre-Biased Load The ISL6420A is designed to power up into a pre-biased load. This is achieved by transitioning from Diode Emulation mode to a Forced Continuous Conduction mode during startup. The lower gate turns ON for a short period of time and the voltage on the phase pin is sensed. When this goes negative the lower gate is turned OFF and remains OFF till the next cycle. As a result the inductor current will not go negative during soft-start and thus will not discharge the prebiased load. The waveform for this condition is shown below. Application Guidelines Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. VIN ISL6420A UGATE Q1 LO VOUT PHASE LGATE Q2 D2 CIN LOAD Gate Control Logic CO GND RETURN FIGURE 14. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS 14 FN9169.1 October 13, 2005 ISL6420A Figure 14 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 14 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL6420A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6420A must be sized to handle up to 2A peak current. Figure 15 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, Css close to the SS pin because the internal current source is only 30µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. +VIN BOOT D1 CBOOT The modulator transfer function is the small-signal transfer function of Vout/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage DVOSC. VIN OSC DRIVER PWM COMPARATOR LO +5V Q2 CO VCC CVCC LO - DRIVER + VOUT PHASE CO ESR (PARASITIC) VOUT PHASE SS/EN CSS Figure 16 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (Vout) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). ∆VOSC LOAD ISL6420A Q1 Feedback Compensation ZFB VE/A - ZIN + REFERENCE ERROR AMP GND DETAILED COMPENSATION COMPONENTS FIGURE 15. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES ZFB C2 C1 VOUT ZIN C3 R2 R3 R1 COMP FB + ISL6420A REF FIGURE 16. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN 15 FN9169.1 October 13, 2005 ISL6420A Modulator Break Frequency Equations 100 1 F LC = --------------------------------------2π • L O • C O (EQ. 4) FZ1 FZ2 FP1 FP2 80 OPEN LOOP ERROR AMP GAIN 1 F ESR = --------------------------------------------2π • ( ESR • C O ) (EQ. 5) The compensation network consists of the error amplifier (internal to the ISL6420A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180°. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 16. Use these guidelines for locating the poles and zeros of the compensation network: Compensation Break Frequency Equations 1 F Z1 = ---------------------------------2π • R 2 • C1 (EQ. 6) 1 F P1 = ------------------------------------------------------C1 • C2 2π • R2 • ---------------------- C1 + C2 (EQ. 7) GAIN (dB) 60 40 20 20LOG (R2/R1) 20LOG (VIN/∆VOSC) 0 -40 -60 COMPENSATION GAIN MODULATOR GAIN -20 CLOSED LOOP GAIN FLC 10 100 1K FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 17. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. Component Selection Guidelines Output Capacitor Selection 1 F Z2 = -----------------------------------------------------2π • ( R1 + R3 ) • C3 (EQ. 8) 1 F P2 = ---------------------------------2π • R3 • C3 (EQ. 9) 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Figure 17 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 17. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 17 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. 16 An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0µF ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger FN9169.1 October 13, 2005 ISL6420A case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transients. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current and the output capacitors ESR. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT ∆I L = -------------------------------- ⋅ ---------------Fs x L V IN (EQ. 10) ∆V OUT = ∆I L ⋅ ESR (EQ. 11) Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. A more specific equation for determining the input ripple is the following, 2 I RMS = I MAX ⋅ ( D – D ) Increasing the value of inductance reduces the ripple current and voltage. However, larger inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6420A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O × I TRAN t RISE = ------------------------------V IN – V OUT (EQ. 12) L O × I TRAN t FALL = -----------------------------V OUT (EQ. 13) where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. 17 (EQ. 14) For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. MOSFET Selection/Considerations The ISL6420A requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. 2 1 P UFET = I O ⋅ R DS ( ON ) ⋅ D + --- I O ⋅ V IN ⋅ t sw ⋅ f sw 2 2 P LFET = I O ⋅ R DS ( ON ) ⋅ ( 1 – D ) (EQ. 15) (EQ. 16) Where D is the duty cycle = Vo/Vin, tSW is the switching interval, and fSW is the switching frequency. FN9169.1 October 13, 2005 ISL6420A These equations assume linear voltage-current transitions and do not adequately model power loss due the reverserecovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the ISL6420A and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Schottky Selection Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. 18 FN9169.1 October 13, 2005 ISL6420A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE I) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - 0.02 0.05 - A2 - 0.65 1.00 9 A3 b 0.20 REF 0.18 D 0.30 5, 8 4.00 BSC D1 D2 0.25 9 - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.50 BSC - k 0.20 - - - L 0.35 0.60 0.75 8 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 θ - - 12 9 9 Rev. 2 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 19 FN9169.1 October 13, 2005 ISL6420A Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) M20.15 N INDEX AREA H 0.25(0.010) M E GAUGE PLANE -B1 2 INCHES 3 0.25 0.010 SEATING PLANE -A- 20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) B M A D L h x 45° -C- α e A2 A1 B C 0.10(0.004) 0.17(0.007) M C A M B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - A2 - 0.061 - 1.54 - B 0.008 0.012 0.20 0.30 9 C 0.007 0.010 0.18 0.25 - D 0.337 0.344 8.56 8.74 3 E 0.150 0.157 3.81 3.98 4 e 0.025 BSC 0.635 BSC - H 0.228 0.244 5.80 6.19 - h 0.0099 0.0196 0.26 0.49 5 L 0.016 0.050 0.41 1.27 6 8° 0° N α 20 0° 20 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 7 8° Rev. 1 6/04 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN9169.1 October 13, 2005