dsPIC30F FAMILY REFERENCE MANUAL dsPIC30F Family Reference Manual Errata Sheet The dsPIC30F Family Reference Manual (DS70046B) correctly describes the function of the dsPIC30F devices, except for the anomalies described below. 4. All of the issues listed will be addressed in future releases of the Family Reference Manual. 5. 6. Errata Summary The following list summarizes the errata described in further detail through the remainder of this document: 1. 2. 3. Typographical errors in several register descriptions, bit descriptions, and source code examples have been corrected. The conditions leading to a Stack Error Trap have been clarified. Restrictions on the instructions that can be used at or near the end of a DO loop have been clarified. 7. 8. 9. 10. 11. 12. 13. 2004 Microchip Technology Inc. The timing for Program Space Visibility (PSV) operations has been clarified and the effect of instruction stalls on PSV has been corrected. The function of the NVMADRU register has been documented. Run-Time Self Programming (RTSP) can be used to program 32 instruction locations at one time, not 4 instructions as the current documentation indicates. Causes of Address Error Traps have been clarified. Control bits for tuning the 8 MHz RC oscillator have been documented. Clock switching operation has been clarified. Differences in QEI DFLTCON register among device variants has been documented. The 10-bit A/D sampling requirements have been changed. The 12-bit A/D sampling requirements have been changed. Wake-up operation from Sleep and Idle modes has been clarified. DS80169E-page 1 dsPIC30F Family Reference Manual 1. Page 2-2, Section 2.1 Introduction On page 2-2, Section 2.1 Introduction, paragraph 5 should be replaced with the following: The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. Furthermore, RAM may be connected to the program memory bus on devices with an external bus and used to extend the internal data RAM. 2. Page 2-10, Section 2.3.3 Stack Pointer Overflow On page 2-10, Section 2.3.3 Stack Pointer Overflow, the last sentence in paragraph 2 should be replaced by the following: If the contents of the Stack Pointer (W15) are greater than the contents of the SPLIM register by 2 and a push operation is performed, a Stack Error Trap will not occur. The Stack Error Trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a Stack Error Trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value, 0x1FFE. Note: 3. A Stack Error Trap may be caused by any instruction that uses the contents of the W15 register to generate an effective address (EA). Thus, if the contents of W15 are greater than the contents of the SPLIM register by 2, and a CALL instruction is executed, or if an interrupt occurs, a Stack Error Trap will be generated. Page 2-34, Section 2.9.2.5 DO Loop Restrictions On page 2-34, Section 2.9.2.5 DO Loop Restrictions, the following paragraph and bullets should be added to the end of this section: The instruction that is executed two instructions before the last instruction in a DO loop should not modify any of the following: •CPU priority level governed by the IPL (SR<7:5>) bits •Peripheral Interrupt Enable bits governed by the IEC0, IEC1 and IEC2 registers •Peripheral Interrupt Priority bits governed by the IPC0 through IPC11 registers If the restrictions above are not followed, the DO loop may execute incorrectly. 4. Page 2-34, Section 2.9.2.5.1 Last Instruction Restrictions On page 2-34, Section 2.9.2.5.1 Last Instruction Restrictions, the following bullet should be added to the end of the bulleted list: 6. DISI instruction DS80169E-page 2 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 5. Page 2-37, Section 2.10.2.4 Instruction Stalls and Program Space Visibility On page 2-37, Section 2.10.2.4 Instruction Stalls and Program Space Visibility should be replaced with the following: 2.10.2.4 Instruction Stalls and Program Space Visibility (PSV) When program space (PS) is mapped to data space by enabling the PSV (CORCON<2>) bit, and the X space EA falls within the visible program space window, the read or write cycle is redirected to the address in program space. Accessing data from program space takes up to 3 instruction cycles. Instructions operating in PSV address space are subject to RAW data dependencies and consequent instruction stalls, just like any other instruction. Consider the following code segment: ADD W0,[W1],[W2++]; PSV = 1, W1=0x8000, PSVPAG=0xAA MOV [W2],[W3] This sequence of instructions would take 5 instruction cycles to execute. 2 instruction cycles are added to perform the PSV access via W1. Furthermore, an instruction stall cycle is inserted to resolve the RAW data dependency caused by W2. 6. Page 2-39, Table 2-8 dsPIC30F Core Register Map (Continued) On page 2-39, Table 2-8 dsPIC30F Core Register Map (Continued), in the first row of the table, correct bits names for bit 8 through bit 12 in the CORCON register as follows: TABLE 1: Bit Location in CORCON CORCON BIT NAMES Bit Name (Incorrect) Bit Name (Please read as) - US 11 US EDT 10 EDT DL2 12 2004 Microchip Technology Inc. DS80169E-page 3 dsPIC30F Family Reference Manual 7. Page 3-19, Register 3-1: MODCON: Modulo and Bit-Reversed Addressing Control Register, bit 7-4 On page 3-19, Register 3-1: MODCON: Modulo and Bit-Reversed Addressing Control Register, the description for bit4 through bit7 should be modified as follows. All other bit definitions do not change and hence are not described: Register 3-1: MODCON: Modulo and Bit-Reversed Addressing Control Register Upper Byte: R/W-0 R/W-0 XMODEN YMODEN bit 15 U-0 — Lower Byte: R/W-0 U-0 — R/W-0 R/W-0 R/W-0 BWM<3:0> R/W-0 bit 8 R/W-0 R/W-0 YWM<3:0> R/W-0 R/W-0 R/W-0 R/W-0 XWM<3:0> R/W-0 bit 7 bit 7-4 bit 0 YWM<3:0>: Y AGU W Register Select for Modulo Addressing bits 1111 = Modulo addressing disabled 1110 = W14 selected for modulo addressing 1101 = W13 selected for modulo addressing | | 0000 = W0 selected for modulo addressing Note: A write to the MODCON register should not be followed by an instruction that performs an indirect read operation using a W register. Unexpected results may occur. Some instructions perform an implicit indirect read. These are: POP, RETURN, RETFIE, RETLW and ULNK. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared DS80169E-page 4 x = Bit is unknown 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 8. Page 4-10, Section 4.4.3 PSV Timing On page 4-10, Section 4.4.3 PSV Timing should be replaced with the following: 4.4.3 PSV Timing Instructions that use PSV will require two extra instruction cycles to complete execution, except the following instructions that require only one extra cycle to complete execution: -The MAC class of instructions with data pre-fetch operands -All MOV instructions including the MOV.D instruction The additional instruction cycles are used to fetch the PSV data on the program memory bus. 4.4.3.1 Using PSV in a REPEAT Loop Instructions that use PSV within a REPEAT loop eliminate the extra instruction cycle(s) required for the data access from program memory, hence incurring no overhead in execution time. However, the following iterations of the REPEAT loop will incur an overhead of two instruction cycles to complete execution: -The first iteration -The last iteration -Instruction execution prior to exiting the loop due to an interrupt -Instruction execution upon re-entering the loop after an interrupt is serviced 4.4.3.2 PSV and Instruction Stalls Refer to Item 5 in this FRM Errata Document for more information about instruction stalls using PSV. 9. . Page 5-5, Table 5-1 NVMCON Register Values On page 5-5, Table 5-1 NVMCON Register Values should be replaced with the following: Table 5-1: NVMCON Register Values NVMCON Register Values for RTSP Program and Erase Operations Memory Type Flash PM Operation 0x4041 Program 1 row (32 instr. words) 0x4001 1 data word 0x4044 16 data words 0x4045 1 data word 0x4004 16 data words 0x4005 1 config. register 0x4008 Data EEPROM Program Note: 2004 Microchip Technology Inc. NVMCON Value 1 row (32 instr. words) Erase Configuration Register Data Size Erase (see Note) Write The device configuration registers may be written to a new value without performing an erase cycle. DS80169E-page 5 dsPIC30F Family Reference Manual 10. Page 5-6, Section 5.3.2 NVMADR Register On page 5-6, Section 5.3.2 NVMADR Register should be replaced with the following: 5.3.2 NVM Address Registers There are two NVM Address Registers - NVMADRU and NVMADR. These two registers when concatenated form the 24-bit effective address (EA) of the selected row or word for programming operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA. The register pair, NVMADRU:NVMADR, capture the EA<23:0> of the last table-write instruction that has been executed and select the row of Flash or EEPROM memory to write/erase. Figure 5-2 shows how the program memory EA is formed for programming and erase operations. Although the NVMADRU and NVMADR registers are automatically loaded by the table-write instructions, the user can also directly modify their contents before the programming operation begins. A write to these registers will be required prior to an erase operation, because no tablewrite instructions are required for any erase operation. Figure 5-2: NVM Addressing with TBLPAG and NVM Address Registers 24-bit PM address TBLPAG Reg W Register EA NVMADRU Register NVMADR Register EA<0> is Byte Select Using NVMADR Addressing 8 bits TBLPAG<7> selects User or Configuration Space DS80169E-page 6 16 bits NVMADR register loaded with contents of W register EA used during last table-write instruction. NVMADRU register loaded with contents of TBLPAG register during last table-write instruction 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 11. Page 5-7, Register 5-1 NVMCON On page 5-7, Register 5-1: NVMCON: NonVolatile Memory Control Register, the definition of the WREN and PROGOP bits should be modified as follows. All other bit definitions do not change and hence are not described here. Register 5-1: NVMCON: Non-Volatile Memory Control Register Upper Byte: R/S-0 R/W-0 WR WREN bit 15 R/W-0 WRERR Lower Byte: R/W-0 R/W-0 U-0 — U-0 — R/W-0 U-0 — U-0 — R/W-0 R/W-0 PROGOP<7:0> U-0 — bit 8 R/W-0 R/W-0 bit 7 R/W-0 bit 0 bit 14 WREN: Write (Erase or Program) Enable bit 1 = Enable an erase or program operation 0 = No operation allowed (Device clears this bit on completion of the write/erase operation) bit 7-0 PROGOP<7:0>: Programming Operation Command Byte bits Erase Operations: 0x41 = Erase 1 row (32 instruction words) from 1 panel of program Flash 0x44 = Erase 1 data word from data Flash 0x45 = Erase 1 row (16 data words) from data Flash Programming Operations: 0x01 = Program 1 row (32 instruction words) into Flash program memory 0x04 = Program 1 data word into data EEPROM 0x05 = Program 1 row (16 data words) into data EEPROM 0x08 = Program 1 data word into device configuration register Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2004 Microchip Technology Inc. DS80169E-page 7 dsPIC30F Family Reference Manual 12. Page 5-8, Register 5-2: NVMADR: Non-Volatile Memory Address Register, bit 15-0 On page 5-8, Register 5-2: NVMADR: Non-Volatile Memory Address Register, bit 15-0 should be replaced with the following: : Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<15:8> R/W-x R/W-x R/W-x bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<7:0> R/W-x R/W-x R/W-x bit 7 bit 15-0 bit 0 NVMADR<15:0>: NV Memory Write Address bits Selects the location to program or erase in program or data Flash memory. This register may be read or written by user. This register will contain the address of EA<15:0> of the last table write instruction executed, until written by the user. Note: The NVMADRU register function is similar to the NVMADR register and holds the upper 8 bits of the location to be programmed or erased. The value of the TBLPAG register is automatically loaded into the NVMADRU register during a table write instruction. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared DS80169E-page 8 x = Bit is unknown 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 13. Page 5-10, Section 5.4.2.1 Flash Program Memory Programming Algorithm On page 5-10, Section 5.4.2.1 Flash Program Memory Programming Algorithm should be replaced with the following: 5.4.2.1 Flash Program Memory Programming Algorithm The user can erase and program Flash Program Memory by rows (32 instruction words). The general process is as follows: 1. 2. 3. 4. 5. 6. Read one row of program Flash (32 instruction words) and store into data RAM as a data “image”. The RAM image must be read from an even 32-word program memory address boundary. Update the RAM data image with the new program memory data. Erase program Flash row. • Setup NVMCON register to erase 1 row of Flash program memory. • Write address of row to be erased into NVMADRU and NVMADR registers. • Disable interrupts. • Write the key sequence to NVMKEY to enable the erase. • Set the WR bit. This will begin erase cycle. • CPU will stall for the duration of the erase cycle. • The WR bit is cleared when erase cycle ends. • Re-enable interrupts. Write 32 instruction words of data from RAM into the Flash program memory write latches. Program 32 instruction words into program Flash. • Setup NVMCON to program one row of Flash program memory. • Disable interrupts. • Write the key sequence to NVMKEY to enable the program cycle. • Set the WR bit. This will begin the program cycle. • CPU will stall for duration of the program cycle. • The WR bit is cleared by the hardware when program cycle ends. • Re-enable interrupts. Repeat steps 1 through 6, as needed, to program the desired amount of Flash program memory Note: 2004 Microchip Technology Inc. The user should remember that the minimum amount of program memory that can be modified using RTSP is 32 instruction word locations. Therefore, it is important that an image of these locations be stored in general purpose RAM before an erase cycle is initiated. An erase cycle must be performed on any previously written locations before any programming is done. DS80169E-page 9 dsPIC30F Family Reference Manual 14. Page 5-11, Section 5.4.2.2 Erasing a Row of Program Memory On page 5-11, Section 5.4.2.2 Erasing a Row of Program Memory should be replaced with the following: 5.4.2.2 Erasing a Row of Program Memory The following is a code sequence that can be used to erase a row (32 instructions) of program memory. The NVMCON register is configured to erase one row of program memory. The NVMADRU and NVMADR registers are loaded with the address of the row to be erased. The program memory must be erased at ‘even’ row boundaries. Therefore, the 6 LSbits of the value written to the NVMADR register have no effect when a row is erased. The erase operation is initiated by writing a special unlock, or key sequence to the NVMKEY register before setting the WR control bit (NVMCON<15>). The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence. Two NOP instructions should be inserted in the code at the point where the CPU will resume operation. Finally, interrupts can be enabled (if required). ; Setup NVMCON to erase one row of Flash program memory MOV #0x4041,W0 MOV W0,NVMCON ; Setup address pointer to row to be ERASED MOV #tblpage(PROG_ADDR),W0 MOV W0,NVMADRU MOV #tbloffset(PROG_ADDR),W0 MOV W0,NVMADR ; Disable interrupts, if enabled PUSH SR MOV #0x00E0,W0 IOR SR ; Write the KEY sequence MOV #0x55,W0 MOV W0, NVMKEY MOV #0xAA, W0 MOV W0, NVMKEY ; Start the erase operation BSET NVMCON,#WR ; Insert two NOPs after the erase cycle (required) NOP NOP ; Re-enable interrupts, if needed POP SR Note: When erasing a row of program memory, the user writes the upper 8 bits of the erase address directly to the NVMADRU and NVMADR registers. Together, the contents of the NVMADRU and NVMADR registers form the complete address of the program memory row to be erased. The NVMADRU and NVMADR registers specify the address for all Flash erase and program operations. However, these two registers do not have to be directly written by the user for Flash program operations. This is because the table write instructions used to write the program memory data automatically transfers the TBLPAG register contents and the table write address into the NVMADRU and NVMADR registers. The above code example could be modified to perform a ‘dummy’ table write operation to capture the program memory erase address. DS80169E-page 10 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 15. Page 5-12, Section 5.4.2.3 Loading Write Latches On page 5-12, Section 5.4.2.3 Loading Write Latches should be replaced with the following: 5.4.2.3 Loading Write Latches The following is a sequence of instructions that can be used to load the 768-bits of write latches (32 instruction words). Four TBLWTL and four TBLWTH instructions are needed to load the write latches selected by the table pointer. The TBLPAG register is loaded with the 8 MSbits of the program memory address. The user does not need to write the NVMADRU:NVMADR register-pair for a Flash programming operation. The 24-bits of the program memory address are automatically captured into the NVMADRU:NVMADR register-pair when each table write instruction is executed. The program memory must be programmed at an ‘even’ 32 instruction word address boundary. In effect, the 6 LSbits of the value captured in the NVMADR register are not used during the programming operation. The row of 32 instruction words do not necessarily have to be written in sequential order. The 6 LSbits of the table write address determine which of the latches will be written. However, all 32 instruction words should be written for each programming cycle to overwrite old data. Note: The following code example is the ‘Load_Write_Latch’ code referred to in subquent examples. ; Set up a pointer to the first program memory location to be written. MOV #tblpage(PROG_ADDR),W0 MOV W0,TBLPAG MOV #tbloffset(PROG_ADDR),W0 ; Perform the TBLWT instructions to write the latches ; W0 is incremented in the TBLWTH instruction to point to the ; next instruction location. MOV #LOW_WORD_0,W2 MOV #HIGH_BYTE_0,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; MOV #LOW_WORD_1,W2 MOV #HIGH_BYTE_1,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; MOV #LOW_WORD_2,W2 MOV #HIGH_BYTE_2,W3 TBLWTL W2, [W0] ; TBLWTH W3, [W0++] MOV #LOW_WORD_3,W2 MOV #HIGH_BYTE_3,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; ........ ........ MOV #LOW_WORD_31,W2 MOV #HIGH_BYTE_31,W3 TBLWTL W2,[W0] TBLWTH W3,[W0++] ; 2004 Microchip Technology Inc. 1st_program_word 2nd_program_word 3rd_program_word 4th_program_word 32nd_program_word DS80169E-page 11 dsPIC30F Family Reference Manual 16. Page 6-6, Section 6.2 Non-Maskable Traps On page 6-6, Section 6.2 Non-Maskable Traps, the second paragraph should be replaced with the following: The dsPIC30F has four implemented sources of non-maskable traps: •Oscillator Failure Trap •Stack Error Trap •Address Error Trap •Arithmetic Error Trap 17. Page 6-7, Section 6.2.2 Hard Traps On page 6-7, Section 6.2.2 Hard Traps, paragraph 1 should be replaced with the following: Hard traps include exceptions of priority level 13 through level 15, inclusive. The address error (level 13) and oscillator error (level 14) traps fall into this category. 18. Page 6-8, Section 6.2.2.3 Address Error Trap (Hard Trap, Level 13) On page 6-8, Section 6.2.2.3 Address Error Trap (Hard Trap, Level 13), the following additional circumstances under which an Address Error Trap may occur, should be included in the numbered list of items: 4.Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address. 5.Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN instruction. 19. Page 6-10, Section 6.2.5 Wake-up from SLEEP and IDLE On page 6-10, Section 6.2.5 Wake-up from SLEEP and IDLE, the existing note should be replaced with the following: Note: User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from SLEEP or IDLE mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. 20. Page 6-43, Table 6-3: Special Function Registers Associated with Interrupt Controller On page 6-43, Table 6-3: Special Function Registers Associated with Interrupt Controller, row 3, Bit 0, SFR Name: IFS0, should be replaced with the following: INT0IF DS80169E-page 12 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 21. Page 7-7, Register 7-1 OSCCON On page 7-7, Register 7-1: OSCCON, the register description should be modified as follows to include the TUN<3:0> bits for the on-chip Fast RC oscillator. All other bit definitions do not change and hence are not described. Register 7-1: Upper Byte: R/W-0 TUN3 bit 15 OSCCON: Oscillator Control Register R/W-0 TUN2 R-y R-y COSC<1:0> Lower Byte: R/W-0 R/W-0 POST<1:0> bit 7 U-0 TUN1 R-0 LOCK U-0 TUN0 U-0 — R/W-y R/W-y NOSC<1:0> bit 8 R/W-0 CF U-0 — R/W-0 LPOSCEN R/W-0 OSWEN bit 0 bit 15-14 TUN<3:2>: Upper 2 bits of the TUN bit-field. Refer to the description of TUN<1:0> (OSCCON<11:10>) bits for details. bit 11-10 TUN<1:0>: Lower 2 bits of the TUN bit-field. The four bit field specified by TUN<3:0> allows the user to tune the internal fast RC oscillator which has a nominal frequency of 8 MHz. The user may be able to tune the frequency of the FRC oscillator within a range of +/- 12% (or 960 kHz) in steps of 1.5% around the factory-calibrated frequency setting, as follows: TUN<3:0> = 0111 provides the highest frequency ...... TUN<3:0> = 0000 provides the factory-calibrated frequency ...... TUN<3:0> = 1000 provides the lowest frequency Note: Refer to the device-specific data sheet for the tuning range and tuning step size for the FRC ocillator on your device. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown y = Value set from configuration bits on POR or BOR Note: The OSCCON register description and functionality may vary depending on the clock sources available on the selected device. Please refer to the specific device data sheet for additional details on this register.. 2004 Microchip Technology Inc. DS80169E-page 13 dsPIC30F Family Reference Manual 22. Page 7-23, Section 7.17.3 Clock Switching Tips On page 7-23, Section 7.17.3 Clock Switching Tips, add the following note to the end: Note: The application should not attempt to switch to a clock of frequency lower than 100 KHz when the fail-safe clock monitor is enabled. If such clock switching is performed, the device may generate an oscillator fail trap and switch to the Fast RC oscillator. 23. Page 7-24, Section 7.17.7.2 Aborting a Clock Switch On page 7-24, Section 7.17.7.2 Aborting a Clock Switch, should be replaced with the following: 7.17.7.2 Aborting a Clock Switch The following code sequence would be used to ABORT an unsuccessful clock switch: MOV MOV.B MOV.B MOV.B MOV.B BCLR #OSCCON,W1 #0x46,W2 #0x57,W3 W2, [W1] W3, [W1] OSCCON,#OSWEN ; ; ; ; ; ; pointer to OSCCON first unlock code second unlock code write first unlock code write second unlock code ABORT the switch 24. Page 10-4, Section 10.3.6 Wake-up from SLEEP on Interrupt On page 10-4, Section 10.3.6 Wake-up from SLEEP on Interrupt, the following text should be added: User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from SLEEP mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. 25. Page 10-4, Section 10.4 IDLE Mode On page 10-4, Section 10.4 IDLE Mode, the following text should be added: User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from IDLE mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater. DS80169E-page 14 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 26. Page 15-6, Register 15-2: PTMR: PWM Time Base Register, bit 14-0 On page 15-6, Register 15-2: PTMR: PWM Time Base Register, the description of bit 0 through bit 14 should be replaced as follows. All other bit definitions do not change and hence are not described. Register 15-2: Upper Byte: R-0 PTDIR bit 15 PTMR: PWM Time Base Register R/W-0 R/W-0 R/W-0 R/W-0 PTMR <14:8> R/W-0 R/W-0 R/W-0 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR <7:0> R/W-0 R/W-0 R/W-0 bit 7 bit 14-0 bit 0 PTMR <14:0>: PWM Timebase Register Count Value Legend: R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 27. Page 15-32, Section 15.10 PWM Fault Pins On page 15-32, Section 15.10 PWM Fault Pins, paragraph 2 should be replaced with the following: The fault pins may have other multiplexed functions depending on the dsPIC device variant. When used as a fault input, each fault pin is readable via its corresponding PORT register. The FLTA and FLTB pins function as active low inputs so that it is easy to wire-OR many sources to the same input through an external pull-up resistor. When not used with the PWM module, these pins may be used as general purpose I/O or another multiplexed function. Each fault pin has its own interrupt vector, interrupt flag bit, interrupt enable bit, and interrupt priority bits associated with it. 2004 Microchip Technology Inc. DS80169E-page 15 dsPIC30F Family Reference Manual 28. Page 15-32, Section 15.10.1 Fault Pin Enable Bits On page 15-32, Section 15.10.1 Fault Pin Enable Bits, paragraph 2 should be replaced with the following: If all enable bits are cleared in the FLTACON or FLTBCON registers, then that fault input pin has no effect on the PWM module and no fault interrupts will be produced. 29. Page 17-9, Register 17-4 ADCHS On page 17-9, Section 17-4 ADCHS, the following note should be added to the ADCHS register description: Note: The ADCHS register description and functionality will vary depending on the number of A/D inputs available on the selected device. Please refer to the specific device datasheet for additional details on this register. 30. Page 17-14, Section 17.7 Selecting the A/D Conversion Clock On page 17-14, Section 17.7 Selecting the A/D Conversion Clock, paragraph 3 should be replaced with the following: For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 154 nsec (for VDD = 5V). Also remove Table 17-1: Typical TAD vs. Device Operating Frequencies. 31. Page 17-37, Table 17-5 Converting Three Inputs, Four Times and Four Inputs, One time Per Interrupt On page 17-37, Table 17-5 Converting Three Inputs, Four Times and Four Inputs, One Timer Per Interrupt, the initialization of the SMPI <3:0> (ADCON2<5:2>) bits should be modified as follows: SMPI<3:0> = 0011 DS80169E-page 16 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 32. Page 17-46, Section 17.16 A/D Sampling Requirements The entire Section 17.16 should be replaced with the following text and figures: The analog input model of the 10-bit A/D converter is shown in Figure 17-21. The total sampling time for the A/D is a function of the internal amplifier settling time and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The source impedance (RS), the interconnect impedance (RIC), and the internal sampling switch (RSS) impedance combine to directly affect the time required to charge the capacitor CHOLD. The combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy of the A/D converter, the maximum recommended source impedance, RS, is 5 kΩ. After the analog input channel is selected (changed), this sampling function must be completed prior to starting the conversion. The internal holding capacitor will be in a discharged state prior to each sample operation. At least 1 TAD time period should be allowed between conversions for the sample time. For more details, see the device electrical specifications. Figure 17-21: 10-bit A/D Converter Analog Input Model VDD Rs VA ANx RIC ≤ 250Ω VT = 0.6V Sampling Switch RSS ≤ 3 kΩ RSS CPIN VT = 0.6V I leakage ± 500 nA CHOLD = DAC capacitance = 4.4 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I leakage = leakage current at the pin due to various junctions RIC = interconnect resistance RSS = sampling switch resistance CHOLD = sample/hold capacitance (from DAC) Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ. 33. Page 18-12, Section 18.7 Selecting the A/D Conversion Clock On page 18-12, Section 18.7 Selecting the A/D Conversion Clock, paragraph 3 should be replaced with the following: For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 667 nsec (for VDD = 5V). Also remove Table 18-1: Typical TAD vs. Device Operating Frequencies. 2004 Microchip Technology Inc. DS80169E-page 17 dsPIC30F Family Reference Manual 34. Page 18-27, Section 18.15 A/D Sampling Requirements The entire Section 18.15 should be replaced with the following text and figures: The analog input model of the 12-bit A/D converter is shown in Figure 18-11. The total sampling time for the A/D is a function of the internal amplifier settling time and the holding capacitor charge time. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the voltage level on the analog input pin. The source impedance (RS), the interconnect impedance (RIC), and the internal sampling switch (RSS) impedance combine to directly affect the time required to charge the capacitor CHOLD. The combined impedance of the analog sources must therefore be small enough to fully charge the holding capacitor within the chosen sample time. To minimize the effects of pin leakage currents on the accuracy of the A/D converter, the maximum recommended source impedance, RS, is 2.5 kΩ. After the analog input channel is selected (changed), this sampling function must be completed prior to starting the conversion. The internal holding capacitor will be in a discharged state prior to each sample operation. At least 1 TAD time period should be allowed between conversions for the sample time. For more details, see the device electrical specifications. Figure 18-11: 12-bit A/D Converter Analog Input Model VDD Rs VA ANx RIC ≤ 250Ω VT = 0.6V Sampling Switch RSS ≤ 3 kΩ RSS CPIN VT = 0.6V I leakage ± 500 nA CHOLD = DAC capacitance = 18 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions = interconnect resistance RIC = sampling switch resistance RSS = sample/hold capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 2.5 kΩ. DS80169E-page 18 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 35. Page 19-10, Section 19.4.1 Enabling the UART, Page 19-13, Section 19.5.3 Setup for UART Transmit and Page 19-20, Section 19.9 Initialization Add the following note to these subsections: Note: The UTXEN bit should not be set until the UARTEN bit has been set. Otherwise, UART transmissions will not be enabled. 36. Page 19-13, Section 19.5.3 Setup for UART Transmit On page 19-13, Section 19.5.3 Setup for UART Transmit, delete Step 3 in this section. 37. Page 19-17, Section 19.6.4 Setup for UART Reception On page 19-17, Section 19.6.4 Setup for UART Reception, delete Step 3 in this section. 38. Page 19-20, Section 19.9 Initialization On page 19-20, Section 19.9 Initialization, Example 19-2 and Example 19-3 should be replaced with the following: Example 19-2: 8-bit Transmit/Receive (UART1) MOV MOV #baudrate,W0 W0,U1BRG ; Set Baudrate BSET BCLR BCLR BSET BCLR BCLR IPC2,#U1TXIP2 IPC2,#U1TXIP1 IPC2,#U1TXIP0 IPC2,#U1RXIP2 IPC2,#U1RXIP1 IPC2,#U1RXIP0 ; Set UART TX interrupt priority ; ; ; Set UART RX interrupt priority ; ; CLR U1STA MOV #0x8800,W0 MOV W0,U1MODE BSET U1STA,#UTXEN ; Enable transmit BSET BSET IEC0,#U1TXIE IEC0,#U1RXIE ; Enable transmit interrupts ; Enable receive interrupts 2004 Microchip Technology Inc. ; Enable UART for 8-bit data, ; no parity, 1 STOP bit, ; no wakeup DS80169E-page 19 dsPIC30F Family Reference Manual Example 19-3: DS80169E-page 20 8-bit Transmit/Receive (UART1), Address Detect Enabled MOV MOV #baudrate,W0 W0,U1BRG ; Set Baudrate BSET BCLR BCLR BSET BCLR BCLR IPC2,#U1TXIP2 IPC2,#U1TXIP1 IPC2,#U1TXIP0 IPC2,#U1RXIP2 IPC2,#U1RXIP1 IPC2,#U1RXIP0 ; Set UART TX interrupt priority ; ; ; Set UART RX interrupt priority ; ; BSET U1STA,#ADDEN ; Enable address detect MOV #0x8883,W0 ; UART1 enabled for 9-bit data, ; no parity, 1 STOP bit, ; wakeup enabled MOV W0,U1MODE BSET U1STA,#UTXEN ; Enable transmit BSET BSET IEC0,#U1TXIE IEC0,#U1RXIE ; Enable transmit interrupts ; Enable receive interrupts 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 39. Page 21-9, Register 21-1 I2CCON On page 21-9, Register 21-1: I2CCON: I2C Control Register, the description of the ACKDT bit should be corrected as follows. All other bit definitions do not change and hence are not described. Register 21-1: Upper Byte: R/W-0 I2CEN bit 15 I2CCON: I2C Control Register U-0 R/W-0 — I2CSIDL R/W-1 HC SCLREL R/W-0 R/W-0 STREN ACKDT Lower Byte: R/W-0 GCEN bit 7 bit 5 R/W-0 R/W-0 R/W-0 IPMIEN A10M DISSLW R/W-0 HC ACKEN R/W-0 HC RCEN R/W-0 HC PEN R/W-0 SMEN bit 8 R/W-0 HC RSEN R/W-0 HC SEN bit 0 ACKDT: Acknowledge Data bit (When operating as I2C Master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during acknowledge 0 = Send ACK during acknowledge Legend: R = Readable W = Writable HC = Cleared by Hardware ‘1’ = Bit is set at POR C = Clearable bit HS = Set by Hardware ‘0’ = Bit cleared at POR U = Unimplemented bit, read as ‘0’ S = Settable bit x = Bit is unknown at POR 40. I2C Interrupt Bit Names Table 2 below, shows changes to the nomenclature of the I2C module’s interrupt enable, status flag and priority bits. These changes should be applied to the entire document. TABLE 2: Bit Location in SFR INTERRUPT CONTROLLER REGISTER MAP: I2C BIT NAMES Bit Name (Incorrect) Bit Name (Please read as) IFS0<14> BCLIF MI2CIF IFS0<13> I2CIF SI2CIF IEC0<14> BCLIE MI2CIE IEC0<13> I2CIE SI2CIE IPC3<10:8> BCLIP<2:0> MI2CIP<2:0> IPC3<6:4> I2CIP<2:0> SI2CIP<2:0> 2004 Microchip Technology Inc. DS80169E-page 21 dsPIC30F Family Reference Manual 41. Page 22-12, Equation 22-1 DCI Bit Clock Generator Value On page 22-12, Equation 22-1: DCI Bit Clock Generator Value, should be replaced by the following: Equation 22-1: DCI Bit Clock Generator Value f CY BCG<11:0> = ---------- – 1 2f CSCK 42. Page 22-24, Section 22.5.5.3 I2S Data Justification On page 22-24, Section 22.5.5.3 I2S Data Justification, paragraph 2 should be replaced by the following: If DJST = 1, the I2S data transfers will be MSb left justified. The MSb of the data word will be presented on the CSDO pin during the same serial clock cycle as the rising or falling edge of the FS signal. After the data word has been transmitted, the state of the CSDO pin is dictated by the CSDOM (DCICON1<6>) bit. 43. Page 23-38, Section 23.5.2 Disable Mode On page 23-38, Section 23.5.2 Disable Mode, add the following note to the end. Note: Typically, if the CAN module is allowed to transmit in a particular mode of operation and a transmission is requested immediately after the CAN module has been placed in that mode of operation, the module waits for 11 consecutive recessive bits on the bus before starting transmission. If the user switches to Disable Mode within this 11-bit period, then this transmission is aborted and the corresponding TXABT bit is set and TXREQ bit is cleared. 44. Pages 23-22 through 23-27, Table 23-1 and Table 23-2 CAN1/CAN2 Register Map On pages 23-22 through 23-27 in Tables 23-1 and 23-2, the nomenclature of the CAN module transmit and receive buffer registers as well as the addresses of the CAN2 module registers should be changed/corrected as follows: DS80169E-page 22 2004 Microchip Technology Inc. 300 302 304 306 308 30A 30C 30E 310 312 314 316 318 31A 31C 31E 320 322 324 326 328 32A 32C 32E 330 332 334 336 338 33A 33C 33E C1RXF0SID C1RXF0EIDL unused C1RXF1SID C1RXF1EIDH C1RXF1EIDL unused C1RXF2SID C1RXF2EIDH C1RXF2EIDL unused C1RXF3SID C1RXF3EIDH C1RXF3EIDL unused C1RXF4SID C1RXF4EIDH C1RXF4EIDL unused C1RXF5SID C1RXF5EIDH C1RXF5EIDL unused C1RXM0SID C1RXM0EIDH C1RXM0EIDL unused C1RXM1SID C1RXM1EIDH C1RXM1EIDL unused ADR 2004 Microchip Technology Inc. — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — — — — — EID<5:0> — — — — — — 12 EID<5:0> — — 13 — — — — — — — — — — 14 15 CAN1 REGISTER MAP C1RXF0EIDH File Name TABLE 23-1: — — — — — — — — 11 9 — — — — — — — — — — — — — — — — — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> — EID<17:14> SID<10:6> 10 — — — — — — — — — — — — — — — — 8 Bit — — — — — — — — — — — — — — — — 7 — — — — — — — — — — — — — — — — 6 — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> 5 — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> 4 — — — — — — — — — — — — — — — — 3 — — — — — — — — — — — — — — — — 2 — — — — — — — — — — — — — — — — — — — — — — — — 1 — — MIDE — — MIDE — — EXIDE — — EXIDE — — EXIDE — — EXIDE — — EXIDE — — EXIDE 0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx RESET dsPIC30F Family Reference Manual DS80169E-page 23 DS80169E-page 24 34C 34E 350 C1TX2B4 C1TX2CON C1TX1SID 358 35A 35C 35E 360 362 362 366 368 36A 36C 36E C1TX1B2 C1TX1B3 C1TX1B4 C1TX1CON C1TX0SID C1TX0EID C1TX0DLC C1TX0B1 C1TX0B2 C1TX0B3 C1TX0B4 C1TX0CON 356 34A C1TX2B3 C1TX1B1 348 C1TX2B2 352 346 C1TX2B1 352 342 C1TX2DLC C1TX1EID 342 C1TX2EID C1TX1DLC 340 ADR — — — 15 SID<10:6> 13 — — SID<10:6> — — — — — — Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 1 EID<5:0> — Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 1 — — Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 3 EID<5:0> EID<17:14> — — 11 Transmit Buffer 0 Byte 1 SID<10:6> — EID<17:14> — 12 EID<5:0> EID<17:14> 14 CAN1 REGISTER MAP (CONTINUED) C1TX2SID File Name TABLE 23-1: — — — — — — — — TX RTR — — — TX RTR — — — TX RTR — — — — 9 10 — TX RB1 — — — TX RB1 — — — TX RB1 — — 8 7 — TX RB0 — TX RB0 — TX RB0 Bit TX ABT TX ABT TX ABT 6 TX REQ TX ERR TX REQ Transmit Buffer 0 Byte 6 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 0 DLC<3:0> EID<13:6> TX ERR Transmit Buffer 0 Byte 6 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 0 SID<5:0> TX LARB TX REQ EID<13:6> TX ERR Transmit Buffer 0 Byte 6 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 DLC<3:0> TX LARB 3 Transmit Buffer 0 Byte 0 SID<5:0> TX LARB 4 EID<13:6> DLC<3:0> SID<5:0> 5 — — — — — — 2 — TX IDE 0 — TX IDE — TX IDE TXPRI[1:0] — SRR TXPRI[1:0] — SRR TXPRI[1:0] — SRR 1 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx RESET dsPIC30F Family Reference Manual 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. 382 384 386 388 38A 38C 38E 390 392 394 396 398 C1RX1SID C1RX1EID C1RX1DLC C1RX0B1 C1RX0B2 C1RX0B3 C1RX0B4 C1RX0CON C1CTRL C1CFG1 C1CFG2 C1INTF C1INTE Legend: x = Unknown 39A 380 C1RX1CON 39C 3FE 37E C1RX1B4 Reserved 37C C1RX1B3 C1EC 378 37A C1RX1B2 376 C1RX1B1 — — RXB0 OVR — CAN CAP — — — RXB1 OVR WAK FIL — — — — — — — — — — — — 372 374 — — 370 C1RX1EID 14 15 ADR — 12 Receive Buffer 1 Byte 3 — — — TXBO — C SIDL — — — RXBP — CAN CKS — — — — — — RX RTR — — — — — — RX WARN SEG2PH[2:0] — REQOP[2:0] — RX RTR EID<17:14> TX WARN Transmit Error Counter — TXBP — — ABAT — Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 3 9 EID<17:14> SID<10:6> Receive Buffer 0 Byte 1 — Receive Buffer 1 Byte 7 — 10 SID<10:6> Receive Buffer 1 Byte 5 EID<0:5> — — — 11 Receive Buffer 1 Byte 1 EID<0:5> — — 13 CAN1 REGISTER MAP (CONTINUED) C1RX1DLC C1RX1SID File Name TABLE 23-1: — — E WARN — — RX RB1 — RX RB1 8 — 7 OPMODE[2:0] — — — — 6 — WAK IE IVR IE — WAK IF SAM IVR IF SEG2 PHTS SJW[1:0]S RX FUL — RX FUL Bit — ERR IE ERR IF — — EID<13:6> 4 3 RX ERR xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx RESET TXB1 IE TXB1 IF — — — TXB0 IE TXB0 IF JTOFF — RXB1 IE RXB1 IF PRSEG[2:0] ICODE[2:0] RXB0 DBEN BRP[5:0] RX RTR R0 Receive Error Counter TXB2 IE TXB2 IF SEG1PH[2:0] — RX ERR Receive Buffer 0 Byte 6 Receive Buffer 0 Byte 4 Receive Buffer 0 Byte 2 Receive Buffer 0 Byte 0 — RXB0 IE RXB0 IF — xxxx 0000 0000 0000 0000 0000 0480 0000 xxxx xxxx xxxx xxxx xxxx FIL HIT 0 RX IDE RX IDE 0 xxxx DLC[3:0] SRR FILHIT[2:0] DLC[3:0] SRR 1 EID<13:6> 2 RX RB0 RX RTR R0 Receive Buffer 1 Byte 6 Receive Buffer 1 Byte 4 Receive Buffer 1 Byte 2 Receive Buffer 1 Byte 0 RX RB0 SID<5:0> — — SID<5:0> 5 dsPIC30F Family Reference Manual DS80169E-page 25 DS80169E-page 26 3FA 3FC 3FE unused 3F8 C2RXM1SID C2RXM1EIDH 3F6 unused C2RXM1EIDL 3F2 3F4 3F0 C2RXM0SID C2RXM0EIDH 3EE unused C2RXM0EIDL 3EA 3EC 3E8 C2RXF5SID C2RXF5EIDH 3E6 unused C2RXF5EIDL 3E2 3E4 3E0 C2RXF4SID C2RXF4EIDH 3DE unused C2RXF4EIDL 3DA 3DC — — — — — — — — — — — — — — — — — — — — — — — — — — — — 3D8 C2RXF3SIDH C2RXF3EID — C2RXF3EIDL — — — — — — 3D6 — — — — — — — — — — — — — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — — EID<5:0> — — unused — — EID<5:0> — — — — 3D2 — 12 EID<5:0> — — 13 — 3D4 3D0 C2RXF2SID — — — — C2RXF2EIDH 3CE unused — — — — — — — 14 15 C2RXF2EIDL 3CA 3CC 3C8 C2RXF1SID C2RXF1EIDH 3C6 unused C2RXF1EIDL 3C2 3C4 C2RXF0EIDH C2RXF0EIDL 3C0 ADR CAN2 REGISTER MAP C2RXF0SID File Name TABLE 23-2: — — — — — — — — 11 9 — — — — — — — — — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> — — EID<17:14> SID<10:6> 10 — — — — — — — — — — — — — — — — 8 Bit — — — — — — — — — — — — — — — — 7 — — — — — — — — — — — — — — — — 6 — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> — — SID<5:0> 5 — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> — — EID<13:6> 4 — — — — — — — — — — — — — — — — 3 — — — — — — — — — — — — — — — — 2 — — — — — — — — — — — — — — — — — — — — — — — — 1 — — MIDE — — MIDE — — EXIDE — — EXIDE — — EXIDE — — EXIDE — — EXIDE — — EXIDE 0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx RESET dsPIC30F Family Reference Manual 2004 Microchip Technology Inc. 2004 Microchip Technology Inc. 41A 41C 41E 420 C2TX1B3 C2TX1B4 C2TX1CON C2TX0SID 42A 42C 42E C2TX0B3 C2TX0B4 C2TX0CON 428 418 C2TX1B2 C2TX0B2 416 C2TX1B1 426 414 C2TX1DLC C2TX0B1 412 C2TX1EID 424 410 C2TX1SID 422 40E C2TX2CON C2TX0EID 40C C2TX2B4 C2TX0DLC 408 40A 406 C2TX2B1 C2TX2B3 404 C2TX2B2 402 C2TX2EID 400 ADR — — — 15 SID<10:6> 13 — Transmit Buffer 0 Byte 3 — SID<10:6> — — — — — — Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 1 EID<5:0> — Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 5 Transmit Buffer 0 Byte 3 Transmit Buffer 0 Byte 1 — — Transmit Buffer 0 Byte 7 Transmit Buffer 0 Byte 5 EID<5:0> EID<17:14> — — 11 Transmit Buffer 0 Byte 1 SID<10:6> — EID<17:14> — 12 EID<5:0> EID<17:14> 14 CAN2 REGISTER MAP (CONTINUED) C2TX2DLC C2TX2SID File Name TABLE 23-2: — — — — — — — — TX RTR — — — TX RTR — — — TX RTR — — — — 9 10 — TX RB1 — — — TX RB1 — — — TX RB1 — — 8 7 — TX RB0 — TX RB0 — TX RB0 Bit TX ABT TX ABT TX ABT 6 TX REQ TX ERR TX REQ Transmit Buffer 0 Byte 6 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 0 DLC<3:0> EID<13:6> TX ERR Transmit Buffer 0 Byte 6 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 Transmit Buffer 0 Byte 0 SID<5:0> TX LARB TX REQ EID<13:6> TX ERR Transmit Buffer 0 Byte 6 Transmit Buffer 0 Byte 4 Transmit Buffer 0 Byte 2 DLC<3:0> TX LARB 3 Transmit Buffer 0 Byte 0 SID<5:0> TX LARB 4 EID<13:6> DLC<3:0> SID<5:0> 5 — — — — — — 2 — TX IDE 0 — TX IDE — TX IDE TXPRI[1:0] — SRR TXPRI[1:0] — SRR TXPRI[1:0] — SRR 1 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx RESET dsPIC30F Family Reference Manual DS80169E-page 27 DS80169E-page 28 440 442 444 446 448 44A 44C 44E 450 452 454 C2RX1SID C2RX1EID C2RX1DLC C2RX0B1 C2RX0B2 C2RX0B3 C2RX0B4 C2RX0CON C2CTRL C2CFG1 C2CFG2 Legend: x = Unknown 45A 43E C2RX1CON 45C 4FE 43C C2RX1B4 Reserved 43A C2RX1B3 C2EC 438 C2RX1B2 458 436 C2RX1B1 C2INTE 434 C2RX1DLC 456 432 C2RX1EID C2INTF 430 ADR — — — — RXB0 OVR — CAN CAP — — — RXB1 OVR WAK FIL — — — — — — — — — — — — 14 15 — 12 — — — TXBO — C SIDL — — — RXBP — CAN CKS — — — — — — RX RTR — — — — — — RX WARN SEG2PH[2:0] — REQOP[2:0] — RX RTR EID<17:14> TX WARN Transmit Error Counter — TXBP — — ABAT — Receive Buffer 0 Byte 7 Receive Buffer 0 Byte 5 Receive Buffer 0 Byte 3 9 EID<17:14> SID<10:6> Receive Buffer 0 Byte 1 — Receive Buffer 1 Byte 7 Receive Buffer 1 Byte 5 — 10 SID<10:6> Receive Buffer 1 Byte 3 EID<0:5> — — — 11 Receive Buffer 1 Byte 1 EID<0:5> — — 13 CAN2 REGISTER MAP (CONTINUED) C2RX1SID File Name TABLE 23-2: — — E WARN — — RX RB1 — RX RB1 8 — 7 OPMODE[2:0] — — — — 6 — WAK IE IVR IE — WAK IF SAM IVR IF SEG2 PHTS SJW[1:0]S RX FUL — RX FUL Bit — ERR IE ERR IF — — EID<13:6> 4 3 RX RTR R0 TXB1 IE TXB1 IF — — 2 SRR FILHIT[2:0] — TXB0 IE — RXB1 IE RXB1 IF PRSEG[2:0] ICODE[2:0] JTOFF DLC[3:0] TXB0 IF 1 SRR DLC[3:0] RXB0 DBEN BRP[5:0] RX RTR R0 Receive Error Counter TXB2 IE TXB2 IF SEG1PH[2:0] — RX ERR Receive Buffer 0 Byte 6 Receive Buffer 0 Byte 4 Receive Buffer 0 Byte 2 Receive Buffer 0 Byte 0 RX RB0 EID<13:6> RX ERR Receive Buffer 1 Byte 6 Receive Buffer 1 Byte 4 Receive Buffer 1 Byte 2 Receive Buffer 1 Byte 0 RX RB0 SID<5:0> — — SID<5:0> 5 — RXB0 IE RXB0 IF — FIL HIT 0 RX IDE RX IDE 0 xxxx 0000 0000 0000 0000 0000 0480 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx RESET dsPIC30F Family Reference Manual 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual 45. Page 24-7, Section 24.3.4.1 General Code Segment Configuration Bit Group On page 24-7, Section 24.3.4.1 General Code Segment Configuration Bit Group, add the following note to the end. Note: 2004 Microchip Technology Inc. If the code protection configuration fuse group (FGS<GCP:GWRP>) bits have been programmed, an erase of the entire code-protected device is only possible at voltages, VDD >= 4.5 volts. DS80169E-page 29 dsPIC30F Family Reference Manual 46. Page 16-7, Section 16.2 DFLTCON Page 16-8, Section 16.3 Programmable Digital Noise Filters Page 16-14, Section 16.5.3.2 Index Pulse De-skew The second set of control bits sets the digital filter characteristics for the QEA and QEB pins. The DS70063B document correctly depicts the DFLTCON control register for these device variants. Other device variants have one set of control bits that set the digital filter characteristics for the INDX, QEA and QEB pins. The DFLTCON register for these device variants is provided in Register 16-1 below. If the device variant has this DFLTCON register, then paragraph 5 of Section 16.3 “Programmable Digital Noise Filters” is not applicable. Also, Section 16.5.3.2. “Index Pulse De-skew” is not applicable. The control bits used to control the QEI digital input filters may differ depending upon the device variant that is used. This affects the control bits found in the DFLTCON register. Please refer to the specific device data sheet to determine which DFLTCON control bits are implemented for the device you are using. Some devices have two sets of control bits to control the digital input filters. One set of control bits sets the digital filter characteristics for the INDX pin. Register 16-1: Upper Half: U-0 — bit 15 DFLTCON: Digital Filter Control Register U-0 — Lower Half: R/W-0 QEOUT bit 7 bit 15-11 bit 10-9 bit 8 bit 7 bit 6-4 bit 3-0 U-0 — U-0 — R/W-0 QECK<2:0> U-0 — R/W-0 R/W-0 IMV<1:0> U-0 — R/W-0 CEID bit 8 U-0 — U-0 — U-0 — bit 0 Unimplemented: Read as ‘0’ IMV<1:0>: Index Match Value – These bits allow the user to specify the state of the QEA and QEB input pins during an Index pulse when the POSCNT register is to be reset. In 4X Quadrature Count Mode: IMV1= Required State of Phase B input signal for match on index pulse IMV0= Required State of Phase A input signal for match on index pulse In 2X Quadrature Count Mode: IMV1= Selects Phase input signal for Index state match (0 = Phase A, 1 = Phase B) IMV0= Required State of the selected Phase input signal for match on index pulse CEID: Count Error Interrupt Disable 1 = Interrupts due to count errors are disabled 0 = Interrupts due to count errors are enabled QEOUT: QEA/QEB/INDX pin Digital Filter Output Enable 1 = Digital filter outputs enabled 0 = Digital filter outputs disabled (normal pin operation) QECK<2:0>: QEA/QEB/INDX Digital Filter Clock Divide Select Bits 111 = 1:256 Clock Divide 110 = 1:128 Clock Divide 101 = 1:64 Clock Divide 100 = 1:32 Clock Divide 011 = 1:16 Clock Divide 010 = 1:4 Clock Divide 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide Unimplemented: Read as ‘0’ Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown y = Value set from configuration bits on POR or BOR DS80169E-page 30 2004 Microchip Technology Inc. dsPIC30F Family Reference Manual APPENDIX A: REVISION HISTORY Revision A (10/2003) Original version of the document. Revision B (01/2004) First revision of the document. Revision C (02/2004) Added clarification to QEI DFLTCON register. Revision D (05/2004) Additions made to Errata #21 and Errata #29. Added new Erratas #19, #24 and #25. New Errata #32 – updated document and Figure 17-21. Added new Figure 17-21a 65/2004) Revision E (06/2004) Additions made to Errata #30, Errata #32 and Errata #34. Errata #44 was updated. Added new Errata #33 and Errata #35. 2004 Microchip Technology Inc. DS80169E-page 31 dsPIC30F Family Reference Manual NOTES: DS80169E-page 32 2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. DS80169E-page 33 WORLDWIDE SALES AND SERVICE AMERICAS China - Beijing Korea Corporate Office Unit 706B Wan Tai Bei Hai Bldg. No. 6 Chaoyangmen Bei Str. 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