906

NTE906
Integrated Circuit
Dual, High Frequency, Differential Amplifier
Description:
The NTE906 is an integrated circuit in a 12–Lead TO5 type package consisting of two independent
differential amplifiers with associated constant–current transistors on a common monolithic substrate. The six transistors which comprise the amplifiers are general–purpose devices which exhibit
low 1/f noise and a value of fT in excess of 1GHz. These features make the NTE906 useful from DC
to 500MHz. Bias and load resistors have been omitted to provide maximum application flexibility.
The monolithic construction of the NTE906 provides close electrical and thermal matching of the amplifiers. This feature makes this device particularly useful in dual–channel applications where
matched performance of the two channels is required.
Features:
D Power Gain: 23dB (Typ) @ 200MHz
D Noise Figure: 4.6dB (Typ) @ 200MHz
D Two Different Amplifiers on a Common Substrate
D Independently Accessible Input and Outputs
Absolute Maximum Ratings: (TA = +25°C unless otherwise specified)
Power Dissipation, PD
Any One Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mW
Total Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600mW
Derate Above +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mW/°C
Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to +125°C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65° to +150°C
The following ratings apply for each transistor:
Collector–Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Collector–Base Voltage, VCBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector–Substrate Voltage (Note 1), VCIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Emitter–Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Note 1. The collector of each transistor is isolated from the substrate by an integral diode. The substrate (Pin9) must be connected to the most negative point in the external circuit to maintain
isolation between transistors and to provide for normal transistor action.
Electrical Characteristics: (TA = +25°C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
–
0.25
–
mV
–
0.3
–
µA
Static Characteristics (For Each Differential Amplifier)
Input Offset Voltage
VIO
Input Offset Current
IIO
Input Bias Current
IIB
–
13.5
33
µA
|∆VIO|
∆T
–
1.1
–
µV/°C
Temperature Coefficient Magnitude
of Input–Offset Voltage
I3 = I9 = 2mA
(For Each Transistor)
DC Forward Base–Emitter Voltage
VBE
VCE = 6V, IC = 1mA
–
774
–
mV
Temperature Coefficient of
Base–Emitter Voltage
∆VBE
∆T
VCE = 6V, IC = 1mA
–
–0.9
–
mV/°
C
Collector Cutoff Current
ICBO
VCB = 10V, IE = 0
–
0.0013
100
nA
Collector–Emitter Breakdown Voltage
V(BR)CEO IC = 1mA, IB = 0
15
24
–
V
Collector–Substrate Breakdown Voltage
V(BR)CIO IC = 10µA, IB = 0, IE = 0
20
60
–
V
Emitter–Base Breakdown Voltage
V(BR)EBO IE = 10µA, IC = 0
5
7
–
V
Dynamic Characteristics
1/f Noise Figure (For Single Transistor)
NF
f = 100kHz, RS = 500Ω,
IC = 1mA
–
1.5
–
dB
Gain–Bandwidth Product
(For Single Transistor)
fT
VCE = 6V, IC = 5mA
–
1.38
–
GHz
Note 2
–
0.28
–
pF
Note 3
–
0.28
–
pF
IC = 0, VCI = 5V
–
1.65
–
pF
Collector–Base Capacitance
Collector–Substrate Capacitance
CCB
CCI
IC = 0, VCB = 5V
(For Each Differential Amplifier)
Common–Mode Rejection Ratio
CMR
I3 = I9 = 2mA
–
100
–
dB
AGC Range, One Stage
AGC
Bias Voltage = –6V
–
75
–
dB
Bias Voltage = –4.2V, f = 10MHz
–
22
–
dB
Voltage Gain, Single–Ended Output
A
Insertion Power Gain
GP
Noise Figure
NF
Input Admittance
Reverse Transfer Admittance
Forward Transfer Admittance
Output Admittance
Y11
Y12
Y21
Y22
Note 2. Pins 1 & 12 or Pins 6 & 7.
Note 3. Pins 10 & 11 or Pins 4 & 5.
f = 200MHz,
VCC = 12V,
Cascode
–
23
–
dB
Cascode
–
4.6
–
dB
For Cascode
Configuration
I3 = I9 = 2mA
Cascode
–
1.5+j2.45
–
mmho
Diff. Amp
–
0.878+j1.3
–
mmho
For Diff. Amplifier
Configuration
I3 = I9 = 4mA
(each Collector
IC ' 2mA
Cascode
–
0–j0.008
–
mmho
Diff. Amp
–
0–j0.013
–
mmho
Cascode
–
17.9–j30.7
–
mmho
Diff. Amp
–
–10.5+j13
–
mmho
Cascode
–
–0.503–j15
–
mmho
Diff. Amp
–
0.071+j0.62
–
mmho
Pin Connection Diagram
(Top View)
Q4 Vin (Bias)
Q4 VEE/Substrate
& Case
Q1 Vin 10
8
6
7
9
Q6 Vin
Q1 Vout 11
Q2 Vout
Q6 Vout
6
Q5 Vout
5
4
12
Q2 Vin
1
3
Q5 Vin
Q3 VEE
1
2
Q3 Vin (Bias)
.370 (9.4) Dia Max
.335 (8.5) Dia Max
.180
(4.57)
Max
.500
(12.7)
Min
.018 (0.48) Dia Typ
.245 (6.23) Dia
4
3
5
2
6
7
1
8
12
11
10
9
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