RFD3N08L, RFD3N08LSM
Data Sheet
3A, 80V, 0.800 Ohm, Logic Level,
N-Channel Power MOSFETs
2836.4
• 3A, 80V
• rDS(ON) = 0.800Ω
• Temperature Compensating PSPICE® Model
• On Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Formerly developmental type TA09922.
Ordering Information
PACKAGE
File Number
Features
The RFD3N08L and RFD3N08LSM are N-Channel
enhancement mode silicon gate power field effect transistors
specifically designed for use with logic level (5V) driving
sources in applications such as programmable controllers,
automotive switching, and solenoid drivers. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.
PART NUMBER
July 1999
BRAND
RFD3N08L
TO-251AA
F3N08L
RFD3N08LSM
TO-252AA
F3N08L
Symbol
D
NOTE: When ordering, include the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e. RFD3N08LSM9A
G
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
DRAIN
(FLANGE)
GATE
SOURCE
6-26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD3N08L, RFD3N08LSM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS
Drain to Gate Voltage (RGS = 20KΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Figures 3, 5) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed Avalanche Energy Rating (Figure 6) (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Operating and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RFD3N08L,
RFD3N08LSM
80
80
±10
3
Refer to Peak Current Curve
30
0.2
Refer to UIS Curve
-55 to 175
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
V
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 12)
80
Gate to Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
2.5
V
VDS = Rated BVDSS, VGS = 0V
-
-
25
µA
VDS = 0.8 x Rated BVDSS,
VGS = 0V 125oC
-
-
250
µA
VGS = ±10V
-
-
±100
nA
ID = 3A, VGS = 5V, (Figures 9, 10)
-
-
0.800
Ω
VDD = 40V, ID = 3A,
RL = 13.3Ω, VGS = 5V,
RG = 25Ω,
(Figures 13, 15, 18, 19)
-
-
75
ns
-
15
-
ns
-
45
-
ns
td(OFF)
-
22
-
ns
tf
-
15
-
ns
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
IDSS
IGSS
rDS(ON)
Turn-On Time
t(ON)
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
t(OFF)
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Characterisics
CRSS
VDD = 64V, ID = 3A,
Ig(REF) = 0.1mA
RL = 21.3Ω
(Figures 15, 20, 21)
VDS = 25V, VGS = 0V, f = 1MHz,
(Figure 14)
-
-
45
ns
-
6.8
8.5
nC
-
3.8
4.8
nC
-
0.18
0.24
nC
-
-
125
pF
-
-
55
pF
-
-
15
pF
Thermal Resistance, Junction to Case
RθJC
-
-
5.0
oC/W
Thermal Resistance, Junction to Ambient
RθJA
-
-
100
oC/W
MIN
TYP
MAX
UNITS
ISD = 3A
-
-
1.25
V
ISD = 3A, dISD/dt = 100A/µs
-
-
85
ns
Source to Drain Diode Ratings and Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
NOTES:
2. Pulsed: pulse duration = 300µs max, duty cycle = 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. Refer to Intersil Application Notes AN9321 and AN9322.
6-27
RFD3N08L, RFD3N08LSM
1.2
3.5
1.0
3.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves Unless Otherwise Specified
0.8
0.6
0.4
0.2
2.5
2.0
1.5
1.0
0.5
0
125
50
75
100
TC , CASE TEMPERATURE (oC)
25
0
150
0
25
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
50
75
100
125
TC, CASE TEMPERATURE (oC)
175
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE
1
0.5
PDM
0.2
0.1 0.1
t1
t2
0.05
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
30
IDM, PEAK CURRENT CAPABILITY (A)
20
ID, DRAIN CURRENT (A)
10
100µs
1ms
1
10ms
100ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
0.1
1
VDSS MAX = 80V
TC = 25oC
TJ = MAX RATED
DC
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
6-28
200
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I = I25
10
VGS = 10V
175 - TC
150
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1
10-5
10-4
TC = 25oC
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD3N08L, RFD3N08LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
10
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
VGS = 10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
20
STARTING TJ = 25oC
STARTING TJ = 150oC
8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
6
VGS = 5V
VGS = 4.5V
4
VGS = 4V
VGS = 3.5V
2
VGS = 3V
1
0.001
0.01
0.1
tAV, TIME IN AVALANCHE (ms)
0
1
0
2
4
6
8
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
10
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
8
-55oC
6
25oC
4
175oC
2
ID = 4A
2
ID = 3A
1.5
ID = 1.5A
1
2.5
3.5
4
4.5
3
VGS, GATE TO SOURCE VOLTAGE (V)
2
7.5
5
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 3A
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
0
1.5
3
4.5
6
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 8. TRANSFER CHARACTERISTICS
3
ID = 0.75A
0.5
0
0
NORMALIZED ON RESISTANCE
FIGURE 7. SATURATION CHARACTERISTICS
rDS(ON), ON-STATE RESISTANCE (Ω)
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
2
1.5
1
1.5
1
0.5
0.5
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
6-29
200
0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
RFD3N08L, RFD3N08LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
100
VDD = 40V, ID = 3A, RL = 13.3Ω
1.5
1.0
0.5
60
tf
40
td(OFF)
20
td(ON)
0
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
COSS
90
60
CRSS
30
0
0
30
40
50
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
VDS, DRAIN TO SOURCE VOLTAGE (V)
120
20
5.00
80
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
CISS
150
10
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
180
0
3.75
60
RL = 26.67Ω
IG(REF) = 0.1mA
VGS = 5V
2.50
40
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25BVDSS
20
0
25
20
IG(REF)
IG(ACT)
t, TIME (µs)
80
1.25
IG(REF)
IG(ACT)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-30
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
VGS, GATE TO SOURCE VOLTAGE (V)
0
-80
C, CAPACITANCE (pF)
tr
80
SWITCHING TIME (ns)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
RFD3N08L, RFD3N08LSM
Test Circuits and Waveforms
(Continued)
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
RG
-
VDD
10%
10%
0
DUT
90%
VGS
VGS
0
50%
10%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
DUT
Ig(REF)
VGS = 5V
VGS
-
VGS = 1V
0
Qg(TH)
IG(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
6-31
FIGURE 21. GATE CHARGE WAVEFORMS
RFD3N08L, RFD3N08LSM
PSPICE Electrical Model
SUBCKT RFD3N08L 2 1 3 ;
rev 5/10/95
CA 12 8 4.10e-10
CB 15 14 3.25e-10
CIN 6 8 1.10e-10
LDRAIN
DPLCAP
5
DRAIN
2
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL1
+51
RSCL2
EBREAK 11 7 17 18 93.57
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRESH 6 21 19 8 1
EZTEMPCO 20 6 18 22 1
5
ESCL
51
DBREAK
50
ESG
IT 8 17 1
EZTEMPCO
20 + 18
22
RGATE
RLGATE
16
EVTHRESH
+ 19
8
9
6
EBREAK
21
14
13
S1B
S2A
15
EGS
6
8
RSOURCE 7
3
SOURCE
RLSOURCE
RBREAK
18
17
S2B
+
MOS2
LSOURCE
13
CA
DBODY
CIN
RIN
8
S1A
12
13
8
+
17
18
MOS1
MOS1 16 6 8 8 MSTRONG M = 0.80
MOS2 16 21 8 8 MWEAK M = 0.20
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 174.2e-3
RGATE 9 20 24.9
RIN 6 8 1e9
RLDRAIN 2 5 10
RLGATE 1 9 58
RLSOURCE 3 7 58
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 200.2e-3
RTHRESH 22 8 RTHRESHMOD 1
RZTEMPCO 18 19 RZTEMPCOMOD 1
11
RDRAIN
6
8
+
LGATE
GATE
1
LDRAIN 2 5 1e-9
LGATE 1 9 5.8e-9
LSOURCE 3 7 5.8e-9
S1A
S1B
S2A
S2B
RLDRAIN
RZTEMPCO
CB
+
5
EDS 8
14
IT
19
VBAT
+
22
RTHRESH
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*10),6))}
.MODEL DBDMOD D (IS = 9.90e-14 RS = 6.00e-2 TRS1 = 1.42e-3 TRS2 = -3.58e-6 CJO = 1.40e-10 TT = 5.75e-8 M = 0.4)
.MODEL DBREAKMOD D (RS = 2.32 TRS1 = 1.03e-3 TRS2 = -6.17e-11)
.MODEL DPLCAPMOD D (CJO = 1.13e-10 IS = 1e-30 N = 10 M=0.6)
.MODEL MSTRONG NMOS (VTO = 1.773 KP = 1.70 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u)
.MODEL MWEAK NMOS (VTO = 1.496 KP = 2.09 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u)
.MODEL RBREAKMOD RES (TC1 = 8.19e-4 TC2 = 5.9e-7)
.MODEL RDRAINMOD RES (TC1 = 1.55e-2 TC2 = 8.58e-5)
.MODEL RDSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RSCLMOD RES (TC1 = 0 TC2 = 0)
.MODEL RTHRESHMOD RES (TC1 = -5.0e-4 TC2 = -6.0e-6)
.MODEL RZTEMPCOMOD RES (TC1 = -1.19e-3 TC2 = 1.12e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.2 VOFF= -3.2)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.2 VOFF= -5.2)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.60 VOFF= 4.4)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.4 VOFF= -0.60)
.ENDS
NOTE:
1. For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE
Power Electronics Specialist Conference Records, 1991.
6-32
RFD3N08L, RFD3N08LSM
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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6-33
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