ICM7242 ® Data Sheet February 9, 2007 FN2866.4 Long Range Fixed Timer Features The ICM7242 is a CMOS timer/counter circuit consisting of an RC oscillator followed by an 8-bit binary counter. It will replace the 2242 in most applications, with a significant reduction in the number of external components. • Replaces the 2242 in Most Applications Three outputs are provided. They are the oscillator output, and buffered outputs from the first and eighth counters. • Monostable or Astable Operation Ordering Information • Low Supply Current . . . . . . . . . . . . . . . . . . . . 115µA at 5V PART TEMP. PART NUMBER MARKING RANGE (°C) PACKAGE PKG. DWG. # ICM7242IPA 7242 IPA -25 to +85 8 Ld PDIP E8.3 ICM7242IPAZ (See Note) 7242 IPAZ -25 to +85 8 Ld PDIP** (Pb-free) E8.3 0 to +70 8 Ld SOIC (Pb-free) M8.15 -25 to +85 8 Ld SOIC (Pb-free) M8.15 ICM7242CBAZ* 7242 CBAZ ICM7242IBAZ* 7242 IBAZ *Add “-T” suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. • Timing From Microseconds to Days • Cascadable • Wide Supply Voltage Range . . . . . . . . . . . . . . . 2V to 16V • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout ICM7242 (8 LD PDIP, SOIC) TOP VIEW VDD 1 8 TB I/O ÷2 OUT 2 7 RC ÷128/256 OUT 3 6 TRIGGER VSS 4 5 RESET NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1996, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ICM7242 Functional Block Diagram R1 50k CL Q CL Q S Q CL Q + Q S Q S S - R2 86k R + S Q R Q R3 50k Q Q - 7 RC Q Q CL CL CL Q Q S Q CL S Q S 1 4 8 5 VDD VSS TB I/O RESET 2 Q CL Q S 6 2 3 TRIGGER ÷2 OUT ÷128/256 OUTPUT FN2866.4 February 9, 2007 ICM7242 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD to VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Input Voltage (Note 1) Terminals (Pins 5, 6, 7, 8). . . . . . . . . . (VSS -0.3V) to (VDD +0.3V) Continuous Output Current (Each Output). . . . . . . . . . . . . . . . 50mA Thermal Resistance (Typical, Note2) θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range ICM7242I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25°C to +85°C ICM7242C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same supply be applied to the device before its supply is established and, that in multiple supply systems, the supply to the ICM7242 be turned on first. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = 5V, TA = +25°C, R = 10kΩ, C = 0.1µF, VSS = 0V, Unless Otherwise Specified PARAMETER SYMBOL Guaranteed Supply Voltage VDD Supply Current IDD TEST CONDITIONS MIN TYP MAX UNITS 2 - 16 V Reset - 125 - µA Operating, R = 10kΩ, C = 0.1µF - 340 800 µA Operating, R = 1MΩ, C = 0.1µF - 220 600 µA TB Inhibited, RC Connected to VSS - 225 - µA - 5 - % Timing Accuracy RC Oscillator Frequency Temperature Drift Δf/Δt Independent of RC Components - 250 - ppm/°C Time Base Output Voltage VOTB ISOURCE = 100µA - 3.5 - V ISINK = 1.0mA - 0.40 - V Time Base Output Leakage Current ITBLK RC = Ground - - 25 µA Trigger Input Voltage VTRIG VDD = 5V - 1.6 2.0 V VDD = 15V - 3.5 4.5 V VDD = 5V - 1.3 2.0 V VDD = 15V - 2.7 4.0 V - 10 - µA - 1 - MHz 2 6 - MHz - 13 - MHz Reset Input Voltage VRST Trigger/Reset Input Current ITRIG, IRST Max Count Toggle Rate fT VDD = 2V VDD = 5V Counter/Divider Mode VDD = 15V 50% Duty Cycle Input with Peak to Peak Voltages Equal to VDD and VSS Output Saturation Voltage VSAT All Outputs Except TB Output VDD = 5V, IOUT = 3.2mA - 0.22 0.4 V Output Sourcing Current ISOURCE VDD = 5V Terminals 2 and 3, VOUT = 1V - 300 - µA 10 - - pF 1k - 22M Ω MIN Timing Capacitor (Note 3) CT Timing Resistor Range (Note 3) RT VDD = 2 - 16V NOTE: 3. For design only, not tested. 3 FN2866.4 February 9, 2007 ICM7242 Test Circuit VDD ÷21 (RC/2) OUTPUT ÷28 (RC/256) OUTPUT 1 8 2 7 3 6 4 5 RESET TIME BASE INPUT/OUTPUT VDD C R TRIGGER TIME BASE PERIOD = 1.0RC; 1s = 1MΩ x 1µF NOTE: 4. ÷21 and ÷28 outputs are inverters and have active pullups. Application Information Operating Considerations Shorting the RC terminal or output terminals to VDD may exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages). There is a limitation of 50pF maximum loading on the TB I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount. For greatest accuracy, use timing component values shown in Figure 8. For highest frequency operation it will be desirable to use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200kHz. The timing capacitor should be connected between the RC pin and the positive supply rail, VDD , as shown in Figure 1. When system power is turned off, any charge remaining on the capacitor will be discharged to ground through a large internal diode between the RC node and VSS. Do NOT reference the timing capacitor to ground, since there is no high current path in this direction to safely discharge the capacitor when power is turned off. The discharge current from such a configuration could potentially damage the device. When driving the counter section from an external clock, the optimum drive waveform is a square wave with an amplitude equal to the supply voltage. If the clock is a very slow ramp triangular, sine wave, etc., it will be necessary to “square up” the waveform; this can be done by using two CMOS inverters in series, operating from the same supply voltage as the ICM7242. The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and long range timers; it makes a much better low frequency oscillator/timer than a 555 or ICM7555, because of the onchip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency signals. external resistors used for the 2242 will not be required for the ICM7242. The ICM7242 will, however, plug into a socket for the 2242 having these resistors. The timing diagram for the ICM7242 is shown in Figure 1. Assuming that the device is in the RESET mode, which occurs on power up or after a positive signal on the RESET terminal (if TRIGGER is low), a positive edge on the trigger input signal will initiate normal operation. The discharge transistor turns on, discharging the timing capacitor C, and all the flip-flops in the counter chain change states. Thus, the outputs on terminals 2 and 3 change from high to low states. After 128 negative timebase edges, the ÷28 output returns to the high state. TRIGGER INPUT (TERMINAL 6) TIMEBASE INPUT (TERMINAL 8) ÷2 OUTPUT (TERMINAL 2) 128RC ÷128/256 OUTPUT (TERMINAL 3) (ASTABLE OR “FREE RUN” MODE) 128RC ÷128/256 OUTPUT (TERMINAL 3) (MONOSTABLE OR “ONE SHOT” MODE) 128RC FIGURE 1. TIMING DIAGRAMS OF OUTPUT WAVEFORMS FOR THE ICM7242 (COMPARE WITH FIGURE 5) VDD fIN/2 OUTPUTS fIN/256 fIN 1 8 2 7 3 6 4 5 >3/4 (V+) <1/4 (V+) VDD FIGURE 2. USING THE ICM7242 AS A RIPPLE COUNTER (DIVIDER) Because outputs will not be ANDed, output inverters are used instead of open drain N-Channel transistors, and the 4 FN2866.4 February 9, 2007 ICM7242 To use the 8-bit counter without the timebase, Terminal 7 (RC) should be connected to ground and the outputs taken from Terminals 2 and 3. The ICM7242 may be used for a very low frequency square wave reference. For this application the timing components are more convenient than those that would be required by a 555 timer. For very low frequencies, devices may be cascaded (see Figure 3). VDD 1 8 2 R 1 8 7 2 7 3 6 3 6 4 5 4 5 C ICM7242 ICM7242 TABLE 1. COMPARING THE ICM7242 WITH THE 2242 CHARACTERISTICS ICM7242 2242 2V to 16V 4V to 15V Operating Temperature Range -25°C to 85°C 0°C to 70°C Supply Current, VDD = 5V 0.7mA (Max) 7mA (Max) TB Output No Yes ÷2 Output No Yes ÷256 Output No Yes 3.0MHz 0.5MHz Resistor to Inhibit Oscillator No Yes Resistor in Series with Reset for Monostable Operation No Yes Capacitor TB Terminal for HF Operation No Sometimes Operating Voltage Pullup Resistors Toggle Rate f = RC/216 FIGURE 3. LOW FREQUENCY REFERENCE (OSCILLATOR) For monostable operation the ÷28 output is connected to the RESET terminal. A positive edge on TRIGGER initiates the cycle (NOTE: TRIGGER overrides RESET). By selection of R and C, a wide variety of sequence timing can be realized. A typical flow chart for a machine tool controller could be as shown in Figure 5. VDD 1 R 8 2 C 7 ICM7242 OUTPUT 3 TRIGGER 6 4 5 ICM7242 ICM7242 WAIT 5s ENABLE 10s ENABLE 5s COUNT TO 185 WAIT 5s ICM7242 ICM7240 ICM7242 TRIGGERING CAN BE OBTAINED FROM A PREVIOUS STAGE, START A LIMIT SWITCH, -OPERATOR SWITCH, ETC. S1 STOP RESET 100kΩ START TRIGGER TERMINAL 6 TB OUTPUT TERMINAL 8 OUTPUT TERMINAL 3 STOP WAIT 5s ENABLE 10s WAIT 5s COUNT TO 185 ENABLE 5s FIGURE 5. FLOW CHART FOR MACHINE TOOL CONTROLLER FIGURE 4. MONOSTABLE OPERATION The ICM7242 is superior in all respects to the 2242 except for initial accuracy and oscillator stability. This is primarily due to the fact that high value p-resistors have been used on the ICM7242 to provide the comparator timing points. By cascading devices, use of low cost CMOS AND/OR gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical applications include injection molding machine controllers, phonograph record production machines, automatic sequencers (no metal contacts or moving parts), milling machine controllers, process timers, automatic lubrication systems, etc. Sequence Timing • Process Control • Machine Automation • Electro-Pneumatic Drivers • Multi Operation (Serial or Parallel Controlling) 5 FN2866.4 February 9, 2007 ICM7242 VDD VDD R (NOTE) C TRIGGER VDD R (NOTE) C A 6 S1 50k 3 ICM7242 A 33k 100pF 10k ICM7242 B 33k D 1µF 6 3 R (NOTE) C C 1µF 6 5 R (NOTE) C B 1µF VDD VDD 10k ICM7242 C 5 100pF 3 6 33k 5 10k 3 ICM7242 D 100pF 33k 5 100pF PUSH S1 TO START SEQUENCE: MUST BE SHORTER THAN “ON TIMEA” TRIGGER 128RC OUTPUT A (NOTE) 128RC OUTPUT B (NOTE) 128RC OUTPUT C (NOTE) 128RC OUTPUT D (NOTE) ON TIMEA NOTE: ON TIMEB ON TIMEC ON TIMED Select RC values for desired “ON TIME” for each ICM7242. FIGURE 6. SEQUENCE TIMER 6 FN2866.4 February 9, 2007 ICM7242 Typical Performance Curves 100M 260 240 TA = -20°C 10M TIMING RESISTOR, R (Ω) SUPPLY CURRENT (µA) 220 200 180 160 TA = +25°C 140 120 TA = +75°C 100 80 60 RECOMMENDED RANGE OF TIMING COMPONENT VALUES 100k 10k 1k RESET MODE 40 1M TA = +25°C 20 100 100pF 0.001 0 0 2 4 6 8 10 12 14 16 0.01 FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE VDD = 5.0V 1,000 TRIGGER PULSE WIDTH (ns) CAPACITANCE (µF) TA = +25°C 10kΩ 10 100kΩ 1 0.1 0.01 1MΩ 1kΩ 0.001 100p 10MΩ 10p 1p 0.1 1 10 100 1k 10k 100k 1M 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 10M VDD = 16V VDD = 5V VDD = 2V 0 1 2 3 VDD = 5V VDD = 2V VDD = 16V 2 3 4 5 6 7 RESET AMPLITUDE (V) 8 9 FIGURE 11. MINIMUM RESET PULSE WIDTH vs RESET AMPLITUDE 7 4 5 6 7 8 9 10 FIGURE 10. MINIMUM TRIGGER PULSE WIDTH vs TRIGGER AMPLITUDE NORMALIZED FREQUENCY DEVIATION (%) RESET PULSE WIDTH (ns) TA = 25°C 1 1000 10,000 TRIGGER AMPLITUDE (V) FIGURE 9. TIMEBASE FREE RUNNING FREQUENCY vs R AND C 0 100 TA = +25°C TIME BASE FREQUENCY (Hz) 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 10 FIGURE 8. RECOMMENDED RANGE OF TIMING COMPONENT VALUES FOR ACCURATE TIMING 10,000 100 1 0.1 TIMING CAPACITOR, C (µF) SUPPLY VOLTAGE (V) 10 +10.0 TA = +25°C +8.0 +6.0 +4.0 +2.0 0.0 -2.0 R C 10kΩ 1MΩ 1kΩ 100kΩ 10kΩ 100kΩ 0.001µF 100pF 0.1µF 0.001µF 0.01µF 0.01µF -4.0 -6.0 -8.0 -10.0 2 4 6 10 12 14 8 SUPPLY VOLTAGE (V) 16 18 20 FIGURE 12. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE MODE vs SUPPLY VOLTAGE FN2866.4 February 9, 2007 ICM7242 (Continued) 100M +5 +4 MAXIMUM DIVIDER FREQUENCY (Hz) NORMALIZED FREQUENCY DEVIATION (%) Typical Performance Curves 5V ≤ VDD ≤ 15V +3 R = 10MΩ C = 0.1µF +2 +1 R = 1kΩ C = 0.1µF 0 -1 -2 -3 -4 -5 -25 10M TA = +25°C RC CONNECTED TO GROUND 1M 100k 10k 0 25 50 75 0 2 4 TEMPERATURE (°C) 12 14 16 18 20 100 TA = +25°C OUTPUT SATURATION CURRENT (mA) DISCHARGE SINK CURRENT (mA) 10 FIGURE 14. MAXIMUM DIVIDER FREQUENCY vs SUPPLY VOLTAGE VDD = 15V VDD = 5V 10 VDD = 2V 1 0.1 0.01 8 SUPPLY VOLTAGE (V) FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE MODE vs TEMPERATURE 100 6 0.1 1 10 DISCHARGE SATURATION VOLTAGE (V) FIGURE 15. DISCHARGE OUTPUT CURRENT vs DISCHARGE OUTPUT VOLTAGE 8 TA = +25°C VDD = 15V VDD = 5V 10 VDD = 2V 1 0.1 0.01 0.1 1 10 OUTPUT SATURATION VOLTAGE (V) FIGURE 16. OUTPUT SATURATION CURRENT vs OUTPUT SATURATION VOLTAGE FN2866.4 February 9, 2007 ICM7242 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 5 D1 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 8 2.54 BSC - 7.62 BSC 0.430 - 0.150 2.93 8 6 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 9 FN2866.4 February 9, 2007 ICM7242 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 8 0° 8 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN2866.4 February 9, 2007