Datasheet

UNISONIC TECHNOLOGIES CO., LTD
S3525
CMOS IC
PC POWER SUPPLY
SUPERVISOR
„
DESCRIPTION
The UTC S3525 is specially designed for switching power supply
system. it provides protection circuits, power good output (PGO)
indicator, fault protection output (FPOB) and a PSONB control.
The protection circuits include over voltage protection (OVP),
under voltage protection (UVP) and over current protection (OCP)
monitoring for system voltages and currents.
When 3.3V, 5V or 12V voltage is decreasing to 2.68V, 4.3V and
9.9V respectively, the under voltage protection (UVP) function will be
enabled. FPOB will be set to high to turn off the PWM controller IC.
Toggling the PSONB from low to high will reset the fault protection
latch.
The voltage difference across external current shunt is used for
OCP functions. An external resistor can be used to adjust protection
threshold.
The power supply is turned on after 38mS delay time when
PSONB signal is set from high to low. To turn off power supply,
PSONB signal is set from low to high with the delay time 38mS. The
PGI circuitry provides a power-down warning signal for PGO. When
PGI input is lower than the internal 1.20V reference voltage, PGO
signal is pulled low.
„
FEATURES
* OVP/UVP monitors 3.3V, 5V, 12V input voltage level.
* OCP monitors IS33, IS5, IS12 input current sense.
* Fault protection output (FPOB) with Open Drain Output stage.
* Power good output (PGO) with Open Drain Output stage.
* 38ms de-bounce time for PSONB input signal.
* 300ms time delay from PGI to PGO.
* 2.4ms time delay for PSONB to turn off FPOB.
„
ORDERING INFORMATION
Ordering Number
Lead Free Plating
Halogen Free
S3525L-D14-T
S3525G-D14-T
S3525L-S14-R
S3525G-S14-R
S3525L-S14-T
S3525G-S14-T
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Copyright © 2010 Unisonic Technologies Co., Ltd
Package
Packing
DIP-14
SOP-14
SOP-14
Tube
Tape Reel
Tube
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S3525
CMOS IC
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PIN ASSIGNMENT
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FUNCTION DESCRIPTION
PGI
PSONB
UV&OC Protection OV Protection
PGI<1.2V
L
No
No
PGI<1.2V
L
No
Yes
PGI<1.2V
L
Yes
No
PGI<1.2V
L
Yes
Yes
PGI>1.2V
L
No
No
PGI>1.2V
L
No
Yes
PGI>1.2V
L
Yes
No
PGI>1.2V
L
Yes
Yes
X
H
X
X
Note: FPOB=L means: fault is not latched. FPOB=H means: fault is latched
PGO=L means: fault. PGO=H means: No fault
X=do not care
„
FPOB
L
H
L
H
L
H
H
H
H
PGO
L
L
L
L
H
L
L
L
L
PIN DESCRIPTIONS
PIN NO.
PIN NAME
TYPE
1
PGI
Input
2
GND
Supply
3
FPOB
Output
4
PSONB
Input
5
IS12AB
Input
6
RI
Input
7
8
9
10
11
12
13
V12B
IS5
IS33
V12A
V33
V5
VDD
Input
Input
Input
Input
Input
Input
Supply
14
PGO
Output
DESCRIPTION
Power Good Input. For ATX SMPS, it detects AC line voltage through the
main transformer.
Ground
Fault Protection Output. Output signal to control the primary PWM IC through
an opto-coupler. When FPOB is low, the PWM IC is enabled.
Remote On/Off logic input from CPU or main-board. The power supply will
be turned on/off after 38mS delay.
12V AB over current protection.
Reference setting. One external resistor Ri connected between RI and GND
pin will determine a reference current, IREF = 1.20/Ri, for OCP programming.
12V over/under voltage protection.
5V over current protection.
3.3V over current protection
12V over/under voltage protection.
3.3V over/under voltage protection
5V over/under voltage protection.
Power supply.
Power good logic output, 0 or 1(open-drain). Power good=1 means that the
power supply is good for operation. The power good delay is 300mS.
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CMOS IC
BLOCK DIAGRAM
V cc
PGI
Bandgap
Reference
VREF=1.2V
+
UN
-
73 μs
debounce
clr
PGO
225ms
delay
V12A
IS33
+
I REF*8
VS33
73 μs
debounce
+
OV
+
UN
V12A
IS12AB
Power On Reset
+
IREF*8
VS12A
2.4ms
+
UN
V12A
PWR
Internal
Power
VCCI=3.6V
38 ms
debounce
delay
+
OV
-
FPOB
RQ
S Q
PSONB
75ms/ 300ms
delay
+
-
VS12B
+
OV
+
UN
V12A
IS5
PWR
OSC
CLK
+
-
V12A
IREF*8
VS5
+
OV
+
UN
-
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VREF=1.2V
+
RI
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CMOS IC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
UNIT
-0.3 ~ 16
V
V5,V33, PSONB, IS5, IS33
-0.3 ~ 7
V
Input Voltage
VIN
IS12AB, V12B
-0.3 ~ 16
V
PGI
-0.3 ~ VDD+0.3
V
FPOB
-0.3 ~ 7
V
Output Voltage
VOUT
PGO
-0.3 ~ 7
V
Operating Temperature
TOPR
-40 ~ +125
°C
Storage Temperature
TSTG
-55 ~ +150
°C
Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
Supply Voltage, VDD, V12A
„
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
VDD
Supply Voltage VDD
Supply Voltage VCC2
Input Voltage
Output Voltage
Output Sink Current
V5,V33 ,PGI ,PSONB
V12A, V12B
FPOB
PGO
FPOB
PGO
TYP
12
12
VIN
VOUT
IO(SINK)
RI Output Current
Supply Voltage Rising Time (VDD)
„
MIN
4
9.5
IO(RI)
tR
10
1
MAX
15
15
7
15
7
7
30
10
65
UNIT
V
V
V
V
V
V
mA
mA
uA
ms
ELECTRICAL CHARACTERISTICS (Ta=25°C and VDD=5V and V12A=12V)
PARAMETER
Over Voltage Detection
Over Voltage Threshold
SYMBOL
V12A, V12B
V5
V33
Low Level Output Voltage (FPOB)
VOL
Output Leakage Current (FPOB)
PSONB
High-Level Input Voltage
Low-Level Input Voltage
Input Pull-up Current
PGI and PGO
ILEAK
Under Voltage Threshold
Input Threshold Voltage (PGI)
Low Level Output Voltage (PGO)
Output Leakage Current (PGO)
VIH
VIL
IIN
MIN
TYP
MAX UNIT
13.2
5.7
3.7
13.8
6.1
3.9
14.4
6.5
4.1
0.3
0.7
5
ISINK=10mA
ISINK=30mA
V(FPOB)=5V
2
PSONB=0V
V12A, V12B
V5
V33
VI(THD)
VOL
ISINK=10mA
ILEAK
PGO=5V
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TEST CONDITIONS
10
4.30
2.69
1.20
V
uA
0.8
V
V
uA
10.5
4.47
2.83
1.24
0.4
5
V
V
V
V
V
uA
120
9.5
4.1
2.55
1.16
V
V
V
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CMOS IC
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
SWITCHING CHARACTERISTICS
PSONB ON(PSONB Low to FPOB Low)
PSONB OFF(PSONB Hi to PGO Low)
PGI to PGO Delay Time
Timing PGO Low to FPOB high
UVD/OCD Turn on Delay Time
Noise Deglitch Time
Noise Deglitch Time for Latch
TOTAL DEVICE
Low Voltage
Supply Current
SYMBOL
T(PSONB ON)
T(PSONB OFF)
TPG
TPSOFF
TUVP1
TUVP2
tg1
tg2
VDD
IDD
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TEST CONDITIONS
VDD=5V
VDD=5V
VDD=5V
VDD=5V
FPOB=Low & PGI > 1.2V
FPOB=Low & PGI < 1.2V
MIN
TYP
MAX UNIT
32
32
200
2.0
65
260
63
63
38
38
300
2.4
75
300
75
75
62
62
490
4
122
488
120
120
ms
ms
ms
ms
ms
ms
μs
μs
1
V
mA
3.0
PSONB=5V
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CMOS IC
APPLICATION INFORMATION
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CMOS IC
APPLICATION INFORMATION
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CMOS IC
TYPICAL TIMMING DIAGRAM
1) PGI (UNDER-VOLTAGE):
2) V33, V5, V12A, V12B (UNDER-VOLTAGE) or IS33, IS5, IS12AB (OVER-CURRENT):
tUVP2 = 300ms
PSONB
t PSOFF
tUVP2 + t g2
FPOB
t(PSONB ON)
t(PSONB ON)
PGO
t PG +t g1
t(PSONB OFF)
PGI
V33 /V5 /V12
IS33 /IS5 /IS12
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CMOS IC
TYPICAL TIMMING DIAGRAM(Cont.)
3) V33, V5, V12A, V12B (OVER-VOLTAGE).
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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