IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER™ IDT5T915 DESCRIPTION: FEATURES: The IDT5T915 2.5V differential (DDR) clock buffer is a user-selectable single-ended or differential input to five differential outputs built on advanced metal CMOS technology. The differential clock buffer fanout from a single or differential input to five differential or single-ended outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T915 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The IDT5T915 true or complementary outputs can be asynchronously enabled/disabled. Multiple power and grounds reduce noise. • • • • • • • • Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion < 300ps (max) High speed propagation delay < 2ns (max) Up to 250MHz operation Very low CMOS power levels Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface • Selectable differential or single-ended inputs and five differential outputs • 2.5V VDD • Available in TSSOP package APPLICATIONS: • Clock and signal distribution FUNCTIONAL BLOCK DIAGRAM TxS GL G(+) OUTPUT CONTROL Q1 OUTPUT CONTROL Q1 OUTPUT CONTROL Q2 OUTPUT CONTROL Q2 OUTPUT CONTROL Q3 OUTPUT CONTROL Q3 OUTPUT CONTROL Q4 OUTPUT CONTROL Q4 OUTPUT CONTROL Q5 OUTPUT CONTROL Q5 RxS A A/VREF G(-) The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE FEBRUARY 2003 1 © 2003 Integrated Device Technology, Inc. DSC-5893/21 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD GL 1 48 Description Power Supply Voltage(2) Supply(2) Max Unit –0.5 to +3.6 V –0.5 to +3.6 V –0.5 to +3.6 V GND VDDQ Output Power VI Input Voltage VO Output Voltage(3) –0.5 to VDDQ +0.5 V VREF Reference Voltage(3) –0.5 to +3.6 V VDD 2 47 VDDQ VDD 3 46 VDDQ GND 4 45 GND TSTG Storage Temperature –65 to +165 °C GND 5 44 GND TJ Junction Temperature 150 °C G(+) 6 43 GND VDDQ 7 42 VDDQ Q1 8 41 Q2 Q1 9 40 Q2 GND 10 39 GND VDDQ 11 38 VDDQ A/VREF 12 37 Q3 A 13 36 Q3 VDDQ 14 35 VDDQ GND 15 34 GND Q5 16 33 Q4 Q5 17 32 Q4 VDDQ 18 31 VDDQ G(-) 19 30 VDDQ GND 20 29 GND GND 21 28 GND VDD 22 27 VDDQ VDD 23 26 GND RxS 24 25 TxS NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V. CAPACITANCE(1,2) (TA = +25°C, F = 1.0MHz) Symbol CIN Parameter Min Typ. Max. Unit Input Capacitance — 3.5 — pF NOTES: 1. This parameter is measured at characterization but not tested. 2. Capacitance applies to all inputs except RxS and TxS. TSSOP TOP VIEW RECOMMENDED OPERATING RANGE Symbol TA VDD(1) VDDQ(1) VT Description Ambient Operating Temperature Internal Power Supply Voltage HSTL Output Power Supply Voltage Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 2.5V LVTTL Output Power Supply Voltage Termination Voltage Min. –40 2.4 1.4 1.65 Typ. +25 2.5 1.5 1.8 VDD VDDQ / 2 Max. +85 2.6 1.6 1.95 NOTE: 1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa. 2 Unit °C V V V V V IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol A A/VREF I/O I I Type Adjustable(1) Adjustable(1) VDD VDDQ PWR PWR Description Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input. Complementary clock input. A/VREF is the "complementary" side of A if the input is in differential mode. If operating in single-ended mode, A/VREF is connected to GND. For single-ended operation in differential mode, A/VREF should be set to the desired toggle voltage for A: 2.5V LVTTL VREF = 1250mV 1.8V LVTTL, eHSTL VREF = 900mV HSTL VREF = 750mV LVEPECL VREF = 1082mV Gate control for "true", Qn, outputs. When G(+) is LOW, the "true" outputs are enabled. When G(+) is HIGH, the "true" outputs are asynchronously disabled to the level designated by GL(4). Gate control for "complementary", Qn, outputs. When G(-) is LOW, the "complementary" outputs are enabled. When G(-) is HIGH, the "complementary" outputs are asynchronously disabled to the opposite level as GL(4). Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputs disable LOW and "complementary" outputs disable HIGH. Clock outputs Complementary clock outputs Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in conjuction with VDDQ to set the interface levels. Power supply for the device core and inputs Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be connected to VDD. G(+) I LVTTL(5) G(-) I LVTTL(5) GL I LVTTL(5) Qn Qn RxS TxS O O I I Adjustable(2) Adjustable(2) 3 Level(3) 3 Level(3) GND PWR Power supply return for all power NOTES: 1. Inputs are capable of translating the following interface standards. User can select between: Single-ended 2.5V LVTTL levels Single-ended 1.8V LVTTL levels or Differential 2.5V/1.8V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL levels 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage. 3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant. 4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID. 3 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE INPUT/OUTPUT SELECTION(1) Input Output 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL Input 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 2.5V LVTTL DSE 1.8V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE LVEPECL DSE eHSTL DSE eHSTL DSE HSTL DSE HSTL DSE 2.5V LVTTL DIF 2.5V LVTTL DIF 1.8V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF LVEPECL DIF eHSTL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE Output eHSTL HSTL DIF 2.5V LVTTL SE 1.8V LVTTL HSTL 1.8V LVTTL SE 2.5V LVTTL DSE 2.5V LVTTL DSE 1.8V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE LVEPECL DSE eHSTL DSE eHSTL DSE HSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF eHSTL DIF HSTL DIF NOTE: 1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF. Differential (DIF) inputs are used only in differential mode. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol VIHH VIMM VILL I3 Parameter Input HIGH Voltage Level(1) Input MID Voltage Level(1) Input LOW Voltage Level(1) 3-Level Input DC Current (RxS, TxS) Test Conditions 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD VIN = VDD/2 VIN = GND HIGH Level MID Level LOW Level NOTE: 1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. 4 Min. VDD – 0.4 VDD/2 – 0.2 — — –50 –200 Max — VDD/2 + 0.2 0.4 200 +50 — Unit V V V µA IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current(9) IIL Input LOW Current(9) VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2,8) VCM DC Common Mode Input Voltage(3,8) VIH DC Input HIGH(4,5,8) VIL DC Input LOW(4,6,8) Single-Ended Reference Voltage(4,8) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA IOH = -8mA IOH = -100µA IOL = 8mA IOL = 100µA Min. Typ.(7) Max Unit — — — - 0.3 0.2 680 VREF + 100 — — — — - 0.7 ±5 ±5 - 1.2 +3.6 — 900 — VREF - 100 — µA V V V mV mV mV mV — — 0.4 0.1 V V V V 750 750 VDDQ - 0.4 VDDQ - 0.1 — — NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail. POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current IDDQQ Quiescent VDDQ Power Supply Current IDDD ITOT Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current ITOTQ Total Power VDDQ Supply Current IDDDQ Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF Typ. 20 Max 30 Unit mA 0.1 0.3 mA 20 30 µA/MHz VDD = Max., VDDQ = Max., CL = 0pF 30 50 µA/MHz VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF 20 35 35 60 40 50 70 120 mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. 5 mA IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL Symbol Parameter VDIF Input Signal Swing(1) VX Differential Input Signal Crossing Point VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate (2) Value Units 1 V 750 mV Crossing Point V 1 V/ns (4) NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current(9) IIL Input LOW Current(9) VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2,8) VCM DC Common Mode Input Voltage(3,8) VIH DC Input HIGH(4,5,8) VIL DC Input LOW(4,6,8) VREF Single-Ended Reference Voltage(4,8) Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA IOH = -8mA IOH = -100µA IOL = 8mA IOL = 100µA Min. Typ.(7) Max Unit — — — - 0.3 0.2 800 VREF + 100 — — — — - 0.7 ±5 ±5 - 1.2 +3.6 — 1000 — VREF - 100 — µA V V V mV mV mV mV — — 0.4 0.1 V V V V VDDQ - 0.4 VDDQ - 0.1 — — 900 900 NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail. 6 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current IDDQQ Quiescent VDDQ Power Supply Current IDDD ITOT Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current ITOTQ Total Power VDDQ Supply Current IDDDQ Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF Typ. 20 Max 30 Unit mA 0.1 0.3 mA 20 30 µA/MHz VDD = Max., VDDQ = Max., CL = 0pF 40 60 µA/MHz VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF 20 35 40 80 40 50 80 160 mA mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL Symbol Parameter Value Units VDIF Input Signal Swing (1) 1 V VX Differential Input Signal Crossing Point(2) 900 mV VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate(4) Crossing Point V 1 V/ns NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVEPECL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current(6) IIL Input LOW Current(6) VIK Clamp Diode Voltage VIN DC Input Voltage VCM DC Common Mode Input Voltage(3,5) VREF Single-Ended Reference Voltage(4,5) VIH DC Input HIGH DC Input LOW VIL Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. Typ.(2) Max Unit — — — - 0.3 915 — 1275 555 — — - 0.7 — 1082 1082 — — ±5 ±5 - 1.2 3.6 1248 — 1620 875 µA V V mV mV mV mV NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25°C ambient. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation while in differential mode, A/VREF is tied to the DC Voltage VREF. 5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail. 7 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL Symbol Parameter Value Units VDIF (1) Input Signal Swing 732 mV VX Differential Input Signal Crossing Point(2) 1082 mV VTHI Input Timing Measurement Reference Level(3) Crossing Point V tR, tF Input Signal Edge Rate 1 V/ns (4) NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V LVTTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current(10) IIL Input LOW Current(10) VIK Clamp Diode Voltage VIN DC Input Voltage Single-Ended Inputs(2) VIH DC Input HIGH VIL DC Input LOW Differential Inputs VDIF DC Differential Voltage(3,9) VCM DC Common Mode Input Voltage(4,9) VIH DC Input HIGH(5,6,9) VIL DC Input LOW(5,7,9) VREF Single-Ended Reference Voltage(5,9) Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. Typ.(8) Max Unit — — — - 0.3 — — - 0.7 ±5 ±5 - 1.2 +3.6 µA — 0.7 V V — 1350 — VREF - 100 — V mV mV mV mV — — 0.4 0.1 V V V V 1.7 — 0.2 1150 VREF + 100 — — IOH = -12mA IOH = -100µA IOL = 12mA IOL = 100µA VDDQ - 0.4 VDDQ - 0.1 — — 1250 1250 V V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail. 8 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current IDDQQ Quiescent VDDQ Power Supply Current IDDD ITOT Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current ITOTQ Total Power VDDQ Supply Current IDDDQ Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF Typ. 20 Max 30 Unit mA 0.1 0.3 mA 25 40 µA/MHz VDD = Max., VDDQ = Max., CL = 0pF 45 70 µA/MHz VDDQ = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF VDDQ = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF 25 45 40 100 40 70 80 200 mA mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL Symbol Parameter Value Units VDIF Input Signal Swing (1) VDD V VX Differential Input Signal Crossing Point(2) VDD/2 V VTHI Input Timing Measurement Reference Level tR, tF Input Signal Edge Rate(4) (3) Crossing Point V 2.5 V/ns NOTES: 1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL Symbol Parameter Value Units VIH Input HIGH Voltage VDD V VIL Input LOW Voltage 0 V VTHI Input Timing Measurement Reference Level(1) tR, tF Input Signal Edge Rate(2) VDD/2 V 2 V/ns NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform. 9 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V LVTTL(1) Symbol Parameter Input Characteristics IIH Input HIGH Current(12) IIL Input LOW Current(12) VIK Clamp Diode Voltage DC Input Voltage VIN Single-Ended Inputs(2) VIH DC Input HIGH DC Input LOW VIL Differential Inputs VDIF DC Differential Voltage(3,9) VCM DC Common Mode Input Voltage(4,9) VIH DC Input HIGH(5,6,9) VIL DC Input LOW(5,7,9) Single-Ended Reference Voltage(5,9) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA IOH = -6mA IOH = -100µA IOL = 6mA IOL = 100µA Min. Typ.(8) Max Unit — — — - 0.3 — — - 0.7 ±5 ±5 - 1.2 VDDQ + 0.3 µA 1.073(11) — — 0.683(11) V V 0.2 825 VREF + 100 — — — 975 — VREF - 100 — V mV mV mV mV — — 0.4 0.1 V V V V VDDQ - 0.4 VDDQ - 0.1 — — 900 900 V V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply. 11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIL = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply. 12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail. 10 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1) Symbol IDDQ Parameter Quiescent VDD Power Supply Current IDDQQ Quiescent VDDQ Power Supply Current IDDD ITOT Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current ITOTQ Total Power VDDQ Supply Current IDDDQ Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF Typ. 20 Max 30 Unit mA 0.1 0.3 mA 20 40 µA/MHz VDD = Max., VDDQ = Max., CL = 0pF 55 80 µA/MHz VDDQ = 1.8V., FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V., FREFERENCE CLOCK = 200MHz, CL = 15pF VDDQ = 1.8V., FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V., FREFERENCE CLOCK = 200MHz, CL = 15pF 25 40 50 120 40 60 100 240 mA mA NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH. DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL Symbol Parameter Value Units VDIF Input Signal Swing (1) VDDI V VX Differential Input Signal Crossing Point(2) VDDI/2 mV VTHI Input Timing Measurement Reference Level(3) tR, tF Input Signal Edge Rate(4) Crossing Point V 1.8 V/ns NOTES: 1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform. SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL Symbol Parameter Value VIH Input HIGH Voltage VIL Input LOW Voltage VTHI Input Timing Measurement Reference Level(2) tR, tF Input Signal Edge Rate(3) (1) VDDI V 0 V VDDI/2 mV 2 V/ns NOTES: 1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. 2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform. 11 Units IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(5) Symbol Skew Parameters tSK(O) tSK(INV) tSK(P) tSK(PP) Parameter tPLH Typ. Max Unit Same Device Output Pin-to-Pin Skew(1) Single-Ended and Differential Modes — — 25 ps Inverting Skew(2) Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes — — 25 — — 300 ps Pulse Skew(3) Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes — — 300 — — 300 ps Part-to-Part Skew(4) Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes — — 300 — — 300 ps Single-Ended in Differential Mode (DSE) VOX Propagation Delay Min. — 300 — VDDQ/2 - 200 VDDQ/2 VDDQ/2 + 200 mV 2.5V / 1.8V LVTTL Outputs — — 2.5 ns HSTL / eHSTL Outputs — — 2 350 — 1050 1350 HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level Propagation Delay A to Qn/Qn tPHL tR Output Rise Time (20% to 80%) 2.5V / 1.8V LVTTL Outputs HSTL / eHSTL Outputs 350 — tF Output Fall Time (20% to 80%) 2.5V / 1.8V LVTTL Outputs 350 — 1050 ps HSTL / eHSTL Outputs 350 — — — 1350 250 MHz — — 200 fO Frequency Range (HSTL/eHSTL outputs) Frequency Range (2.5V/1.8V LVTTL outputs) Output Gate Enable/Disable Delay ps tPGE Output Gate Enable to Qn/Qn — — 3.5 ns tPGD Output Gate Enable to Qn/Qn Driven to GL Designated Level — — 3 ns NOTES: 1. Skew measured between all outputs or output pairs under identical input and output interfaces, transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. For differential LVTTL outputs, the true outputs are compared only with other true outputs and the complementary outputs are compared only with other complementary outputs. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals. 2. For operating with either 1.8V or 2.5V LVTTL output interfaces with both true and complementary outputs enabled. Inverting skew is the skew between true and complementary outputs switching in opposite directions under identical input and output interfaces, transitions and load conditions on any one device. 3. Skew measured is the difference between propagation delay times tPHL and tPLH of any output or output pair under identical input and output interfaces, transitions and load conditions on any one device. For single ended and differential LVTTL outputs, this measurement is made when each output voltage passes through VDDQ/2. The measurement applies to both true and complementary signals. For differential HSTL outputs, the measurement takes place at the crossing point of the true and complementary signals. 4. Skew measured is the magnitude of the difference in propagation times between any outputs or output pairs of two devices, given identical transitions and load conditions at identical VDD/VDDQ levels and temperature. 5. Guaranteed by design. 12 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE AC DIFFERENTIAL INPUT SPECIFICATIONS(1) Symbol tW Parameter Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2) Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2) HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL VDIF AC Differential Voltage(3) VIH AC Input HIGH VIL LVEPECL (4,5) AC Input LOW(4,6) Min. 1.73 2.17 Typ. — — Max — — Unit ns 400 — — mV Vx + 200 — — mV — — Vx - 200 mV VDIF AC Differential Voltage(3) 400 — — mV VIH AC Input HIGH(4) 1275 — — mV VIL AC Input LOW — — 875 mV (4) NOTES: 1. For differential input mode, RxS is tied to GND. 2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined by VDIF has been met or exceeded. 3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state. 4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range. 5. Voltage required to switch to a logic HIGH, single-ended operation only. 6. Voltage required to switch to a logic LOW, single-ended operation only. 13 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE DIFFERENTIAL AC TIMING WAVEFORMS 1/fo tW tW A VIH VTHI VIL A VIH VTHI VIL tPHL tPLH VOH VOX VOL Qn Qn tSK(O) tSK(O) Qm Qm VOH VOX VOL HSTL and eHSTL Output Propagation and Skew Waveforms 1/fo tW tW A VIH VTHI VIL A VIH VTHI VIL tPHL tPLH VOH VTHO VOL Qn comp tPHL comp tPLH VOH VTHO VOL Qn tSK(O) tSK(O) VOH VTHO VOL Qm tSK(O) tSK(O) VOH VTHO VOL Qm 1.8V or 2.5V LVTTL Output Propagation and Skew Waveforms NOTES: 1. For the HSTL and eHSTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the crossing point of each Qn and Qn. 2. For 1.8V and 2.5V LVTTL outputs, tPHL and tPLH are measured from the input passing through VTHI or input pair crossing to the slower of Qn or Qn passing through VTHO. 3. Pulse skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from the rising and falling edges of a single pulse. Note that the tPHL and tPLH shown above are not valid measurements for this calculation because they are not taken from the same pulse. 14 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE A VIH VTHI VIL A VIH VTHI VIL GL VIH VTHI VIL tPLH VIH VTHI VIL G(+) tPGE tPGD Qn VOH VTHO VOL Qn Differential Gate Disable/Enable Showing Runt Pulse Generation NOTES: 1. The waveforms shown only gate "true" output, Qn. 2. As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem. 15 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE SDR AC TIMING WAVEFORMS 1/fo tW tW A VIH VTHI VIL A VIH VTHI VIL tPHL tPLH VOH VTHO VOL Qn tSK(O) tSK(O) VOH VTHO VOL Qm Propagation and Skew Waveforms NOTES: 1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO. 2. Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse. A VIH VTHI VIL A VIH VTHI VIL GL VIH VTHI VIL tPLH VIH VTHI VIL Gx tPGE tPGD VOH VTHO VOL Qn SDR Gate Disable/Enable Showing Runt Pulse Generation NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem. 16 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND CONDITIONS VDDI R1 VIN 3 inch, ~50Ω Transmission Line VDD VDDQ R2 VDDI A D.U.T. Pulse Generator R1 VIN A 3 inch, ~50Ω Transmission Line R2 Test Circuit for Differential Input(1) DIFFERENTIAL INPUT TEST CONDITIONS Symbol VDD = 2.5V ± 0.1V Unit R1 100 Ω R2 100 Ω VDDI VCM*2 V HSTL: Crossing of A and A eHSTL: Crossing of A and A VTHI LVEPECL: Crossing of A and A V 1.8V LVTTL: VDDI/2 2.5V LVTTL: VDD/2 NOTE: 1. This input configuration is used for all input interfaces. For single-ended testing, the VIN input is tied to GND. For testing single-ended in differential input mode, the VIN is left floating. 17 IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE VDDQ VDD VDDQ VDDQ R1 VDDQ VDD R1 D.U.T. R2 CL Qn VDDQ Qn D.U.T. CL R1 R2 Qn CL R2 Test Circuit for SDR Outputs Test Circuit for Differential Outputs SDR OUTPUT TEST CONDITIONS DIFFERENTIAL OUTPUT TEST CONDITIONS Symbol VDD = 2.5V ± 0.1V Symbol Unit VDD = 2.5V ± 0.1V Unit VDDQ = Interface Specified VDDQ = Interface Specified CL 15 pF CL 15 pF R1 100 Ω R1 100 Ω R2 100 Ω R2 100 Ω VTHO VDDQ / 2 V VOX HSTL: Crossing of Qn and Qn V eHSTL: Crossing of Qn and Qn VTHO 1.8V LVTTL: VDDQ/2 2.5V LVTTL: VDDQ/2 18 V IDT5T915 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Process I -40°C to +85°C (Industrial) PA Thin Shrink Small Outline Package 5T915 2.5V Differential 1:5 Clock Buffer Terabuffer™ CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 19 for Tech Support: [email protected] (408) 654-6459