UNISONIC TECHNOLOGIES CO., LTD U74HC4046A CMOS IC PHASE LOCKED LOOP WITH VCO DESCRIPTION The U74HC4046A is a phase-locked-loop circuit including a linear voltage-controlled oscillator (VCO), three different phase comparators SOP-16 (PC1, PC2 and PC3), a common signal input amplifier and a common comparator input. The signal can be directly coupled to large voltage signals or with a series capacitor coupled to small voltage signals. Small voltage signals can be kept within the linear region of the input amplifiers with a self-bias input circuit. The U74HC4046A and a passive low-pass filter form a second-order loop PLL. With a linear op-amp, the VCO achieves excellent linearity. TSSOP-16 The VCO requires an external capacitor and resistor. R1 (between R1 and GND) and capacitor C1 (between C1A and C1B) determine the frequency range of the VCO. R2 (between R2 and GND) enables the VCO to have a frequency offset if required. For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a wide choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is provided in order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, but the DEMOUT voltage of U74HC4046 equals the VCO input voltage. When DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the comparator input (COMPIN). If the VCO input is held at a constant DC level, the VCO output signal has a duty factor of 50% (maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption. FEATURES * Low Power Consumption * Operating Power Supply Voltage Range: Digital Section 2.0 to 6.0 V VCO Section 3.0 to 6.0 V * Up to 17 MHz (typ.) Centre Frequency at VCC = 4.5 V * Excellent VCO Frequency Linearity * VCO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption * Minimal Frequency Drift * Three Phase Comparators: EXCLUSIVE-OR; Edge-Triggered JK Flip-Flop; Edge-Triggered RS Flip-Flop * Zero Voltage Offset due to OP-Amp Buffering * Standard Output Capability * MSI ICC Category www.unisonic.com.tw Copyright © 2013 Unisonic Technologies Co., Ltd 1 of 19 QW-R502-461.C U74HC4046A CMOS IC ORDERING INFORMATION Ordering Number Lead Free Halogen Free U74HC4046AL-S16-R U74HC4046AG-S16-R U74HC4046AL-P16-R U74HC4046AG-P16-R UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw Package Packing SOP-16 TSSOP-16 Tape Reel Tape Reel 2 of 19 QW-R502-461.C U74HC4046A CMOS IC PIN CONFIGURATION LOGIC SYMBOL IEC SYMBOL PCPOUT 1 16 VCC PC1OUT 2 15 PC3OUT COMPIN 3 14 SIGIN VCOOUT 4 13 PC2OUT INH 5 12 R2 C1A 6 11 R1 C1B 7 10 DEMOUT GND 8 9 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw VCOIN 3 of 19 QW-R502-461.C U74HC4046A CMOS IC PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC FUNCTION Phase comparator pulse output Phase comparator 1output Comparator input VCO output Inhibit input Capacitor C1 connection A Capacitor C1 connection B Ground VCO input Demodulator output Resistor R1 connection Resistor R2 connection Phase comparator 2 output Signal input Phase comparator 3 output Positive supply voltage UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 4 of 19 QW-R502-461.C U74HC4046A FUNCTIONAL DIAGRAM LOGIC DIAGRAM UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw CMOS IC 5 of 19 QW-R502-461.C U74HC4046A CMOS IC ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage DC Input Diode Current DC Output Diode Current DC Output Source or Sink Current SYMBOL TEST CONDITIONS MIN TYP MAX VCC -0.5 +7 ±IIK for VIN <−0.5 V or VIN > VCC + 0.5 V 20 ±IOK for VOUT <−0.5 V or VOUT > VCC + 0.5 V 20 ±IO for −0.5 V < VOUT < VCC + 0.5 V 25 ±ICC, DC VCC or GND Current 50 ±IGND Power Dissipation per Package for temperature range: − 40 to +125 °C 750 Plastic DIL above +70 °C: derate linearly with 12 mW/K PD Power Dissipation per Package for temperature range: − 40 to +125 °C 500 Plastic Mini-Pack(SO) above +70 °C: derate linearly with 8 mW/K Storage Temperature Range TSTG -65 +150 Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. mA mW mW °C RECOMMENDED OPERATING CONDITIONS PARAMETER DC Supply Voltage DC Supply Voltage if VCO Section is not used DC Input Voltage Range DC Output Voltage Range SYMBOL VCC VCC VIN VOUT Input Rise and Fall Times (pin 5) tR, tF Ambient Operating Temperature TOPR UNIT V mA mA mA TEST CONDITIONS VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V see DC and AC CHARACTERISTICS MIN 3.0 2.0 0 0 TYP 5.0 5.0 6.0 6.0 6.0 -40 -40 MAX 6.0 6.0 VCC VCC 1000 500 400 +85 +125 UNIT V V V V ns ns ns °C °C QUICK REFERENCE DATA (GND = 5V; T = 25 °C) PARAMETER VCO Centre Frequency Input Capacitance (pin 5) SYMBOL TEST CONDITIONS fo C1 = 40 pF; R1 = 3 kΩ;VCC = 5V CIN CPD (Note) Power Dissipation Capacitance per Package Note : CPD is used to determine the dynamic power dissipation (PD in μW): MIN TYP MAX UNIT 19 MHz 3.5 pF 24 pF PD = C PD × VCC × fi + ∑ (C L × VCC × fO ) 2 2 where: fi = input frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; fo =output frequency in MHz; 2 ∑ (CL × VCC × fO ) = sum of outputs. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 19 QW-R502-461.C U74HC4046A CMOS IC DC CHARACTERISTICS (TA =25°C , unless otherwise specified) Quiescent Supply Current (Voltages are referenced to GND (ground = 0 V)) SYMBOL TEST CONDITIONS MIN PARAMETER Pins 3, 5 and 14 at VCC; Quiescent Supply Current VCC=6.0V Pin 9 at GND; IIN at pins ICC (VCO Disabled) 3 and 14 to be excluded Phase Comparator Section PARAMETER SYMBOL TEST CONDITIONS MIN DC Coupled VCC=2.0V 1.5 (HIGH Level Input Voltage SIGIN, VCC=4.5V 3.15 VIH COMPIN) VCC=6.0V 4.2 DC Coupled VCC=2.0V (LOW Level Input Voltage SIGIN, VCC=4.5V VIL COMPIN) VCC=6.0V 1.9 VCC=2.0V HIGH Level Output Voltage VI=VIH or VIL, VOH VCC=4.5V 4.4 (PCPOUT, PCnOUT) - IOUT = 20μA VCC=6.0V 5.9 HIGH Level Output Voltage VCC=4.5V, - IO = 4.0 mA 3.98 VI=VIH or VIL, VOH (PCPOUT, PCnOUT) VCC=6.0V ,- IO = 5.2 mA 5.48 VCC=2.0V VI=VIH or VIL, LOW Level Output Voltage VOL VCC=4.5V (PCPOUT, PCnOUT) - IOUT = 20μA VCC=6.0V LOW Level Output Voltage VCC=4.5V , IO = 4.0 mA VOL VI=VIH or VIL, (PCPOUT, PCnOUT) VCC=6.0V , IO = 5.2 mA VCC=2.0V VCC=3.0V VI = VCC or Input Leakage Current ±IIN (SIGIN, COMPIN ) GND VCC=4.5V VCC=6.0V VOUT = VCC or GND, VI=VIH or VIL, 3-State (OFF-state current PC2OUT) ±IOZ VCC=6.0V VCC=3.0V VIN at self-bias operating Input Resistance (SIGIN, COMPIN) RIN VCC=4.5V point; ΔVI = 0.5V; VCC=6.0V (Fig. 7) VCO Section (Voltages are Referenced to GND (Ground = 0 V)) SYMBOL TEST CONDITIONS PARAMETER VCC=3.0V HIGH Level Input Voltage INH VIH VCC=4.5V VCC=6.0V VCC=3.0V LOW Level Input Voltage INH VIL VCC=4.5V VCC=6.0V VCC=3.0V VI=VIH or VIL, HIGH Level Output Voltage VCOOUT VOH VCC=4.5V - IOUT = 20μA VCC=6.0V VCC=4.5V, -IOUT = 4.0 mA HIGH Level Output Voltage VCOOUT VOH VI=VIH or VIL VCC=6.0V, -IOUT = 5.2 mA VCC=3.0V VI=VIH or VIL, LOW Level Output Voltage VCOOUT VOL VCC=4.5V IOUT = 20μA VCC=6.0V VCC=4.5V, IOUT = 4.0 mA LOW Level Output Voltage VCOOUT VOL VI=VIH or VIL VCC=6.0V, IOUT = 5.2 mA VCC=4.5V, IOUT = 4.0 mA LOW Level Output Voltage C1A, C1B VOL VI=VIH or VIL VCC=6.0V, IOUT=5.2 mA Input Leakage Current(INH, VCOIN) ±IIN VCC=6.0V, VI=VCC or GND UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN 2.1 3.15 4.2 2.9 4.4 5.9 3.98 5.48 TYP MAX UNIT 8.0 TYP 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 4.32 5.81 0 0 0 0.15 0.16 μA MAX UNIT V 0.5 1.35 1.8 V V V 0.1 0.1 0.1 0.26 0.26 3.0 7.0 18.0 30.0 0.5 800 250 150 V V μA μA kΩ kΩ kΩ TYP MAX 1.7 2.4 3.2 1.3 0.9 2.1 1.35 2.8 1.8 3.0 4.5 6.0 4.32 5.81 0 0.1 0 0.1 0 0.1 0.15 0.26 0.16 0.26 0.4 0.4 0.1 UNIT V V V V V V V μA 7 of 19 QW-R502-461.C U74HC4046A CMOS IC DC CHARACTERISTICS(Cont.) VCO Section (Cont.) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX VCC=3.0V 3.0 300 R1 VCC=4.5V 3.0 300 VCC=6.0V 3.0 300 Resistance Range VCC=3.0V 3.0 300 R2 VCC=4.5V (Note) 3.0 300 VCC=6.0V 3.0 300 40 VCC=3.0V Capacitor Range C1 VCC=4.5V 40 VCC=6.0V 40 1.1 1.9 VCC=3.0V Over the range Operating Voltage Range at VCOIN VVCOIN VCC=4.5V specified for R1; 1.1 3.4 VCC=6.0V for linearity (Fig10) 1.1 4.9 Note: The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/ or R2 are/is > 10 kΩ. Demodulator Section (Voltages are Referenced to GND (Ground = 0 V)) PARAMETER SYMBOL TEST CONDITIONS VCC=3.0V At RS > 300 kΩ Resistor Range RS VCC=4.5V the leakage current can VCC=6.0V influence VDEMOUT VCC=3.0V VI = VVCOIN =1/2 VCC; Offset Voltage VCOIN to VDEMOUT VOFF VCC=4.5V values taken over RS VCC=6.0V range VCC=3.0V Dynamic Output Resistance at RD VCC=4.5V VDEMOUT = 1/2 VCC DEMOUT VCC=6.0V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN 50 50 50 TYP ±30 ±20 ±10 25 25 25 UNIT kΩ kΩ pF V MAX UNIT 300 300 kΩ 300 mV Ω 8 of 19 QW-R502-461.C U74HC4046A CMOS IC AC CHARACTERISTICS (TA =25°C , unless otherwise specified) Phase Comparator Section (GND = 0 V; tR = tF =6ns; CL = 50pF) PARAMETER SYMBOL TEST CONDITIONS VCC=2.0V Propagation Delay SIGIN, tPHL/ tPLH VCC=4.5V Fig.8 COMPIN to PCPOUT VCC=6.0V VCC=2.0V Propagation Delay SIGIN, tPHL/ tPLH VCC=4.5V Fig.8 COMPIN to PC3OUT VCC=6.0V VCC=2.0V 3-State Output Enable Time tPZH/ tPZL VCC=4.5V Fig.9 SIGIN, COMPIN to PC2OUT VCC=6.0V VCC=2.0V 3-State Output Disable Time tPHZ/ tPLZ VCC=4.5V Fig.9 SIGIN, COMPIN to PC2OUT VCC=6.0V VCC=2.0V Output Transition Time tPHZ/ tPLZ VCC=4.5V Fig.8 VCC=6.0V VCC=2.0V AC Coupled Input Sensitivity VCC=3.0V (Peak-To-Peak Value) VIN(P-P) fi = 1MHz VCC=4.5V at SIGIN or COMPIN VCC=6.0V VCO Section (GND = 0 V; tR = tF = 6 ns; CL = 50 pF) PARAMETER SYMBOL TEST CONDITIONS VCC=3.0V VIN = VVCOIN = 1/2 VCC; Frequency Stability with Δf/T R1 = 100 kΩ; R2 = ∞; VCC=4.5V Temperature Change C1= 100 pF VCC=6.0V VCC=3.0V VVCOIN = 1/2 VCC; VCO Centre Frequency R1 = 3 kΩ;R2 = ∞; fo VCC=4.5V (duty Factor = 50%) C1 = 40 pF VCC=6.0V VCC=3.0V R1 = 100 kΩ; R2 = ∞; ΔfVCO VCO Frequency Linearity VCC=4.5V C1 = 100 pF;(Fig.10) VCC=6.0V VCC=3.0V δVCO Duty Factor at VCOOUT VCC=4.5V VCC=6.0V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw MIN MIN TYP 96 35 28 77 28 22 83 30 24 99 36 29 19 7 6 9 11 15 33 TYP MAX 340 68 58 270 54 46 280 56 48 325 65 55 75 15 13 UNIT ns ns ns ns ns mV MAX UNIT %/K 7.0 11.0 13.0 10.0 17.0 21.0 1.0 0.4 0.3 50 50 50 MHz % % 9 of 19 QW-R502-461.C U74HC4046A CMOS IC PHASE COMPARATORS If the signal swing is between the standard HC family input logic levels, the signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14. Capacitive coupling is required for signals with smaller swings. Phase comparator 1 (PC1) This is an EXCLUSIVE-OR network. To obtain the maximum locking range, the signal and comparator input frequencies (fI) must have a 50% duty factor. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: VDEMOUT = V CC (φ SIGIN − φ COMPIN ) π Where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). K P = V CC ( V / r ) The phase comparator gain is: π As shown in Fig.1, the average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT) is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN). The average of VDEMOUT is equal to VCC/2 when there is no signal or noise at SIGIN and with this input the VCO oscillates at the centre frequency (fO). As shown in Fig.2 it is the typical waveforms for the PC1 loop locked at fO. π Fig.1 Phase comparator 1: average output voltage versus input phase difference. SIGIN COMPIN VCOOUT PC1OUT VCOIN VCC GND Fig.2 Typical waveforms for PLL using phase comparator 1, loop locked at fO. The frequency capture range (2fc) is he frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the low-pass filter characteristics determine the capture range which can be made as large as the lock range. This configuration retains lock even with very noisy input signals. Typical behavior of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 10 of 19 QW-R502-461.C U74HC4046A CMOS IC PHASE COMPARATORS (Cont.) Phase comparator 2 (PC2) This is a positive edge-triggered phase and frequency detector. If the PLL is using the comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 is comprised of two D-type flip-flops, control-gating and a 3-state output stage. The circuit function is as an up-down counter (Logic Diagram) for SIGIN causes an up-count and COMPIN causes a down-count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is VDEMOUT = V CC (φ SIGIN − φ COMPIN ) 4π where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter). The phase comparator gain is: K P = V CC ( V / r ) 4π As shown in Fig.3, VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN. Typical waveforms for the PC2 loop locked at fo are shown in Fig.4. 4π Fig.3 Phase comparator 2: average output voltage versus input phase difference. Fig.4 Typical waveforms for PLL using phase comparator 2, loop locked at fo. If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”. If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition. For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO. And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when no signal present at SIGIN. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 11 of 19 QW-R502-461.C U74HC4046A CMOS IC PHASE COMPARATORS (Cont.) Phase comparator 3 (PC3) This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. If this comparator is used, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. The transfer characteristic of PC3, assuming ripple (fr = fj) is suppressed, is: VDEMOUT = V CC (φ SIGIN − φ COMPIN ) 2π where VDEMOUT = VPC3OUT (via low-pass filter). K P = V CC ( V / r ) 2π The phase comparator gain is: As shown in Fig.5, the average output voltage from PC3, fed to the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of SIGIN and COMPIN. As shown in Fig.6, it is the typical waveforms for the PC3 loop locked at fo. VCC VDEMOUT(AV) 1/2VCC VDEMOUT = VPC3OUT = DEMOUT = ( SIGIN VCC 2π - ( SIGIN - COMPIN) COMPIN) 0 0 180 360 DEMOUT Fig.5 Phase comparator 3: average output voltage versus input phase difference. Fig.6 Typical waveforms for PLL using phase comparator 3, loop locked at fo. The phase-to-output response characteristic of PC3 (Fig.5) differs from that of PC2, as the phase angle between SIGIN and COMPIN varies between 0o and 360o and 180o is the centre frequency. And the voltage swing of PC3 is greater than that of PC2 for input phase differences, but as a consequence the ripple content of VCO input signal is higher. Both of the PLL lock range and capture range of this type of phase comparator are dependent on the low-pass filter. The VCO adjusts to its lowest frequency via PC3, when no signal present at SIGIN. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 12 of 19 QW-R502-461.C U74HC4046A CMOS IC FIGURE REFERENCES FOR DC CHARACTERISTICS IIN VIN VIN Self-Bias Operating Point Fig.7 Typical input resistance curve at SIGIN, COMPIN. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 13 of 19 QW-R502-461.C U74HC4046A CMOS IC AC WAVEFORMS SIGIN, COMPIN VM PCPOUT PC1OUT PC3OUT tPHL tPLH VM VM= 50%, VH= 90%, VL= 10% tTHL tTLH Fig.8 Waveforms showing input (SIGIN, COMPIN) to output (PCPOUT, PC1OUT, PC3OUT) propagation delays and the output transition times. Fig.9 Waveforms showing the 3-state enable and disable times for PC2OUT. Fig.10 Definition of VCO frequency linearity: ∆V = 0.5 V over the VCC range: For VCO linearity f’0 = (f1+f2)/2, linearity (f’0+f0)/f’0 ×100% UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 14 of 19 QW-R502-461.C U74HC4046A CMOS IC APPLICATION INFORMATION This is a reference for the values of external components to be used with the U74HC4046A in a PLL system. The ranges of the values of the components: Component R1 R2 R1+R2 C1 Value 3 kΩ ~ 300 kΩ 3 kΩ ~ 300 kΩD Parallel value > 2.7 kΩ Greater than 40 pF VCO Frequency Without Extra Offset (Phase comparator: PC1, PC2 or PC3) Frequency Characteristic: With R2 = ∞ and R1 between 3 kΩ and 300 kΩ, the characteristics of the VCO operation will be as shown in Fig.11 (Due to R1, C1 time constant a small offset remains when R2 = ∞). Fig.11 Frequency characteristic of VCO operating without offset: f0 = centre frequency; 2fL = frequency lock range. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 15 of 19 QW-R502-461.C U74HC4046A CMOS IC APPLICATION INFORMATION(Cont.) VCO Frequency with Extra Offset (Phase Comparator: PC1, PC2 or PC3) Frequency characteristic: With R1 and R2 between 3 kΩ and 300 kΩ, the characteristics of the VCO operation will be as shown in Fig.12. fVCO fMAX 2fL f0 due to R1, C1 fMIN fOFF due to R2, C1 0.9V ½ VCC VCC–0.9V VCC VCOIN Fig.12 Frequency characteristic of VCO operating with offset: f0 = centre frequency; 2fL = frequency lock range. PC1, PC2 or PC3 Selection of R1, R2 and C1 Given fo and fL, determine the value of R1×C1 Calculate fOFF from the equation fOFF = fO – 1.6fL Obtain the values of C1 and R2 Calculate the value of R1 from the value of C1 and R1×C1. Subject Phase comparator Design considerations with φ VCO adjusts to f PC1 o DEMOUT = 90° and VVCONIN = 1/2 VCD (Fig.1). PLL Conditions with no VCO adjusts to fo with φDEMOUT = -360° and VVCONIN = min. (Fig.3). PC2 Signal at the SIGIN Input VCO adjusts to fo with φDEMOUT = -360° and VVCONIN = min. (Fig.5). PC3 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 16 of 19 QW-R502-461.C U74HC4046A CMOS IC APPLICATION INFORMATION(Cont.) PLL Frequency Capture Range (Phase comparator: PC1, PC2 or PC3) Loop filter component selection F( jω ) τ ω τ A small capture range (2fC) is obtained if 2f ≈ 1 2π f / τ C L π Fig.13 Simple loop filter for PLL without offset; R3 ≥ 500 Ω. R3 F( jω ) R4 m= INPUT (a) C2 OUTPUT τ 1 = R3 × C2 τ 2 = R4 × C2 τ 3 = (R3 + 4)× C2 R4 R3 + R4 τ -1/ 2 τ -1/ 3 m 1/ τ 3 1/ τ 2 ω (b) Amplitude Characteristic (c) Pole-Zero Diagram Fig.14 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω. Subject Phase comparator PC1 or PC3 PLL Locks on Harmonics at Centre Frequency PC2 PC1 Noise Rejection at Signal Input PC2 or PC3 PC1 AC Ripple Content when PLL is Locked PC2 PC3 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw Design considerations Yes No High Low fr = 2fi, large ripple content at φDEMOUT = 90° fr = fi, small ripple content at φDEMOUT = 0° fr = fi, large ripple content at φDEMOUT = 180° 17 of 19 QW-R502-461.C U74HC4046A CMOS IC PLL DESIGN EXAMPLE Fig.15 Frequency Synthesizer. The parameters of the frequency synthesizer in Fig.15: Output frequency: 2 MHz to 3 MHz Frequency steps: 100kHz Settling time: 1ms Overshoot: < 20% The Open-Loop Gain is: H (s ) × G(s ) = K p × K f × K o × K n Where: Kp = phase comparator gain Kf = low-pass filter transfer gain Ko = Kv/s VCO gain Kn = 1/n divider ratio The programmable counter ratio Kn can be found as follows: f 2MHz NMin = out = = 20 fstep 100kHz NMax = fout 3MHz = = 30 fstep 100kHz The VCO is set by the values of R1, R2 and C1, R2 = 10 kΩ (adjustable). The values can be determined using the information in the section “DESIGN CONSIDERATIONS”. With fo = 2.5MHz and fL =500 kHz this gives the following values (VCC = 5.0 V): R1 = 10 kΩ; R2 = 10 kΩ; C1 = 500 pF The VCO gain is: KV = 2fL × 2 × π 1MHz = × 2π ≈ 2 × 10 6 r / s / V 0.9 − (VCC − 0.9) 3.2 The gain of the phase comparator is: The transfer gain of the filter is given by: The characteristics equation is: Kp = VCC = 0.4V / s 4π Kf = 1 + τ 2S 1 + (τ 1 + τ 2 )S Where: τ 1 = R3C2 and τ 2 = R4C2 1 + H(S) × G(S) = 0 This results in: S 2 + 1 + K p × K v × K n × τ 2 S + K p × K v × K n = 0 (τ 1 + τ 2 ) (τ 1 + τ 2 ) K p × Kv × K n The natural frequency ωn is defined as follows: ωn = Damping Value ζ is Defined as follows: ζ = 1 2ωn × (τ 1 + τ 2 ) 1+ K p × Kv × K n × τ 2 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw (τ 1 + τ 2 ) 18 of 19 QW-R502-461.C U74HC4046A CMOS IC UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 19 of 19 QW-R502-461.C