Datasheet

UNISONIC TECHNOLOGIES CO., LTD
U74HCT7046
CMOS IC
PHASE LOCKED LOOP WITH VCO &
LOCK DETECTOR
„
DESCRIPTION
The U74HCT7046 is phase-locked-loop circuit that comprise a linear
voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2),
a lock detector, a common signal input amplifier and a common
comparator input.
The lock detector capacitor should be connected between pin
15(CLD) and pin 8(GND).For a frequency range of 100kHz to 10MHz,the
lock detector capacitor must be 1000pF to 10pF,respectively.
The signal can be directly coupled to large voltage signals, or with a
series capacitor coupled to small signals. Small voltage signals can be
kept within the linear region of the input amplifiers with a self-bias input
circuit. The U74HCT7046 and a passive low-pass filter form a
second-order loop PLL. With a linear op-amp, the VCO achieves
excellent linearity.
The VCO requires external capacitor and resistor. R1 (between R1
and GND) and capacitor C1 (between C1A and C1B) determine the
frequency range of the VCO. R2 (between R2 and GND) enables the
VCO to have a frequency offset if required.
For the high input impedance of the VCO, the design of low-pass filters is simplified, and the designer has a wide
choice of resistor/capacitor ranges. At pin 10 (DEMOUT), a demodulator output of the VCO input voltage is provided
in order not to load the low-pass filter. In conventional techniques, the DEMOUT voltage is one threshold voltage
lower than the VCO input voltage, but the DEMOUT voltage of U74HCT7046 equals the VCO input voltage. When
DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; but if unused, DEMOUT should be
left open. The VCO output (VCOOUT) can be connected directly or via a frequency-divider to the comparator input
(COMPIN). If the VCO input is held at a constant DC level, the VCO output signal has a duty factor of 50%
(maximum expected deviation 1%). A LOW level at the inhibit input (INH) enables the VCO and demodulator, while
a HIGH level turns both off to minimize standby power consumption.
„
FEATURES
* Operating Power Supply Voltage Range:
Digital Section 4.5 to 5.5 V
VCO Section 4.5 to 5.5 V
* Up to 18 MHz (typ.) Centre Frequency at VCC = 5V
* Excellent VCO Frequency Linearity
* VCO-Inhibit Control For ON/OFF Keying and for Low Standby Power Consumption
* Minimal Frequency Drift
* Zero Voltage Offset due to OP-Amp Buffering
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CMOS IC
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
U74HCT7046L-S16-R
U74HCT7046G-S16-R
U74HCT7046L-S16-T
U74HCT7046G-S16-T
U74HCT7046L-P16-R
U74HCT7046G-P16-R
U74HCT7046L-P16-T
U74HCT7046G-P16-T
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Package
Packing
SOP-16
SOP-16
TSSOP-16
TSSOP-16
Tape Reel
Tube
Tape Reel
Tube
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„
„
CMOS IC
PIN CONFIGURATION
LD
1
16
VCC
PC1OUT
2
15
CLD
COMPIN
3
14
SIGIN
VCOOUT
4
13
PC2OUT
INH
5
12
R2
C1A
6
11
R1
C1B
7
10 DEMOUT
GND
8
9
VCOIN
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
LD
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCOIN
DEMOUT
R1
R2
PC2OUT
SIGIN
CLD
VCC
FUNCTION
Lock Detector Output(Active High)
Phase comparator 1output
Comparator input
VCO output
Inhibit input
Capacitor C1 connection A
Capacitor C1 connection B
Ground(0V)
VCO input
Demodulator output
Resistor R1 connection
Resistor R2 connection
Phase comparator 2 output
Signal input
Lock Detector Capacitor Input
Positive supply voltage
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„
LOGIC SYMBOL
„
IEC SYMBOL
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CMOS IC
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U74HCT7046
„
CMOS IC
LOGIC DIAGRAM
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CMOS IC
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
DC Supply Voltage
VCC
-0.5
+7
DC Input Diode Current
±IIK
for VIN<−0.5V or VIN>VCC+0.5V
20
DC Output Diode Current
±IOK
for VOUT<−0.5V or VOUT>VCC+0.5V
20
DC Output Source or Sink Current
±IO
for −0.5V<VOUT<VCC+0.5V
25
DC VCC or GND Current
±ICC / IGND
50
Storage Temperature Range
TSTG
-65
+150
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„
RECOMMENDED OPERATING CONDITIONS
PARAMETER
DC Supply Voltage
DC Supply Voltage if VCO Section is not used
DC Input Voltage Range
DC Output Voltage Range
Input Rise and Fall Times (pin 5)
Ambient Operating Temperature
„
UNIT
V
mA
mA
mA
mA
°C
SYMBOL
TEST CONDITIONS
VCC
VCC
VIN
VOUT
tR, tF
VCC = 4.5V
see DC and AC
TOPR
CHARACTERISTICS
MIN TYP MAX UNIT
4.5 5.0 5.5
V
4.5 5.0 5.5
V
0
VCC
V
0
VCC
V
6.0 500 ns
-40
+85 °C
-40
+125 °C
DC CHARACTERISTICS (TA =25°C , unless otherwise specified)
Quiescent Supply Current (Voltages are referenced to GND, Ground = 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
Quiescent Supply Current
ICC
VCC=5.5V, VI= VCC or GND
VCC=4.5V~ 5.5V,
Additional Quiescent Device Current
ΔICC
Per Input Pin:1 Unit Load
VI= VCC -2.1V (Pin 5 is excluded)
Phase Comparator Section
PARAMETER
DC Coupled
(HIGH Level Input Voltage SIGIN, COMPIN)
DC Coupled
(LOW Level Input Voltage SIGIN, COMPIN)
HIGH Level Output Voltage
(LD,PCnOUT) CMOS Loads
HIGH Level Output Voltage
(LD,PCnOUT) CMOS Loads
LOW Level Output Voltage
(LD,PCnOUT) TTL Loads
LOW Level Output Voltage
(LD,PCnOUT) TTL Loads
Input Leakage Current (SIGIN, COMPIN )
SYMBOL
100
VCC=4.5V
3.15 2.4
VIL
VCC=4.5V
2.1
VOH
VOH
VOL
VOL
±IIN
±IOZ
Input Resistance (SIGIN, COMPIN)
RIN
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VI=VIH or VIL, VCC=4.5V,
-IOUT = 20μA
VI=VIH or VIL, VCC=4.5V,
-IOUT =4.0 mA
VI=VIH or VIL, VCC=4.5V,
-IOUT = 20μA
VI=VIH or VIL, VCC=4.5V,
-IOUT =4.0 mA
VI =GND to VCC, VCC=5.5V
VOUT = VCC or GND, VI=VIH or VIL,
VCC=5.5V
VCC=4.5V,
VIN at self-bias operating point,
ΔVI = 0.5V(Fig. 7)
360
uA
MIN TYP MAX UNIT
VIH
3-State (OFF-state current PC2OUT)
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TEST CONDITIONS
MIN TYP MAX UNIT
8.0 μA
4.4
V
1.35
V
4.5
V
3.98 4.32
V
0
0.1
V
0.15 0.26
V
±30
μA
±0.5
μA
250
kΩ
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CMOS IC
DC CHARACTERISTICS (Cont.)
VCO Section (Voltages are Referenced to GND, Ground=0V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX
HIGH Level Input Voltage INH
VIH
VCC=4.5V~5.5V
2
1.6
LOW Level Input Voltage INH
VIL
VCC=4.5V~5.5V
1.2 0.8
VI=VIH or VIL
4.4 4.5
HIGH Level Output Voltage VCOOUT
VOH
VCC=4.5V, -IOUT = 20μA
VCC=4.5V, -IOUT = 4.0 Ma
3.9 4.3
HIGH Level Output Voltage VCOOUT
VOH
VI=VIH or VIL
VI=VIH or VIL
0
0.1
LOW Level Output Voltage VCOOUT
VOL
VCC=4.5V, IOUT = 20μA
0.1
VI=VIH or VIL
0.26
LOW Level Output Voltage VCOOUT
VOL
5
VCC=4.5V, IOUT = 4.0 mA
VI=VIH or VIL
0.4
LOW Level Output Voltage C1A, C1B
VOL
VCC=4.5V, IOUT = 4.0 mA
Input Leakage Current(INH, VCOIN)
±IIN
VCC=5.5V, VI=GND to VCC
±0.1
Resistance Range
R1 / R2
VCC=4.5V (Note1)
3.0
300
Capacitor Range
C1
VCC=4.5V (no limit Max.)
40
VCC=4.5V, Over the range
specified for R1; for linearity
1.1
3.4
Operating Voltage Range at VCOIN
VVCOIN
(Fig10)
Note: 1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when
R1 and/ or R2 are/is>10 kΩ.
Demodulator Section (Voltages are Referenced to GND (Ground=0V))
PARAMETER
SYMBOL
TEST CONDITIONS
VCC=4.5V, At RS>300kΩ
the leakage current can influence
Resistor Range
RS
VDEMOUT
VCC=4.5V, VI = VVCOIN =1/2 VCC,
Offset Voltage VCOIN to VDEMOUT
VOFF
values taken over RS range
Dynamic Output Resistance at DEMOUT
RD
VCC=4.5V, VDEMOUT = 1/2 VCC
„
UNIT
V
V
V
V
V
V
V
μA
kΩ
pF
V
MIN TYP MAX UNIT
50
300
kΩ
±20
mV
25
Ω
AC CHARACTERISTICS (TA =25°C , unless otherwise specified)
Phase Comparator Section (GND=0V, tR=tF=6ns, CL=50pF)
PARAMETER
SYMBOL
TEST CONDITIONS
Propagation Delay SIGIN,
tPHL/ tPLH VCC=4.5V (Fig.8)
COMPIN to PC1OUT
Output Transition time
tTHL/ tTLH VCC=4.5V (Fig.8)
3-State Output Enable Time
tPZH/ tPZL VCC=4.5V (Fig.9)
SIGIN, COMPIN to PC2OUT
3-State Output Disable Time
tPHZ/ tPLZ VCC=4.5V (Fig.9)
SIGIN, COMPIN to PC2OUT
AC Coupled Input Sensitivity
VIN(P-P)
VCC=4.5V (fi = 1MHz)
(Peak-To-Peak Value) at SIGIN or COMPIN
VCO Section (GND=0V, tR=tF=6ns, CL=50pF)
PARAMETER
SYMBOL
Frequency Stability with
Δf/T
Temperature Change
VCO Centre Frequency
fo
(duty Factor = 50%)
VCO Frequency Linearity
Duty factor at VCOOUT
ΔfVCO
δVCO
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TEST CONDITIONS
VCC=4.5V, VIN=VVCOIN=1/2 VCC,
R1=100 KΩ; R2=∞; C1=100pF
VCC=4.5V, VVCOIN = 1/2 VCC,
R1=3KΩ, R2 =∞, C1=40pF
VCC=4.5V, R1=100kΩ,
R2=∞,C1=100pF (Fig.10)
VCC=4.5V
MIN TYP MAX UNIT
21
40
ns
7
15
ns
27
56
ns
35
65
ns
15
mV
MIN TYP MAX UNIT
0.15
11
%/K
17
MHz
0.4
%
50
%
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CMOS IC
PHASE COMPARATORS.
If the signal swing is between the standard HC family input logic levels, the signal input (SIGIN) can be directly
coupled to the self-biasing amplifier at pin 14. Capacitive coupling is required for signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. To obtain the maximum locking range, the signal and comparator input
frequencies (fI) must have a 50% duty factor.
The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is:
VDEMOUT = V CC (φ SIGIN − φ COMPIN )
π
Where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter).
The phase comparator gain is:
K P = V CC ( V / r )
π
As shown in Fig.1, the average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at
the demodulator output at pin 10 (VDEMOUT) is the resultant of the phase differences of signals (SIGIN) and the
comparator input (COMPIN). The average of VDEMOUT is equal to VCC/2 when there is no signal or noise at SIGIN and
with this input the VCO oscillates at the centre frequency (fO). As shown in Fig.2 it is the typical waveforms for the
PC1 loop locked at fO.
π
Fig.1 Phase comparator 1: average output voltage versus input phase difference.
SIGIN
COMPIN
VCOOUT
PC1OUT
VCOIN
VCC
GND
Fig.2 Typical waveforms for PLL using phase comparator 1, loop locked at fO.
The frequency capture range (2fc) is he frequency range of input signals on which the PLL will lock if it was
initially out-of-lock. The frequency lock range (2fL) is the frequency range of input signals on which the loop will stay
locked if it was initially in lock. The capture range is smaller or equal to the lock range.
With PC1, the low-pass filter characteristics determine the capture range which can be made as large as the
lock range.
This configuration retains lock even with very noisy input signals. Typical behavior of this type of phase
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comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency.
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CMOS IC
PHASE COMPARATORS (Cont.)
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detector. If the PLL is using the comparator, the loop is
controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 is
comprised of two D-type flip-flops, control-gating and a 3-state output stage. The circuit function is as an up-down
counter (Logic Diagram) for SIGIN causes an up-count and COMPIN causes a down-count.
The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is
VDEMOUT = V CC (φ SIGIN − φ COMPIN )
4π
where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter).
The phase comparator gain is:
K P = V CC ( V / r )
4π
As shown in Fig.3, VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN. Typical
waveforms for the PC2 loop locked at fo are shown in Fig.4.
4π
Fig.3 Phase comparator 2: average output voltage versus input phase difference.
Fig.4 Typical waveforms for PLL using phase comparator 2, loop locked at fo.
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CMOS IC
PHASE COMPARATORS (Cont.)
If the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type
output driver at PC2OUT is held “ON” for a time corresponding to the phase difference (φDEMOUT). If the phase of SIGIN
lags that of COMPIN, the n-type driver is held “ON”.
If the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held “ON” for most of the
input signal cycle time, and for the remainder of the cycle both n and p-type drivers are “OFF” (3-state). If the
frequency of SIGIN is lower than that of COMPIN, the n-type driver that is held “ON” for most of the cycle. Then the
voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs
are equal in both phase and frequency. At this stable state the voltage on C2 remains constant as the PC2 output is
in 3-state and the VCO input at pin 9 is a high impedance. Also in the condition, the signal at the phase comparator
pulse output (PCPOUT) is a HIGH level, and it indicates a locked condition.
For PC2, there is no phase difference between SIGIN and COMPIN over the full frequency range of the VCO.
And as the low-pass filter, the power dissipation is reduced because both p and n-type drivers are “OFF” for most of
the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the
capture range and this is independent of the low-pass filter. The VCO adjusts to its lowest frequency via PC2 when
no signal present at SIGIN.
„
LOCK DETECTOR THEORY OF OPERATION
Detection of a locked condition is accomplished by a NOR gate and an envelope detector.When the PLL is in
Lock, the output of the NOR gate is High and the lock detector output (Pin 1) is at a constant high level. As the loop
tracks the signal on Pin 14 (signal in), the NOR gate outputs pulses whose widths represent the phase differ-ences
between the VCO and the input signal. The time between pulses will be approximately equal to the time constant of
the VCO center frequency. During the rise time of the pulse, the diode across the 1.5kΩ resistor is forward biased
and the time constant in the path that charges the lock detector capacitor is T = (150Ω x CLD).
During the fall time of the pulse the capacitor discharges through the 1.5kΩ and the 150Ω resistors and the
channel resistance of the n-device of the NOR gate to ground (T = (1.5kΩ + 150Ω + Rn-channel) x CLD).
The waveform preset at the capacitor resembles a sawtooth.The lock detector capacitor value is determined by
the VCO center frequency. The typical range of capacitor for a frequency of 10MHz is about 10pF and for a
frequency of 100kHz is about 1000pF. As long as the loop remains locked and tracking, the level of the sawtooth will
not go below the switching threshold of the Schmitt-trigger inverter. If the loop breaks lock, the width of the error
pulse will be wide enough to allow the sawtooth waveform to go below threshold and a level change at the output of
the Schmitt trigger will indicate a loss of lock. The lock detector capacitor also acts to filter out small glitches that can
occur when the loop is either seeking or losing lock.
„
FIGURE REFERENCES FOR DC CHARACTERISTICS
IIN
VIN
VIN
Self-Bias Operating Point
Fig.7 Typical input resistance curve at SIGIN, COMPIN.
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AC WAVEFORMS
Fig.8 Waveforms showing input (SIGIN, COMPIN) to output (PC1OUT)
propagation delays and the output transition times.
Fig.9 Waveforms showing the 3-state enable and disable times for PC2OUT.
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AC WAVEFORMS(Cont.)
Fig.10 Definition of VCO frequency linearity: ∆V = 0.5 V over the VCC range:
for VCO linearity f’0 = (f1+f2)/2, linearity (f’0+f0)/f’0 ×100%
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APPLICATION INFORMATION
This is a reference for the values of external components to be used with the U74HCT7046 in a PLL system.
The ranges of the values of the components:
Component
R1
R2
R1+R2
C1
Value
3 kΩ ~ 300 kΩ
3 kΩ ~ 300 kΩ
Parallel value > 2.7 kΩ
Greater than 40 pF
VCO Frequency Without Extra Offset (Phase comparator: PC1, PC2)
Frequency Characteristic:
With R2 = ∞ and R1 between 3 kΩ and 300 kΩ, the characteristics of the VCO operation will be as shown in Fig.11
(Due to R1, C1 time constant a small offset remains when R2=∞).
Fig.11 Frequency characteristic of VCO operating without offset:
f0 = centre frequency; 2fL = frequency lock range.
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APPLICATION INFORMATION(Cont.)
VCO Frequency with Extra Offset (Phase Comparator: PC1, PC2)
Frequency characteristic:
With R1 and R2 between 3 kΩ and 300 kΩ, the characteristics of the VCO operation will be as shown in Fig.12.
fVCO
fMAX
2fL
f0
due to R1, C1
fMIN
fOFF
due to R2, C1
0.9V
½ VCC
VCC–0.9V
VCC
VCOIN
Fig.12 Frequency characteristic of VCO operating with offset:
f0 = centre frequency; 2fL = frequency lock range.
PC1, PC2
Selection of R1, R2 and C1
Given fo and fL, determine the value of R1×C1
Calculate fOFF from the equation fOFF = fO – 1.6fL
Obtain the values of C1 and R2
Calculate the value of R1 from the value of C1 and R1×C1.
Subject
Phase comparator
Design considerations
VCO
adjusts
to
f
with
φ
PC1
PLL Conditions with no
o
DEMOUT = 90° and VVCONIN = 1/2 VCD (Fig.1).
VCO adjusts to fo with φDEMOUT = -360° and VVCONIN = min. (Fig.3).
Signal at the SIGIN Input
PC2
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APPLICATION INFORMATION(Cont.)
PLL Frequency Capture Range (Phase comparator: PC1, PC2)
Loop filter component selection
F( jω )
τ
ω
τ
A small capture range (2fC) is obtained if 2f ≈ 1 2π f / τ
C
L
π
Fig.13 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
R3
F( jω )
R4
m=
INPUT
(a)
C2
OUTPUT
τ 1 = R3 × C2
τ 2 = R4 × C2
τ 3 = (R3 + 4)× C2
R4
R3 + R4
τ
-1/ 2
τ
-1/ 3
m
1/ τ 3
1/ τ 2
ω
(b) Amplitude Characteristic
(c) Pole-Zero Diagram
Fig.14 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
Subject
Phase comparator
PC1
PLL Locks on Harmonics at Centre Frequency
PC2
PC1
Noise Rejection at Signal Input
PC2
PC1
AC Ripple Content when PLL is Locked
PC2
Design considerations
Yes
No
High
Low
fr = 2fi, large ripple content at φDEMOUT = 90°
fr = fi, small ripple content at φDEMOUT = 0°
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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