Datasheet

UNISONIC TECHNOLOGIES CO., LTD
UCD4014B
Preliminary
CMOS IC
CMOS 8-STAGE STATIC SHIFT
REGISTERS
„
DESCRIPTION
SOP-16
The UTC UCD4014B is a 8-stage synchronous parallel or serial
input/serial output registers having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and
individual parallel inputs to each register stage. Each register is a
D-type master-slave flip-flop. Q6, Q7, and Q8 are outputs. With the
positive clock line transition in the UCD4014B parallel/serial entry is
made into the register synchronously.
In
UCD4014B
serial
entry
is
controlled
by
the
PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL
CONTROL input is low, data is serially shifted into the 8-stage register
synchronously with the positive transition of the clock line. When the
PARALLEL/SERIAL CONTROL input is high, data is jammed into the
8-stage register via the parallel input lines and synchronous with the
positive transition of the clock line.
„
TSSOP-16
FEATURES
* Up to 20V operation voltage
* 12MHz (typ.) clock rate at 10V
* Maximum input current of 1μA at 18V
* Fully static operation
* 8 master-slave flip-flops plus output buffering and control gating
„
APPLICATIONS
* General-purpose register
* Parallel input/serial output data queueing
* Parallel to serial data conversion
„
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UCD4014BL-S16-R
UCD4014BG-S16-R
UCD4014BL-S16-T
UCD4014BG-S16-T
UCD4014BL-P16-R
UCD4014BG-P16-R
UCD4014BL-P16-T
UCD4014BG-P16-T
www.unisonic.com.tw
Copyright © 2013 Unisonic Technologies Co., Ltd
Package
Packing
SOP-16
SOP-16
TSSOP-16
TSSOP-16
Tape Reel
Tube
Tape Reel
Tube
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„
PIN CONFIGURATION
„
LOGIC DIAGRAM
Preliminary
P1
P2
P3
P4
P5
P6
P7
P8
7
6
5
4
13
14
15
1
P
SERIAL IN
11
D
CLOCK
10
CL
P
Q
P
Q
D
CL
PS
PARALLEL/SERIAL
CONTROL
CMOS IC
CL
PS
P
Q
D
CL
PS
P
Q
D
CL
PS
P
Q
D
P
Q
D
CL
PS
P
Q
D
CL
PS
Q
D
CL
PS
PS
9
2
12
3
Q6
Q7
Q8
Fig.1 logic diagram
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„
Preliminary
CMOS IC
TRUE TABLE
CL
SER IN
PAR SER
CONTROL
P1
Pn
Q1
(INTERNAL)
Qn
X
1
0
0
0
0
X
1
1
0
1
0
X
1
0
1
0
1
X
1
1
1
1
1
0
0
X
X
0
Qn-1
1
0
X
X
1
Qn-1
X
X
X
X
Q1 (NC)
QN (NC)
Note: X = Don’t Care Case, NC = No Change
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„
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
VCC
-0.5 ~ 20
V
Input Voltage
VIN
-0.5 ~ VCC + 0.5
V
Output Voltage
VOUT
-0.5 ~ VCC + 0.5
V
Input Clamp Current (VIN<0, or VIN>VCC)
IIK
±10
mA
mW
500
TA=-55°C~+100°C
PD
Power Dissipation
mW
TA=+100°C~+125°C
200
Storage Temperature
TSTG
-65 ~ +150
°C
Note: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
„
RECOMMENDED OPERATING COMDITIONS
PARAMETER
Supply Voltage
SYMBOL
VCC
Clock Pulse Width
tW
Clock Frequency
fCL
Clock Rise and Fall Time
tr, tf
Set-up Time, Serial Input
Set-up Time, Parallel Input
tS
Set-up Time, Parallel/Serial Control
„
CONDITIONS
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
VCC = 5V
VCC = 10V
VCC = 15V
MIN
3
180
80
50
120
80
60
80
50
40
180
80
60
MAX
18
3
6
8.5
15
15
15
-
UNIT
V
ns
MHz
μs
ns
ns
ns
ELECTRICAL CHARACTERISTICS (TA =25°C , unless otherwise specified)
PARAMETER
SYMBOL
Quiescent Supply Current
ICC
Output Low (Sink) Current
IOL
Output High (Source) Current
IOH
Output Voltage: Low-Level
VOL
TEST CONDITIONS
VIN=0, 5V, VCC=5V
VIN=0, 10V, VCC=10V
VIN=0, 15V, VCC=15V
VIN=0, 20V, VCC=20V
VOUT=0.4V, VIN=0,5V, VCC=5V
VOUT=0.5V, VIN=0,10V, VCC=10V
VOUT=1.5V, VIN=0,15V, VCC=15V
VOUT=4.6V, VIN=0, 5V, VCC=5V
VOUT=2.5V, VIN=0, 5V, VCC=5V
VOUT= 9.5V, VIN=0,10V, VCC=10V
VOUT=13.5V, VIN=0,15V, VCC=15V
VIN=0,5V, VCC=5V
VIN=0,10V, VCC=10V
VIN=0,15V, VCC=15V
UNISONIC TECHNOLOGIES CO., LTD
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MIN
0.51
1.3
3.4
-0.51
-1.6
-1.3
-3.4
TYP
0.04
0.04
0.04
0.08
1
2.6
6.8
-1
-3.2
-2.6
-6.8
0
0
0
MAX UNIT
5
10
μA
20
100
mA
mA
0.05
0.05
0.05
V
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Preliminary
ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER
Output Voltage: High-Level
SYMBOL
VOH
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Current
„
CMOS IC
II(LEAK)
TEST CONDITIONS
VIN = 0, 5V, VCC = 5V
VIN = 0, 10V, VCC = 10V
VIN = 0, 15V, VCC = 15V
VOUT = 0.5, 4.5V, VCC = 5V
VOUT = 1, 9V, VCC = 10V
VOUT = 1.5, 13.5V, VCC = 15V
VOUT = 0.5, 4.5V, VCC = 5V
VOUT = 1, 9V, VCC = 10V
VOUT = 1.5, 13.5V, VCC = 15V
VIN = 0, 18 V, VCC = 18V
MIN
4.95
9.95
14.95
TYP
5
10
15
MAX UNIT
V
1.5
3
4
3.5
7
11
V
V
±10-5
±0.1
μA
SWITCHING CHARACTERISTICS (TA =25°C, Input tr, tf =20ns, CL =50Pf, RL = 200KΩ)
PARAMETER
SYMBOL
Propagation Delay Time
tPLH / tPHL
Transition Time
tTHL/ tTLH
Maximum Clock Input Frequency
fCL
Minimum Clock Pulse Width
tW
Clock Rise and Fall Time
tr / tf
Minimum Setup Time, Serial Inputs
tS
Minimum Setup Time, Parallel Inputs
tS
Minimum Hold Time, Serial In,
Parallel In, Parallel/Serial Control
tH
Average Input Capacitance
CI
TEST CONDITIONS
VCC=5V
VCC=10V
VCC=15V
VCC=5V
VCC=10V
VCC=15V
VCC=5V
VCC=10V
VCC=15V
VCC=5V
VCC=10V
VCC=15
VCC=5V
VCC=10V
VCC=15V
VCC=5V
VCC=10V
VCC=15V
VCC=5V
VCC=10V
VCC=15V
VCC=5V
VCC=10V
VCC=15V
Any Input
UNISONIC TECHNOLOGIES CO., LTD
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MIN
3
6
8.5
TYP
160
80
60
100
50
40
6
12
17
90
40
25
60
40
30
40
25
20
5
MAX UNIT
320
ns
160
120
200
ns
100
80
MHz
180
80
50
15
15
15
120
80
60
80
50
40
0
0
0
7.5
ns
μs
ns
ns
ns
pF
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„
Preliminary
CMOS IC
TEST CIRCUITS AND WAVEFORMS
Test
tPLH/tPHL
Inputs
VIN
VCC
tr, tf
20 ns
S1
GND
VM
VLOAD
CL
RL
VCC/2
VCC
50 pF
200 KΩ
90%
VCC
90%
Input
10%
10%
tR
tF
0V
Fig 2. Voltage Waveforms Input Rise and Fall Times
VIN
Input
VM
VM
0V
tPHL
tPLH
90%
Output
VOH
90%
VM
VM
10%
10%
tR
tF
tPHL
VOL
tPLH
90%
90%
Output
VM
10%
tF
VOH
VM
10%
VOL
tR
Fig 3. Voltage Waveforms Propagation Delay and Output Transition Times
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤1MHz, ZO = 50Ω.
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„
Preliminary
CMOS IC
TEST CIRCUITS AND WAVEFORMS(Cont.)
500uF
CL
CL
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
I
0.1uF
CL
CK
SER.DATA
(¼ fCK )
Fig 4. Dynamic power dissipation test circuit
VCC
VCC
GND
INPUTS
I
GND
Fig 5. Quiescent device current test circuit
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„
Preliminary
CMOS IC
TEST CIRCUITS AND WAVEFORMS(Cont.)
VCC
INPUTS
OUTPUTS
VIH
+
V IL
-
GND
GND
Fig 6. Input voltage test circuit
Fig 7. Input current test circuit
Note:measure inputs sequentially, to both VCC and GND; connect all unused inputs to either VCC or GND.
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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