HI1175 8-Bit, 20 MSPS, Flash A/D Converter August 1997 Features Description • Resolution . . . . . . . . . . . . . . . . . . 8-Bit ±0.3 LSB (DNL) The HI1175 is an 8-bit, analog-to-digital converter built in a 1.4µm CMOS process. The low power, low differential gain and phase, high sampling rate, and single 5V supply make the HI1175 ideal for video and imaging applications. • Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS • Low Power Consumption . . . .60mW (at 20 MSPS Typ) (Reference Current Excluded) • Built-In Sample and Hold Circuit • Built-In Reference Voltage Self Bias Circuit • Three-State TTL Compatible Output • Single +5V Power Supply • Low Input Capacitance . . . . . . . . . . . . . . . . . 11pF (Typ) • Reference Impedance . . . . . . . . . . . . . . . . . . 300Ω (Typ) The adoption of a 2-step flash architecture achieves low power consumption (60mW) at a maximum conversion speed of 20 MSPS (Min), 35 MSPS typical with only a 2.5 clock cycle data latency. The HI1175 also features digital output enable/disable and a built in voltage reference. The HI1175 can be configured to use the internal reference or an external reference if higher precision is required. Ordering Information • Evaluation Board Available (HI1175-EV) PART NUMBER • Low Cost • Direct Replacement for the Sony CXD1175 Applications • Video Digitizing • PC Video Capture • Image Scanners • TV Set Top Boxes • Multimedia • Personal Communication Systems (PCS) TEMP. RANGE (oC) PKG. NO. PACKAGE HI1175JCP -40 to 85 24 Ld PDIP E24.4-S HI1175JCB -40 to 85 24 Ld SOIC M24.2-S HI1175-EV 25 Evaluation Board Pinout HI1175 (PDIP, SOIC) TOP VIEW OE 1 24 DVSS DVSS 2 23 VRB D0 (LSB) 3 22 VRBS D1 4 21 AVSS D2 5 20 AVSS D3 6 19 VIN D4 7 18 AVDD D5 8 17 VRT D6 9 16 VRTS D7 (MSB) 10 15 AVDD DVDD 11 14 AVDD CLK 12 13 DVDD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-1069 File Number 3577.6 HI1175 Functional Block Diagram OE 1 DVSS 2 D0 (LSB) 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 24 DVSS REFERENCE VOLTAGE 23 VRB 22 LOWER ENCODER (4-BIT) LOWER DATA LATCHES LOWER COMPARATORS WITH S/H (4-BIT) VRBS 0.6V (Typ) 21 AVSS 20 AVSS LOWER ENCODER (4-BIT) 19 VIN LOWER COMPARATORS WITH S/H (4-BIT) 18 AVDD 17 VRT UPPER DATA LATCHES UPPER ENCODER (4-BIT) D7 (MSB) 10 UPPER COMPARATORS WITH S/H (4-BIT) 16 VRTS 2.6V (Typ) 15 AVDD DVDD 11 14 AVDD CLK 12 13 DVDD CLOCK GENERATOR Typical Application Schematic HC04 CA158A +5V +5V R4 + - C9 + 4.7µF R13 R11 R3 ICL8069 C10 0.1µF 13 12 14 11 15 10 D7 (MSB) 16 9 D6 17 8 D5 7 D4 19 6 D3 20 5 D2 21 4 D1 22 3 D0 (LSB) 23 2 24 1 R5 R12 + - CA158A C12 0.1µF HA2544 VIN + C8 18 † HI1175 R1 R2 C11 0.1µF † CLK CLOCK IN C7 + 4.7µF : Ceramic Chip Capacitor 0.1µF +5V : Analog GND : Digital GND NOTE: It is necessary that AVDD and DVDD pins be driven from the same supply. The gain of analog input signal can be changed by adjusting the ratio of R2 to R1. 4-1070 HI1175 Pin Descriptions and Equivalent Circuits PIN NUMBER SYMBOL 1 OE EQUIVALENT CIRCUIT DESCRIPTION When OE = Low, Data is valid. When OE = High, D0 to D7 pins high impedance. DVDD 1 DVSS 2, 24 DVSS 3-10 D0 to D7 Digital GND. D0 (LSB) to D7 (MSB) Output. D1 11, 13 DVDD 12 CLK Digital +5V. Clock Input. DVDD 12 DVSS 16 VRTS Shorted with VRT generates, +2.6V. AVDD 16 17 VRT 23 VRB Reference Voltage (Top). AVDD Reference Voltage (Bottom). 17 23 AVSS 14, 15, 18 AVDD 19 VIN Analog +5V. Analog Input. AVDD 19 AVSS 20, 21 AVSS 22 VRBS Analog GND. AVSS 22 4-1071 Shorted with VRB generates +0.6V. HI1175 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage, VRT, VRB . . . . . . . . . . . . . . . . . . . . . VDD to VSS Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage, CLK. . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Output Voltage, VOH, VOL . . . . . . . . . . . . . . . . . . VDD to VSS Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions (Note 1) Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS , DVDD , DVSS . . . . . . . . . . . . . . . +4.75V to +5.25V |DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V and Below Analog Input Range, VIN . . . . . . . VRB to VRT (1.8VP-P to 2.8VP-P) Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EOT -60 -35 -10 mV EOB 0 +15 +45 mV SYSTEM PERFORMANCE Offset Voltage Integral Non-Linearity, INL fC = 20 MSPS, VIN = 0.6V to 2.6V - ±0.5 ±1.3 LSB Differential Non-Linearity, DNL fC = 20 MSPS, VIN = 0.6V to 2.6V - ±0.3 ±0.5 LSB Effective Number of Bits, ENOB fIN = 1MHz - 7.6 - Bits Spurious Free Dynamic Range fIN = 1MHz - 51 - dB Signal to Noise Ratio, SINAD fC = 20MHz, fIN = 1MHz - 46 - dB RMS Signal = -----------------------------------------------------------------RMS Noise + Distor tion fC = 20MHz, fIN = 3.58MHz - 46 - dB Maximum Conversion Speed, fC VIN = 0.6V to 2.6V, fIN = 1kHz Ramp 20 35 - MSPS - - 0.5 MSPS - 1.0 - % Differential Phase Error, DP - 0.5 - Degree Aperture Jitter, tAJ - 30 - ps Sampling Delay, tDS - 4 - ns Data Latency, tLAT - - 2.5 Cycles - 18 - MHz - 11 - pF DYNAMIC CHARACTERISTICS Minimum Conversion Speed Differential Gain Error, DG NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS ANALOG INPUTS Analog Input Bandwidth (-1dB), BW Analog Input Capacitance, CIN VIN = 1.5V + 0.07VRMS 4-1072 HI1175 Electrical Specifications fC = 20 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 1) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reference Pin Current, IREF 4.5 6.6 8.7 mA Reference Resistance (VRT to VRB), RREF 230 300 450 Ω 0.60 0.64 0.68 V 1.96 2.09 2.21 V 2.25 2.39 2.53 V VIH 4.0 - - V VIL - - 1.0 V VIH = VDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD -0.5V -1.1 - - mA VOL = 0.4V 3.7 - - mA VOH = VDD - 0.01 16 µA VOL = 0V - 0.01 16 µA - 18 30 ns - 12 17 mA REFERENCE INPUT INTERNAL VOLTAGE REFERENCE Self Bias Mode 1 VRB Short VRB and VRBS , Short VRT and VRTS VRT - VRB Self Bias Mode 2, VRT VRB = AGND, Short VRT and VRTS DIGITAL INPUTS Digital Input Voltage Digital Input Current IIH VDD = Max IIL DIGITAL OUTPUTS Digital Output Current IOH OE = VSS , VDD = Min IOL Digital Output Current IOZH OE = VDD , VDD = Max IOZL TIMING CHARACTERISTICS Output Data Delay, tDL POWER SUPPLY CHARACTERISTIC Supply Current, IDD fC = 20 MSPS, NTSC Ramp Wave Input NOTE: 2. Electrical specifications guaranteed only under the stated operating conditions. Timing Diagrams tPW1 tPW0 CLOCK ANALOG INPUT DATA OUTPUT : POINT FOR ANALOG SIGNAL SAMPLING N N+1 N-3 N-2 tD = 18ns FIGURE 1. 4-1073 N-2 N-1 N+3 N N+4 N+1 HI1175 Timing Diagrams VI (1) VI (2) VI (3) VI (4) ANALOG INPUT EXTERNAL CLOCK S (1) UPPER COMPARATOR BLOCK C (1) S (2) MD (0) UPPER DATA S (1) LOWER COMPARATOR BLOCK A S (3) MD (1) RV (0) LOWER REFERENCE VOLTAGE C (2) C (1) H (0) LOWER COMPARATOR BLOCK B LOWER DATA B C (0) RV (3) S (3) H (3) C (3) LD (1) S (2) H (2) LD (-2) DIGITAL OUTPUT C (4) MD (3) RV (2) LD (-1) LOWER DATA A S (4) MD (2) RV (1) H (1) C (3) C (2) S (4) LD (0) OUT (-2) OUT (-1) H (4) LD (2) OUT (0) OUT (1) FIGURE 2. Typical Performance Curves 20 100 20 IDD (mA) IDD (mA) 15 15 10 10 50 5 4.0 4.5 5.0 5 5.5 POWER SUPPLY VOLTAGE (V) FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE 0 5 10 15 20 25 30 35 SAMPLING RATE (MSPS) FIGURE 4. SUPPLY CURRENT AND POWER vs SAMPLING RATE 4-1074 POWER DISSIPATION (mW) VPP = 5.0V, VRT = 2.5V, VRB = 0.5V TA = 25oC, VIN = 2VP-P HI1175 Typical Performance Curves 50 TA = 25oC, VRT = 2.5V, VRB = 0.5V VDD = 5.0V, fC = 20 MSPS 49 ENCODE 21MHz 48 1.0 47 ENCODE 31MHz 46 (dB) DIFFERENTIAL NON-LINEARITY (LSB) 1.4 (Continued) 0.6 45 ENCODE 26MHz 44 43 42 0.2 41 0 0 2 4 6 8 40 10 0 1 2 INPUT FREQUENCY (MHz) FIGURE 5. DIFFERENTIAL NON-LINEARITY vs INPUT FREQUENCY -30 7.75 -33 7.50 -35 11 -38 ENCODE 21MHz -40 6.75 (dB) (BITS) 10 ENCODE 26MHz 7.25 6.50 ENCODE 26MHz 6.25 9 FIGURE 6. HI1175JCP SNR vs INPUT FREQUENCY 8.00 7.00 3 4 5 6 7 8 INPUT FREQUENCY (MHz) ENCODE 31MHz -43 -45 6.00 ENCODE 21MHz -48 5.75 -50 ENCODE 31MHz 5.50 -53 5.25 -55 5.00 0 1 2 3 4 5 6 7 8 INPUT FREQUENCY (MHz) 9 10 11 0 FIGURE 7. HI1175JCP ENOB vs INPUT FREQUENCY 1 2 3 4 5 6 7 8 INPUT FREQUENCY (MHz) 9 10 11 FIGURE 8. HI1175JCP THD vs INPUT FREQUENCY 1.0 8.00 7.75 0.8 7.50 fIN = 1MHz 0.6 7.00 fIN = 5MHz 6.75 INL (LSB) ENOB (BITS) 7.25 6.50 6.25 6.00 0.4 0.2 fIN = 10MHz 5.75 5.50 0 5.25 5.00 21 26 31 -0.2 -55 36 CLOCK FREQUENCY (MHz) FIGURE 9. ENOB vs CLOCK FREQUENCY -35 -15 5 25 45 65 TEMPERATURE (oC) 85 FIGURE 10. INL vs TEMPERATURE 4-1075 105 125 HI1175 Typical Performance Curves (Continued) 5.0 20 4.5 IOH = -3.7mA 18 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 14 fC = 20MHz 12 IOH = 1.1mA 0.5 0 -55 fC = 35MHz 16 -35 -15 5 25 45 65 TEMPERATURE (oC) 85 105 10 -55 125 FIGURE 11. DIGITAL OUTPUT VOLTAGE vs TEMPERATURE -35 -15 5 25 45 65 TEMPERATURE (oC) 85 105 125 FIGURE 12. SUPPLY CURRENT vs TEMPERATURE 0.2 54 fIN = 1MHz 0.15 53 0.1 SFDR (dB) DNL (LSB) 52 0.05 0 51 50 -0.05 49 -0.1 -0.15 -55 -35 -15 5 25 45 65 TEMPERATURE (oC) 85 105 48 -55 125 FIGURE 13. DNL vs TEMPERATURE -35 -15 5 25 45 65 TEMPERATURE (oC) 85 105 125 105 125 FIGURE 14. SFDR vs TEMPERATURE -48 8.0 fIN = 1MHz 7.9 -49 fIN = 1MHz 7.8 ENOB (BITS) THD (dB) -50 -51 -52 7.7 7.6 7.5 7.4 -53 -54 -55 7.3 -35 -15 5 25 45 65 TEMPERATURE (oC) 85 105 125 FIGURE 15. THD vs TEMPERATURE 7.2 -55 -35 -15 5 25 45 65 TEMPERATURE (oC) 85 FIGURE 16. ENOB vs TEMPERATURE 4-1076 HI1175 Typical Performance Curves (Continued) 2.5 2.2 VRT SHORTED TO VRTS VRB = AGND VRB SHORTED TO VRBS VRT SHORTED TO VRTS 2.15 VRT - VRB (V) VRT (V) 2.45 2.4 2.35 2.1 2.05 2.3 -40 -15 10 35 60 2.0 -40 85 10 -15 TEMPERATURE (oC) 35 60 85 TEMPERATURE (oC) FIGURE 17. VRT vs TEMPERATURE FIGURE 18. VRT - VRB vs TEMPERATURE 0.75 25 VRB SHORTED TO VRBS VRT SHORTED TO VRTS OUTPUT RISING EDGE 20 DATA DELAY (ns) VRB (V) 0.7 0.65 OUTPUT FALLING EDGE 15 10 0.6 5 0.55 -40 -15 10 35 60 0 -40 85 10 -15 TEMPERATURE (oC) 35 60 85 TEMPERATURE (oC) FIGURE 19. VRB vs TEMPERATURE FIGURE 20. OUTPUT DATA DELAY vs TEMPERATURE A/D OUTPUT CODE TABLE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP MSB D6 D5 D4 D3 D2 D1 LSB VRT 255 1 1 1 1 1 1 1 1 • • • • • • • • VRB • • • • • • 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 0 0 0 • • • 0 • • • 0 0 0 4-1077 0 0 HI1175 Detailed Description Power, Grounding, and Decoupling The HI1175 is a 2-step A/D converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can be obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling (S), hold (H), and compare (C). To reduce noise effects, separate the analog and digital grounds. In order to avoid latchup at power up, it is necessary that AVDD and DVDD be driven from the same supply. The operation of the part is illustrated in Figure 2. A reference voltage that is between VRT -VRB is constantly applied to the upper 4-bit comparator group. VI(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples VI(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LD(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 cycle clock delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B alternate generating the lower data in order to increase the overall A/D sampling rate. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1µF capacitor close to the pin. Analog Input The input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with an amplifier with sufficient bandwidth and drive capability. In order to prevent parasitic oscillation, it may be necessary to insert a low value (i.e., 0.24Ω) resistor between the output of the amplifier and the A/D input. Reference Input The range of the A/D is set by the voltage between VRT and VRB . The internal bias generator will set VRTS to 2.6V and VRBS to 0.6V. These can be used as the part reference by shorting VRT and VRTS and VRB to VRBS . The analog input range of the A/D will now be from 0.6V to 2.6V and is referred to as Self Bias Mode 1. Self Bias Mode 2 is where VRB is connected to AGND and VRT is shorted to VRTS . The analog input range will now be from 0V to 2.4V. Test Circuits +V S2 - S1 : ON IF A < B S2 : ON IF A > B S1 + -V A<B A>B COMPARATOR VIN DUT HI1175 8 “0” A8 TO A1 A0 B8 TO B1 B0 8 BUFFER “1” DVM 8 CLK (20MHz) 000 • • • 00 TO 111 • • • 10 CONTROLLER FIGURE 21. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT 4-1078 HI1175 Test Circuits (Continued) 2.6V ERROR RATE fC -1kHz SG HPF 0.6V 1 100 IRE 0 -40 SG (CW) VIN AMP 2 NTSC SIGNAL SOURCE 40 IRE MODULATION COUNTER HI20201 DUT HI1175 8 TTL 1 8 10-BIT D/A ECL 620 2 VECTOR SCOPE CLK 2.6V BURST DG DP -5.2V 620 0.6V SYNC -5.2V TTL fC ECL FIGURE 22. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT VDD VRT 2.6V IOL VIN IOH VIN VRB 0.6V VDD VRT 2.6V VRB 0.6V HI1175 HI1175 CLK CLK VOL OE GND VOH OE + GND - + - FIGURE 23. DIGITAL OUTPUT CURRENT TEST CIRCUIT ICL8069 REFERENCE AMP HA5020 (Single) HA5022(Dual) HA5024 (Quad) HA5013 (Triple) A/D DSP/µP HI1175 (8-Bit) HSP9501 HSP48901 HSP43881 HSP43168 D/A HI3338 (8-Bit) HI1171 (8-Bit) HSP9501: Programmable Data Buffer HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit HSP43881: Digital Filter, 30MHz, 1-D and 2-D FIR Filters HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz CMOS Logic Available in HC, HCT, AC, ACT and FCT. HA5013: HA5020: HA5022: HA5024: Triple, 125MHz, IOUT = 20mA Single, 100MHz, IOUT = 30mA, Output Enable/Disable Dual, 125MHz, IOUT = 20mA, Output Enable/Disable Quad, 125MHz, IOUT = 20mA, Output Enable/Disable FIGURE 24. 8-BIT SYSTEM COMPONENTS 4-1079 AMP HA5020 (Single) HI1175 Static Performance Definitions Offset, full scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full scale values. The results are all displayed in LSBs. Offset Error (EOB) The first code transition should occur at a level 1/2 LSB above the bottom reference voltage. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero. Total Harmonic Distortion This is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the 2nd and 3rd harmonic component respectively to the RMS value of the measured input signal. Spurious Free Dynamic Range (SFDR) Full Scale Error (EOT) The last code transition should occur for a analog input that is 11/2 LSBs below full scale. Full scale error is defined as the deviation of the actual code transition from this point. Differential Linearity Error (DNL) SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. Full Power Input Bandwidth DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed to have no missing codes. Integral Linearity Error (INL) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. Full power bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Timing Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI1175. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 1024 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from fullscale for all these tests. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to fullscale. Sampling Delay (tSD) Sampling delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. Aperture Jitter (tAJ) This is the RMS variation in the sampling delay due to variation of internal clock path delays. Data Latency (tLAT) Signal-to-Noise Ratio (SNR) SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number Of Bits (ENOB) After the analog sample is taken, the data on the bus is available after 2.5 cycles of the clock. This is due to the architecture of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input by 2.5 cycles. Output Data Delay (tD) Output Data Delay is the delay time from when the data is valid (rising clock edge) to when it shows up at the output bus. This is due to internal delays at the digital output. The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB. 4-1080 HI1175 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-1081 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029