INTERSIL HFA3863IN

HFA3863
TM
Data Sheet
P RE L I M I NA R Y
April 2000
File Number
4856
Direct Sequence Spread Spectrum
Baseband Processor
Features
The Intersil HFA3863 Direct Sequence
Spread Spectrum (DSSS) baseband
processor is part of the PRISM® 2.4GHz
radio chipset, and contains all the
functions necessary for a full or half duplex
packet baseband transceiver.
• RAKE Receiver with Decision Feedback Equalizer
The HFA3863 has on-board A/D’s and D/A for analog I and Q
inputs and outputs, for which the HFA3783 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSK and DQPSK, with data scrambling capability,
are available along with Complementary Code Keying to provide
a variety of data rates. Built-in flexibility allows the HFA3863 to be
configured through a general purpose control bus, for a range of
applications. Both Receive and Transmit AGC functions with 7-bit
AGC control obtain maximum performance in the analog
portions of the transceiver. The HFA3863 is housed in a thin
plastic quad flat package (TQFP) suitable for PCMCIA board
applications. It is pin compatible with the HFA3861B.
• Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK
Ordering Information
• DSSS PCMCIA or Mini-PCI Wireless Transceiver
PART NUMBER
TEMP.
RANGE (oC)
• Complete DSSS Baseband Processor
• Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps
• Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm
• Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V
• Supports Full or Half Duplex Operations
• On-Chip A/D and D/A Converters for I/Q Data (6-Bit,
22MSPS), AGC, and Adaptive Power Control (7-Bit)
• Targeted for Multipath Delay Spreads 125ns at 11Mbps,
250ns at 5.5Mbps
• Supports Short Preamble and Antenna Diversity
Applications
• Enterprise WLAN Systems
• Systems Targeting IEEE 802.11b Standard
• Spread Spectrum WLAN RF Modems
PACKAGE
HFA3863IN
-40 to 85
64 Ld TQFP
HFA3863IN96
-40 to 85
Tape and Reel
PKG. NO.
Q64.10x10
• TDMA or CSMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable PDA/Notebook Computer
• Wireless Digital Audio, Video, Multimedia
Pinout
SDI
RESET
TX_PE
RX_PE
CCA
TX_RDY
TXD
VDDD
GNDd
TXCLK
MD_RDY
RXD
RXCLK
TEST7
TEST6
TEST5
• PCN / Wireless PBX / Wireless Local Loop
• Wireless Bridges
Simplified Block Diagram
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDA
TX_AGC_IN
RX-IF_DET
GNDa
IREF
VDDA
TX_I+
TX_IGNDa
COMPCAP2
COMPRES2
GNDa
TX_Q+
TX_QVDDA
COMPRES1
GNDd
VDDD
SD
SCLK
R/W
CS
GNDd
VDDD
GNDa
RX_I+
RX_IVDDA
RX_Q+
RX_QGNDa
VREF
• Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant
TEST4
TEST3
TEST2
TEST1
TEST0
GNDd
MCLK
VDDD
ANT-SEL
ANT-SEL
RX-RF_AGC
VDDD
GNDd
TX_IF_AGC
RX_IF_AGC
COMPCAP1
ANT_SEL
1
RX_RF_AGC
RX_IF_DET
THRESH.
DETECT
RX_IF_AGC
RX_I±
RX_Q±
7
IF
DAC
I ADC
AGC
CTL
6
6
DEMOD
Q ADC
VREF
I/O
DATA I/O
TX_I±
I DAC
TX_Q±
Q DAC
6
6
MOD
TX
ALC
TX_IF_AGC
TX
DAC
7
TX_AGC_IN
TX
ADC
6
44MHz MCLK
4-1
1
HFA 3863 BBP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
PRISM is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
Typical Application Diagram
ANTSEL
HFA3683A RF/IF
CONV (FILE# 4634)
I ADC
Q ADC
∑
∑
I/O LO
AGC
CTL
6
6
Q DAC
RADIO
DATA
INTERFACE
RADIO
CONTROL
PORTS
6
HOST
INTERFACE
LOGIC
MOD
GP SERIAL
PORTS
7
6
MEMORY
ACCESS
ARBITER
TX
ALC
HFA3863 BBP
(FILE# 4816)
EXTERNAL
MEMORY
44MHz MCLK
T/Rsw
DIFFERENTIAL SIGNALS
TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3863
For additional information on the PRISM® chip set, call (321) 724-7800 to access
Intersil’s AnswerFAX system. When prompted, key in the four-digit document
number (File #) of the data sheets you wish to receive.
The four-digit file numbers are shown in the Typical Application Diagram, and
correspond to the appropriate circuit.
HFA3863
REF IN
16-BIT
PIPELINED
CONTROL
PROCESSOR
6
HFA3783 QUAD IF
(FILE# 4633)
TX
DAC
TX
ADC
HFA3841
MAC
(FILE# 4661)
WEP
ENGINE
CPU
DEMOD
I/O
I DAC
REF IN
REF IN
7
IF
LO
RF
LO
HFA3963
RFPA
(FILE# TBD)
1
REFOUT
PLL
PLL
1
HOSTPC
INTERFACE
4-2
RF
DAC
RF
ADC
IF
DAC
HFA3863
Pin Descriptions
NAME
PIN
TYPE I/O
VDDA (Analog)
12, 17, 22,
31
Power
DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip).
VDDD (Digital) 2, 8, 37, 41,
57
Power
DC power supply 2.7 - 3.6V.
Ground
DC power supply 2.7 - 3.6V, ground (not hard wired together on chip).
Ground
DC power supply 2.7 - 3.6V, ground.
GNDa
(Analog)
9, 15, 20,
25, 28
GNDd (Digital) 1, 7, 36, 43,
56
VREF
DESCRIPTION
16
I
Voltage reference for A/D’s and D/A’s.
IREF
21
I
Current reference for internal ADC and DAC devices. Requires a 12kΩ resistor to ground.
RXI, ±
10/11
I
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-.
RXQ, ±
13/14
I
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-.
ANTSEL
39
O
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for
differential drive of antenna switches.
ANTSEL
40
O
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for
differential drive of antenna switches.
RX_IF_DET
19
I
Analog input to the receive power A/D converter for AGC control.
RX_IF_AGC
34
O
Analog drive to the IF AGC control.
RX_RF_AGC
38
O
Drive to the RF AGC stage attenuator. CMOS digital.
TX_AGC_IN
18
I
Input to the transmit power A/D converter for transmit AGC control.
TX_IF_AGC
35
O
Analog drive to the transmit IF power control.
TX_PE
62
I
When active, the transmitter is configured to be operational, otherwise the transmitter is in standby
mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to
the HFA3863. The rising edge of TX_PE will start the internal transmit state machine and the falling
edge will initiate shutdown of the state machine. TX_PE envelopes the transmit data except for the
last bit. The transmitter will continue to run for 4µs after TX_PE goes inactive to allow the PA to
shutdown gracefully.
TXD
58
I
TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network
processor to the HFA3863. The data is received serially with the LSB first. The data is clocked in the
HFA3863 at the rising edge of TXCLK.
TXCLK
55
O
TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3863, synchronously. Transmit data on the TXD bus is clocked into the HFA3863 on the rising
edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock
will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY
59
O
TX_RDY is an output to the external network processor indicating that Preamble and Header
information has been generated and that the HFA3863 is ready to receive the data packet from the
network processor over the TXD serial bus.
CCA
60
O
Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are
described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD
53
O
RXD is an output to the external network processor transferring demodulated Header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with
MD_RDY.
RXCLK
52
O
RXCLK is the bit clock output. This clock is used to transfer Header information and payload data
through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is
held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been
detected. Data should be sampled on the rising edge. This polarity is programmable and can be
inverted.
4-3
HFA3863
Pin Descriptions
(Continued)
NAME
PIN
TYPE I/O
DESCRIPTION
MD_RDY
54
O
MD_RDY is an output signal to the network processor, indicating header data and a data packet are
ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data
transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns
to its inactive state when RX_PE goes inactive or an error is detected in the header.
RX_PE
61
I
When active, the receiver is configured to be operational, otherwise the receiver is in standby mode.
This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled.
SD
3
I/O
SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal
registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the
register address immediately followed by 8 more bits representing the data that needs to be written or
read at that register. In the 4 wire interface mode, this pin is three-stated unless the R/W pin is high.
SCLK
4
I
SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input
clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is
11MHz or one half the master clock frequency, whichever is lower.
SDI
64
I
Serial Data Input in 3 wire mode described in Tech Brief 383. This pin is not used in the 4 wire interface
described in this data sheet. It should not be left floating.
R/W
5
I
R/W is an input to the HFA3863 used to change the direction of the SD bus when reading or writing
data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read
while a low level is a write.
CS
6
I
CS is a Chip select for the device to activate the serial control port. The CS doesn’t impact any of the
other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low
signal. When inactive SD, SCLK, and R/W become “don’t care” signals.
TEST 7:0
51, 50, 49,
48, 47, 46,
45, 44
I/O
This is a data port that can be programmed to bring out internal signals or data for monitoring. These
bits are primarily reserved by the manufacturer for testing. A further description of the test port is given
in the appropriate section of this data sheet.
RESET
63
I
Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3863 goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up. See the section on Control Register 2 bit 0 for important initialization information.
MCLK
42
I
Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to
generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
TXI ±
23/24
O
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24-.
TXQ ±
29/30
O
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-.
CompCap
33
I
Compensation Capacitor.
CompCap2
26
I
Compensation Capacitor.
CompRes1
32
I
Compensation Resistor.
CompRes2
27
I
Compensation Resistor.
NOTE: See CR10[3].
External Interfaces
There are three primary digital interface ports for the
HFA3863 that are used for configuration and during normal
operation of the device as shown in Figure 1. These ports
are:
• The Control Port, which is used to configure, write
and/or read the status of the internal HFA3863
registers.
• The TX Port, which is used to accept the data that
needs to be transmitted from the network processor.
• The RX Port, which is used to output the received
demodulated data to the network processor.
4-4
In addition to these primary digital interfaces the device
includes a byte wide parallel Test Port which can be
configured to output various internal signals and/or data.
The device can also be set into various power consumption
modes by external control. The HFA3863 contains three
Analog to Digital (A/D) converters and four Digital to Analog
converters. The analog interfaces to the HFA3863 include,
the In phase (I) and quadrature (Q) data component inputs/
outputs, and the RF and IF receive automatic gain control
and transmit output power control.
HFA3863
expansion. The serial transfers are accomplished through
the serial data pin (SD). SD is a bidirectional serial data
bus. Chip Select (CS), and Read/Write (R/W) are also
required as handshake signals for this port. The clock used
in conjunction with the address and data on SD is SCLK.
This clock is provided by the external source and it is an
input to the HFA3863. The timing relationships of these
signals are illustrated in Figures 2 and 3. R/W is high when
data is to be read, and low when it is to be written. CS is an
asynchronous reset to the state machine. CS must be
active (low) during the entire data transfer cycle. CS selects
the serial control port device only. The serial control port
operates asynchronously from the TX and RX ports and it
can accomplish data transfers independent of the activity at
the other digital or analog ports.
HFA3863
ANALOG
INPUTS
RXI
RXQ
AGC
A/D
REFERENCE
VREF
IREF
ANALOG
OUTPUTS
TXD
TXCLK
TX_RDY
RXD
RXC
MD_RDY
CS
SD
SCLK
R/W
SDI
TX_PE
RX_PE
RESET
POWER
DOWN
SIGNALS
TEST
PORT
AGC
TXI
TXQ
8
TEST
ANT_SEL
TX_PORT
RX_PORT
CONTROL_PORT
FIGURE 1. EXTERNAL INTERFACES
Control Port (4 Wire)
The HFA3863 has 96 internal registers that can be
configured through the control port. These registers are
listed in the Configuration and Control Internal Register
table. Table 9 lists the configuration register number, a brief
name describing the register, the HEX address to access
each of the registers and typical values. The type indicates
whether the corresponding register is Read only (R) or
Read/Write (R/W). Some registers are two bytes wide as
indicated on the table (high and low bytes).
The serial control port is used to serially write and read
data to/from the device. This serial port can operate up to a
11MHz rate or 1/2 the maximum master clock rate of the
device, MCLK (whichever is lower). MCLK must be running
and RESET must be inactive during programming. This
port is used to program and to read all internal registers.
The first 8 bits always represent the address followed
immediately by the 8 data bits for that register. The LSB of
the address is a don’t care, but reserved for future
FIRST ADDRESS BIT
7
6
5
4
3
FIRST DATABIT OUT
2
1
0
7
6
5
4
3
2
1
0
SCLK
7
SD
6
5
MSB
4
3
2
1
7
ADDRESS IN
6
5
MSB
4
3
2
1
0
DATA OUT
LSB
R/W
CS
NOTES:
1. The HFA3863 always uses the rising edge of SCLK to sample address and data and to generate read data.
2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data.
FIGURE 2. CONTROL PORT READ TIMING
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCLK
SD
7
MSB
6
5
4
3
ADDRESS IN
2
1
0
7
MSB
6
5
4
3
2
DATA IN
R/W
CS
FIGURE 3. CONTROL PORT WRITE TIMING
4-5
1
0
LSB
HFA3863
TX Port
The transmit data port accepts the data that needs to be
transmitted serially from an external data source. The data is
modulated and transmitted as soon as it is received from the
external data source. The serial data is input to the HFA3863
through TXD using the next rising edge of TXCLK to clock it in
the HFA3863. TXCLK is an output from the HFA3863. A
timing scenario of the transmit signal handshakes and
sequence is shown on timing diagram Figure 4.
The external processor initiates the transmit sequence by
asserting TX_PE. TX_PE envelopes the transmit data packet
on TXD. The HFA3863 responds by generating a Preamble
and Header. Before the last bit of the Header is sent, the
HFA3863 begins generating TXCLK to input the serial data on
TXD. TXCLK will run until TX_PE goes back to its inactive
state indicating the end of the data packet. The user needs to
hold TX_PE high for as many clocks as there bits to transmit.
For the higher data rates, this will be in multiples of the
number of bits per symbol. The HFA3863 will continue to
output modulated signal for 4µs after the last data bit is
output, to supply bits to flush the modulation path. TX_PE
must be held until the last data bit is output from the
MAC/FIFO. The minimum TX_PE inactive pulse required to
restart the preamble and header generation is 2.22µs and to
reset the modulator is 4.22µs.
The HFA3863 internally generates the preamble and header
information from information supplied via the control registers.
The external source needs to provide only the data portion of
the packet and set the control registers. The timing diagram of
this process is illustrated on Figure 4. Assertion of TX_PE will
initialize the generation of the preamble and header. TX_RDY,
which is an output from the HFA3863, is used (if needed) to
indicate to the external processor that the preamble has been
generated and the device is ready to receive the data packet
(MPDU) to be transmitted from the external processor.
Signals TX_RDY, TX_PE and TXCLK can be set individually,
by programming Configuration Register (CR) 1, as either
active high or active low signals.
The transmit port is completely independent from the
operation of the other interface ports including the RX port,
therefore supporting a full duplex mode.
RX Port
The timing diagram Figure 5 illustrates the relationships
between the various signals of the RX port. The receive data
port serially outputs the demodulated data from RXD. The
data is output as soon as it is demodulated by the HFA3863.
RX_PE must be at its active state throughout the receive
operation. When RX_PE is inactive the device's receive
functions, including acquisition, will be in a stand by mode.
TXCLK
TX_PE
LAST DATA BIT SAMPLED
FIRST DATA BIT SAMPLED
TXD
LSB
DATA PACKET
MSB
DEASSERTED WHEN LAST
CHIP OF MPDU CLEARS
MOD PATH OF 3861 EXCEPT FOR
TX FILTER AND D/A
TX_RDY
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXCLK.
FIGURE 4. TX PORT TIMING
RXCLK
RX_PE
HEADER
FIELDS
DATA
PROCESSING
PREAMBLE/HEADER
MD_RDY
RXD
LSB
DATA PACKET
NOTE: MD_RDY active after CRC16. See detailed timing diagrams (Figures 21, 22, 23).
FIGURE 5. RX PORT TIMING
4-6
MSB
HFA3863
RXCLK is an output from the HFA3863 and is the clock for
the serial demodulated data on RXD. MD_RDY is an output
from the HFA3863 and it may be set to go active after the
SFD or CRC fields. Note that RXCLK becomes active after
the Start Frame Delimiter (SFD) to clock out the Signal,
Service, and Length fields, then goes inactive during the
header CRC field. RXCLK becomes active again for the
data. MD_RDY returns to its inactive state after RX_PE is
deactivated by the external controller, or if a header error is
detected. A header error is either a failure of the CRC
check, or the failure of the received signal field to match
one of the 4 programmed signal fields. For either type of
header error, the HFA3863 will reset itself after reception of
the CRC field. If MD_RDY had been set to go active after
CRC, it will remain low.
MD_RDY and RXCLK can be configured through CR 1, bits
1 and 0 to be active low, or active high. The receive port is
completely independent from the operation of the other
interface ports including the TX port, supporting therefore a
full duplex mode.
The AGC circuit is designed to adjust for signal level
variations and optimize A/D performance for the I and Q
inputs by maintaining the proper headroom on the 6-bit
converters. There are two gain stages being controlled. At
RF, the gain control is a 30dB step change. This RF gain
control optimizes the receiver dynamic range when the
signal level is high and maintains the noise figure of the
receiver when it is needed most at low signal level. At IF the
gain control is linear and covers the bulk of the gain control
range of the receiver.
The AGC loop is partially digital which allows for holding the
gain fixed during a packet. The AGC sensing mechanism
uses a combination of the I and Q A/D converters and the
detected signal level in the IF to determine the gain settings.
The A/D outputs are monitored in the HFA3863 for the
desired nominal level. When it is reached, by adjusting the
receiver gain, the gain control is locked for the remainder of
the packet.
RX_AGC_IN Interface
RX I/Q A/D Interface
The PRISM baseband processor chip (HFA3863) includes
two 6-bit Analog to Digital converters (A/Ds) that sample the
balanced differential analog input from the IF down converter
device (HFA3783). The I/Q A/D clock, samples at twice the
chip rate with a nominal sampling rate of 22MHz.
The interface specifications for the I and Q A/Ds are listed in
Table 1. The HFA3863 is designed to be DC coupled to the
HFA3783.
TABLE 1. I, Q, A/D SPECIFICATIONS
PARAMETER
AGC Circuit
The signal level in the IF stage is monitored to determine
when to impose the 30dB gain reduction in the RF stage.
This maximizes the dynamic range of the receiver by
keeping the RF stages out of saturation at high signal levels.
When the IF circuits’ sensor output reaches 0.5VDD, the
HFA3863 comparator switches in the 30dB pad and also
adds 30dB of gain to the IF AGC amplifier. This
compensates the IF AGC and RSSI measures.
TX I/Q DAC Interface
The transmit section outputs balanced differential analog
signals from the transmit DACs to the HFA3783. These are
DC coupled and digitally filtered.
MIN
TYP
MAX
0.90
1.00
1.10
Input Bandwidth (-0.5dB)
-
11MHz
-
Test Port
Input Capacitance (pF)
-
2
-
Input Impedance (DC)
5kΩ
-
-
-
22MHz
-
The HFA3863 provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. The test port is programmable through configuration
register (CR 34). Any signal on the test port can also be read
from configuration register (CR50) via the serial control port.
Additionally, the transmit DACs can be configured to show
signals in the receiver via CR 14. This allows visibility to
analog like signals that would normally be very difficult to
capture.
Full Scale Input Voltage (VP-P)
fS (Sampling Frequency)
The voltages applied to pin 16, VREF and pin 21, IREF set
the references for the internal I and Q A/D converters. In
addition, For a nominal I/Q input of 400mVP-P, the
suggested VREF voltage is 1.2V.
4-7
HFA3863
RX_RF_AGC
RX_IF_DET
1
THRESH.
DETECT
RX_IF_AGC
RX_I±
HFA3683
HFA3783
RX_Q±
1
7
AGC
CTL
IF
DAC
I ADC
Q ADC
6
6
DEMOD
DATA I/O
I/O
HFA3863
FIGURE 6. AGC CIRCUIT
Power Down Modes
Transmitter Description
The power consumption modes of the HFA3863 are
controlled by the following control signals.
The HFA3863 transmitter is designed as a Direct Sequence
Spread Spectrum Phase Shift Keying (DSSS PSK)
modulator. It can handle data rates of up to 11Mbps (refer to
AC and DC specifications). The various modes of the
modulator are Differential Binary Phase Shift Keying
(DBPSK) for 1Mbps, Differential Quaternary Phase Shift
Keying (DQPSK) for 2Mbps, and Complementary Code
Keying (CCK) for 5.5Mbps and 11Mbps. These implement
data rates as shown in Table 3. The major functional blocks
of the transmitter include a network processor interface,
DPSK modulator, high rate modulator, a data scrambler and
a spreader, as shown in Figure 7. CCK is essentially a
quadra-phase form of M-ARY Orthogonal Keying. A
description of that modulation can be found in Chapter 5 of:
“Telecommunications System Engineering”, by Lindsey and
Simon, Prentis Hall publishing.
Receiver Power Enable (RX_PE, pin 61), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 62), which disables
the transmitter when inactive.
Reset (RESET, pin 63), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a
maximum of 10µs before the device is operational.
The contents of the Configuration Registers are not effected
by any of the power down modes. No reconfiguration is
required when returning to operational modes. Activation of
RESET does NOT corrupt learned values of AGC settings
and noise floor values.
Table 2 describes the power down modes available for the
HFA3863 (VCC = 3.3V). The table values assume that all
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
The preamble is always transmitted as the DBPSK
waveform while the header can be configured to be either
DBPSK, or DQPSK, and data packets can be configured
for DBPSK, DQPSK, or CCK. The preamble is used by the
receiver to achieve initial PN synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer
link. The transmitter generates the synchronization
preamble and header and knows when to make the DBPSK
to DQPSK or CCK switchover, as required.
TABLE 2. POWER DOWN MODES
RX_PE
TX_PE
RESET
AT
44MHz
SLEEP
Inactive
Inactive
Active
1mA
STANDBY
Inactive
Inactive
Inactive
1.5mA
Both transmit and receive operations disabled. Device will resume its operational
state within 1µs of RX_PE or TX_PE going active.
TX
Inactive
Active
Inactive
15mA
Receiver operations disabled. Receiver will return in its operational state within 1µs
of RX_PE going active.
RX
Active
Inactive
Inactive
50mA
Transmitter operations disabled. Transmitter will return to its operational state within
2 MCLKs of TX_PE going active.
Active
300µA
All inputs at VCC or GND.
MODE
NO CLOCK
ICC Standby
4-8
DEVICE STATE
Both transmit and receive functions disabled. Device in sleep mode. Control
Interface is still active. Register values are maintained. Device will return to its active
state within 10µs.
HFA3863
TABLE 3. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHz)
TX SETUP CR 5
BITS 1, 0
RX SIGNAL CR 63
BITS 7, 6
DATA RATE
(Mbps)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
CCK
22
10
10
5.5
1.375
CCK
22
11
11
11
1.375
802.11 DSSS BPSK
1Mbps
BARKER
802.11 DSSS QPSK
2Mbps
BARKER
5.5Mbps CCK
COMPLEX
SPREAD FUNCTIONS
11Mbps CCK
COMPLEX
SPREAD FUNCTIONS
DATA
1 BIT ENCODED TO
ONE OF 2 CODE
WORDS
(TRUE-INVERSE)
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
4 BITS ENCODED
TO ONE OF 16
COMPLEX CCK
CODE WORDS
8 BITS ENCODED
TO ONE OF 256
COMPLEX CCK
CODE WORDS
IOUT
QOUT
11 CHIPS
CHIP
RATE
SYMBOL
RATE
11 CHIPS
8 CHIPS
8 CHIPS
11 MC/S
11 MC/S
11 MC/S
11 MC/S
1 MS/S
1 MS/S
1.375 MS/S
1.375 MS/S
I vs. Q
FIGURE 7. MODULATION MODES
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps,
it uses two of those bits to select one of 4 complex spread
sequences from a table of CCK sequences and then QPSK
modulates that symbol with the remaining 2 bits. Thus, there
are 4 possible spread sequences to send at four possible
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase
reference for the data portion of the packet is the phase of
the last bit of the header. At 11Mbps, one byte is used as
above where 6 bits are used to select one of 64 spread
sequences for a symbol and the other 2 are used to QPSK
modulate that symbol. Thus, the total possible number of
4-9
combinations of sequence and carrier phases is 256. Of
these only one is sent.
The bit rate Table 3 shows examples of the bit rates and the
symbol rates and Figure 7 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3863 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions.
The HFA3863 generates its own preamble and header
information. It uses two packet preamble and header
configurations. The first is backwards compatible with the
existing IEEE 802.11-1997 1 and 2Mbps modes and the
second is the optional shortened mode which maximizes
throughput at the expense of compatibility with legacy
equipment.
HFA3863
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1's
(before entering the scrambler) plus a start frame delimiter
(SFD). The actual transmitted pattern of the preamble is
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform (1Mbps). The duration of
the long preamble and header is 192µs.
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at
2Mbps. The synchronization preamble is all 0’s to distinguish
it from the long header mode and the short preamble SFD is
the time reverse of the long preamble SFD. The duration of
the short preamble and header is 96µs.
Start Frame Delimiter (SFD) Field (16 Bits) - This field is
used to establish the link frame timing. The HFA3863 will not
declare a valid data packet, even if it PN acquires, unless it
detects the SFD. The HFA3863 receiver auto-detects if the
packet is long or short preamble and sets SFD time-out. The
timer starts counting after initialization of the de-scrambler is
complete.
The four fields for the header shown in Figure 8 are:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The HFA3863
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
fields.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. Bit 2 is used by the HFA3863 to indicate
that the carrier reference and the bit timing references are
derived from the same oscillator (locked oscillators).
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits) - This field includes the
16-bit CCITT - CRC 16 calculation of the three header fields.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The HFA3863 receiver will
indicate a CCITT - CRC 16 error via CR24 bit 2 and will
lower MD_RDY and reset the receiver to the acquisition
mode if there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones complement of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x16 + x12 + x5 + 1
4-10
The protected bits are processed in transmit order. All CRC
calculations are made ahead of data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR 3 - Defines the short preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of 56d = 38h
for the optional short preamble.
CR 4 - Defines the long preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of
128d = 80h for the mandatory long preamble.
CR 5 Bits 0, 1 - These bits of the register set the Signal field
to indicate what modulation is to be used for the data portion
of the packet.
CR 6 - The value to be used in the Service field.
CR 7 and 8 - Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol and is in microseconds required to
transmit the data at the chosen data rate.
The packet consists of the preamble, header and MAC
Protocol Data Unit (MPDU). The data is transmitted exactly
as received from the control processor. Some dummy bits
will be appended to the end of the packet to ensure an
orderly shutdown of the transmitter. This prevents spectrum
splatter. At the end of a packet, the external controller is
expected to de-assert the TX_PE line to shut the
transmitter down.
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consists of a 7-bit shift register with feedback from
specified taps of the register. Both transmitter and receiver
use the same scrambling algorithm. The scrambler can be
disabled by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the
HFA3863 has the property that it can lock up (stop scrambling) on
random data followed by repetitive bit patterns. The probability of this
happening is 1/128. The patterns that have been identified are all
zeros, all ones, repeated 10s, repeated 1100s, and repeated
111000s. Any break in the repetitive pattern will restart the scrambler.
To ensure that this does not cause any problem, the CCK waveform
uses a ping pong differential coding scheme that breaks up repetitive
0s patterns.
HFA3863
PREAMBLE (SYNC)
128/56 BITS
SFD
16 BITS
SIGNAL FIELD
8 BITS
SERVICE FIELD
8 BITS
LENGTH FIELD
16 BITS
CRC16
16 BITS
HEADER
PREAMBLE
FIGURE 8. 802.11 PREAMBLE/HEADER
Scrambling is done by division with a prescribed polynomial
as shown in Figure 9. A shift register holds the last quotient
and the output is the exclusive or of the data and the sum of
taps in the shift register. The transmit scrambler seed for the
long preamble or for the short preamble can be set with
CR48 or CR49.
SERIAL
DATA OUT
SERIAL DATA
IN
XOR
Z-1 Z-2 Z-3 Z-4
Z-5 Z-6 Z-7
XOR
FIGURE 9. SCRAMBLING PROCESS
For the 1Mbps DBPSK data rates and for the header in all
rates using the long preamble, the data coder implements
the desired DBPSK coding by differential encoding the serial
data from the scrambler and driving both the I and Q output
channels together. For the 2Mbps DQPSK data rate and for
the header in the short preamble mode, the data coder
implements the desired coding as shown in the DQPSK
Data Encoder table. This coding scheme results from
differential coding of dibits (2 bits). Vector rotation is
counterclockwise although bits 6 and 7 of configuration
register CR 1 can be used to reverse the rotation sense of
the TX or RX signal if desired.
TABLE 4. DQPSK DATA ENCODER
scrambler and differential encoder. The I and Q Channels
are then both multiplied with the 11-bit Barker word at the
spread rate. The I and Q signals go to the Quadrature
upconverter (HFA3724) to be modulated onto a carrier.
Thus, the spreading and data modulation are BPSK
modulated onto the carrier.
For the 2Mbps DQPSK mode, the serial data is formed into
dibits or bit pairs in the differential encoder as detailed
above. One of the bits from the differential encoder goes to
the I Channel and the other to the Q Channel. The I and Q
Channels are then both multiplied with the 11-bit Barker
word at the spread rate. This forms QPSK modulation at the
symbol rate with BPSK modulation at the spread rate.
Transmit Filter Description
To minimize the requirements on the analog transmit
filtering, the transmit section shown in Figure 11 has an
output digital filter. This filter is a Finite Impulse Response
(FIR) style filter whose passband shape is set by tap
coefficients. This filter shapes the spectrum to meet the
radio spectral mask requirements while minimizing the peak
to average amplitude on the output. To meet the particular
spread spectrum processing gain regulatory requirements in
Japan on channel 14, an extra FIR filter shape has been
included that has a wider main lobe. This increases the 90%
power bandwidth from about 11MHz to 14MHz. It has the
unavoidable side effect of increasing the amplitude
modulation, so the available transmit power is compromised
by 2dB when using this filter (CR 11 bit 5).
PHASE SHIFT
DIBIT PATTERN (d0, d1)
d0 IS FIRST IN TIME
0
00
CCK Modulation
+90
01
+180
11
-90
10
For the CCK modes, the spreading code length is 8 complex
chips and based on complementary codes. The chipping
rate is 11Mchip/s. The following formula is used to derive the
CCK code words that are used for spreading both 5.5 and
11Mbps:
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and
CCK spread spectrum signals. The modulator is capable of
automatically switching its rate where the preamble is
DBPSK modulated, and the data and/or header are
modulated differently. The modulator can support date rates
of 1, 2, 5.5 and 11Mbps. The programming details to set up
the modulator are given at the introductory paragraph of this
section. The HFA3863 utilizes Quadraphase (I/Q)
modulation at baseband for all modulation modes.
In the 1Mbps DBPSK mode, the I and Q Channels are
connected together and driven with the output of the
4-11
 j ( ϕ1 + ϕ2 + ϕ3 + ϕ4 ) j ( ϕ1 + ϕ3 + ϕ4 ) j ( ϕ1 + ϕ2 + ϕ4 )
c = e
,
,e
,e

–e
j ( ϕ1 + ϕ4 )
,e
j ( ϕ1 + ϕ2 + ϕ3 )
,e
j ( ϕ1 + ϕ3 )
, –e
j ( ϕ1 + ϕ2 )
,e
jϕ 1 


(LSB to MSB), where c is the code word.
The terms: ϕ1, ϕ2, ϕ3, and ϕ4 are defined below for
5.5Mbps and 11Mbps.
This formula creates 8 complex chips (LSB to MSB) that are
transmitted LSB first. The coding is a form of the generalized
Hadamard transform encoding where the phase ϕ1 is added
HFA3863
to all code chips, ϕ2 is added to all odd code chips, ϕ3 is
added to all odd pairs of code chips and ϕ4 is added to all
odd quads of code chips.
The phase ϕ1 modifies the phase of all code chips of the
sequence and is DQPSK encoded for 5.5 and 11Mbps. This
will take the form of rotating the whole symbol by the
appropriate amount relative to the phase of the preceding
symbol. Note that the last chip of the symbol defined above
is the chip that indicates the symbol’s reference phase.
For the 5.5Mbps CCK mode, the output of the scrambler is
partitioned into nibbles. The first two bits are encoded as
differential symbol phase modulation in accordance with
Table 5. All odd numbered symbols of the MPDU are given
an extra 180 degree (π) rotation in addition to the standard
DQPSK modulation as shown in the table. The symbols of
the MPDU shall be numbered starting with “0” for the first
symbol for the purposes of determining odd and even
symbols. That is, the MPDU starts on an even numbered
symbol. The last data dibits d2, and d3 CCK encode the
basic symbol as specified in Table 6. This table is derived
from the CCK formula above by setting ϕ2 = (d2*pi)+ pi/2, ϕ3
= 0, and ϕ4 = d3*pi. In the table d2 and d3 are in the order
shown and the complex chips are shown LSB to MSB (left to
right) with LSB transmitted first.
DIBIT PATTERN (d(0), d(1)) EVEN SYMBOLS ODD SYMBOLS
d(0) IS FIRST IN TIME
PHASE CHANGE PHASE CHANGE
(+jω)
(+jω)
00
0
π
01
π/2
3π/2 (-π/2)
11
π
0
10
3π/2 (-π/2)
π/2
TABLE 6. 5.5Mbps CCK ENCODING TABLE
CHIPS
00
1j
1
1j
-1
1j
1
-1j
1
01
-1j
-1
-1j
1
1j
1
-1j
1
10
-1j
1
-1j
-1
-1j
1
1j
1
11
1j
-1
1j
1
-1j
1
1j
1
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes the phase ϕ1 based on
DQPSK. The DQPSK encoder is specified in Table 6 above.
The phase change for ϕ1 is relative to the phase ϕ1 of the
preceding symbol. In the case of rate change, the phase
change for ϕ1 is relative to the phase ϕ1 of the preceding
CCK symbol. All odd numbered symbols of the MPDU are
given an extra 180 degree (π) rotation in accordance with the
4-12
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode ϕ2, ϕ3,
and ϕ4 respectively based on QPSK as specified in Table 7.
Note that this table is binary, not Grey, coded.
TABLE 7. QPSK ENCODING TABLE
DIBIT PATTERN (d(i), d(i+1))
d(i) IS FIRST IN TIME
PHASE
00
0
01
π/2
10
π
11
3π/2 (-π/2)
TX Power Control
The transmitter power can be controlled by the MAC via two
registers. The first register, CR58, contains the results of
power measurements digitized by the HFA3863. By
comparing this measurement to what the MAC needs for
transmit power, the MAC can determine whether to raise or
lower the transmit power. It does this by writing the power
level desired to register CR31.
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
TABLE 5. DQPSK ENCODING TABLE
d2, d3
DQPSK modulation as shown in Table 7. Symbol numbering
starts with “0” for the first symbol of the MPDU.
The Clear Channel Assessment (CCA) circuit implements the
carrier sense portion of a Carrier Sense Multiple Access
(CSMA) networking scheme. The Clear Channel Assessment
(CCA) monitors the environment to determine when it is clear to
transmit. The CCA circuit in the HFA3863 can be programmed
to be a function of RSSI (energy detected on the channel),
CS1, SQ1, or various combinations. The CCA output goes to
the Media Access Controller (MAC). The MAC decides on
transmission based on traffic to send and the CCA indication.
The CCA indication can be ignored, allowing transmissions
independent of any channel conditions. The CCA in
combination with the visibility of the various internal parameters
(i.e., Energy Detection measurement results), can assist the
MAC in executing algorithms that can adapt to the environment.
These algorithms can increase network throughput by
minimizing collisions and reducing transmissions liable to
errors.
There are three measures that can be used in the CCA
assessment. The receive signal strength indication (RSSI)
which indicates the energy at the antenna, CS1 and carrier
sense (SQ1). CS1 becomes active anytime the AGC portion
of the circuit becomes unlocked, which is likely at the onset
of a signal that is strong enough to support 11Mbps, but may
not occur with the onset of a signal that is only strong
enough to support 1 or 2MBps. CS1 stays active until the
AGC locks and a SQ1 assessment is done, if SQ1 is false,
then CS1 is cleared, which deasserts CCA. If SQ1 is true,
then tracking is begun, and CCA continues to show the
HFA3863
channel busy. CS1 may occur at any time during acquisition
as the AGC state machine runs asynchronously with respect
to slot times.
SQ1 becomes active only when a spread signal with the
proper PN code has been detected, and the peak correlation
amplitude to sidelobe ratio exceeds a set threshold, so it
may not be adequate in itself.
A SQ1 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period. When this happens,
SQ1 is updated between 8 and 9µs into the 10µs dwell. If
CS1 is not active, two consecutive SQ1’s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
The Receive Signal Strength Indication (RSSI) measurement
is derived from the state of the AGC circuit. ED is the
comparison result of RSSI against a threshold. The threshold
may be set to an absolute power value, or it may be set to be
N dB above the measured noise floor. See CR 35. The
HFA3863 measures and stores the RSSI level when it detects
no presence of BPSK or QPSK signals. The average value of
a 256 value buffer is taken to be the noise floor. Thus, the
value of the noise floor will adapt to the environment. A
separate noise floor value is maintained for each antenna. An
initial value of the noise floor is established within 50µs of the
chip being active and is refined as time goes on. Deasserting
RX_PE does not corrupt the learned values. If the absolute
power metric is chosen, this threshold is normally set to
between -70 and -80dBm.
If desired, ED may be used in the acquisition process as well
as CCA. ED may be used to mask (squelch) weak signals
and prevent radio reception of signals too weak to support
the high data rates, signals from adjacent cells, networks, or
buildings.
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming details
on these registers can be found under the Control Registers
section of this document).
The CCA output from pin 60 of the device can be defined as
active high or active low through CR 1 (bit 2).
CR9(6:5) allow CCA to be programmed to be a function of
ED only, the logical operation of (CS1 OR SQ1), the logical
function of (ED AND (CS1 OR SQ1)), or (ED OR (CS1 OR
SQ1)).
CR9(7) lets the user select from sampled CCA mode, which
means CCA will not glitch, is updated once per symbol and
is valid for reading at 15.8µs or 18.7µs. In non-sampled
mode, CCA may change at any time, potentially several
4-13
times per slot, as ED and CS1 operate asynchronously to
slot times.
In a typical system CCA will be monitored to determine when
the channel is clear. Once the channel is detected busy,
CCA should be checked periodically to determine if the
channel becomes clear. Once MD_RDY goes active, CCA
should be ignored for the remainder of the message. Failure
to monitor CCA until MD_RDY goes active (or use of a timeout circuit) could result in a stalled system as it is possible for
the channel to be busy and then become clear without an
MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive
signal, the RF to IF downconverter HFA3683, the IF to
baseband converter HFA3783, and the baseband processor.
The AGC loop (Figure 6) is digitally controlled by the BBP.
Basically it operates as follows:
Initially, the receiver is set for high gain. The percent of time
that the A/D converters in the baseband processor are
saturated is monitored along with signal amplitude and the
gain is adjusted down until the amplitude is what will
optimize the demodulator’s performance. If the amount of
saturation is great, the initial gain adjust steps are large. If
the signal overload is small, they are less. When the gain is
about right and the A/Ds’ outputs are within the lock window
(CR19), the BBP declares AGC lock and stops adjusting for
the duration of the packet. If the signal level then varies more
than a preset amount (CR20, CR29), the AGC is declared
unlocked and the gain again allowed to readjust.
The BBP looks for the locked state following an unlocked
state (CS1) as one indication that a received signal is on the
antenna. This starts the receive process of looking for PN
correlation (SQ1). Once PN correlation and AGC lock are
found, the processor begins acquisition.
For large signals, the power level in the RF stage output is
also monitored and if it is large, the LNA stage is shut down.
This removes 30dB of gain from the receive chain which is
compensated for by replacing 30dB of gain in the IF AGC
stage. There is some hysteresis in this operation and once
the AGC locks, it is locked as well. This improves the
receiver dynamic range.
rxRfAGC Pad Operation
30dB Pad Engaging (RF Chip Low Gain):
If the AGC is not locked onto a packet, a '1' on the
ifCompDet input will engage in the 30dB attenuation pad.
This causes the AGC to go out of lock and also forces the
attenuation accumulator to be set to the programmed value
of CR27. The AGC then attempts to lock on the signal.
If the AGC is locked on a packet, ifCompDet is ignored.
HFA3863
30dB Pad Releasing (RF Chip High Gain):
If the AGC is not locked onto a packet and the attenuation
accumulator sum falls below the programmable threshold
(CR27), the pad will release. This is for the case where a
noise spike kicked in the 30dB pad and the pad should
release when the noise spike ends. Since the noise floor is
different for different environments, it is possible that in many
cases CR27's programmed value will be below the noise floor
and the pad will not be removed except by RXPE going low.
There is a recommended value to program CR27 (24dB), but
that depends on what environment the radio is in.
During a packet (after AGC lock), the 30dB pad is held
constant and the CR27 threshold is ignored.
RXPE low forces the pad to release whether in the middle of
a packet or not. At the end of a packet, RXPE always goes
low, forcing the pad to release.
Notes: The attenuation accumulator is basically about equal to
the current RSSI value.
The accumulator output, after going thru the interpolator
lookup table, feeds the AGC D/A.
The pad value is programmable (CR17), but is
recommended to be set to 30dB.
ifCompDet is a signal from the HFA3783 chip. A '1' indicates
its inputs are near saturation and it needs the RF chip to
switch from high gain to low gain.
RxIfDet is the input to the HFA3863 chip connected to
ifCompDet.
rxRfAGC is the output of the HFA3863 chip and '1' is high
gain, '0' is low gain.
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, or CCK symbols. The demodulator
includes a frequency tracking loop that tracks and removes
the carrier frequency offset. In addition, it tracks the symbol
timing, and differentially decodes and descrambles the data.
The data is output through the RX Port to the external
processor.
The PRISM baseband processor, HFA3863 uses
differentially coherent demodulation. The HFA3863 is
designed to achieve rapid settling of the carrier tracking loop
during acquisition. Rapid phase fluctuations are handled
with a relatively wide loop bandwidth which is then stepped
down as the packet progresses. Coherent processing
improves the BER performance margin as opposed to
differentially coherent processing for the CCK data rates.
The baseband processor uses time invariant correlation to
strip the Barker code spreading and phase processing to
4-14
demodulate the resulting signals in the header and
DBPSK/DQPSK demodulation modes. These operations are
illustrated in Figure 13 which is an overall block diagram of
the receiver processor.
In processing the DBPSK header, input samples from the I
and Q A/D converters are correlated to remove the
spreading sequence. The peak position of the correlation
pulse is used to determine the symbol timing. The sample
stream is decimated to the symbol rate and corrected for
frequency offset prior to PSK demodulation. Phase errors
from the demodulator are fed to the NCO through a lead/lag
filter to maintain phase lock. The carrier is de-rotated by the
carrier tracking loop. The demodulated data is differentially
decoded and descrambled before being sent to the header
detection section.
In the 1Mbps DBPSK mode, data demodulation is performed
the same as in header processing. In the 2Mbps DQPSK
mode, the demodulator demodulates two bits per symbol
and differentially decodes these bit pairs. The bits are then
serialized and descrambled prior to being sent to the output.
In the CCK modes, the receiver removes carrier frequency
offsets and uses a bank of correlators to detect the
modulation. A biggest picker finds the largest correlation in
the I and Q Channels and determines the sign of those
correlations. For this to happen, the demodulator must know
the starting phase which is determined by referencing the
data to the last bit of the header. Each symbol demodulated
determines 1 or 2 nibbles of data. This is then serialized and
descrambled before being passed to the output.
Carrier tracking is via a lead/lag filter using a digital Costas
phase detector. Chip tracking in the CCK modes is chip
decision directed or slaved to the carrier tracking depending
on whether or not the locked oscillator desing is utilized in
the radio.
Acquisition Description
A projected worst case time line for the acquisition of a
signal with a short preamble and header is shown. The
synchronization part of the preamble is 56 symbols long
followed by a 16-bit SFD. The receiver must monitor the
antenna to determine if a signal is present. The timeline is
broken into 10µs blocks (dwells) for the scanning process.
This length of time is necessary to allow enough integration
of the signal to make a good acquisition decision. This worst
case time line example assumes that the signal arrives part
way into the first dwell such as to just barely catch detection.
The signal and the scanning process are asynchronous and
the signal could start anywhere. In this timeline, it is
assumed that the signal is present in the first 10µs dwell, but
was missed due to power amplifier ramp up.
Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. A CS1 followed by SQ1 active, or two
HFA3863
received. At this time the demodulator is tracking and in the
coherent PSK demodulation mode so it will no longer
acquire new signals. If a much larger signal overrides the
signal being demodulated (a collision), the demodulator will
abort the tracking process and attempt to acquire the new
signal. Failure to find an SFD within the SFD timeout
interval will result in a receiver reset and return to
acquisition mode.
consecutive SQ1’s will cause the part to finish the
acquisition phase and enter the tracking phase.
Prior to initial acquisition the NCO is inactive (0Hz) and
carrier phase measurement are done on a symbol by symbol
basis. After acquisition, coherent DPSK demodulation is in
effect. After a brief setup time as illustrated on the timeline,
the signal begins to emerge from the demodulator.
It takes 7 more symbols to seed the descrambler before
valid data is available. This occurs in time for the SFD to be
TX
POWER
RAMP
SFD
56 SYMBOL SYNC
2
20 SYMBOLS
20 SYMBOLS
7 SYM
AGC SETTLE AND LOCK
AND INITIAL DETECTION
VERIFY AND CIR/FREQUENCY
ESTIMATION AND CMF/NCO
JAMMING
SEED
DESCRAMBLER
START SFD SEARCH
FIGURE 10. ACQUISITION TIMELINE, NON DIVERSITY
4-15
16 SYMBOLS
SFD DET
START DATA
HFA3863
VDD (ANALOG)
(12, 17, 22, 31)
VDD (DIGITAL)
(2, 8, 37, 41, 57)
GND (ANALOG)
(9, 15, 20, 25, 28)
GND (DIGITAL)
(1, 7, 36, 43, 56)
IREF (21)
(52) RXCLK
TX_IF_AGC (35)
6-BIT
DAC
ANTSEL (39)
ANTSEL (40)
REGISTER
TRANSMIT
FILTER
DAC
TXI (23, 24)
TXQ (29, 30)
TRANSMIT
PORT
TX AGC
CONTROL
OUTPUT MUX
6-BIT
ADC
DAC
OUTPUT MUX
TX_AGC_IN (18)
TEST CONTROL
VREF (16)
(60) CCA
PREAMBLE/HEADER
CRC-16
GENERATOR
(59) TX_RDY
(55) TXCLK
MODULATOR,
BARKER/CCK
TX_DATA
SCRAMBLER
TX
STATE
CONTROL
TIMING
GENERATOR
MCLK
(4) SCLK
(64) SDI
(5) R/W
(6) CS
TEST 7
TEST 6
TEST 5
TEST 4
TEST 3
TEST 2
(44) (45) (46) (47) (48) (49) (50) (51)
TEST 1
(42)
MCLK
(3) SD
TEST PORT
TEST 0
(62) TX_PE
SERIAL CONTROL
PORT
PROCESSOR INTERFACE
(58) TXD
FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
Channel Matched Filter (CMF) Description
The receive section shown in Figure 13 operates on the
RAKE receiver principle which maximizes the SNR of the
signal by combining the energy of multipath signal
components. The RAKE receiver is implemented with a
Channel Matched Filter (CMF) using a FIR filter structure
with 16 taps. The CMF is programmed by calculating the
Channel Impulse Response (CIR) of the channel and
mathematically manipulating that to form the tap coefficients
of the CMF. Thus, the CMF is set to compensate the channel
characteristics that distort the signal. Since the calculation of
the CIR is inaccurate at low SNR or in the presence of strong
CW interference, the chip has thresholds (CR 36 to 39) that
4-16
are set to substitute a default CMF shape under those
conditions. This default CMF shape is designed to
compensate only the known transmit and receive non
linearity.
PN Correlators Description
There are two types of correlators in the HFA3863 baseband
processor. The first is a parallel matched filter correlator that
correlates for the Barker sequence used in preamble,
header, and PSK data modes. This Barker code correlator is
designed to handle BPSK spreading with carrier offsets up
to ±50ppm and 11 chips per symbol. Since the spreading is
BPSK, the correlator is implemented with two real
HFA3863
correlators, one for the I and one for the Q Channel. The
same Barker sequence is always used for both I and Q
correlators.
For DBPSK, the decoding is simple differential decoding.
TABLE 8. DQPSK DATA DECODER
These correlators are time invariant matched filters otherwise
known as parallel correlators. They use one sample per chip for
correlation although two samples per chip are processed. The
correlator despreads the samples from the chip rate back to the
original symbol rate giving 10.4dB processing gain for 11 chips
per symbol. While despreading the desired signal, the
correlator spreads the energy of any non correlating interfering
signal.
The second form of correlator is the parallel correlator bank
used for detection of the CCK modulation. For the CCK
modes, the 64 wide bank of parallel correlators is
implemented with a Fast Walsh Transform to correlate the 4
or 64 code possibilities. This greatly simplifies the circuitry of
the correlation function. It is followed by a biggest picker
which finds the biggest of 4 or 64 correlator outputs
depending on the rate. This is translated into 2 or 6 data bits.
The detected output is then processed through the
differential phase decoder to demodulate the last two bits of
the symbol.
Data Demodulation and Tracking
Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks
tracked by the symbol timing loop (bit sync) as shown in
Figure 12. The frequency and phase of the signal is
corrected using the NCO that is driven by the phase locked
loop. Averaging the phase errors over 10 symbols gives the
necessary frequency information for seeding the NCO
operation.
Data Decoder and Descrambler
Description
The data decoder that implements the desired DQPSK
coding/decoding as shown in Table 8. The data is formed
into pairs of bits called dibits. The left bit of the pair is the first
in time. This coding scheme results from differential coding
of the dibits. Vector rotation is counterclockwise for a positive
phase shift, but can be reversed with bit 7 or 6 of CR 1.
DIBIT PATTERN (D0, D1)
D0 IS FIRST IN TIME
PHASE SHIFT
0
00
+90
01
+180
11
-90
10
The data scrambler and de-scrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler is designed
to ensure smearing of the discrete spectrum lines produced
by the PN code.
One thing to keep in mind is that both the differential decoding
and the descrambling cause error extension or burst errors.
This is due to two properties of the processing. First, the
differential decoding process causes errors to occur on pairs of
symbols. When a symbol’s phase is in error, the next symbol
will also be decoded wrong since the data is encoded in the
change in phase from one symbol to the next. Thus, two errors
are made on two successive symbols. Therefore up to 4 bits
may be wrong although on the average only 2 are. In QPSK
mode, these may occur next to one another or separated by up
to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
It should be taken into account if a forward error correction
scheme is contemplated.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusiveor of the data and the sum of taps in the shift register.
SAMPLES
AT 2X CHIP
RATE
CORRELATION
PEAK
CORRELATION TIME
T0
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE RECEIVED SIGNAL
T0 + 1 SYMBOL CORRELATOR
OUTPUT REPEATS
FIGURE 12. CORRELATION PROCESS
4-17
EARLY
ON-TIME
LATE
T0 + 2 SYMBOLS
HFA3863
VDD (ANALOG)
(12, 17, 22, 31)
GND (ANALOG)
(9, 15, 20, 25, 28)
VDD (DIGITAL)
(2, 8, 37, 41, 57)
GND (DIGITAL)
(1, 7, 36, 43, 56)
(60) CCA
RX_IF_DET (19)
RX_IF_AGC (34)
DPSK
DEMOD
8
EQUAL.
BIAS
ADDER
LOOP
FILTER
TIMING
GENERATOR
MCLK
(5) R/W
(6) CS
6-BIT
DAC
TXI (23, 24)
6-BIT
DAC
TXQ (29, 30)
(46) (47) (48) (49) (50) (51)
FIGURE 13. DSSS BASEBAND PROCESSOR, RECEIVE SECTION
4-18
(64) SDI
TEST 7
(45)
TEST 4
(44)
TEST 3
(42)
MCLK
TEST 2
(61)
RX_PE
(4) SCLK
TEST PORT
TEST 1
(63)
RESET
(3) SD
SERIAL CONTROL
PORT
MUX
MUX
TEST CONTROL
RECEIVE
STATE
MACHINE
ANTENNA
SWITCH
CONTROL
TEST 0
ANTSEL (39)
SYMBOL
DECISION
(54) MD_RDY
DECISION FEEDBACK
EQUALIZER
COHERENT
TIMING
INTEGRATOR
ANTSEL (40)
CCK
CORREL
(52) RXCLK
RECEIVE
PORT
SYMBOL
TRACKING
NCO
(53) RXD
RX_DATA
DESCRAMBLER
TEST 6
6
PEAK
EXTRACT.
PREAMBLE/HEADER
CRC-16 DETECT
6-BIT
A/D
6
CORRELATOR
BARKER
6-BIT
A/D
BIT
SYNC
8
TEST 5
RXQ (13, 14)
CMF
TRAINING
CHANNEL
MATCHED FILTER
RXI (10, 11)
CLEAR CHANNEL
ASSESSMENT/
SIGNAL QUALITY
DIVERSITY
CONTROL
DOWN CONVERT
ANT SEL (39, 40)
INTERPOLATING
BUFFER
RX-RF-AGC (38)
AGC
CONTROL
6-BIT
DAC
HFA3863
Data Demodulation in the CCK Modes
Tracking
In this mode, the demodulator uses Complementary Code
Keying (CCK) modulation for the two highest data rates. It is
slaved to the low rate processor which it depends on for
acquisition of initial timing and phase tracking information.
The low rate section acquires the signal, locks up symbol
and carrier tracking loops, and determines the data rate to
be used for the MPDU data.
Carrier tracking is performed on the de-rotated signal
samples from the complex multiplier in a four phase Costas
loop. This forms the error term that is integrated in the lead/lag
filter for the NCO, closing the loop. Tracking is only measured
when there is a chip transition. Note that this tracking is
dependent on a positive SNR in the chip rate bandwidth.
The demodulator for the CCK modes takes over when the
preamble and header have been acquired and processed.
On the last bit of the header, the phase of the signal is
captured and used as a phase reference for the high rate
differential demodulator.
The signal from the A/D converters is carrier frequency and
phase corrected by a DESPIN stage. This removes the
frequency offset and aligns the I and Q Channels properly for
the correlators. The sample rate is decimated to 11MSPS for
the correlators after the DESPIN since the data is now
synchronous in time.
The demodulator knows the symbol timing, so the
correlation is batch processed over each symbol. The
correlation outputs from the correlator are compared to each
other in a biggest picker and the chosen one determines 6
bits of the symbol. The QPSK phase of the chosen one
determines two more bits for a total of 8 bits per symbol. Six
bits come from which of the 64 correlators had the largest
output and the last two are determined from the QPSK
differential demod of that output. In the 5.5Mbps mode, only
4 of the correlator outputs are monitored. This demodulates
2 bits for which of 4 correlators had the largest output and 2
more for the QPSK demodulation of that output for a total of
4 bits per symbol.
Equalizer Description
The HFA3863 employs a Decision Feedback Equalizer
(DFE) to improve performance in the presence of significant
multipath distortion. The DFE combats Inter Chip
Interference (ICI) and Inter Symbol Interference (ISI). The
equalizer is trained on the sample data collected during the
first part of the acquisition after the AGC has settled and the
antenna selected. The same data is used for CMF
calculations and equalizer training. Once the equalizer has
been set up, it is used to process the incoming symbols in a
decision feedback manner. After the Fast Walsh transform is
performed, the detected symbols are corrected for ICI before
the bigger picker where the symbol decision process is
performed. Once a symbol has been demodulated, the
calculated residual energy from that symbol is subtracted
from the incoming data for the next symbol. That corrects for
the ISI component. The DFE is not adapted during the
packet as the channel impulse response is not expected to
vary significantly during that brief time. Register CR10 bits 4
and 5 can disable these equalizers separately.
4-19
The symbol clock is tracked by a sample interpolator that
can adjust the sample timing forwards and backwards by 72
increments of 1/8th chip. This approach means that the
HFA3863 can only track an offset in timing for a finite interval
before the limits of the interpolator are reached. Thus,
continuous demodulation is not possible.
Locked Oscillator Tracking
Symbol tracking can be slaved to the carrier offset tracking
for improved performance as long as at both the transmitting
and the receiving radios, the bit clocks and carrier frequency
clocks are locked to common crystal oscillators. A bit carried
in the SERVICE field (bit 2) indicates whether or not the
transmitter has locked clocks. When the same bit is set at
the receiver (CR6 bit 2), the receiver knows it can track the
bit clock by counting down the carrier tracking offset. This is
much more accurate than tracking the bit clock directly.
CR33 bit 6 can enable or disable this capability.
Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
demodulator uses coherent processing for data
demodulation. The figures below show the performance of
the baseband processor when used in conjunction with the
HFA3783 IF and the PRISM recommended IF filters. Off the
shelf test equipment are used for the RF processing. The
curves should be used as a guide to assess performance in
a complete implementation.
Factors for carrier phase noise, multipath, and other
degradations will need to be considered on an
implementation by implementation basis in order to predict
the overall performance of each individual system.
Figure 14 shows the curves for theoretical DBPSK/DQPSK
demodulation with coherent demodulation and
descrambling as well as the PRISM performance measured
for DBPSK and DQPSK. The theoretical performance for
DBPSK and DQPSK are the same as shown on the
diagram. Figure 15 shows the theoretical and actual
HFA3863
performance of the CCK modes. The losses in both figures
include RF and IF radio losses; they do not reflect the
HFA3863 losses alone. The HFA3863 baseband
processing losses from theoretical are, by themselves, a
small percentage of the overall loss.
The PRISM demodulator performs with an implementation
loss of less than 4dB from theoretical in a AWGN
environment with low phase noise local oscillators. For the
1 and 2Mbps modes, the observed errors occurred in
groups of 4 and 6 errors. This is because of the error
extension properties of differential decoding and
descrambling. For the 5.5 and 11Mbps modes, the errors
occur in symbols of 4 or 8 bits each and are further
extended by the descrambling. Therefore the error patterns
are less well defined.
Eb/N0
7
8
9
10
11
12
1.E+00
1.E-01
1.E-02
BER 2.0
1.E-04
THY 1, 2
BER
1.E-03
BER 1.0
1.E-05
1.E-06
1.E-07
1.E-08
FIGURE 14. BER vs Eb/N0 PERFORMANCE FOR PSK MODES
Eb/N0
1.E+00
5
6
7
8
9
10
11
12
13
14
1.E-01
BER 11
1.E-02
BER
1.E-03
1.E-04
1.E-05
THY 11
THY 5.5
BER 5.5
1.E-06
1.E-07
1.E-08
1.E-09
FIGURE 15. BER vs Eb/N0 PERFORMANCE FOR CCK MODES
4-20
Clock Offset Tracking Performance
The PRISM baseband processor is designed to accept data
clock offsets of up to ±25ppm for each end of the link (TX
and RX). This effects both the acquisition and the tracking
performance of the demodulator. The budget for clock offset
error is 0.75dB at ±50ppm. No appreciable degradation was
seen for operation in AWGN at ±50ppm. Symbol tracking is
accomplished by one of two methods. If both ends of the link
employ locked oscillators for their bit timing and carrier
frequency generation, symbol tracking is done by dividing
down the carrier frequency offset. If either one of the ends of
the link do not have locked oscillators, then symbol tracking
is done by a conventional early-late chip tracking method.
Carrier Offset Frequency Performance
The correlators used for acquisition for all modes and for
demodulation in the 1 and 2Mbps modes are time invariant
matched filter correlators otherwise known as parallel
correlators. They use two samples per chip and are tapped
at every other shift register stage. Their performance with
carrier frequency offsets is determined by the phase roll rate
due to the offset. For an offset of +50ppm (combined for both
TX and RX) will cause the carrier to phase roll 22.5 degrees
over the length of the correlator. This causes a loss of
0.22dB in correlation magnitude which translates directly to
Eb/N0 performance loss. In the PRISM chip design, the
carrier phase locked loop is inactive during acquisition.
During tracking, the carrier tracking loop corrects for offset,
so that no degradation is noted. In the presence of high
multipath and high SNR, however, some degradation is
expected.
RSSI Performance
The RSSI value is reported on CR62 in hex and is linear with
signal level in dB. Figure 16 shows the RSSI curve
measured on a whole evaluation radio. This takes into
account the full gain adjust range of all radio parts. To get
signal level in dBm on a radio, simply subtract the RSSI
value in decimal from 100.
HFA3863
ED Threshold
120
The performance of the ED threshold is shown in Figure 18.
Setting this threshold will effect CCA only. Using ED as part
of the CCA measure will allow deferral to large signals even
if they are not correlated to the desired spread signals.
RSSI
100
ED can be read from CR61 bit 4. Using ED and RSSI can
assist the MAC in determining the presence of non
correlating signals such as frequency hoppers or microwave
ovens. For example, the MAC can elect to try to transmit
over microwave oven interference but not count the results in
rate shifting algorithms.
60
40
20
40
0
-100
-80
-60
-40
-20
0
SIGNAL LEVEL IN dBm
FIGURE 16. RSSI vs SIGNAL LEVEL
Signal Quality Estimate
A signal quality measure is available on CR51 for use by the
MAC. This measure is the SNR in the carrier tracking loop
and can be used to determine when the demodulator is
working near to the noise floor and likely to make errors.
Figure 17 shows the performance of the SQ measure versus
signal to noise level.
ED THRESHOLD VALUE IN DECIMAL
RSSI IN DE
80
30
20
10
0
STARTS MISSING
MISSING
-10
0
10
20
30
40
SNR IN SPREAD BANDWIDTH
100
FIGURE 18. ED THRESHOLD vs SNR IN dB AT 1Mbps
90
80
A Default Register Configuration
70
60
50
40
PER
30
MEAN
20
STDDEV
10
0
-10
-5
0
5
10
15
20
25
SNR IN THE SPREAD BANDWIDTH AT 1Mbps
FIGURE 17. SIGNAL QUALITY MEASURE AND PER vs SNR
4-21
The registers in the HFA3863 are addressed with 7-bit numbers
where the lower 1 bit of an 8-bit hexadecimal address is left as
unused. This results in the addresses being in increments of 2
as shown in the table below. Table 9 shows the register values
for a default 802.11 configuration with various rate
configurations. The data is transmitted as either DBPSK,
DQPSK, or CCK depending on the configuration chosen. It is
recommended that you start with the simplest configuration
(DBPSK) for initial test and verification of the device and/or the
radio design. The user can later modify the CR contents to
reflect the system and the required performance of each
specific application.
HFA3863
TABLE 9. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY
CONFIGURATION
REGISTER
NAME
TYPE
REGISTER
ADDRESS HEX
RECOMMENDED
FOR
1/2/5.5/11Mbps
R
00
30
CR0
Part/Version Code
CR1
I/O Polarity
R/W
02
00
CR2
RX Configure
R/W
04
001
CR3
TX Preamble Length for Short Preamble
R/W
06
38
CR4
TX Preamble Length for Long Preamble
R/W
08
80
CR5
TX Signal Field
R/W
0A
00/01/02/03
CR6
TX Service Field
R/W
0C
04
CR7
TX Length Field, High
R/W
0E
04
CR8
TX Length Field, Low
R/W
10
00
CR9
RX/TX Configure
R/W
12
A2
CR10
RX Configure 1
R/W
14
C8
CR11
RX/TX Configure
R/W
16
03
CR12
A/D Test Modes 1
R/W
18
00
CR13
A/D Test Modes 2
R/W
1A
00
CR14
A/D Test Modes 3
R/W
1C
00
CR15
AGC GainClip
R/W
1E
5C
CR16
AGC Saturation Counts
R/W
20
82
CR17
AGC RxRfpad Value
R/W
22
1E
CR18
AGC HiSat
R/W
24
C7
CR19
AGC LockinLevel/CW Detect Threshold
R/W
26
17
CR20
AGC LockWindow, Pos Side
R/W
28
6A
CR21
AGC Backoff
R/W
2A
12
CR22
AGC Lookup Table Addr and Control
R/W
2C
00
CR23
AGC Lookup Table Data
R/W
2E
00
CR24
AGC LoopGain
R/W
30
2D
CR25
AGC Manual Setting
R/W
32
20
CR26
AGC Test Modes
R/W
34
82
CR27
AGC RX_RF Threshold
R/W
36
18
CR28
AGC Low and Mid SatAtten
R/W
38
79
CR29
AGC LockWindow, Negative Side
R/W
3A
CA
CR30
Carrier Sense 2 Scale Factor
R/W
3C
24
CR31
Manual TX Power Control
R/W
3E
F0
CR32
Test Modes 1
R/W
40
00
CR33
Test Modes 2
R/W
42
00
CR34
Test Bus Address
R/W
44
00
CR35
ED Threshold
R/W
46
7F
CR36
CMF Coefficient Control, Delay Spread
R/W
48
8B
CR37
CW RSSI Threshold
R/W
4A
0F
CR38
SNR Threshold #1
R/W
4C
06
CR39
SNR Threshold #2
R/W
4E
0C
CR40
DC Offset Threshold
R/W
50
0F
CR41
Preamble/Header Tracking Loop Lead Coefficient
R/W
52
2E
CR42
Preamble/Header Tracking Loop Lag Coefficient
R/W
54
20
CR43
Data Tracking Loop Lead Coefficient
R/W
56
10
CR44
Data Tracking Loop Lag Coefficient
R/W
58
10
4-22
HFA3863
TABLE 9. CONTROL REGISTER VALUES FOR DUAL ANTENNA DIVERSITY (Continued)
CONFIGURATION
REGISTER
NAME
TYPE
REGISTER
ADDRESS HEX
RECOMMENDED
FOR
1/2/5.5/11Mbps
CR45
False Alarm Rate Scale Factor
R/W
5A
02
CR46
Preamble Timeline Control
R/W
5C
2E
CR47
Acquisition Control
R/W
5E
1E
CR48
Scrambler Seed for Long Preamble
R/W
60
26
CR49
Read Only Register Mux Control For Registers 50 to 63
Scrambler Seed for Short Preamble
R/W
62
5B
CR50
a&b: Test Bus Read
R
64
N/A
CR51
a: Noise floorAntA
b: Signal Quality Measure Based on Carrier Tracking
R
66
N/A
CR52
a: Noise floorAntB
b: Received Signal Field
R
68
N/A
CR53
a: DC offset I channel
b: Received Service Field
R
6A
N/A
CR54
a. DC offset Q Channel
b: Received Length Field, Low
R
6C
N/A
CR55
a: Multipath Metric on Last Packet
b: Received Length Field, High
R
6E
N/A
CR56
a. Multipath count
b: Calculated CRC on Received Header, Low
R
70
N/A
CR57
a. Packet Signal Quality Metric
b: Calculated CRC on Received Header, High
R
72
N/A
CR58
b: TX Power Measurement
R
74
N/A
CR59
a: Header Signal Quality Metric
b: RX Mean Power
R
76
N/A
CR60
b: RX_IF AGC
R
78
N/A
CR61
b: RX Status Register
R
7A
N/A
CR62
b: RSSI
R
7C
N/A
CR63
b: RX Status Register
R
7E
N/A
NOTE: See CR2 bit 0 description for initialization procedure.
AGC REGISTER SETTINGS (Continued)
AGC REGISTER SETTINGS
CR22
DECIMAL
CR23
HEX
CR22
DECIMAL
CR23
HEX
00
0C
16
4B
01
10
17
50
02
14
18
55
03
18
19
5A
04
1C
20
63
05
20
21
6D
24
22
76
07
28
23
7F
08
2E
24
7F
09
34
25
7F
10
38
26
7F
3C
27
7F
12
3F
28
7F
13
43
29
7F
14
46
30
7F
15
48
31
7F
06
11
4-23
HFA3863
Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE
Bit 7:4
Part Code
3 = HFA3863 series
Bit 3:0
Version Code
0 = 3863 Version
CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY
This register is used to define the phase of clocks and other interface signals. 00h is normal setting.
Bit 7
This control bit selects the phase of the receive carrier rotation sense.
Logic 1 = Inverted rotation (CW), Invert Q in.
Logic 0 = normal rotation (CCW).
Bit 6
This control bit selects the phase of the transmit carrier rotation sense.
Logic 1 = Inverted rotation (CW), Invert Q out.
Logic 0 = normal rotation (CCW).
Bit 5
This control bit selects the phase of the transmit output clock (TXCLK) pin.
Logic 1 = Inverted TXCLK.
Logic 0 = NON-Inverted TXCLK.
Bit 4
This control bit selects the active level of the Transmit Ready (TX_RDY) output which is an output pin at the test port, pin.
Logic 1 = TX_RDY Active 0.
Logic 0 = TX_RDY Active 1.
Bit 3
This control bit selects the active level of the transmit enable (TX_PE) input pin.
Logic 1 = TX_PE Active 0.
Logic 0 = TX_PE Active 1.
Bit 2
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin.
Logic 1 = CCA Active 1.
Logic 0 = CCA Active 0.
Bit 1
This control bit selects the active level of the MD_RDY output pin.
Logic 1 = MD_RDY is Active 0.
Logic 0 = MD_RDY is Active 1.
Bit 0
This controls the phase of the RX_CLK output.
Logic 1 = Invert Clk.
Logic 0 = Non-Inverted Clk.
CONFIGURATION REGISTER 2 ADDRESS (04h) R/W RX CONFIGURE
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bits 7:1
Reserved.
Bit 0
Initialization.
0 = Normal Operation.
1 = Soft Initialization of learned behavior registers such as DCoffset, NoiseFloor, FAR, RecPacketsNOcs1, and
RecPacketsUSEdef. Holds AGC logic reset. At part initialization, must be set, then after CR47 is loaded, cleared.
CONFIGURATION REGISTER 3 ADDRESS (06h) R/W TX PREAMBLE LENGTH FOR SHORT PREAMBLE
Bits 0 - 7
This register contains the count for the Preamble length counter for short preambles selected by CR5 bit 3. Setup while TX_PE
is low. For IEEE 802.11 use38h. For other than IEEE 802.11 applications, in general increasing the preamble length will improve
low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. A 2
symbol TX power amplifier ramp up is added to programmed value.
CONFIGURATION REGISTER 4 ADDRESS (08h) R/W TX PREAMBLE LENGTH FOR LONG PREAMBLE
Bits 0 - 7
This register contains the count for the Preamble length counter for long preambles selected with CR5 bit 3 or CR11 bit 4.
Setup while TX_PE is low. For IEEE 802.11 use 80h. For other than IEEE 802.11 applications, in general increasing the preamble
length will improve low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value
is 56d = 38h. A 2 symbol TX power amplifier ramp up is added to programmed value. If you program 128 you get 130.
4-24
HFA3863
CONFIGURATION REGISTER 5 ADDRESS (0Ah) R/W TX SIGNAL FIELD
Bits 7:5
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 4
TX/RX filter / CMF weight select.
0 = US.
1 = Japan.
Bits 3
Select preamble mode.
0 = Normal, long preamble interoperable with 1 and 2Mbps legacy equipment.
1 = short preamble and header mode (optional in 802.11).
Bit 2
Reserved, must be set to 0.
Bits 1:0
TX data Rate. Must be set at least 2µs before needed in TX frame. This selects TX signal field code from the registers above.
00 = DBPSK - 11 chip sequence (1Mbps).
01 = DQPSK - 11 chip sequence (2Mbps).
10 = CCK - 8 chip sequence (5.5Mbps).
11 = CCK - 8 chip sequence (11Mbps).
CONFIGURATION REGISTER 6 ADDRESS (0Ch) R/W TX SERVICE FIELD
Bits 7:0
Bit 7 may be employed by the MAC in 802.11 situations to resolve an ambiguity in the length field when in the 11Mbps mode.
Bit 2 should be set to a 1 where the reference oscillator of the radio is common for both the carrier frequency and the data
clock. All other bits should be set to 0 to ensure compatibility.
CONFIGURATION REGISTER 7 ADDRESS (0Eh) R/W TX LENGTH FIELD (HIGH)
Bits 7:0
This 8-bit register contains the higher byte (bits 8-15) of the transmit Length Field described in the Header. This byte combined
with the lower byte indicates the number of microseconds the data packet will take.
CONFIGURATION REGISTER 8 ADDRESS (10h) R/W TX LENGTH FIELD (LOW)
Bits 7:0
This 8-bit register contains the lower byte (bits 0-7) of the transmit Length Field described in the Header. This byte combined
with the higher byte indicates the number of microseconds the data packet will take.
CONFIGURATION REGISTER 9 ADDRESS (12h) R/W TX CONFIGURE
Bit 7
CCA sample mode time.
0 = 18.7µs.
1 = 15.8µs.
Bits 6:5
CCA mode.
00 - CCA is based only on ED.
01 - CCA is based on (CS1 OR SQ1).
10 - CCA is based on (ED AND (CS1 OR SQ1)).
11 - CCA is based on (ED OR (CS1 OR SQ1)).
Bit 4
TX test modes.
0 = Alternating bits for carrier suppression test. (Needs scrambler off (CR32 [2] = 1)).
1 = all chips set to 1 for CW carrier. This allows frequency measurement.
Bit 3
Enable TX test modes.
0 = normal operation.
1 = Invoke tests described by bit 4.
Bit 2
Antenna choice for TX when TX antenna diversity is disabled.
0 = Set AntSel low.
1 = Set AntSel high.
Bit 1
TX Antenna Mode.
0 = Disable diversity, set AntSel pin to value in bit 2.
1 = Enable diversity, set AntSel pin to antenna for which last valid received header CRC occurred.
Bit 0
High Rate cover code disable.
0 = Enable.
1 = Disable.
4-25
HFA3863
CONFIGURATION REGISTER 10 ADDRESS (14h) R/W RX CONFIGURE
Bit 7
AGC freeze during packet.
0 = Disable (do not disable unless MAC can handle baseband processor aborting during MPDU reception).
1 = Enable.
Bit 6
CIR estimate/ Dot product clock control.
0 = on during acquisition.
1 = only on after detect.
Bit 5
ISI equalizer control.
0 = enable equalizer.
1 = disable equalizer.
Bit 4
ICI equalizer control.
0 = enable equalizer.
1 = disable equalizer.
Bit 3
MD_RDY control.
0 = After CRC16.
1 = After SFD.
Bit 2
Slot diversity mode control.
0 = disabled, Antenna diversity on for entire slot.
1 = enabled, Antenna diversity disabled for last half of slot - saves acquisition time, use in system where nodes are slot aligned.
Bit 1
Antenna choice for Receiver when single antenna acquisition is selected.
0 = Antenna select pin low.
1 = Antenna select pin high.
Bit 0
Single or dual antenna acquire.
0 = dual antenna for diversity acquisition.
1 = single antenna.
CONFIGURATION REGISTER 11 ADDRESS (16h) R/W RX-TX CONFIGURE
Bit 7
Continuous internal RX 22 and 44MHz clocks; (Only Reset active will stop).
0 = normal.
1 = continuous, overrides CR10 bit 6.
Bit 6
A/D input coupling.
0 = DC.
1 = AC (external bias network required).
Bit 5
Reserved.
Bit 4
Short Preamble test mode.
0 = use CR3 for short preamble.
1 = run TX and RX short preamble using preamble length in CR4.
Bit 3
CCA mode.
0 = normal (raw) mode CCA. CCA will immediately respond to changes in ED, CS1, and SQ1 as configured.
1 = Sampled mode CCA. CCA will update once per slot (20µs), will be valid at 18.7µs or 15.8µs as determined by CR9 bit 7.
Bits 2:0
Precursor value in CIR estimate.
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1
Bit 7
All DAC and A/D clock source control.
0 = normal internal clocks.
1 = clock via SDI pin.
Bit 6
TX DAC clock.
0 = enable.
1 = disable.
Bit 5
RX DAC clock.
0 = enable.
1 = disable.
Bit 4
I DAC clock.
0 = enable.
1 = disable.
4-26
HFA3863
CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 (Continued)
Bit 3
Q DAC clock.
0 = enable.
1 = disable.
Bit 2
RF A/D clock.
0 = enable.
1 = disable.
Bit 1
I A/D clock.
0 = enable.
1 = disable.
Bit 0
Q A/D clock.
0 = enable.
1 = disable.
CONFIGURATION REGISTER 13 ADDRESS (1Ah) R/W A/D TEST MODES 2
Bit 7
Standby.
1 = enable.
0 = disable.
Bit 6
SLEEPTX.
1 = enable.
0 = disable.
Bit 5
SLEEP RX.
1 = enable.
0 = disable.
Bit 4
SLEEP IQ.
1 = enable.
0 = disable.
Bit 3
Analog TX Shut_down.
1 = enable.
0 = disable.
Bit 2
Analog RX Shut_down.
1 = enable.
0 = disable.
Bit 1
Analog Standby.
1 = enable.
0 = disable.
Bit 0
Enable manual control of mixed signal power down signals using bits 1:7.
1 = enable.
0 = disable, normal operation (devices controlled by RESET, TX_PE, RX_PE).
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3
Bit 7
Digital format, select output of I/Q and RF A/D converters.
0 = 2’s complement.
1 = binary.
Bits 6:4
I/Q DAC input control. This DAC gives an analog look at various internal digital signals that are suitable for analog
representation.
000 = normal (TX filter).
001 = down converter output.
010 = E/L integrator - upper 6 bits of the TCHIPacc on (Q) and zeros on (I).
011 = I/ Q A/D’s.
100 = Bigger picker output. Upper 6 bits of FWT_I winner and FWT_Q winner.
101 = CMF weights - upper 6 bits of all 16 CMF weights are circularly shifted with full scale negative sync pulse interleaved
between them.
110 = Test Bus pins (5:0) when configured as inputs, CR32(4), ((5:0) to both I and Q inputs).
111 = Barker Correlator/ low rate samples - as selected by bit 7 CR32.
4-27
HFA3863
CONFIGURATION REGISTER 14 ADDRESS (1Ch) R/W A/D TEST MODES 3 (Continued)
Bit 3
Enable test bus into RX and TX DAC (if below bit 2 is 0).
0 = normal.
1 = enable.
Bit 2
Enable RF A/D into RX DAC.
0 = normal.
1 = enable.
Bit 1
VRbit1.
Bit 0
VRbit0.
CONFIGURATION REGISTER 15 ADDRESS (1Eh) R/W AGC GAIN CLIP
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC gain clip (7-bit value, 0-127) this is the attenuator accumulator upper limit. The lower limit is 0.
CONFIGURATION REGISTER 16 ADDRESS (20h) R/W AGC SATURATION COUNTS
Bits 7:4
AGC mid Saturation counts (0-15 range) these are the counts to kick in the low and mid attenuator steps (CR28).
Bits 3:0
AGC low Saturation Count (0-15 range).
CONFIGURATION REGISTER 17 ADDRESS (22h) R/W AGC RF PAD VALUE
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
RXRF_AGC pad value to use in the RSSI calculation, Range 0 - 63dB (nominally 30dB).
CONFIGURATION REGISTER 18 ADDRESS (24h) R/W AGC HI SAT
Bits 7:4
AGC high saturation attenuation value (0-30).
Note: hi saturation attenuation step actual value is programmed value times 2. This attenuation step will occur if the # of I and
Q sats is greater than hi saturation count.
Bits 3:0
AGC hi sat count (0-15 range).
CONFIGURATION REGISTER 19 ADDRESS (26h) R/W AGC LOCK IN LEVEL
Bits 7:5
CW detector scale multiplication factor. (xxxx.x). See CR35 and CR 49.
Set to 00h for forcing CW detect always active.
Set to 0Fh for forcing CW detector always inactive.
Bits 4:0
AGC Lock-in level (0-7.5 range). Note this is the inner lock window.
CONFIGURATION REGISTER 20 ADDRESS (28h) R/W AGC LOCK WINDOW POS.
Bits 7:5
AGC max lock count for antenna search. The number of updates required to lock AGC must be less than or equal to this count
for antenna diversity search to be allowed to run. Range 0 to 7.
Bit 4:0
AGC Lock Window positive side (0-15.5 range). Note: this is the outer lock window.
CONFIGURATION REGISTER 21 ADDRESS (2Ah) R/W AGC BACKOFF
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5:0
AGC Backoff (xxxxx.x, 0-31.5 range) in half dB steps. This sets the operating headroom in the I and Q ADCs.
CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC LOOKUP TABLE ADDRESS
Bits 7,6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5
AGC Look up table read control bit.
1 = Read AGC table at address given below.
0 = Read contents of CR23.
Bits 4:0
AGC lookup table address (32 address bits).
4-28
HFA3863
CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC look up table data, unsigned.
CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC LOOP GAIN
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6:0
AGC loop gain (0.xxxx - x.00000, 0 - 1.0000 range), nominally 0.7.
CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC RX_IF AND RF
Bits 7
AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1.
When Polarity bit (CR26[6]) is zero:
1 = removes 30dB pad.
0 = inserts 30dB pad.
Bits 6:0
AGC RX_IF, This CR is input to RF-IF DAC if AGC override Enable (CR 26[2]) is set to 1.
Bits 7
AGC continuous update.
0 = disable, no updates during AGC freeze.
1 = allow updates during freeze AGC and AGC_lock.
See also CR17[7].
Bit 6
rxRFAGC polarity control.
0 = normal.
1 = invert.
Bit 5
AGC extra update disable. Allows final 32 sample update tweak after AGC_lock is declared.
0 = enable an extra update.
1 = disable extra update.
Bits 3:4
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 2
AGC override Enable.
0 = normal, disabled.
1 = enabled, CR25 controls receiver gain in both RF and IF via RXRF_AGC and RXIF_AGC lines.
Bit 1
AGC 2nd antenna power abort.
0 = AGC lock on 2nd antenna is required to finish antenna dwell.
1 = abort 2nd antenna lock search immediately if power is lower on 2nd antenna than on 1st antenna.
Bit 0
AGC Sat Step disable if within CR29[7:5] window.
0 = disable sat step.
1 = enable sat step.
CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES
CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD
Bit 7
RXRF AGC disable.
0 = normal.
1 = disables threshold.
Bits 6:0
RF AGC threshold (0-64 range). The RxRf_Agc pad is removed if the AGC voltage falls below this threshold.
CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR
Bits 7:4
Mid saturation attenuation (0-30 range). Note: mid saturation attenuation is programmed as this value times 2. The mid and
low attenuator steps will occur if the number of I and Q saturations are greater than the mid and low saturation counts set by
CR16.
Bits 3:0
low saturation attenuation (0-15 range).
CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC LOCK WINDOW NEGATIVE SIDE
Bits 7:5
AGC Saturation Block Level, 1xx.x, range 4.0 to 7.5 dB. Disable saturation attenuation step if less than or equal to this level.
Bits 4:0
AGC lock window negative side. (0-15.5 range) (this is the outer lock window) Note: set as a positive number, logic will convert
to negative.
4-29
HFA3863
CONFIGURATION REGISTER ADDRESS 30 (3Ch) R/W CARRIER SENSE 2 SCALE FACTOR
Bits 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Carrier Sense 2 (CS2) scale factor (0-7.875 range) (000000 - 111111).
CONFIGURATION REGISTER 31 ADDRESS (3Eh) TX POWER CONTROL
Bits 7:1
Sets the transmit power. 7 bits to DAC input, -64 to 63 range.
Note: rising edge of TXPE is required for value in CR 31 to be applied to DAC.
Bit 0
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
CONFIGURATION REGISTER 32 ADDRESS (40h) R/W TEST MODES 1
Bit 7
Selection bit for DAC input test mode 7.
0 = Barker.
1 = Low rate I/Q samples.
Bit 6
force high rate mode.
0 = normal.
1 = force high rate mode.
Bit 5
Length Field counter.
0 = disable (non 802.11 systems, length field may be in bits not microseconds).
1 = enabled.
Bit 4
Tristate test bus and enable inputs.
0 = Normal.
1 = enable inputs on test bus.
Bit 3
Disable spread sequence for 1 and 2Mbps.
0 = Normal.
1 = disabled.
Bit 2
Disable scrambler.
0 = normal scrambler operation.
1 = scrambler disabled (taps set to 0).
Bit 1
PN generator enable (RX 44MHz clock).
0 = not enabled.
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
Bit 0
PN generator enable (RX 22MHz clock).
0 = not enabled.
1 = enabled. Bit must first be written to a ‘0’ before a ‘1’ to initialize logic.
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2
Bit 7
Coherent AGC disable.
0 = normal, enabled.
1 = disable.
Bit 6
Time Tracking Mode.
0 = enable detection of the Service field bit showing that the carrier and bit timing are locked to the same oscillator.
1 = disable detection and force locked time tracking.
Note. for automatic locked time tracking operation, bit 2 of the received Service field as well as bit 2 of CR6 of the receiver
must be a “1”.
Bit 5
DC offset compensation control. Final digital DC input offset compensation.
0 = enable DC offset compensation.
1 = disable DC offset compensation.
Bit 4
Bypass I/Q A/Ds.
0 = disable bypass.
1 = 4 MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed.
Bit 3
disable time adjust during packet. Note: this turns off bit tracking.
0 = normal.
1 = time tracking disabled (overrides bit 6 also).
4-30
HFA3863
CONFIGURATION REGISTER ADDRESS 33 (42h) R/W TEST MODES 2 (Continued)
Bit 2
Internal digital loop back mode (SDI pin becomes LOCK input to acquisition block).
0 = normal chip operation loop back disabled.
1 = loop back enabled, A/D and D/A converters bypassed, chip will not respond to external signals.
Bit 1
enable PN to lower test bus address (2-0).
0 = normal.
1 = PN to test bus address.
Bit 0
enable PN to upper test bus address (7-3).
0 = normal.
1 = PN to test bus address.
CONFIGURATION REGISTER ADDRESS 34 (44h) R/W TEST BUS ADDRESS
Bits 7:0
Address bits for various tests. See Tech Brief #TBD for a description of the factory test modes.
CONFIGURATION REGISTER ADDRESS 35 (46h) R/W ED THRESHOLD
Bit 7
Energy Detect Threshold control.
0 = threshold is relative to noise floor.
1 = threshold is absolute.
Bits 6:0
ED Threshold. Range 0 - 127dBm. RSSI > threshold triggers ED.
CONFIGURATION REGISTER ADDRESS 36 (48h) R/W DELAY SPREAD THRESHOLD FOR CMF CONTROL
Bit 7:5
Delay spread count. Range 0 - 7. Used for evaluation only.
Bits 4:0
Delay spread threshold. 0.xxxx.
This and the next 3 thresholds are used in the following formula to determine which CMF weights to use. CW detect is not
configurable.
If (CW and RSSI < (CW RSSI threshold + NoiseFloor)) or (no CW and RSSI < (SNR threshold #1 + NoiseFloor)) or (no CW
and delay spread < threshold and RSSI < (SNR threshold #2 + NoiseFloor)) then;
use Default CMF weights,
else,
use Calculated CMF weights.
CONFIGURATION REGISTER ADDRESS 37 (4Ah) R/W CW RSSI THRESHOLD FOR CMF CONTROL
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6
Force default CMF weights.
0 = normal.
1 = force default CMF weights.
Bit 5
Force calculated CMF weights.
0 = normal.
1 = force calculated CMF weights.
Note: this cannot be combined with bit 6. A “1” on both will produce undefined results.
Bits 4:0
CW RSSI threshold, range 0 to 31dB.
CONFIGURATION REGISTER ADDRESS 38 (4Ch) R/W SNR THRESHOLD #1 FOR CMF CONTROL
Bits 7:4
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 3:0
SNR threshold #1 range 0 to 15dB.
CONFIGURATION REGISTER ADDRESS 39 (4Eh) R/W SNR THRESHOLD #2 FOR CMF CONTROL
Bits 7:4
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 4:0
SNR threshold #2, range 0 to 31dB.
CONFIGURATION REGISTER ADDRESS 40 (50h) R/W DC OFFSET THRESHOLD
Bits 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 5:0
DC offset Threshold, range 0 to 63dB. RSSI > (threshold + NoiseFloor) enables DC offset calculation and compensation.
4-31
HFA3863
CONFIGURATION REGISTER ADDRESS 41 (52h) R/W PREAMBLE/HEADER LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Preamble Lead Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 42 (54h) R/W PREAMBLE/HEADER LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Preamble Lag Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 43 (56h) R/W MPDU LEAD COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Header Lead Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 44 (58h) R/W MPDU LAG COEFFICIENT
Bit 7:6
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 5:0
Header Lag Coefficient (0-4 range) (000000 - 100000).
CONFIGURATION REGISTER ADDRESS 45 (5Ah) R/W FALSE ALARM RATE OF SQ1
Bits 7:0
False alarm rate of SQ1. Enable/disable with CR47 bit 7.
Rate = N*32/2^16. For example 01h = 0.05% False Alarm Rate (FAR) and 10h = 0.78% FAR.
CONFIGURATION REGISTER ADDRESS 46 (5Ch) R/W ACQUISITION TIMELINE
Bit 7
Long Preamble timeline disable.
0 = enable long preamble timeline processing.
1 = disable long preamble timeline processing (process all preambles as if short).
Bit 6
Long Preamble timeline diversity metric selection.
0 = H factors.
1 = RSSI.
Bits 5:0
SQ1 threshold #2, range 0 to 7.875. (000.00 - 111.111).
Used for verify cycle.
CONFIGURATION REGISTER ADDRESS 47 (5Eh) R/W ACQUISITION THRESHOLDS
Bit 7
Disable False alarm Rate Processing.
0 = Enable, SQ1 #1 threshold is adjusted in real time by FAR logic.
1 = Disable, SQ1 #1 threshold is set to value of CR 47 (5:0).
Bit 6
ED and SQ2 control for acquisition.
0 = SQ1.
1 = ED and SQ1.
Bits 5:0
SQ1 threshold #1, range 0 to 7.875. (000.00 - 111.111).
Used for initial detect and initial setting for FAR.
CONFIGURATION REGISTER ADDRESS 48 (60h) R/W SCRAMBLER SEED, LONG PREAMBLE
Bit 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6:0
Scrambler seed for long preamble. Bit 3 of CR5 selects CR48 or CR49.
CONFIGURATION REGISTER ADDRESS 49 (62h) R/W SCRAMBLER SEED AND READ ONLY REGISTER MUX CONTROL
Bit 7
Read only register mux control.
0 = READ ONLY registers read ‘b’ value.
1 = READ ONLY registers read ‘a’ value.
Bits 6:0
Scrambler seed for short preamble. Bit 3 of CR5 selects CR48 or CR49.
CONFIGURATION REGISTER ADDRESS 50 (64h) R TEST BUS READ
Bit 7:0
a&b: reads value on test bus.
4-32
HFA3863
CONFIGURATION REGISTER ADDRESS 51 (66h) R SIGNAL QUALITY MEASURE
Bit 7:0
a: NOISEfloorAntA [7:0] unsigned, range 0-255.
b: measures signal quality based on the SNR in the carrier tracking loop.
CONFIGURATION REGISTER ADDRESS 52 (68h) R RECEIVED SIGNAL FIELD
Bit 7:0
a: NOISEfloorAntB [7:0] unsigned, range 0-255.
b: 8-bit value of received signal field.
CONFIGURATION REGISTER ADDRESS 53 (6Ah) R RECEIVED SERVICE FIELD
Bit 7:0
a: I DC offset, signed, sxxxx.xx.
b: 8-bit value of received service field.
CONFIGURATION REGISTER ADDRESS 54 (6Ch) R RECEIVED LENGTH FIELD, LOW
Bit 7:0
a: Q DC offset, signed, sxxxx.xx.
b: 8-bit value of received length field, low byte.
CONFIGURATION REGISTER ADDRESS 55 (6Eh) R RECEIVED LENGTH FIELD, HIGH
Bit 7:0
a: Multipath metric, 11111111 (large multipath) to 00000000 (no multipath) on last packet received.
b: 8-bit value of received length field, high byte.
CONFIGURATION REGISTER ADDRESS 56 (70h) R CALCULATED CRC ON RECEIVED HEADER, LOW
Bit 7:0
a: Multipath count. How many of last 15 packets had multipath greater than the programmed threshold (CR36 <7:5>).
b: 8-bit value of CRC calculated on header, low byte.
CONFIGURATION REGISTER ADDRESS 57 (72h) R CALCULATED CRC ON RECEIVED HEADER, HIGH
Bit 7:0
a: Packet signal quality metric. (1, 2, 5.5, 11Mbps) smaller value is poorer quality. Valid for reading after RXPE inactive.
b: 8-bit value of CRC calculated on header, high byte.
CONFIGURATION REGISTER ADDRESS 58 (74h) R TX POWER MEASUREMENT
Bit 7:0
a&b: 8-bit value of transmit power measurement (-128 to 127 range) 64 sample average.
CONFIGURATION REGISTER ADDRESS 59 (78h) R RX MEAN POWER
Bit 7:0
a: Header Signal Quality Metric. (1, 2Mbps) Smaller value is poorer quality. Valid for reading after RXPE inactive.
b: Average power of received signal after log table lookup (0--33 range in dB). Minus 33 is minimum power, 0 is maximum.
CONFIGURATION REGISTER ADDRESS 60 (7Ah) R RX_IF_AGC
Bit 7
a&b: unused.
Bits 6:0
a&b: AGC output to the DAC, MSB unused.
CONFIGURATION REGISTER ADDRESS 61 (7Ch) R RECEIVE STATUS
Bit 7:5
a&b: unused.
Bit 4
a&b: ED, energy detect past threshold.
Bit 3
a&b: TX PWR det Register semaphore - a 1 indicates CR58 has updated since last read.
Bit 2
a&b: AGC_lock - a 1 indicates AGC is within limits of lock window CR20.
Bit 1
a&b: hwStopBHit - a 1 indicates rails hit, AGC updates stopped.
Bit 0
a&b: RX_RF_AGC - status of AGC output to RF chip.
CONFIGURATION REGISTER ADDRESS 62 (7Eh) R RSSI
Bit 7:0
a&b: 8-bit value of Packet RSSI, unsigned, range 0 to 255 dB.
4-33
HFA3863
CONFIGURATION REGISTER ADDRESS 63 (80h) R RECEIVE STATUS
Bit 7:6
a&b: signal field value (HRfieldmatch/QPSKwd_OK).
00 = 1.
01 = 2.
10 = 5.5.
11 = 11.
Bit 5
a&b: SFD found.
Bit 4
a&b: Short preamble detected.
Bit 3
a&b: valid signal field found.
Bit 2
a&b: valid CRC 16.
Bit 1
a&b: Antenna selected by receiver when last valid header CRC occurred.
Bit 0
a&b: not used.
4-34
HFA3863
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(Lead Tips Only)
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.70V to +3.60V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200,000 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air (see Tech Brief TB379 for details).
VCC = 3.0V to 3.3V ±10%, TA = -40oC to 85oC
DC Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Current
ICCOP
VCC = 3.6V, CLK Frequency 44MHz
(Notes 5, 6, 7)
-
50
60
mA
Standby Power Supply Current
ICCSB
VCC = Max, Outputs Not Loaded
-
0.5
1
mA
Input Leakage Current
II
VCC = Max, Input = 0V or VCC
-10
1
10
µA
Output Leakage Current
IO
VCC = Max, Input = 0V or VCC
-10
1
10
µA
Logical One Input Voltage
VIH
VCC = Max, Min
0.7 VCC
-
-
V
Logical Zero Input Voltage
VIL
VCC = Min, Max
-
-
VCC /3
V
Logical One Output Voltage
VOH
IOH = -1mA, VCC = Min
VCC -0.2
-
-
V
Logical Zero Output Voltage
VOL
IOL = 2mA, VCC = Min
-
0.1
0.2
V
Input Capacitance
CIN
CLK Frequency 1MHz. All measurements
referenced to GND. TA = 25oC, (Note 6)
-
5
10
pF
-
5
10
pF
Output Capacitance
COUT
NOTES:
4. Output load 40pF.
5. Not tested, but characterized at initial design and at major process/design changes.
6. User must allow for a peak current of 100mA that lasts for 20µs when CIR estimate is being calculated.
AC Electrical Specifications
VCC = 3.0V to 3.3V ±10%, TA = -40oC to 85oC (Note 8)
MCLK = 44MHz
PARAMETER
MCLK Period
SYMBOL
MIN
MAX
UNITS
tCP
22.5
-
ns
40/60
60/40
%
MCLK Duty Cycle
Rise/Fall (All Outputs)
-
10
ns (Notes 8, 9)
TX_PE to IOUT/QOUT (1st Valid Chip)
tD1
2.18
2.3
µs (Notes 8, 10)
TX_PE Inactive Width
tTLP
2.22
-
µs (Notes 8, 11)
TX_CLK Width Hi or Low
tTCD
40
-
ns
TX_RDY Active to 1st TX_CLK Hi
tRC
260
-
ns
Setup TXD to TX_CLK Hi
tTDS
30
-
ns
Hold TXD to TX_CLK Hi
tTDH
0
-
ns
TX_CLK to TX_PE Inactive (1Mbps)
tPEH
0
965
ns (Notes 8, 19)
TX_CLK to TX_PE Inactive (2Mbps)
tPEH
0
420
ns (Notes 8, 19)
TX_CLK to TX_PE Inactive (5.5Mbps)
tPEH
0
160
ns (Notes 8, 19)
4-35
HFA3863
AC Electrical Specifications
VCC = 3.0V to 3.3V ±10%, TA = -40oC to 85oC (Note 8) (Continued)
MCLK = 44MHz
PARAMETER
TX_CLK to TX_PE Inactive (11Mbps)
TX_RDY Inactive to Last Chip of MPDU Out
SYMBOL
MIN
MAX
UNITS
tPEH
0
65
ns (Notes 8, 19)
tRI
-20
800
ns
TXD Modulation Extension
tME
2
-
µs (Notes 8, 12)
RX_PE Inactive Width
tRLP
70
-
ns (Notes 8, 13)
RX_CLK Period (11Mbps Mode)
tRCP
90
-
ns
RX_CLK Width Hi or Low (11Mbps Mode)
tRCD
44
-
ns
RX_CLK to RXD
tRDD
25
60
ns
MD_RDY to 1st RX_CLK
tRD1
940
-
ns (Notes 8, 16)
RXD to 1st RX_CLK
tRD1
940
-
ns
Setup RXD to RX_CLK
tRDS
31
-
ns
RX_CLK to RX_PE Inactive (1Mbps)
tREH
0
925
ns (Notes 8, 14)
RX_CLK to RX_PE Inactive (2Mbps)
tREH
0
380
ns (Notes 8, 14)
RX_CLK to RX_PE Inactive (5.5Mbps)
tREH
0
140
ns (Notes 8, 14)
RX_CLK to RX_PE Inactive (11Mbps)
tREH
0
50
ns (Notes 8, 14)
RX_PE inactive to MD_RDY Inactive
tRD2
5
30
ns (Note 15)
Last Chip of SFD in to MD_RDY Active
tRD3
2.77
2.86
µs (Notes 8, 16)
2.77
2.86
µs (Notes 8, 17)
tRPW
50
-
ns (Notes 8, 18)
RX Delay
RESET Width Active
RX_PE to CCA Valid
tCCA
-
16
µs (Note 8)
RX_PE to RSSI Valid
tCCA
-
16
µs (Note 8)
SCLK Clock Period
tSCP
90
-
ns
SCLK Width Hi or Low
tSCW
20
-
ns
Setup to SCLK + Edge (SD, SDI, R/W, CS)
tSCS
30
-
ns
Hold Time from SCLK + Edge (SD, SDI, R/W, CS)
tSCH
0
-
ns
SD Out Delay from SCLK + Edge
tSCD
-
30
ns
SD Out Enable/Disable from R/W
tSCED
-
15
ns (Note 8)
tD2
-
40
ns
TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK
NOTES:
7. AC tests performed with CL = 40pF, IOL = 2mA, and IOH = -1mA. Input reference level all inputs VCC/2. Test VIH = VCC , VIL = 0V;
VOH = VOL = VCC/2.
8. Not tested, but characterized at initial design and at major process/design changes.
9. Measured from VIL to VIH .
10. IOUT/QOUT are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits.
11. TX_PE must be inactive before going active to generate a new packet.
12. IOUT/QOUT are modulated after last chip of valid data to provide ramp down time for RF/IF circuits.
13. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
14. RX_PE active to inactive delay to prevent next RX_CLK.
15. Assumes RX_PE inactive after last RX_CLK.
16. MD_RDY programmed to go active after SFD detect. (Measured from IIN , QIN.)
17. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at IIN , QIN to MD_RDY active.
18. Minimum time to ensure Reset. RESET must be followed by an RX_PE pulse to ensure proper operation. This pulse should not be used for first
receive or acquisition.
19. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within
40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns.
4-36
HFA3863
I and Q A/D AC Electrical Specifications
(Note 20)
PARAMETER
MIN
TYP
MAX
UNITS
0.25
0.50
1.0
V
Input Bandwidth (-0.5dB)
-
20
-
MHz
Input Capacitance
-
5
-
pF
Input Impedance (DC)
5
-
-
kΩ
FS (Sampling Frequency)
-
-
22
MHz
Full Scale Input Voltage (VP-P)
NOTE:
20. Not tested, but characterized at initial design and at major process/design changes.
Test Circuit
DUT
(NOTE 22)
S1
CL
(NOTE 21)
IOH
±
VCC/2
IOL
EQUIVALENT CIRCUIT
NOTES:
21. Includes Stray and JIG Capacitance.
22. Switch S1 Open for ICCSB and ICCOP .
FIGURE 19. TEST LOAD CIRCUIT
Waveforms
tSCP
tSCW
tSCW
SCLK
tSCH
tSCS
SDI, R/W, SD, CS
tSCD
SD (AS OUTPUT)
R/W
SD
tSCED
FIGURE 20. SERIAL CONTROL PORT SIGNAL TIMING
4-37
tSCED
HFA3863
Waveforms
(Continued)
tTLP
TX_PE
tDI
tPEH
tME
IOUT, QOUT
tRI
tTCD
TXRDY
tTCD
tRC
TX_CLK
TXD
tTDH
tTDS
FIGURE 21. TX PORT SIGNAL TIMING
tRLP
RX_PE
tRD3
tREH
IIN, QIN
tRD2
MD_RDY
tRCP
RX_CLK
tCCA
RXD
tRCD
tRD1
CCA, RSSI
tRDD
tRCD
tRDS
NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. RSSI Output on TEST (5:0).
FIGURE 22. RX PORT SIGNAL TIMING
MCLK
tD2
TEST 0-7, CCA, ANTSEL, TEST_CK
RESET
tRPW
MCLK
tCP
FIGURE 23. MISCELLANEOUS SIGNAL TIMING
4-38
HFA3863
Thin Plastic Quad Flatpack Packages (TQFP)
Q64.10x10 (JEDEC MS-026ACD ISSUE B)
D
64 LEAD THIN PLASTIC QUAD FLATPACK PACKAGE
D1
-D-
INCHES
-B-
-AE E1
e
PIN 1
SEATING
A PLANE
-H-
0.08
0.003
-C-
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.005
0.05
0.15
-
A2
0.038
0.041
0.95
1.05
-
b
0.007
0.010
0.17
0.27
6
b1
0.007
0.009
0.17
0.23
-
D
0.468
0.476
11.90
12.10
3
D1
0.390
0.397
9.9
10.10
4, 5
E
0.468
0.476
11.9
12.10
3
E1
0.390
0.397
9.9
10.10
4, 5
L
0.018
0.029
0.45
0.75
N
64
64
e
0.020 BSC
0.50 BSC
7
Rev. 0 7/98
NOTES:
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
0.08
M C A-B S
0.003
D S
b
11o-13o
0.020
0.008 MIN
b1
0o MIN
A2 A1
GAGE
PLANE
L
0o-7o
11o-13o
0.25
0.010
0.09/0.16
0.004/0.006
BASE METAL
WITH PLATING
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
7. “N” is the number of terminal positions.
0.09/0.20
0.004/0.008
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-39
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