INTERSIL HFA3861IV96

HFA3861
ADVANCE INFORMATION
Data Sheet
July 1999
• Complete DSSS Baseband Processor
The Intersil HFA3861 Direct Sequence
Spread Spectrum (DSSS) baseband
processor is part of the PRISM®
2.4GHz radio chipset, and contains all
the functions necessary for a full or half duplex packet
baseband transceiver.
™
The HFA3861 has on-board A/D’s for analog I and Q inputs
and outputs, for which the HFA3783 IF QMODEM is
recommended. Differential phase shift keying modulation
schemes DBPSK and DQPSK, with data scrambling
capability, are available along with Complementary Code
Keying to provide a variety of data rates. Built-in flexibility
allows the HFA3861 to be configured through a general
purpose control bus, for a range of applications. Both
Receive and Transmit AGC functions with 7-bit AGC control
obtain maximum performance in the analog portions of the
transceiver. The HFA3861 is housed in a thin plastic quad
flat package (TQFP) suitable for PCMCIA board
applications.
Ordering Information
PART NO.
• Processing Gain . . . . . . . . . . . . . . . . . . . . FCC Compliant
• Programmable Data Rate. . . . . . . . 1, 2, 5.5, and 11Mbps
• Ultra Small Package . . . . . . . . . . . . . . . . . . . . . 10 x 10mm
• Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V
• Modulation Methods . . . . . . . . DBPSK, DQPSK, and CCK
• Supports Full or Half Duplex Operations
• On-Chip A/D and D/A Converters for I/Q Data (6-Bit,
22MSPS), AGC, and Adaptive Power Control (7-Bit)
• Targeted for Multipath Delay Spreads ~100ns
• Supports Short Preamble Acquisition
Applications
• Enterprise WLAN Systems
• Systems Targeting IEEE 802.11 Standard
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
PKG. TYPE
HFA3861IV
-40 to 85
64 Ld TQFP
HFA3861IV96
-40 to 85
Tape and Reel
PKG. NO.
Q64.10x10
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable PDA/Notebook Computer
• Wireless Digital Audio, Video, Multimedia
Pinout
SDI
RESET
TX_PE
RX_PE
CCA
TX_RDY
TXD
VDDD
GNDd
TXCLK
MD_RDY
RXD
RXCLK
TEST7
TEST6
TEST5
• PCN/Wireless PBX
• Wireless Bridges
Simplified Block Diagram
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDDA
TX_AGC_IN
RX-IF_DET
GNDa
IREF
VDDA
TX_I+
TX_IGNDa
COMPCAP2
COMPRES2
GNDa
TX_Q+
TX_QVDDA
COMPRES1
GNDd
VDDD
SD
SCLK
R/W
CS
GNDd
VDDD
GNDa
RX_I+
RX_IVDDA
RX_Q+
RX_QGNDa
VREF
4699.1
Features
Direct Sequence Spread Spectrum
Baseband Processor
TEMP.
RANGE (oC)
File Number
1
TEST4
TEST3
TEST2
TEST1
TEST0
GNDd
MCLK
NC
ANT-SEL
ANT-SEL
RX-RF_AGC
VDDD
GNDd
TX_IF_AGC
RX_IF_AGC
COMPCAP1
ANT_SEL
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
1
THRESH.
DETECT
IF
DAC
RX_I±
I ADC
RX_Q±
Q ADC
1
7
AGC
CTL
6
6
DEMOD
VREF
I/O
TX_I±
I DAC
TX_Q±
Q DAC
TX_IF_AGC
TX_AGC_IN
44MHz MCLK
TX
DAC
TX
ADC
DATA I/O
6
6
MOD
7
TX
ALC
6
HFA 3861 BBP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
PRISM and PRISM logo are trademarks of Intersil Corporation.
HFA3861
Table of Contents
PAGE
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
Typical Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Control Port (4 Wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
TX Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
RX Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
RX I/Q A/D Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
AGC Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
RX_AGC_IN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
TX I/Q DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Transmitter Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Header/Packet Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Scrambler and Data Encoder Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Spread Spectrum Modulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
CCK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
TX Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Clear Channel Assessment (CCA) and Energy Detect (ED) Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
AGC Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Demodulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
Acquisition Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
PN Correlators Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
Data Demodulation and Tracking Description (DBPSK and DQPSK Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Data Decoder and Descrambler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Data Demodulation in the CCK Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Demodulator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Overall Eb/N0 Versus BER Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Clock Offset Tracking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
Carrier Offset Frequency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
A Default Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
Thin Plastic Quad Flatpack Packages (TQFP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
2
Typical Application Diagram
HFA3683 RF/IF
CONV
I ADC
Q ADC
1
1
7
AGC
CTL
6
6
I/O LO
RF
LO
I DAC
REF IN
HFA3963
RFPA
I/O
IF
LO
Q DAC
REF IN
HOST
INTERFACE
LOGIC
6
MOD
7
6
TX
ALC
GP SERIAL
PORTS
MEMORY
ACCESS
ARBITER
HFA3861 BBP
EXTERNAL
MEMORY
44MHz MCLK
DIFFERENTIAL SIGNALS
TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3861
For additional information on the PRISM® chip set, call (407) 724-7800 to access
Intersil’ AnswerFAX system. When prompted, key in the four-digit document
number (File #) of the data sheets you wish to receive.
The four-digit file numbers are shown in the Typical Application Diagram, and
correspond to the appropriate circuit.
HFA3861
REF IN
RADIO
CONTROL
PORTS
16-BIT
PIPELINED
CONTROL
PROCESSOR
6
HFA3783 QUAD IF
TX
DAC
TX
ADC
HFA3841
MAC
WEP
ENGINE
CPU
DEMOD
REFOUT
PLL
PLL
RADIO
DATA
INTERFACE
HOSTPC
INTERFACE
3
RF
DAC
RF
ADC
IF
DAC
HFA3861
Pin Descriptions
NAME
PIN
TYPE I/O
VDDA (Analog)
12, 17, 22,
31
Power
DC power supply 2.7V - 3.6V (Not Hard wired Together On Chip).
VDDD (Digital)
2, 8, 37, 57
Power
DC power supply 2.7 - 3.6V
GNDa
(Analog)
9, 15, 20,
25, 28,
Ground
DC power supply 2.7 - 3.6V, ground (Not Hard wired Together On Chip).
Ground
DC power supply 2.7 - 3.6V, ground.
GNDd (Digital) 1, 7, 36, 43,
56
DESCRIPTION
VREF
16
I
Voltage reference for A/D’s and D/A’s
IREF
21
I
Current reference for internal ADC and DAC devices. Requires a 12kΩ resistor to ground.
RXI, +/-
10/11
I
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-
RXQ, +/-
13/14
I
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-
ANTSEL
39
O
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for
differential drive of antenna switches.
ANTSEL
40
O
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for
differential drive of antenna switches.
RX_IF_DET
19
I
Analog input to the receive power A/D converter for AGC control.
RX_IF_AGC
34
O
Analog drive to the IF AGC control.
RX_RF_AGC
38
O
Drive to the RF AGC stage attenuator. CMOS digital.
TX_AGC_IN
18
I
Input to the transmit power A/D converter for transmit AGC control.
TX_IF_AGC
35
O
Analog drive to the transmit IF power control.
TX_PE
62
I
When active, the transmitter is configured to be operational, otherwise the transmitter is in standby
mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to
the HFA3861. The rising edge of TX_PE will start the internal transmit state machine and the falling
edge will initiate shut down of the state machine. TX_PE envelopes the transmit data except for the
last bit. The transmitter will continue to run for 4µs after TX_PE goes inactive to allow the PA to shut
down gracefully.
TXD
58
I
TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network
processor to the HFA3861. The data is received serially with the LSB first. The data is clocked in the
HFA3861 at the rising edge of TXCLK.
TXCLK
55
O
TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3861, synchronously. Transmit data on the TXD bus is clocked into the HFA3861 on the rising
edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock
will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY
59
O
TX_RDY is an output to the external network processor indicating that Preamble and Header
information has been generated and that the HFA3861 is ready to receive the data packet from the
network processor over the TXD serial bus.
CCA
60
O
Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are
described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD
53
O
RXD is an output to the external network processor transferring demodulated Header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with
MD_RDY.
RXCLK
52
O
RXCLK is the bit clock output. This clock is used to transfer Header information and payload data
through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is
held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been
detected. Data should be sampled on the rising edge. This polarity is programmable and can be
inverted.
4
HFA3861
Pin Descriptions
(Continued)
NAME
PIN
TYPE I/O
DESCRIPTION
MD_RDY
54
O
MD_RDY is an output signal to the network processor, indicating header data and a data packet are
ready to be transferred to the processor. MD_RDY is an active high signal that signals the start of data
transfer over the RXD serial bus. MD_RDY goes active when the SFD (Note) is detected and returns
to its inactive state when RX_PE goes inactive or an error is detected in the header.
RX_PE
61
I
When active, the receiver is configured to be operational, otherwise the receiver is in standby mode.
This is an active high input signal. In standby, RX_PE inactive, all RX A/D converters are disabled.
SD
3
I/O
SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal
registers. The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the
register address immediately followed by 8 more bits representing the data that needs to be written
or read at that register. In the 4 wire interface mode, this pin is tristated unless the R/W pin is high.
SCLK
4
I
SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input
clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is
11MHz or one half the master clock frequency, whichever is lower.
SDI
64
I
Serial Data Input in 3 wire mode described in Tech Brief TBD. This pin is not used in the 4 wire
interface described in this data sheet. It should not be left floating.
R/W
5
I
R/W is an input to the HFA3861 used to change the direction of the SD bus when reading or writing
data on the SD bus. R/W must be set up prior to the rising edge of SCLK. A high level indicates read
while a low level is a write.
CS
6
I
CS is a Chip select for the device to activate the serial control port. The CS doesn’t impact any of the
other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low
signal. When inactive SD, SCLK, and R/W become “don’t care” signals.
TEST 7:0
51, 50, 49,
48, 47, 46,
45, 44
I/O
This is a data port that can be programmed to bring out internal signals or data for monitoring. These
bits are primarily reserved by the manufacturer for testing. A further description of the test port is given
in the appropriate section of this data sheet.
RESET
63
I
Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3861 goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up.
MCLK
42
I
Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to
generate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
TXI+/-
23/24
O
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/ 24-
TXQ+/-
29/30
O
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-.
CompCap
33
I
Compensation capacitor
CompCap2
26
I
Compensation capacitor
CompRes1
32
I
Compensation Resistor
CompRes2
27
I
Compensation Resistor
NOTE: See CR10<3>.
External Interfaces
There are three primary digital interface ports for the
HFA3861 that are used for configuration and during normal
operation of the device as shown in Figure 1. These ports
are:
• The Control Port, which is used to configure, write
and/or read the status of the internal HFA3861
registers.
• The TX Port, which is used to accept the data that
needs to be transmitted from the network processor.
• The RX Port, which is used to output the received
demodulated data to the network processor.
5
In addition to these primary digital interfaces the device
includes a byte wide parallel Test Port which can be
configured to output various internal signals and/or data.
The device can also be set into various power consumption
modes by external control. The HFA3861 contains four
Analog to Digital (A/D) converters and four Digital to Analog
converters. The analog interfaces to the HFA3861 include,
the In phase (I) and quadrature (Q) data component inputs/
outputs, and the RF and IF receive automatic gain control
and transmit output power control.
HFA3861
Control Port (4 Wire)
are accomplished through the serial data pin (SD). SD is a
bidirectional serial data bus. Chip Select (CS), and
Read/Write (R/W) are also required as handshake signals for
this port. The clock used in conjunction with the address and
data on SD is SCLK. This clock is provided by the external
source and it is an input to the HFA3861. The timing
relationships of these signals are illustrated in Figures 2
and 3. R/W is high when data is to be read, and low when it
is to be written. CS is an asynchronous reset to the state
machine. CS must be active (low) during the entire data
transfer cycle. CS selects the serial control port device only.
The serial control port operates asynchronously from the
TX and RX ports and it can accomplish data transfers
independent of the activity at the other digital or analog
ports.
The serial control port is used to serially write and read data
to/from the device. This serial port can operate up to a 11MHz
rate or 1/2 the maximum master clock rate of the device,
MCLK (whichever is lower). MCLK must be running and
RESET must be inactive during programming. This port is
used to program and to read all internal registers. The first 8
bits always represent the address followed immediately by the
8 data bits for that register. The LSB of the address is a don’t
care, but reserved for future expansion. The serial transfers
The HFA3861 has 96 internal registers that can be
configured through the control port. These registers are
listed in the Configuration and Control Internal Register
table. Table 9 lists the configuration register number, a brief
name describing the register, the HEX address to access
each of the registers and typical values. The type indicates
whether the corresponding register is Read only (R) or
Read/Write (R/W). Some registers are two bytes wide as
indicated on the table (high and low bytes).
HFA3861
ANALOG
INPUTS
RXI
RXQ
AGC
A/D
REFERENCE
VREF
IREF
8
ANALOG
OUTPUTS
TXD
TXCLK
TX_RDY
RXD
RXC
MD_RDY
CS
SD
SCLK
R/W
SDI
TX_PE
RX_PE
RESET
POWER
DOWN
SIGNALS
TEST
PORT
AGC
TXI
TXQ
TEST
ANT_SEL
TX_PORT
RX_PORT
CONTROL_PORT
FIGURE 1. EXTERNAL INTERFACES
FIRST ADDRESS BIT
6
5
4
3
2
7
1
FIRST DATABIT OUT
7
6
5
4
3
0
2
1
0
SCLK
7
SD
6
5
MSB
4
3
2
1
7
ADDRESS IN
6
5
MSB
4
3
2
1
0
DATA OUT
LSB
R/W
CS
NOTES:
1. The HFA3861 always uses the rising edge of SCLK to sample address and data and to generate read data.
2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data.
FIGURE 2. CONTROL PORT READ TIMING
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCLK
SD
7
MSB
6
5
4
3
ADDRESS IN
2
1
0
7
MSB
6
5
4
3
2
DATA IN
R/W
CS
FIGURE 3. CONTROL PORT WRITE TIMING
6
1
0
LSB
HFA3861
TX Port
The transmit data port accepts the data that needs to be
transmitted serially from an external data source. The data is
modulated and transmitted as soon as it is received from the
external data source. The serial data is input to the HFA3861
through TXD using the next rising edge of TXCLK to clock it in
the HFA3861. TXCLK is an output from the HFA3861. A
timing scenario of the transmit signal handshakes and
sequence is shown on timing diagram Figure 4.
The external processor initiates the transmit sequence by
asserting TX_PE. TX_PE envelopes the transmit data packet
on TXD. The HFA3861 responds by generating a Preamble
and Header. Before the last bit of the Header is sent, the
HFA3861 begins generating TXCLK to input the serial data on
TXD. TXCLK will run until TX_PE goes back to its inactive
state indicating the end of the data packet. The user needs to
hold TX_PE high for as many clocks as there bits to transmit.
For the higher data rates, this will be in multiples of the
number of bits per symbol. The HFA3861 will continue to
output modulated signal for 4µs after the last data bit is
output, to supply bits to flush the modulation path. TX_PE
must be held until the last data bit is output from the
MAC/FIFO. The minimum TX_PE inactive pulse required to
restart the preamble and header generation is 2.22µs and to
reset the modulator is 4.22µs.
The HFA3861 internally generates the preamble and header
information from information supplied via the control registers.
The external source needs to provide only the data portion of
the packet and set the control registers. The timing diagram of
this process is illustrated on Figure 4. Assertion of TX_PE will
initialize the generation of the preamble and header. TX_RDY,
which is an output from the HFA3861, is used (if needed) to
indicate to the external processor that the preamble has been
generated and the device is ready to receive the data packet
(MPDU) to be transmitted from the external processor.
Signals TX_RDY, TX_PE and TXCLK can be set individually,
by programming Configuration Register (CR) 1, as either
active high or active low signals.
The transmit port is completely independent from the
operation of the other interface ports including the RX port,
therefore supporting a full duplex mode.
RX Port
The timing diagram Figure 5 illustrates the relationships
between the various signals of the RX port. The receive data
port serially outputs the demodulated data from RXD. The
data is output as soon as it is demodulated by the HFA3861.
RX_PE must be at its active state throughout the receive
operation. When RX_PE is inactive the device's receive
functions, including acquisition, will be in a stand by mode.
TXCLK
TX_PE
LAST DATA BIT SAMPLED
FIRST DATA BIT SAMPLED
TXD
LSB
DATA PACKET
MSB
DEASSERTED WHEN LAST
CHIP OF MPDU CLEARS
MOD PATH OF 3861 EXCEPT FOR
TX FILTER AND D/A
TX_RDY
NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXCLK.
FIGURE 4. TX PORT TIMING
RXCLK
RX_PE
HEADER
FIELDS
DATA
PROCESSING
PREAMBLE/HEADER
MD_RDY
RXD
LSB
DATA PACKET
NOTE: MD_RDY active after CRC16. See detailed timing diagrams (Figures 18, 19, 20).
FIGURE 5. RX PORT TIMING
7
MSB
HFA3861
The voltages applied to pin 16, VREF and pin 21, IREF set
the references for the internal I and Q A/D converters. In
addition, For a nominal I/Q input of 250mVP-P, the
suggested VREF voltage is 1.2V.
RXCLK is an output from the HFA3861 and is the clock for
the serial demodulated data on RXD. MD_RDY is an output
from the HFA3861 and it may be set to go active after the
SFD or CRC fields. Note that RXCLK becomes active after
the Start Frame Delimiter (SFD) to clock out the Signal,
Service, and Length fields, then goes inactive during the
header CRC field. RXCLK becomes active again for the
data. MD_RDY returns to its inactive state after RX_PE is
deactivated by the external controller, or if a header error is
detected. A header error is either a failure of the CRC
check, or the failure of the received signal field to match
one of the 4 programmed signal fields. For either type of
header error, the HFA3861 will reset itself after reception of
the CRC field. If MD_RDY had been set to go active after
CRC, it will remain low.
AGC Circuit
The AGC circuit is designed to optimize A/D performance for
the I and Q inputs by maintaining the proper headroom on
the 6-bit converters. There are two gain stages being
controlled. At RF, the gain control is a 30dB step in gain from
turning off the LNA. This RF gain control optimizes the
receiver dynamic range when the signal level is high and
maintains the noise figure of the receiver when it is needed
most. At IF the gain control is linear and covers the bulk of
the gain control range of the receiver.
MD_RDY and RXCLK can be configured through CR 1, bits
1 and 0 to be active low, or active high. The receive port is
completely independent from the operation of the other
interface ports including the TX port, supporting therefore a
full duplex mode.
The AGC sensing mechanism uses a combination of the
I and Q A/D converters and the detected signal level in the IF
to determine the gain settings. The A/D outputs are
monitored in the HFA3861 for the desired nominal level.
When it is reached, by adjusting the receiver gain, the gain
control is locked for the remainder of the packet.
RX I/Q A/D Interface
RX_AGC_IN Interface
The PRISM baseband processor chip (HFA3861) includes
two 6-bit Analog to Digital converters (A/Ds) that sample the
balanced differential analog input from the IF down
converter. The I/Q A/D clock, samples at twice the chip rate.
The nominal sampling rate is 22MHz.
The signal level in the IF stage is monitored to determine
when to impose the up to 30dB gain reduction in the RF
stage. This maximizes the dynamic range of the receiver by
keeping the RF stages out of saturation at high signal levels.
When the IF circuits’ sensor output reaches 0.5V, the
HFA3861 comparator switches in the 30dB pad and
compensates the IF AGC and RSSI measures.
The interface specifications for the I and Q A/Ds are listed in
Table 1. The HFA3861 is designed to be DC coupled to the
HFA3783.
TABLE 1. I, Q, A/D SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
0.90
1.00
1.10
-
11MHz
-
Input Capacitance (pF)
-
2
-
Input Impedance (DC)
5kΩ
-
-
-
22MHz
-
Full Scale Input Voltage (VP-P)
Input Bandwidth (-0.5dB)
fS (Sampling Frequency)
RX_RF_AGC
RX_IF_DET
1
THRESH.
DETECT
RX_IF_AGC
RX_I±
HFA3683
HFA3783
RX_Q±
1
7
AGC
CTL
IF
DAC
I ADC
Q ADC
6
6
DEMOD
DATA I/O
I/O
HFA3861
FIGURE 6. AGC CIRCUIT
8
HFA3861
TX I/Q DAC Interface
The transmit section outputs balanced differential analog
signals from the transmit DACs to the HFA3783. These are
DC coupled and digitally filtered.
Test Port
The HFA3861 provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. The test port is programmable through configuration
register (CR 34). Any signal on the test port can also be read
from configuration register (CR50) via the serial control port.
Additionally, the transmit DACs can be configured to show
signals in the receiver via CR 14. This allows visibility to
analog like signals that would normally be very difficult to
capture.
Power Down Modes
The power consumption modes of the HFA3861 are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 61), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 62), which disables
the transmitter when inactive.
Reset (RESET, pin 63), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a
maximum of 10µs before the device is back at its
operational mode for transmitters. Add 5ms more to be
operational for receive mode.
The contents of the Configuration Registers are not effected
by any of the power down modes. No reconfiguration is
required when returning to operational modes. Activation of
RESET does corrupt learned values of AGC settings and
noise floor values. Optimum receiver operation may not be
achieved until these values are reestablished (typically
<20µs of operation in noise only needed). The power
savings of activating RESET must be weighed against this.
Table 2 describes the power down modes available for the
HFA3861 (VCC = 3.3V). The table values assume that all
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
Transmitter Description
The HFA3861 transmitter is designed as a Direct Sequence
Spread Spectrum Phase Shift Keying (DSSS PSK)
modulator. It can handle data rates of up to 11Mbps (refer to
AC and DC specifications). The various modes of the
modulator are Differential Binary Phase Shift Keying
(DBPSK) for 1Mbps, Differential Quaternary Phase Shift
Keying (DQPSK) for 2Mbps, and Complementary Code
Keying (CCK) for 5.5Mbps and 11Mbps. These implement
data rates as shown in Table 3. The major functional blocks
of the transmitter include a network processor interface,
DPSK modulator, high rate modulator, a data scrambler and
a spreader, as shown in Figure 7. CCK is essentially a
quadra-phase form of M-ARY Orthogonal Keying. A
description of that modulation can be found in Chapter 5 of:
“Telecommunications System Engineering”, by Lindsey and
Simon, Prentis Hall publishing.
The preamble is always transmitted as the DBPSK
waveform while the header can be configured to be either
DBPSK, or DQPSK, and data packets can be configured
for DBPSK, DQPSK, or CCK. The preamble is used by the
receiver to achieve initial PN synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer
link. The transmitter generates the synchronization
preamble and header and knows when to make the DBPSK
to DQPSK or CCK switchover, as required.
TABLE 2. POWER DOWN MODES
MODE
RX_PE
TX_PE
RESET
AT
44MHz
SLEEP
Inactive
Inactive
Active
1mA
STANDBY
Inactive
Inactive
Inactive
1.5mA
Both transmit and receive operations disabled. Device will resume its operational
state within 1µs of RX_PE or TX_PE going active.
TX
Inactive
Active
Inactive
10mA
Receiver operations disabled. Receiver will return in its operational state within 1µs
of RX_PE going active.
RX
Active
Inactive
Inactive
100mA
Transmitter operations disabled. Transmitter will return to its operational state within
2 MCLKs of TX_PE going active.
Active
300µA
All inputs at VCC or GND.
NO CLOCK
ICC Standby
9
DEVICE STATE
Both transmit and receive functions disabled. Device in sleep mode. Control
Interface is still active. Register values are maintained. Device will return to its active
state within 10µs plus settling time of AC coupling capacitors (about 5ms).
HFA3861
TABLE 3. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHz)
TX SETUP CR 5
BITS 1, 0
RX SIGNAL CR 63
BITS 7, 6
DATA RATE (Mbps)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
CCK
22
10
10
5.5
1.375
CCK
22
11
11
11
1.375
802.11 DSSS BPSK
1Mbps
BARKER
802.11 DSSS QPSK
2Mbps
BARKER
5.5Mbps CCK
COMPLEX
SPREAD FUNCTIONS
11Mbps CCK
COMPLEX
SPREAD FUNCTIONS
4 BITS ENCODED
TO ONE OF 16
COMPLEX CCK
CODE WORDS
8 BITS ENCODED
TO ONE OF 256
COMPLEX CCK
CODE WORDS
DATA
1 BIT ENCODED TO
ONE OF 2 CODE
WORDS
(TRUE-INVERSE)
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
IOUT
QOUT
11 CHIPS
CHIP
RATE
SYMBOL
RATE
11 CHIPS
8 CHIPS
8 CHIPS
11 MC/S
11 MC/S
11 MC/S
11 MC/S
1 MS/S
1 MS/S
1.375 MS/S
1.375 MS/S
I vs Q
FIGURE 7. MODULATION MODES
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps,
it uses two of those bits to select one of 4 complex spread
sequences from a table of CCK sequences and then QPSK
modulates that symbol with the remaining 2 bits. Thus, there
are 4 possible spread sequences to send at four possible
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase
reference for the data portion of the packet is the phase of
the last bit of the header. At 11Mbps, one byte is used as
above where 6 bits are used to select one of 64 spread
sequences for a symbol and the other 2 are used to QPSK
modulate that symbol. Thus, the total possible number of
10
combinations of sequence and carrier phases is 256. Of
these only one is sent.
The bit rate Table 3 shows examples of the bit rates and the
symbol rates and Figure 7 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3861 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions.
The HFA3861 generates its own preamble and header
information. It uses two packet preamble and header
configurations. The first is backwards compatible with the
existing IEEE 802.11-1997 1 and 2Mbps modes and the
second is the optional shortened mode which maximizes
throughput at the expense of compatibility with legacy
equipment.
HFA3861
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1's
(before entering the scrambler) plus a start frame delimiter
(SFD). The actual transmitted pattern of the preamble is
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform (1Mbps). The duration of
the long preamble and header is 192µs.
CRC 16 error via CR24 bit 2 and will lower MD_RDY and
reset the receiver to the acquisition mode if there is an error.
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at
2Mbps. The synchronization preamble is all 0’s to distinguish
it from the long header mode and the short preamble SFD is
the time reverse of the long preamble SFD. The duration of
the short preamble and header is 96µs.
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
Start Frame Delimiter (SFD) Field (16 Bits) - This field is
used to establish the link frame timing. The HFA3861 will not
declare a valid data packet, even if it PN acquires, unless it
detects the SFD. The HFA3861 receiver is programmed to
time out searching for the SFD via CR 10 BITS 4 and 5. The
timer starts counting the moment that initial PN
synchronization has been established on the preamble.
The four fields for the header shown in Figure 8 are:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The HFA3861
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
fields.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x16 + x12 + x5 + 1
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR 4 - Defines the preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of
128d = 80h.
CR 10 bits 4,5 - Define the length of time that the
demodulator searches for the SFD before returning to
acquisition.
CR 5 bits 0,1 - These bits of the register set the Signal field
to indicate what modulation is to be used for the data portion
of the packet.
CR 6 - The value to be used in the Service field.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. These bits are not used by the HFA3861.
CR 7 and 8 - Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol and is in microseconds required to
transmit the data at the chosen data rate.
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
The packet consists of the preamble, header and MAC
protocol data unit (MPDU). The data is transmitted exactly
as received from the control processor. Some dummy bits
will be appended to the end of the packet to insure an
orderly shutdown of the transmitter. This prevents spectrum
splatter. At the end of a packet, the external controller is
expected to de-assert the TX_PE line to shut the
transmitter down.
CCITT - CRC 16 Field (16 Bits)- This field includes the 16-bit
CCITT - CRC 16 calculation of the three header fields. This
value is compared with the CCITT - CRC 16 code calculated
at the receiver. The HFA3861 receiver will indicate a CCITT -
PREAMBLE (SYNC)
128/56 BITS
SFD
16 BITS
PREAMBLE
SIGNAL FIELD
8 BITS
SERVICE FIELD
8 BITS
LENGTH FIELD
16 BITS
HEADER
FIGURE 8. 802.11 PREAMBLE/HEADER
11
CRC16
16 BITS
HFA3861
Scrambler and Data Encoder Description
The modulator has a data scrambler that implements the
scrambling algorithm specified in the IEEE 802.11 standard.
This scrambler is used for the preamble, header, and data in
all modes. The data scrambler is a self synchronizing circuit.
It consist of a 7-bit shift register with feedback from specified
taps of the register. Both transmitter and receiver use the
same scrambling algorithm. The scrambler can be disabled
by setting CR32 bit 2 to 1.
NOTE: Be advised that the IEEE 802.11 compliant scrambler in the
HFA3861 has the property that it can lock up (stop scrambling) on
random data followed by repetitive bit patterns. The probability of this
happening is 1/128. The patterns that have been identified are all zeros, all ones, repeated 10s, repeated 1100s, and repeated 111000s.
Any break in the repetitive pattern will restart the scrambler. To insure
that this does not cause any problem, the CCK waveform uses a ping
pong differential coding scheme that breaks up repetitive 0s patterns.
Scrambling is done by a division using a prescribed
polynomial as shown in Figure 9. A shift register holds the
last quotient and the output is the exclusive-or of the data
and the sum of taps in the shift register. The taps are
programmable. The transmit scrambler seed is Hex 6C for
the long preamble or 1B for the short preamble and can be
set with CR36 or CR37.
SERIAL
DATA OUT
SERIAL DATA
IN
XOR
Z-1 Z-2 Z-3 Z-4
Z-5 Z-6 Z-7
XOR
FIGURE 9. SCRAMBLING PROCESS
For the 1Mbps DBPSK data rates and for the header in all
rates, the data coder implements the desired DBPSK coding
by differential encoding the serial data from the scrambler
and driving both the I and Q output channels together. For
the 2Mbps DQPSK data rate, the data coder implements the
desired coding as shown in the DQPSK Data Encoder table.
This coding scheme results from differential coding of dibits
(2 bits). Vector rotation is counterclockwise although bits 6
and 7 of configuration register CR 1 can be used to reverse
the rotation sense of the TX or RX signal if desired.
TABLE 4. DQPSK DATA ENCODER
PHASE SHIFT
DIBIT PATTERN (d0, d1)
d0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and
CCK spread spectrum signals. The modulator is capable of
automatically switching its rate where the preamble is
12
DBPSK modulated, and the data and/or header are
modulated differently. The modulator can support date rates
of 1, 2, 5.5 and 11Mbps. The programming details to set up
the modulator are given at the introductory paragraph of this
section. The HFA3861 utilizes Quadraphase (I/Q)
modulation at baseband for all modulation modes.
In the 1Mbps DBPSK mode, the I and Q Channels are
connected together and driven with the output of the
scrambler and differential encoder. The I and Q Channels
are then both multiplied with the 11-bit Barker word at the
spread rate. The I and Q signals go to the Quadrature
upconverter (HFA3724) to be modulated onto a carrier.
Thus, the spreading and data modulation are BPSK
modulated onto the carrier.
For the 2Mbps DQPSK mode, the serial data is formed into
dibits or bit pairs in the differential encoder as detailed
above. One of the bits from the differential encoder goes to
the I Channel and the other to the Q Channel. The I and Q
Channels are then both multiplied with the 11-bit Barker
word at the spread rate. This forms QPSK modulation at the
symbol rate with BPSK modulation at the spread rate.
CCK Modulation
The spreading code length is 8 and based on
complementary codes. The chipping rate is 11Mchip/s and
the symbol duration is exactly 8 complex chips long. The
following formula is used to derive the CCK code words that
are used for spreading both 5.5 and 11Mbps:
 j ( ϕ1 + ϕ2 + ϕ3 + ϕ4 ) j ( ϕ1 + ϕ3 + ϕ4 ) j ( ϕ1 + ϕ2 + ϕ4 )
c = e
,
,e
,e

–e
j ( ϕ1 + ϕ4 )
,e
j ( ϕ1 + ϕ2 + ϕ3 )
,e
j ( ϕ1 + ϕ3 )
, –e
j ( ϕ1 + ϕ2 )
,e
jϕ 1 


(LSB to MSB), where c is the code word.
The terms: ϕ1, ϕ2, ϕ3, and ϕ4 are defined below for
5.5Mbps and 11Mbps.
This formula creates 8 complex chips (LSB to MSB) that are
transmitted LSB first. The coding is a form of the generalized
Hadamard transform encoding where ϕ1 is added to all code
chips, ϕ2 is added to all odd code chips, ϕ3 is added to all
odd pairs of code chips and ϕ4 is added to all odd quads of
code chips.
The phases ϕ1 modify the phase of all code chips of the
sequence and are DQPSK encoded for 5.5 and 11Mbps.
This will take the form of rotating the whole symbol by the
appropriate amount relative to the phase of the preceding
symbol. Note that the last chip of the symbol defined above
is the chip that indicates the symbol’s phase.
For the 5.5Mbps CCK mode, the output of the scrambler is
partitioned into nibbles. The first two bits are encoded as
differential modulation in accordance with Table 5 . All odd
numbered symbols of the short Header or MPDU are given
HFA3861
an extra 180 degree (π) rotation in addition to the standard
DQPSK modulation as shown in the table. The symbols of
the MPDU shall be numbered starting with “0” for the first
symbol for the purposes of determining odd and even
symbols. That is, the MPDU starts on an even numbered
symbol. The last data dibits d2, and d3 CCK encode the
basic symbol as specified in Table 6. This table is derived
from the formula above by setting ϕ2 = (d2*pi)+ pi/2, ϕ3 = 0,
and ϕ4 = d3*pi. In the table d2 and d3 are in the order shown
and the complex chips are shown LSB to MSB (left to right)
with LSB transmitted first.
TABLE 5. DQPSK ENCODING TABLE
EVEN SYMBOLS ODD SYMBOLS
DIBIT PATTERN (d(0), d(1)) PHASE CHANGE PHASE CHANGE
d(0) IS FIRST IN TIME
(+jω)
(+jω)
00
0
π
01
π/2
3π/2 (-π/2)
11
π
0
10
3π/2 (-π/2)
π/2
TABLE 6. 5.5Mbps CCK ENCODING TABLE
d2, d3
00 :
1j
1
1j
-1
1j
1
-1j
1
01 :
-1j
-1
-1j
1
1j
1
-1j
1
10 :
-1j
1
-1j
-1
-1j
1
1j
1
11 :
1j
-1
1j
1
-1j
1
1j
1
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes ϕ1 based on DQPSK. The
DQPSK encoder is specified in Table 6 above. The phase
change for ϕ1 is relative to the phase ϕ1 of the preceding
symbol. In the case of rate change, the phase change for ϕ1
is relative to the phase ϕ1 of the preceding CCK symbol. All
odd numbered symbols of the MPDU are given an extra 180
degree (π) rotation in accordance with the DQPSK
modulation as shown in Table 7. Symbol numbering starts
with “0” for the first symbol of the MPDU.
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode ϕ2, ϕ3,
and ϕ4 respectively based on QPSK as specified in Table 7.
Note that this table is binary, not Grey, coded.
TABLE 7. QPSK ENCODING TABLE
DIBIT PATTERN (d(i), d(i+1))
d(i) IS FIRST IN TIME
PHASE
00
0
01
π/2
10
π
11
3π/2 (-π/2)
13
TX Power Control
The transmitter power can be controlled by the MAC via two
registers. The first register, CR58, contains the results of
power measurements digitized by the HFA3861. By
comparing this measurement to what the MAC needs for
transmit power, the MAC can determine whether to raise or
lower the transmit power. It does this by writing the power
level desired to register CR31.
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
The clear channel assessment (CCA) circuit implements the
carrier sense portion of a carrier sense multiple access (CSMA)
networking scheme. The Clear Channel Assessment (CCA)
monitors the environment to determine when it is feasible to
transmit. The CCA circuit in the HFA3861 can be programmed
to be a function of RSSI (energy detected on the channel),
CS1, CS2, or both. The CCA output can be ignored, allowing
transmissions independent of any channel conditions. The
CCA in combination with the visibility of the various internal
parameters (i.e., Energy Detection measurement results), can
assist an external processor in executing algorithms that can
adapt to the environment. These algorithms can increase
network throughput by minimizing collisions and reducing
transmissions liable to errors.
There are three measures that can be used in the CCA
assessment. The receive signal strength indication (RSSI)
which indicates the energy at the antenna, CS1 and carrier
sense (CS2). CS2 becomes active only when a spread
signal with the proper PN code has been detected, and the
peak correlation amplitude exceeds a set threshold, so it
may not be adequate in itself.
CS1 becomes active anytime the AGC portion of the circuit
becomes unlocked, which is likely at the onset of a signal
that is strong enough to support 11Mbps, but may not occur
with the onset of a signal that is only strong enough to
support 1 or 2MBps. CS1 stays active until the AGC locks
and a CS2 assessment is done, if CS2 is false, then CS1 is
cleared, which deasserts CCA. If CS2 is true, then tracking
is begun, and CCA continues to show the channel busy. CS1
may occur at any time during acquisition as the AGC state
machine runs asynchronously with respect to slot times.
A CS2 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period, when this happens,
CS2 is updated between 8 and 9µs into the 10µs dwell. If
CS1 is not active, two consecutive CS2’s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
HFA3861
The receive signal strength indication (RSSI) measurement
is derived from the state of the AGC circuit and the output of
the AGC detector. The RSSI value can be compared to a
programmable threshold. The result of this compare (ED)
will update asynchronously with respect to slot boundaries.
This threshold is normally set to between -70 and -80dBm. A
MAC controlled calibration procedure can be used to
optimize this threshold.
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming details
on these registers can be found under the Control Registers
section of this document).
The CCA output from pin 60 of the device can be defined as
active high or active low through CR 1 (bit 2).
CR9(6:5) allow CCA to be programmed to be a function of
ED only, the logical operation of (CS1 OR CS2), the logical
function of (ED AND (CS1 OR CS2), or just CS2.
CR11(3) lets the user select from sampled CCA mode,
which means CCA will not glitch, is updated once per
symbol and is valid for reading at 19.8µs. In non-sampled
mode, CCA may change at anytime, potentially several times
per slot, as ED and CS1 operate asynchronously to slot
times.
In a typical system CCA will be monitored to determine when
the channel is clear. Once the channel is detected busy,
CCA should be checked periodically to determine if the
channel becomes clear. CCA can be programmed to be
stable to allow asynchronous sampling or even falling edge
detection of CCA. Once MD_RDY goes active, CCA is then
ignored for the remainder of the message. Failure to monitor
CCA until MD_RDY goes active (or use of a time-out circuit)
could result in a stalled system as it is possible for the
channel to be busy and then become clear without an
MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive
signal, the RF to IF downconverter, the IF to baseband
converter, and the baseband processor. The AGC loop is
digitally controlled by the BBP. Basically it operates as
follows:
Initially, the radio is set for high gain. The percent of time that
the A/D converters in the baseband processor are saturated
versus not saturated is monitored along with signal
amplitude and the gain is adjusted down until the amplitude
is what will optimize the demodulator’s performance. If the
amount of saturation is great, the initial gain adjust steps are
large. If the signal overload is small, they are less. If the
signal level then varies more than a preset amount, the AGC
is declared unlocked and the gain again allowed to readjust.
When the gain is right and the A/Ds’ outputs are within the
14
lock window, the BBP declares AGC lock and stops
adjusting for the duration of the packet.
We look for this locked state following an unlocked state as
one indication that a received signal is on the antenna. This
starts the receive process of looking for PN correlation.
Once PN correlation and AGC lock are found, the processor
begins acquisition.
For large signals, the power level in the RF stage output is
also monitored and if it is large, the LNA stage is shut down.
This removes 30dB of gain from the receive chain which is
compensated for by replacing 30dB of gain in the IF AGC
stage. There is some hysteresis in this operation. This
improves the receiver dynamic range.
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, or CCK symbols. The demodulator
includes a frequency tracking loop that tracks and removes
the carrier frequency offset. In addition it tracks the symbol
timing, and differentially decodes (where appropriate) and
descrambles the data. The data is output through the RX
Port to the external processor.
The PRISM baseband processor, HFA3861 uses differential
demodulation for the initial acquisition portion of the
message processing and then switches to coherent
demodulation for the MPDU demodulation. The HFA3861 is
designed to achieve rapid settling of the carrier tracking loop
during acquisition. Rapid phase fluctuations are handled
with a relatively wide loop bandwidth. Coherent processing
improves the BER performance margin as opposed to
differentially coherent processing for the CCK data rates.
The baseband processor uses time invariant correlation to
strip the PN spreading and phase processing to demodulate
the resulting signals in the header and DBPSK/DQPSK
demodulation modes. These operations are illustrated in
Figure 13 which is an overall block diagram of the receiver
processor.
In processing the DBPSK header, input samples from the I
and Q A/D converters are correlated to remove the
spreading sequence. The peak position of the correlation
pulse is used to determine the symbol timing. The sample
stream is decimated to the symbol rate and corrected for
frequency offset prior to PSK demodulation. Phase errors
from the demodulator are fed to the NCO through a lead/lag
filter to maintain phase lock. The demodulated data is
differentially decoded and descrambled before being sent to
the header detection section.
In the 1Mbps DBPSK mode, data demodulation is performed
the same as in header processing. In the 2Mbps DQPSK
mode, the demodulator demodulates two bits per symbol
HFA3861
case time line example assumes that the signal arrives part
way into the first dwell such as to just barely catch detection.
The signal and the scanning process are asynchronous and
the signal could start anywhere. In this timeline, it is
assumed that the signal is present in the first 10µs dwell, but
was missed due to power amplifier ramp up.
and differentially decodes these bit pairs. The bits are then
serialized and descrambled prior to being sent to the output.
In the CCK modes, the receiver uses a complex multiplier to
remove carrier frequency offsets and a bank of correlators to
detect the modulation. A biggest picker finds the largest
correlation in the I and Q Channels and determines the sign
of those correlations. For this to happen, the demodulator
must know absolute phase which is determined by
referencing the data to the last bit of the header. Each
symbol demodulated determines 1 or 2 nibbles of data. This
is then serialized and descrambled before being passed to
the output.
Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. A CS1 followed by CS2 active, or two
consecutive CS2’s will cause the part to exit the acquisition
phase and enter the tracking phase. CR10(7) can be used to
restrict the part to using only consecutive CS2’s as the
requirement to enter tracking.
Chip tracking in the CCK modes is chip decision directed.
Carrier tracking is via a lead/lag filter using a digital Costas
phase detector.
Prior to initial acquisition the NCO was inactive and DPSK
demodulation processing was used. Carrier phase
measurement are done on a symbol by symbol basis
afterward and coherent DPSK demodulation is in effect.
After a brief setup time as illustrated on the timeline of, the
signal begins to emerge from the demodulator.
Acquisition Description
A projected worst case time line for the acquisition of a
signal with a short preamble and header is shown. The
synchronization part of the preamble is 56 symbols long
followed by a 16-bit SFD. The receiver must monitor the
antenna to determine if a signal is present. The timeline is
broken into 10µs blocks (dwells) for the scanning process.
This length of time is necessary to allow enough integration
of the signal to make a good acquisition decision. This worst
It takes 7 more symbols to seed the descrambler before
valid data is available. This occurs in time for the SFD to be
received. At this time the demodulator is tracking and in the
coherent PSK demodulation mode it will no longer
acquire signals.
TX
POWER
RAMP
SFD
56 SYMBOL SYNC
2
20 SYMBOLS
20 SYMBOLS
AGC SETTLE AND LOCK
AND INITIAL DETECTION
VERIFY AND CIR/FREQUENCY
ESTIMATION AND CMF/NCO
JAMMING
7 SYM
SEED
DESCRAMBLER
START SFD DETECTION
FIGURE 10. ACQUISITION TIMELINE
15
16 SYMBOLS
SFD DET
START DATA
HFA3861
VDD (ANALOG)
(12, 17, 22, 31)
VDD (DIGITAL)
(2, 8, 37, 41, 57)
GND (ANALOG)
(9, 15, 20, 25, 28)
GND (DIGITAL)
(1, 7, 36, 43, 56)
(52) RXCLK
IREF (21)
TX AGC
CONTROL
TX_IF_AGC (35)
6-BIT
DAC
SPARE (39)
ANTSEL (40)
REGISTER
TRANSMIT
FILTER
DAC
DAC
TXI (23, 24)
TXQ (29, 30)
TRANSMIT
PORT
6-BIT
ADC
OUTPUT MUX
TX_AGC_IN (18)
TEST CONTROL
VREF (16)
OUTPUT MUX
(60) CCA
PREAMBLE/HEADER
CRC-16
GENERATOR
(59) TX_RDY
(55) TXCLK
TX_DATA
SCRAMBLER
TX
STATE
CONTROL
TIMING
GENERATOR
MCLK
(4) SCLK
(64) SDI
(5) R/W
(6) CS
TEST 7
TEST 6
TEST 5
TEST 4
TEST 3
TEST 2
(44) (45) (46) (47) (48) (49) (50) (51)
TEST 1
(42)
MCLK
(3) SD
TEST PORT
TEST 0
(62) TX_PE
SERIAL CONTROL
PORT
(58) TXD
PROCESSOR INTERFACE
MODULATOR,
BARKER/CCK
FIGURE 11. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
PN Correlators Description
There are two types of correlators in the HFA3861 baseband
processor. The first is a parallel matched correlator that
correlates for the Barker sequence used in preamble,
header, and PSK data modes. This PN correlator is
designed to handle BPSK spreading with carrier offsets up
to ±50ppm and 11 chips per symbol. Since the spreading is
BPSK, the correlator is implemented with two real
correlators, one for the I and one for the Q Channel. The
same Barker sequence is always used for both I and Q
correlators.
16
These correlators are time invariant matched filters otherwise
known as parallel correlators. They use one sample per chip for
correlation although two samples per chip are processed. The
correlator despreads the samples from the chip rate back to the
original data rate giving 10.4dB processing gain for 11 chips per
bit. While despreading the desired signal, the correlator
spreads the energy of any non correlating interfering signal.
The second form of correlator is the correlator function used
for detection of the CCK modulation. For the CCK modes,
HFA3861
the correlation function uses a Fast Walsh Transform to
correlate the 4 or 64 code possibilities followed by a biggest
picker. The biggest picker finds the biggest of 4 or 64
correlator outputs depending on the rate. This is translated
into 2 or 6 bits. The detected output is then processed
through the differential decoder to demodulate the last two
bits of the symbol.
Data Demodulation and Tracking
Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks
tracked by the symbol timing loop (bit sync) as shown in
Figure 12. The frequency and phase of the signal is
corrected using the NCO that is driven by the phase locked
loop. Demodulation of the DBPSK data in the early stages of
acquisition is done by differential detection. Once phase
locked loop tracking of the carrier is established, coherent
demodulation is enabled for better performance. Averaging
the phase errors over 10 symbols gives the necessary
frequency information for proper NCO operation.
Configuration Register 15 sets the search timer for the SFD.
This register sets this time-out length in symbols for the
receiver. If the time out is reached, and no SFD is found, the
receiver resets to the acquisition mode. The suggested
value is the number of preamble symbols plus 16. If different
transmit preamble lengths are used by various transmitters
in a network, the longest value should be used for the
receiver settings.
Data Decoder and Descrambler Description
The data decoder that implements the desired DQPSK
coding/decoding as shown in Table 8. The data is formed
into pairs of bits called dibits. The left bit of the pair is the first
in time. This coding scheme results from differential coding
of the dibits. Vector rotation is counterclockwise for a positive
phase shift, but can be reversed with bit 7 or 6 of CR 1.
For DBPSK, the decoding is simple differential decoding.
TABLE 8. DQPSK DATA DECODER
PHASE SHIFT
DIBIT PATTERN (D0, D1)
D0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
The data scrambler and de-scrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler is designed
to insure smearing of the discrete spectrum lines produced
by the PN code.
One thing to keep in mind is that both the differential decoding
and the descrambling cause error extension or burst errors.
This is due to two properties of the processing. First, the
differential decoding process causes errors to occur on pairs of
symbols. When a symbol’s phase is in error, the next symbol
will also be decoded wrong since the data is encoded in the
change in phase from one symbol to the next. Thus, two errors
are made on two successive symbols. Therefore up to 4 bits
may be wrong although on the average only 2 are. In QPSK
mode, these may occur next to one another or separated by up
to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusiveor of the data and the sum of taps in the shift register.
SAMPLES
AT 2X CHIP
RATE
CORRELATION
PEAK
CORRELATION TIME
T0
CORRELATOR OUTPUT IS
THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE
RECEIVED SIGNAL
T0 + 1 SYMBOL
CORRELATOR
OUTPUT
REPEATS
FIGURE 12. CORRELATION PROCESS
17
T0 + 2 SYMBOLS
EARLY
ON-TIME
LATE
HFA3861
VDD (ANALOG)
(12, 17, 22, 31)
GND (ANALOG)
(9, 15, 20, 25, 28)
VDD (DIGITAL)
(2, 8, 37, 41, 57)
GND (DIGITAL)
(1, 7, 36, 43, 56)
(60) CCA
RX_IF_DET (19)
RX_IF_AGC (34)
RX-RF-AGC (38)
AGC
CONTROL
6-BIT
DAC
CLEAR CHANNEL
ASSESSMENT/
SIGNAL QUALITY
6
COMPLEX
MULTIPLY
EXTRACT.
DPSK
DEMOD
8
(53) RXD
RX_DATA
DESCRAMBLER
(52) RXCLK
RECEIVE
PORT
6-BIT
A/D
6
PEAK
PREAMBLE/HEADER
CRC-16 DETECT
SIN/COS
ROM
SYMBOL
TRACKING
LEAD
/LAG
FILTER
TIMING
GENERATOR
MCLK
(45)
(5) R/W
(6) CS
TXI (23, 24)
6-BIT
DAC
TXQ (29, 30)
(46) (47) (48) (49) (50) (51)
FIGURE 13. DSSS BASEBAND PROCESSOR, RECEIVE SECTION
18
(64) SDI
6-BIT
DAC
TEST 6
(44)
TEST 3
(42)
MCLK
TEST 2
(61)
RX_PE
(4) SCLK
TEST PORT
TEST 1
(63)
RESET
(3) SD
SERIAL CONTROL
PORT
MUX
TEST CONTROL
MUX
RECEIVE
STATE
MACHINE
ANTENNA
SWITCH
CONTROL
TEST 0
ANTSEL (40)
SYMBOL
DECISION
TEST 5
NCO
FAST
WALSH
TRANSFM
TEST 4
CHIP
DE
COVER
(54) MD_RDY
TEST 7
RXQ (13, 14)
6-BIT
A/D
BIT
SYNC
8
CORRELATOR
BARKER
RXI (10, 11)
SAMPLE
INTERPOLATOR,
CHANNEL
MATCHED FILTER
CMF
TRAINING
HFA3861
Data Demodulation in the CCK Modes
In this mode, the demodulator uses Complementary Code
Keying (CCK) modulation for the two highest data rates. It is
slaved to the low rate processor which it depends on for
acquisition of initial timing and phase tracking information.
The low rate section acquires the signal, locks up symbol
and carrier tracking loops, and determines the data rate to
be used for the MPDU data.
The demodulator for the CCK modes takes over when the
preamble and header have been acquired and processed.
On the last bit of the header, the phase of the signal is
captured and used as a phase reference for the high rate
differential demodulator. Control of the demodulator is then
passed to the high rate section.
The signal from the A/D converters is carrier frequency and
phase corrected by a complex multiplier (mixer) that multiplies
the received signal with the output of the Numerically
Controlled Oscillator (NCO) and SIN/COS look up table. This
removes the frequency offset and aligns the I and Q Channels
properly for the correlators. The sample rate is decimated to
11MSPS for the correlators after the complex multiplier since
the data is now synchronous in time.
The Fast Walsh transform correlation section processes the
I and Q channel information. The demodulator knows the
symbol timing, so the correlation is batch processed over
each symbol. The correlation outputs from the correlator are
compared to each other in a biggest picker and the chosen
one determines 6 bits of the symbol. The QPSK phase of the
chosen one determines two more bits for a total of 8 bits per
symbol. Six bits come from which of the 64 correlators had
the largest output and the last two are determined from the
QPSK differential demod of that output. In the 5.5Mbps
mode, only 4 of the correlator outputs are monitored. This
demodulates 2 bits for which of 4 correlators had the largest
output and 2 more for the QPSK demodulation of that output
for a total of 4 bits per symbol.
Tracking
Carrier tracking is performed on the de-rotated signal
samples from the complex multiplier. These are alternately
routed into two streams. The END chip samples are the
same as those used for the correlators. The MID chip
samples should lie on the chip transitions when the tracking
is perfect. A chip phase error is generated if the END sign
bits bracketing the MID samples are different. The sign of the
error is determined by the sign of the END sample after the
MID sample.
Tracking is only measured when there is a chip transition.
Note that this tracking is dependent on a positive SNR in the
chip rate bandwidth.
19
The symbol clock is tracked by a sample interpolator that
can adjust the sample timing forwards and backwards by 72
increments of 1/8th chip. This approach means that the
HFA3861 can only track an offset in timing for a finite interval
before the limits of the interpolator are reached. Thus,
continuous demodulation is not possible.
Carrier tracking is performed in a four phase Costas loop. This
forms the error term that is integrated in the lead/lag filter for
the NCO, closing the loop.
Demodulator Performance
This section indicates the typical performance measures for
a radio design. The performance data below should be used
as a guide. In general, the actual performance depends on
the application, interference environment, RF/IF
implementation and radio component selection.
Overall Eb/N0 Versus BER Performance
The PRISM chip set has been designed to be robust and
energy efficient in packet mode communications. The
de