CD54AC541F3A, CD54ACT541F3A S E M I C O N D U C T O R Octal Buffer/Line Driver Three-State, Non-Inverting July 1998 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The CD54AC541F3A and CD54ACT541F3A are octal buffer/line drivers that utilize the Harris Advanced CMOS Logic technology. The CD54AC541F3A and CD54ACT541F3A are non-inverting three-state buffers having two active-LOW output enables. • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • Meets JEDEC Standard No. 20 Ordering Information • SCR - Latch-Up-Resistant CMOS Process and Circuit Design • Speed of Bipolar FAST/A/S with Significantly Reduced Power Consumption • Functionally and Pin-Compatible with Industry 54 Bipolar Types in the FAST, AS and S Series • ±24mA Output Drive Current, Drives 75Ω Lines without Need for Terminations • Operating Voltage - AC Types . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5V to 5.5V - ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Functional Diagram A1 A2 A3 A4 A5 A6 A7 3 17 4 16 5 15 6 14 7 13 8 12 9 11 1 OE1 OE2 19 -55 to 125 20 Ld CERDIP F20.3 CD54ACT541F3A -55 to 125 20 Ld CERDIP F20.3 Pinout • Fan Out (Over Temperature) - ACL Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2400 - FAST Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 - AS Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 18 CD54AC541F3A 1. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. • Military Operating Temperature Range - Ceramic (CERDIP) 54 Series: . . . . . . . . -55 to 125oC 2 OE1 1 A0 2 19 OE2 A1 3 18 Y0 A2 4 17 Y1 A3 5 16 Y2 A4 6 15 Y3 A5 7 14 Y4 A6 8 13 Y5 A7 9 12 Y6 GND 10 11 Y7 © Harris Corporation 1998 20 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 GND = 10 VCC = 20 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright PKG. NO. PACKAGE NOTE: • Balanced Propagation Delays A0 TEMP. RANGE (oC) PART NUMBER 1 File Number 3914.1 CD54AC541F3A, CD54ACT541F3A Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 2) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 85 24 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 3) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) 4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. For up to 4 outputs per device, add ±25mA for each additional output. 3. Unless otherwise specified, all voltages are referenced to ground. 4. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) VCC (V) VIH - - 1.5 25oC -55oC TO 125oC MIN MAX MIN MAX UNITS 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL - 3 2.1 - 2.1 - V 4.5 3.15 (Note 5) - 3.15 (Note 5) - V 5.5 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 V 3 - 0.9 - 0.9 V 4.5 - 1.35 (Note 5) - 1.35 (Note 5) V 5.5 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - V -4 3 2.58 - 2.4 - V -24 4.5 3.94 (Note 5) - 3.7 (Note 5) - V -50 (Note 6, 7) 5.5 - - 3.85 - V 2 CD54AC541F3A, CD54ACT541F3A DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 V 12 3 - 0.36 - 0.5 V 24 4.5 - 0.36 (Note 5) - 0.5 (Note 5) V 50 (Note 6, 7) 5.5 - - - 1.65 V MIN MAX MIN MAX UNITS Input Leakage Current II VCC or GND - 5.5 - ±0.1 (Note 5) - ±1 (Note 5) µA Three-State Leakage Current IOZ VIH or VIL VO = VCC or GND - 5.5 - ±0.5 (Note 5) - ±10 (Note 5) µA Quiescent Device Current ICC VCC or GND 0 5.5 - 8 (Note 5) - 160 (Note 5) µA High Level Input Voltage VIH - - 4.5 to 5.5 2 (Note 5) - 2 (Note 5) - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 (Note 5) - 0.8 (Note 5) V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - V -24 4.5 3.94 (Note 5) - 3.7 (Note 5) - V -50 (Note 6, 7) 5.5 - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 V 24 4.5 - 0.36 (Note 5) - 0.5 (Note 5) V 50 (Note 6, 7) 5.5 - - - 1.65 V ACT TYPES Low Level Output Voltage VOL VIH or VIL II VCC or GND - 5.5 - ±0.1 (Note 5) - ±1 (Note 5) µA Three-State or Leakage Current IOZ VIH or VIL VO = VCC or GND - 5.5 - ±0.5 (Note 5) - ±10 (Note 5) µA Quiescent Device Current ICC VCC or GND 0 5.5 - 8 (Note 5) - 160 (Note 5) µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 3 mA Input Leakage Current Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load NOTES: 5. Tested 100%. 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum transmission-line-drive capability of 75Ω for 54AC/ACT Series. 3 CD54AC541F3A, CD54ACT541F3A ACT Input Load Table INPUT UNIT LOAD Data 0.5 OE1, OE2 1.3 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX UNITS AC TYPES Propagation Delay, Data to Output Propagation Delay, Enable, Disable to Output tPLH, tPHL 1.5 - - 98 ns 3.3 (Note 9) 3.3 - 10.9 ns 5 (Note 10) 2.3 - 7.8 (Note 8) ns 1.5 - - 150 3.3 5.4 - 18 5 3.6 - 12 (Note 8) 1.5 - - 150 3.3 4.5 - 15 tPZL, tPZH tPLZ, tPHZ 5 3.6 - 12 (Note 8) Minimum (Valley) VOH During Switching of Other Outputs (Output Under Test Not Switching) VOHV See Figure 1 5 - 4 at 25oC - V Maximum (Peak) VOL During Switching of Other Outputs (Output Under Test Not Switching) VOLP See Figure 1 5 - 1 at 25oC - V CO - - - 15 pF Three-State Output Capacitance Input Capacitance CI - - - 10 pF CPD (Note 11) - - 60 - pF Propagation Delay, Data to Output tPLH, tPHL 5 (Note 10) 2.5 - 8.3 (Note 8) ns Propagation Delay, Enable, Disable to Output tPLZ, tPZL, tPZH, tPHZ 5 4 - 13.4 (Note 8) ns Minimum (Valley) VOH During Switching of Other Outputs (Output Under Test Not Switching) VOHV See Figure 1 5 - 4 at 25oC - V Maximum (Peak) VOL During Switching of Other Outputs (Output Under Test Not Switching) VOLP See Figure 1 5 - 1 at 25oC - V Three-State Output Capacitance CO - - - 15 pF Input Capacitance CI - - - 10 pF CPD (Note 11) - - 60 - pF Power Dissipation Capacitance ACT TYPES Power Dissipation Capacitance NOTES: 8. Limits tested 100%. 9. 3.3V Min is at 3.6V, Max si at 3V. 10. 5V Min is at 5.5V, Max is at 4.5V 11. CPD is used to determine the dynamic power consumption per gate. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. 4 CD54AC541F3A, CD54ACT541F3A Burn-In Test Circuit Connections (Use DC II for F3A Burn-In and AC for Life Test) DC BURN-IN I DC BURN-IN II DC OPEN GROUND VCC (6V) OPEN GROUND VCC (6V) CD54AC/ACT541 11-18 1-10, 19 20 11-18 10 1-9, 19, 20 OSCILLATOR AC OPEN GROUND 1/2 VCC (3V) VCC (6V) 50kHz 25kHz CD54AC/ACT541 - 10 11-18 20 1, 19 2-9 NOTE: Each pin except VCC and Gnd will have a resistor of 2kΩ-47kΩ. OUTPUT RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. CD54AC CD54ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 1. 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