µModule Regulator Charges Supercapacitor Backup Supply, Supporting LDO Outputs When the Input Supply Fails Andy Radosevich The LTM8001 is a µModule regulator that combines a 5A switching regulator with an array of five 1.1A low noise LDOs. The switching regulator can be set for constant current, suitable to charge supercapacitors for power backup. The LTM8001 operates from 6V to 36V inputs. The switching regulator is capable of constant output voltage or constant output current regulation at switching frequencies from 200kHz to 1MHz. The output of the switching regulator can be adjusted from 1.2V to 24V and the outputs of the LDOs are adjustable from 0V to 24V. The switching regulator is set to regulate output current at 5.6A (typical) to provide a current limit that is above the maximum output current of 5A. The regulated current level can be easily lowered. The inputs for three of the LDOs are hardwired to the output of the switching regulator, but the input to the remaining bank of two LDOs is undedicated, so it can be connected to the switching regulator or elsewhere. The bias inputs to the LDOs are undedicated but are separated into two inputs: one for the bank of three connected to the switching regulator and the other for the remaining bank of two LDOs. The outputs of the LDOs can be operated separately or paralleled for higher output currents. Figure 1. The LTM8001 producing 3.3V at 1A and 2.5V, 0.5A regulated outputs while charging VIN a supercapacitor for backup 9V TO 15V power. 2-OUTPUT REGULATOR WITH SUPPLY RIDE-THROUGH SUPERCAPACITOR Figure 1 shows the LTM8001 in a dual output application: 3.3V at 1A and 2.5V at 0.5A. This setup also charges a supercapacitor and draws on the supercap to support the outputs in the face of input supply failures. The switching frequency is 600kHz and the output voltage of the switching regulator is 5V when the supercapacitor is fully charged. The input voltage is from 9V to 15V and the LTM8001 charges the supercapacitor at 5.6A, typical. The resistor divider on the RUN pin programs the circuit to turn on for a 9V or higher input, but also ensures that the switching VIN45 10µF 200k circuits.linear.com/629 RUN BIAS123 BIAS45 LTM8001 COMP SS VREF ILIM SYNC GND 3.3V 1A VOUT1 LDO 1 SET1 VOUT2 STEP-DOWN LDO 2 SET2 SWITCHING V REGULATOR LDO 3 OUT3 SET3 LDO 4 600kHz 3.09k 2.5V 0.5A VOUT4 SET4 VOUT5 FBO LDO 5 SET5 RT 68.1k 28 | April 2013 : LT Journal of Analog Innovation Figure 2 shows LDO VBIAS -to-output dropout voltage vs output current. According to Figure 2, the bias of the higher voltage, 3.3V/1A LDO output must be 1.5V higher than 3.3V, or 4.8V for proper regulation. This means that the LDO outputs remain in regulation during the time the supercapacitor voltage decays 100mV from 4.9V to 4.8V. The 0.07Ω ESR of the PM-5R0V155-R supercapacitor reduces the available voltage from the supercapacitor from 5V to 4.9V while the supercapacitor provides 1.5A to the LDOs. If the supercapacitor is 1.5F and the total VOUT0 VIN0 48.7k LTspice IV regulator remains off when back-fed by the supercapacitor when there is an interruption to the input power. 4.7µF 10µF 124k 110k 47µF 5V 1.5F 5V SUPERCAP PM-5ROV155-R design ideas The inputs for three of the LDOs are hardwired to the output of the switching regulator, but the input to the remaining bank of two LDOs is undedicated, so it can be connected to the switching regulator or elsewhere. The outputs of the LDOs can be operated separately or paralleled for higher output currents. BIAS-TO-OUTPUT DROPOUT VOLTAGE (V) 1.52 the LTM8001 parallels LDOs to distribute heat and lower operating temperatures. VIN 10V/DIV 1.50 1.48 VOUT0(SUPERCAP) 2V/DIV 1.46 1.44 1.42 VOUT1,2,3(3.3V) 2V/DIV 1.40 1.38 VOUT4,5(2.5V) 2V/DIV 1.36 1.34 0 200 400 800 600 OUTPUT CURRENT (mA) 1000 500ms/DIV Figure 2. LDO VBIAS -to-output dropout voltage vs output current Figure 3. Supercapacitor power backup system holds up the 3.3V output for well over 100ms output current of the LDOs is 1.5A, the holdup time for the 3.3V LDO output is: regard to power dissipation, it maximizes holdup time if the input supply fails. Power loss is minimized by operating the LDO with inputs that just meet, and do not exceed, the bias dropout requirements of the 3.3V LDO. But the supercapacitor voltage must exceed the input power dropout requirement to meet bias dropout and holdup requirements. To mitigate this increased power dissipation, C ∆V I 1.5 0.1 = 1.5 = 100ms 3.3V HOLDUP TIME = Both the LDO bias and LDO input power are connected to 5V from the supercapacitor. Although 5V is non-optimal with Holdup time is longer when the supercapacitor provides bias to the LDOs compared to using a conventional capacitor for that purpose. This avoids detrimental effects of charging a large capacitor directly with the input voltage. Figure 3 shows that the 3.3V output holdup time exceeds 100ms when the supercapacitor is charged to 5V and the LDO outputs are 3.3V at 1A and 2.5V at 0.5A. CONCLUSION The LTM8001 makes it easy to design a multiple output voltage regulator circuit featuring supercapacitor backup power. It is possible to achieve significant holdup time without adding large and undesirable capacitance directly to input power. Visit www.linear.com/LTM8001 for data sheets, demo boards and other applications information. n (LT3504 continued from page 27) is low. External gate network C1 and D2 limits these inrush currents by controlling Q1’s gate voltage slew rate. Since VIN follows Q1’s gate voltage, the external gate network forces VIN to ramp modestly compared to the abrupt input voltage transient present on VSUPPLY, as shown in Figure 6. LT3504. During normal operation, the LT3504’s built-in boost regulator permits 100% switch duty cycle operation and serves as an excellent MOSFET gate driver. The LT3504, along with a MOSFET and gate clamp, provides a transient-robust, compact multioutput solution. CONCLUSION Visit www.linear.com/LT3504 for data sheets, demo boards and other applications information. n The high voltage standoff capability of the series connected MOSFET blocks dangerous spikes from reaching the VSUPPLY 10V/DIV VIN 10V/DIV 40µs/DIV Figure 6. Fast VSUPPLY dV/dt is blocked from VIN by series MOSFET and gate network April 2013 : LT Journal of Analog Innovation | 29