VEML6040 www.vishay.com Vishay Semiconductors RGBW Color Sensor with I2C Interface FEATURES • Package type: surface mount • Dimensions (L x W x H in mm): 2.0 x 1.25 x 1.0 • Integrated modules: color sensor (RGBW) and signal conditioning IC • FiltronTM technology provides a spectrum matching real human eye responses • Supports low transmittance (dark) lens design • Fluorescent light flicker immunity • Provides 16-bit resolution for each channel (R, G, B, W) DESCRIPTION VEML6040 color sensor senses red, green, blue, and white light and incorporates photodiodes, amplifiers, and analog / digital circuits into a single chip using CMOS process. With the color sensor applied, the brightness, and color temperature of backlight can be adjusted base on ambient light source that makes panel looks more comfortable for end user’s eyes. VEML6040’s adoption of FiltronTM technology achieves the closest ambient light spectral sensitivity to real human eye responses. VEML6040 provides excellent temperature compensation capability for keeping the output stable under changing temperature. VEML6040’s function are easily operated via the simple command format of I2C (SMBus compatible) interface protocol. VEML6040’s operating voltage ranges from 2.5 V to 3.6 V. VEML6040 is packaged in a lead (Pb)-free 4 pin OPLGA package which offers the best market-proven reliability. • Selectable maximum detection range (515.4, 1031, 2062, 4124, 8248, or 16 496) lux with highest sensitivity 0.007865 lux/step • Package: OPLGA • Temperature compensation: -40 °C to +85 °C • Low power consumption I2C (SMBus compatible) interface • Floor life: 168 h, MSL 3, according to J-STD-020 • Output type: I2C bus • Operation voltage: 2.5 V to 3.6 V • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 APPLICATIONS • Handheld device • Notebook • Consumer device • Industrial and mechanical application PRODUCT SUMMARY PART NUMBER VEML6040 OPERATING VOLTAGE RANGE (V) I2C BUS VOLTAGE RANGE (V) PEAK SENSITIVITY (nm) RANGE OF SPECTRAL BANDWIDTH λ0.5 (nm) OUTPUT CODE 2.5 to 3.6 1.7 to 3.6 650, 550, 450 (R, G, B) ± 35, ± 35, ± 40 (R, G, B) 16 bit, I2C Note (1) Adjustable through I2C interface ORDERING INFORMATION ORDERING CODE PACKAGING VOLUME (1) REMARKS VEML6040 Tape and reel MOQ: 2500 pcs 2.0 mm x 1.25 mm x 1.0 mm Note MOQ: minimum order quantity (1) Rev. 1.4, 18-May-16 Document Number: 84276 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL MIN. MAX. UNIT Supply voltage TEST CONDITION VDD 0 3.6 V Operation temperature range Tamb -40 +85 °C Storage temperature range Tstg -40 +85 °C RECOMMENDED OPERATING CONDITIONS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL MIN. MAX. UNIT Supply voltage VDD 2.5 3.6 V Operation temperature range Tamb -40 +85 °C f(I2CCLK) 10 400 kHz I2C TEST CONDITION bus operating frequency PIN DESCRIPTIONS PIN ASSIGNMENT SYMBOL TYPE FUNCTION 1 GND I Ground 2 SDAT I / O (open drain) I2C data bus data input / output 3 SCLK I I2C digital bus clock input 4 VDD I Power supply input BLOCK DIAGRAM VEML6040 GND 1 4 VDD W B G R Control logic SDA 2 Rev. 1.4, 18-May-16 Output buffer I2C interface 3 SCL Document Number: 84276 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT VDD 2.5 - 3.6 V μA Supply voltage Supply current Logic high I2C - 200 - 1.5 - - VIL - - 0.8 VIH 1.4 - - VIL - - 0.6 λPR - 650 - nm λPG - 550 - nm λPB - 450 - nm (3) - 96 - λPG = 518 nm (3) - 74 - - 56 - VDD = 3.3 V Logic low signal input IDD VIH Logic high VDD = 2.6 V Logic low Peak sensitivity wavelength λPR = 619 nm Irradiance responsivity λPB = 467 nm (3) Detectable intensity Minimum Maximum G channel, IT = 1280 ms (1)(2) - 0.007865 - G channel, IT = 40 ms (1)(2) - 16 496 - G channel, IT = 80 ms (1) 0 - 3 Dark offset Operating temperature range V counts/(μW/cm2) lx Tamb -40 - +85 °C IDD - 800 - nA Light condition = dark, VDD = 3.6 V Shutdown current V Notes (1) Test condition: V DD = 3.3 V, temperature: 25 °C (2) Light source: white LED (3) LED spectrum given in fig. 1; IT = 160 ms Average Gain 1 2.0 10000 1.8 Blue 1.0 1000 0.8 Green 0.6 100 0.4 0.2 0 Transient Thermal Impedance Transient Thermal Impedance Relative Responsivity (µW/cm2) Power (W) Red 10 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 Wavelength (nm) 2nd line Fig. 1 - Normalized Spectral Response Rev. 1.4, 18-May-16 Document Number: 84276 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors I2C BUS TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL Clock frequency STANDARD MODE MIN. MAX. f(SMBCLK) 10 t(BUF) 4.7 Hold time after (repeated) start condition; after this period, the first clock is generated t(HDSTA) Repeated start condition setup time t(SUSTA) Stop condition setup time Data hold time Data setup time Bus free time between start and stop condition FAST MODE UNIT MIN. MAX. 100 10 400 kHz - 1.3 - μs 4.0 - 0.6 - μs 4.7 - 0.6 - μs t(SUSTO) 4.0 - 0.6 - μs t(HDDAT) 300 - 90 - ns t(SUDAT) 250 - 100 - ns I2C clock (SCK) low period t(LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t(HIGH) 4.0 - 0.6 - μs Detect clock / data low timeout t(TIMEOUT) 25 35 - - ms Clock / data fall time t(F) - 300 - 300 ns Clock / data rise time t(R) - 1000 - 300 ns t(LOW) t(R) t(F) VIH I2CBus CLOCK (SCLK) VIL t(HDSTA) I2CBus DATA (SDAT) P Stop Condition t(HIGH) t(SUSTA) t(SUSTO) t(BUF) t(HDDAT) t(SUDAT) VIH VIL S Star Condition S P Fig. 2 - I2C Bus Timing Diagram Rev. 1.4, 18-May-16 Document Number: 84276 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors PARAMETER TIMING INFORMATION ACK by VEML6040 ACK by VEML6040 ACK by VEML6040 ACK by VEML6040 Fig. 3 - I2C Bus Timing for Sending Word Command Format ACK by VEML6040 ACK by ACK by VEML6040 VEML6040 ACK by VEML6040 ACK by VEML6040 ACK by VEML6040 ACK by VEML6040 Fig. 4 - I2C Bus Timing for Receiving Word Command Format Rev. 1.4, 18-May-16 Document Number: 84276 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Average Gain 1 1.0 10000 0.8 Green 0.7 Red 1000 White 0.6 0.5 0.4 100 0.3 0.2 Transient Thermal Impedance Transient Thermal Impedance Relative Responsivity (µW/cm2) Normalized Response Blue 0.9 0.1 0 400 450 500 550 600 650 700 750 800 850 900 950 10 1000 Wavelength (nm) 2nd line Fig. 5 - Normalized Spectral Response Fig. 6 - Normalized Output vs. View Angle APPLICATION INFORMATION Pin Connection with the Host VEML6040 integrates R, G, B, and W sensor together with I2C interface. It is very easy for the baseband (CPU) to access VEML6040 output data via I2C interface without extra software algorithms. The hardware schematic is shown in the following diagram. The 0.1 μF capacitor near the VDD pin is used for power supply noise rejection. The 2.2 kΩs are suitable for the pull-up resistors of I2C. 1.7 V to 3.6 V R1 Host Micro Controller R2 VEML6040 GND (1) 2.5 V to 3.6 V C1 VDD (4) SDA (2) I2C bus data SDA SCL (3) I2C bus clock SCL 100 nF Fig. 7 - Hardware Pin Connection Diagram Rev. 1.4, 18-May-16 Document Number: 84276 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors Digital Interface The VEML6040 contains a CONF register (00h) used for operation control and parameter setup. Measurement results are stored in four separate registers, one each for red, green, blue, and white respectively (08h to 0Bh). All registers are accessible via I2C communication. Figure 8 shows the basic I2C communication with the VEML6040. Each of the registers in the VEML6040 are 16 bit wide, so 16 bit should be written when a write command is sent, and 16 bit should be read when a read command is sent. The built in I2C interface is compatible with I2C modes “standard” and “fast”: 100 kHz to 400 kHz Send Word ɦġWrite Command to VEML6040 1 7 S Slave address 1 1 8 1 Wr A Command code A 8 Data byte low 1 8 1 1 A Data byte high A P Receive Word ɦġRead Data from VEML6040 1 7 1 1 8 1 1 7 1 1 8 1 8 1 1 S Slave address Wr A Command code A S Slave address Rd A Data byte low A Data byte high A P S = start condition P = stop condition A = acknowledge Shaded area = VEML6040 acknowledge Fig. 8 - Command Protocol Format Note • Please note the repeat start condition when data is read from the sensor. A stop condition should not be sent here. Slave Address and Function Description VEML6040 uses 10h slave address for 7-bit I2C addressing protocol. VEML6040 has 16-bit resolution for each channel (R, G, B, and W) that provides sensitivity up to 0.0056 lux/step for G, which is advantageous under a low transmittance lens design (dark lens). TABLE 1 - SLAVE ADDRESS AND COMMAND CODE DESCRIPTION SLAVE ADDRESS 0x10 COMMAND CODE DATE BYTE REGISTER R/W LOW / HIGH NAME 00h 01h to 07h 08h 09h 0Ah 0Bh BIT 7 L CONF R/W H Reserved R/W Reserved 6 0 L Reserved R/W Reserved H Reserved R/W Reserved L R_DATA R H R_DATA R R_Data (15 : 8) L G_DATA R G_Data (7 : 0) H G_DATA R G_Data (15 : 8) 5 IT (2 : 0) 4 3 2 1 0 0 TRIG AF SD R_Data (7 : 0) L B_DATA R B_Data (7 : 0) H B_DATA R B_Data (15 : 8) L W_DATA R W_Data (7 : 0) H W_DATA R W_Data (15 : 8) Note • Slave address is 7-bit addressing protocol Rev. 1.4, 18-May-16 Document Number: 84276 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors Configuration Register Format VEML6040 has a 16-bit configuration register for controlling. The description of each command format is shown in the following tables. TABLE 2-1 - COMMAND CODE 00H BITS DESCRIPTION SLAVE ADDRESS: 0x10; REGISTER NAME: CONF; COMMAND CODE: 00H / DATA BYTE LOW X X TRIG AF SD BIT 7 BIT 6 BIT 5 IT BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 IT2 IT1 IT0 0 TRIG AF SD DESCRIPTION IT Integration time setting TRIG Proceed one detecting cycle at manual force mode AF Auto / manual force mode SD Chip shutdown setting TABLE 2-2 - COMMAND CODE 00H REGISTER SETTING BITS SETTING DESCRIPTION BITS SETTING BIT 7 Default = 0 BIT 3 Default = 0 BIT 2 TRIG 0 = no trigger 1 = trigger one time detect cycle BIT 1 AF 1 = force mode BIT 0 SD 1 = disable color sensor (0 : 0 : 0) = 40 ms (0 : 0 : 1) = 80 ms (0 : 1 : 0) = 160 ms BIT 6, 5, 4 IT (2 : 0) (0 : 1 : 1) = 320 ms (1 : 0 : 0) = 640 ms (1 : 0 : 1) = 1280 ms DESCRIPTION 0 = auto mode 0 = enable color sensor TABLE 3-1 - RESERVE COMMAND CODE DESCRIPTION RESERVED COMMAND CODE: 00H / DATA BYTE HIGH Command Bit Reserved 7:0 Description Default = 0x00 TABLE 3-2 - RESERVE COMMAND CODE DESCRIPTION RESERVED COMMAND CODE: 01H TO 07H Command Bit Reserved 7:0 Description Default = 0x00 TABLE 4 - READ OUT COMMAND CODE DESCRIPTION REGISTER R_DATA G_DATA B_DATA W_DATA Rev. 1.4, 18-May-16 COMMAND CODE BIT DESCRIPTION 0x08_L (08H data byte low) 7:0 0x00 to 0xFF, R channel LSB output data 0x08_H (08H data byte high) 7:0 0x00 to 0xFF, R channel MSB output data 0x09_L (09H data byte low) 7:0 0x00 to 0xFF, G channel LSB output data 0x09_H (09H data byte high) 7:0 0x00 to 0xFF, G channel MSB output data 0x0A_L (0AH data byte low) 7:0 0x00 to 0xFF, B channel LSB output data 0x0A_H (0AH data byte high) 7:0 0x00 to 0xFF, B channel MSB output data 0x0B_L (0BH data byte low) 7:0 0x00 to 0xFF, W channel LSB output data 0x0B_H (0BH data byte high) 7:0 0x00 to 0xFF, W channel MSB output data Document Number: 84276 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors Data Access Each of the R, G, B, and W result registers has a 16-bit resolution (2 bytes). One byte is the LSB and the other byte is the MSB. The host needs to follow the read word protocol as shown in figure 7. The data format shows as below. TABLE 5 - 16-BIT DATA FORMAT VEML6040 16-BIT DATA FORMAT Data bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data byte low Data byte high Note S Slave address A Wr Command code A S Slave address Rd A Data byte low A Data byte high A P • Data byte low represents LSB and data byte high represents MSB. The integration time settings result in the corresponding resolutions that are shown in table 6. TABLE 6 - G CHANNEL RESOLUTION AND MAXIMUM DETECTION RANGE IT SETTINGS G SENSITIVITY MAX. DETECTABLE LUX 40 ms 0.25168 16 496 80 ms 0.12584 8248 (0 : 1 : 0) 160 ms 0.06292 4124 (0 : 1 : 1) 320 ms 0.03146 2062 (1 : 0 : 0) 640 ms 0.01573 1031 (1 : 0 : 1) 1280 ms 0.007865 515.4 IT (2 : 0) INTEGRATION TIME (0 : 0 : 0) (0 : 0 : 1) Data Auto-Memorization VEML6040 keeps the last results read. These values will remain in the registers, and can be read from these registers, until the device wakes up and a new measurement is made. Lux and CCT Calculation In order to use the results to calculate the lux or correlated color temperature, please refer to the “Designing the VEML6040 into an Application” application note (www.vishay.com/doc?84331). Rev. 1.4, 18-May-16 Document Number: 84276 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors PACKAGE INFORMATION in millimeters 0.45 ± 0.05 2.00 ± 0.15 0.25 X X 1 4 0.70 1.25 ± 0.15 0~0.06 4 1 1.10 0~0.05 0.35 ± 0.05 TOP VIEW X X 3 2 0.1 3 0~0.04 2 0.625± 0.15 0~0.02 0.55 ± 0.05 1.00± 0.15 1.0 SIDE VIEW 1± 0.10 0.45 0.56 30um ± 10 um DIE 0.1 Fig. 9 - VEML6040 A3OG Package Dimensions LAYOUT NOTICE AND REFERENCE CIRCUIT in millimeters Fig. 10 - VEML6040 PCB Layout Footprint RECOMMENDED STORAGE AND REBAKING CONDITIONS PARAMETER Storage temperature Relative humidity Open time Total time Rebaking Rev. 1.4, 18-May-16 CONDITIONS From the date code on the aluminized envelope (unopened) Tape and reel: 60 °C Tube: 60 °C MIN. 5 - MAX. 50 60 168 12 22 22 UNIT °C % h months h h Document Number: 84276 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors RECOMMENDED INFRARED REFLOW Soldering conditions which are based on J-STD-020 C IR REFLOW PROFILE CONDITION PARAMETER CONDITIONS Peak temperature Preheat temperature range and timing Timing within 5 °C to peak temperature Timing maintained above temperature / time Timing from 25 °C to peak temperature TEMPERATURE TIME 255 °C + 0 °C / - 5 °C (max.: 260 °C) 10 s 150 °C to 200 °C 60 s to 180 s - 10 s to 30 s 217 °C 60 s to 150 s - 8 min (max.) Ramp-up rate 3 °C/s (max.) - Ramp-down rate 6 °C/s (max.) - Temperature (ºC) Recommend Normal Solder Reflow is 235 °C to 255 °C Fig. 11 - VEML6040 OPLGA Solder Reflow Profile Chart RECOMMENDED IRON TIP SOLDERING CONDITION AND WARNING HANDLING 1. Solder the device with the following conditions: 1.1. Soldering temperature: 400 °C (max.) 1.2. Soldering time: 3 s (max.) 2. If the temperature of the method portion rises in addition to the residual stress between the leads, the possibility that an open or short circuit occurs due to the deformation or destruction of the resin increases. 3. The following methods: VPS and wave soldering, have not been suggested for the component assembly. 4. Cleaning method conditions: 4.1. Solvent: methyl alcohol, ethyl alcohol, isopropyl alcohol 4.2. Solvent temperature < 45 °C (max.) 4.3. Time: 3 min (min.) Rev. 1.4, 18-May-16 Document Number: 84276 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VEML6040 www.vishay.com Vishay Semiconductors TAPE PACKAGING INFORMATION in millimeters Fig. 12 - VEML6040 A3OG Package Carrier Tape Fig. 13 - Taping Direction Fig. 14 - Reel Dimensions Rev. 1.4, 18-May-16 Document Number: 84276 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000