A3965: DMOS Dual Full-Bridge PWM Motor Driver

A3965
DMOS Dual Full-Bridge PWM Motor Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2005
Recommended Substitutions:
The A3965 is a fairly unique device within Allegro’s portfolio, typically
fitting niche low-voltage, battery-driven stepper motor applications.
Our closest recommended alternatives are:
• For customers looking for a stepper motor driver for battery-driven
applications, we recommend the A3977, A3982, A3983, or A3984.
• The closest device functionally is the A3966, if supply current and a
low logic voltage (4.75 to 5.5 V) are not issues.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.
3965
PRELIMINARY DATASHEET - 12/4/2002
(Subject to change without notice)
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB ..........................20 V
Output Current, IOUT............................ ±500 mA*
Logic Supply Voltage, VDD ..........................7.0 V
Logic Input Voltage Range,
VIN ......................-0.3 V to VDD + 0.3 V
(tW<30ns) ..................-1.0V to VDD +1V
Sense Voltage, VSENSE ..................................0.5 V
Reference Voltage, VREF .................................3 V
Package Power Dissipation (TA = +25°C), PD
A3965SLB........................... 50°C/W**
Operating Temperature Range,
TA ................................ -20°C to +85°C
Junction Temperature, TJ ......................... +150°C
Storage Temperature Range,
TS............................... -55°C to +150°C
* Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any set of
conditions, do not exceed the specified current rating or a
junction temperature of 150°C.
*Measured with 062" thick FR4, two sided PCB with 1 sq
inch copper area.
1
DMOS DUAL FULL-BRIDGE
PWM MOTOR DRIVER
Designed for Pulse Width Modulated (PWM) current control of low
voltage stepper motors, the A3965S is capable of output currents to ± 500 mA
and operating voltages to 20 V.
The A3965 is particularly attractive for low power or battery
operated motors where minimal power consumption is desired. A SLEEP
mode disables all circuitry and typically draws less than 1µA supply current
from motor and logic supply. During operation the fixed frequency ON
pulses of each H-bridge are 180 degrees out of phase to minimize the peak
demand required of the motor supply allowing savings in size and cost of
external power supply components.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a stepper motor with externally applied
PWM control signals.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of VDD and charge pump, and crossover
current protection. Special power up sequencing is not required.
The A3965 is supplied in a 24-lead plastic SOIC with a copper
batwing tab (suffix ‘LB’).
FEATURES
„
„
„
„
„
„
„
±500 mA, 20 V Output Rating
2.85 to 5.5V Logic Supply Operation
Sleep Mode for Minimum Power Consumption
Fixed Frequency PWM
Offset On Pulses to Minimize Peak Supply Transient Currents
Internal UVLO and Thermal Shutdown Circuitry
Crossover-Current Protection
3965 DMOS Dual Full Bridge
PWM Motor Driver
CP2
CP1
.22uf
VREG
.22uf
Functional Block Diagram
VDD
REGULATOR
CHARGE PUMP
VCP
BANDGAP
VBB
.22uf
UVLO AND
FAULT
DETECT
DMOS H-BRIDGE
VCP
OUT1A
SLEEP
OUT1B
PHASE2
PHASE1
CONTROL
LOGIC
ENABLE1
SENSE1
ENABLE2
GATE
DRIVE
DMOS H-BRIDGE
VBB
OUT2A
OSC
RC
OUT2B
S
1/6
R
S
1/6
Q
R
SENSE2
-
REF1
+
SENSE1
Q
-
REF2
+
SENSE2
.1uF
GROUND
2
3965 DMOS Dual Full Bridge
PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 20 V, VDD = 3.0 V, VSENSE = 0.5 V, fPWM < 50KHz (unless
noted otherwise)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Operating, IOUT = ±500 mA
6
–
20
V
During Sleep Mode
0
20
V
VOUT = VBB
–
<1.0
20
µA
VOUT = 0 V
–
<–1.0
-20
µA
Source Driver, IOUT = -500 mA
–
1.2
1.35
Ω
Sink Driver, IOUT = 500 mA
–
.75
.9
Ω
Source Driver, IOUT = -500 mA; VBB=6V
1.3
1.5
Ω
Sink Driver, IOUT = 500 mA, VBB=6V
.85
1.0
Ω
Output Drivers
Load Supply Voltage Range
Output Leakage Current
Output On Resistance
Body Diode Forward Voltage
Motor Supply Current
Logic Supply Current
VBB
IDSS
RDSON
VF
IBB
IDD
Source Diode, IF = -500 mA
–
1
–
V
Sink Diode, IF = 500mA
–
1
–
V
fPWM < 50 kHz
–
3.5
7
mA
Charge Pump On, Outputs Disabled
–
1.5
3
mA
Sleep Mode
–
–
10
uA
fPWM < 50 kHz
4.5
mA
Outputs Off
3.6
mA
10
µA
5.5
V
Sleep Mode (Inputs below .5V)
<1
Control Logic
Logic Supply Voltage Range
VDD
Logic Input Voltage
VIN(1)
Operating
2.85
VDD*.7
VIN(0)
Logic Input Current
3
–
V
–
VDD*.3
V
IIN(1)
VIN = VDD*.7
-20
<1.0
20
µA
IIN(0)
VIN = VDD*.3
-20
<1.0
20
µA
3965 DMOS Dual Full Bridge
PWM Motor Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 20V, VDD = 3.0 V, VSENSE = 0.5 V (unless noted otherwise)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
-1
0
1
µA
Control Logic
Reference Input Current
IREF
VREF input voltage range
VREF
Reference Divider Ratio
GM Error
Propagation Delay
VREF = VDD
0
VREF/VS
6
VERR
VREF = 1.5V
-5
5
%
(Note 3)
VREF = .5V
-10
10
%
tPD
PWM CHANGE TO SOURCE OFF
–
150
–
ns
PWM CHANGE TO SINK OFF
–
150
–
ns
PWM CHANGE TO SOURCE ON
–
1000
–
ns
PWM CHANGE TO SINK ON
–
1000
–
ns
DISABLE TO SOURCE ON
–
200
–
ns
DISABLE TO SINK ON
–
200
–
ns
300
850
1200
ns
tCOD
PWM RC Frequency
Blank Time
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
fOSC
R = 1000pf, C = 20K
tBLANK
R = 1000pf, C = 20K
Khz
TJ
–
165
∆TJ
–
15
–
°C
2.5
2.8
V
0.10
–
V
Rising VDD
Typical Data is for design information only.
Negative current is defined as coming out of (sourcing) the specified device pin.
VERR =((VREF/6) – VSENSE)/(VREF/6)
0.05
1.6
µs
1.21
UVLO Hysteresis
4
47.4
.8
UVLO Enable Threshold
NOTES: 1.
2.
3.
VDD- .1
°C
3965 DMOS Dual Full Bridge
PWM Motor Driver
Functional Description
Sleep Mode. The input pin SLEEP is dedicated to put the
device into a minimum current draw mode. All circuits are
disabled including the VDD undervoltage monitor.
Fixed Frequency PWM. Selection of an external RC
sets the oscillator frequency as follows:
Shutdown. In the event of a fault due to excessive
junction temperature, or low voltage on VCP or VREG, the
outputs of the device are disabled until the fault condition is
removed. At power up, and in the event of low VDD, the
UVLO circuit disables the drivers
Blank Time. When a source driver turns on, a current
spike occurs due to the reverse recovery currents of the
clamp diodes and/or switching transients related to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source enable latch, the
sense comparator is blanked. The blank duration is
determined by the time it takes to charge the external RC
.38*VDD volts with a 1mA current source.
Current Regulation. Load current is regulated by a
fixed frequency PWM control circuit. When the outputs of
the DMOS H-bridge are turned on, current increases in the
motor winding until it reaches a value given by:
ITRIP = VREF/(6*RSENSE)
At the trip point, the sense comparator resets the source
enable latch, turning off the source. At this point, load
inductance causes the current to recirculate until the end
fixed frequency cycle. (see timing diagram)
VREF. The VREF voltage is divided down by 6 and
compared to the voltage across the sense resistor to set the
value of bridge current that will trip the PWM comparator.
The VREF input is a high impedance input and can be
connected to VDD, if desired, as well as via resistor divider.
Note: When connected to VDD, the VBB voltage must be 1.8V
greater than VDD to allow proper headroom for the buffer
output.
fOSC = 1/ ( 850ns + tBLANK+RTCT))
tBLANK = CT*.38*VDD/ ( 1mA – ( .41*VDD/RT))
VREG. This supply voltage is used to run the sink side
DMOS outputs. VREG is internally monitored and in the
case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22
µF capacitor to ground.
Charge Pump. The Charge Pump is used to generate a
supply above VBB to drive the source side DMOS gates. A
0.22 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.22 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP Voltage is internally monitored and
in the case of a fault condition the outputs of the device are
disabled.
Thermal protection. Circuitry turns OFF all drivers
when the junction temperature reaches 165°C typically. It is
intended only to protect the device from failures due to
excessive junction temperatures and should not imply that
output short circuits are permitted. Thermal shutdown has a
hysteresis of approximately 15°C.
5
3965 DMOS Dual Full Bridge
PWM Motor Driver
Control Logic
Phase
Enable
Sleep
X
X
0
0
1
1
X
1
0
0
0
0
0
1
1
1
1
1
Chopping
(Vs>VREF/6)
X
X
0
1
0
1
OUTA
OUTB
Function
Off
Off
L
L
H
L
Off
Off
H
L
L
L
Sleep
Fast Decay
Forward
Slow Decay Chop
Reverse
Slow Decay Chop
Typical PWM Waveforms (Phase = 1)
RC
BLANK1
OUT1A
IOUT1
VSENSE1
BLANK2
OUT2A
IOUT2
VSENSE2
6
3965 DMOS Dual Full Bridge
PWM Motor Driver
Terminal List
Pin Name
VREG
RC
SLEEP
VDD
OUT1B
GND
SENSE1
OUT1A
ENABLE1
PHASE1
REF1
REF2
PHASE2
ENABLE2
OUT2B
SENSE2
GND
OUT2A
VCP
CP2
CP1
VBB
7
Pin Description
Regulator decoupling Terminal
Analog Input for fixed frequency
Logic input for SLEEP mode
Logic Supply Voltage
DMOS H – Bridge 1 Output B
Ground
Sense Resistor Terminal for Bridge 2
DMOS H – Bridge 1 Output A
Logic Input for Bridge 1 Enable Control
Logic Input for Bridge 1 PHASE Control
Gm Reference Input Voltage Bridge 2
Gm Reference Input Voltage Bridge 1
Logic Input for Bridge 2 PHASE Control
Logic Input for Bridge 2 Enable Control
DMOS H – Bridge 2 Output B
Sense Resistor Terminal for Bridge 1
Ground
DMOS H – Bridge 2 Output A
Reservoir Capacitor Terminal
Charge Pump Capacitor Terminal
Charge Pump Capacitor Terminal
Load Supply
SOIC 24
1
2
3
4
5
6,7
8
9
10
11
12
13
14
15
16
17
18,19
20
21
22
23
24
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