Power Tool Controller 8-Bit Flash MCU HT45F3630 Revision: V1.00 Date: �������������� March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Table of Contents Features................................................................................................................. 6 CPU Features...............................................................................................................................6 Peripheral Features.......................................................................................................................6 General Description.............................................................................................. 7 Block Diagram....................................................................................................... 7 Pin Assignment..................................................................................................... 8 Pin Description..................................................................................................... 8 Absolute Maximum Ratings............................................................................... 10 D.C. Characteristics............................................................................................ 10 A.C. Characteristics............................................................................................ 11 HIRC Characteristics.......................................................................................... 12 I2C A.C. Characteristics...................................................................................... 12 A/D Converter Electrical Characteristics.......................................................... 12 LVD/LVR Electrical Characteristics................................................................... 13 Reference Voltage Characteristics.................................................................... 13 Over Current Protection Electrical Characteristics......................................... 14 High Voltage Output Characteristics................................................................ 15 Power-on Reset Characteristics........................................................................ 15 System Architecture........................................................................................... 16 Clocking and Pipelining...............................................................................................................16 Program Counter.........................................................................................................................17 Stack...........................................................................................................................................18 Arithmetic and Logic Unit – ALU.................................................................................................18 Flash Program Memory...................................................................................... 19 Structure......................................................................................................................................19 Special Vectors...........................................................................................................................19 Look-up Table .............................................................................................................................19 Table Program Example..............................................................................................................20 In Circuit Programming – ICP.....................................................................................................21 On Chip Debug Support – OCDS...............................................................................................22 Data Memory....................................................................................................... 22 Structure .....................................................................................................................................22 General Purpose Data Memory..................................................................................................23 Special Purpose Data Memory...................................................................................................23 Rev. 1.00 2 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Special Function Register Description............................................................. 24 Indirect Addressing Registers – IAR0, IAR1, IAR2.....................................................................24 Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H...............................................................24 Accumulator – ACC ....................................................................................................................25 Program Counter Low Register – PCL .......................................................................................26 Look-up Table Registers – TBLP, TBHP, TBLH ..........................................................................26 Status Register – STATUS .........................................................................................................26 EEPROM Data Memory....................................................................................... 28 EEPROM Data Memory Structure..............................................................................................28 EEPROM Registers....................................................................................................................28 Reading Data from the EEPROM...............................................................................................30 Writing Data to the EEPROM......................................................................................................30 Write Protection...........................................................................................................................30 EEPROM Interrupt......................................................................................................................30 Programming Considerations......................................................................................................31 Oscillators........................................................................................................... 32 Oscillator Overview ....................................................................................................................32 System Clock Configurations......................................................................................................32 Internal RC Oscillator – HIRC.....................................................................................................33 Internal 32kHz Oscillator – LIRC ................................................................................................33 Operating Modes and System Clocks.............................................................. 33 System Clocks............................................................................................................................33 System Operation Modes ...........................................................................................................34 Control Register..........................................................................................................................36 Operating Mode Switching .........................................................................................................37 Standby Current Considerations ................................................................................................41 Wake-up .....................................................................................................................................41 Watchdog Timer.................................................................................................. 42 Watchdog Timer Clock Source....................................................................................................42 Watchdog Timer Control Register...............................................................................................42 Watchdog Timer Operation.........................................................................................................43 Reset and Initialisation ...................................................................................... 44 Reset Functions..........................................................................................................................44 Reset Initial Conditions ..............................................................................................................46 Input/Output Ports ............................................................................................. 49 Pull-high Resistors......................................................................................................................49 Port A Wake-up...........................................................................................................................50 I/O Port Control Registers...........................................................................................................50 I/O Port Source Current Control..................................................................................................51 Pin-shared Functions..................................................................................................................52 I/O Pin Structures........................................................................................................................54 Programming Considerations .....................................................................................................55 Rev. 1.00 3 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Timer Modules – TM........................................................................................... 55 Introduction.................................................................................................................................55 TM Operation..............................................................................................................................55 TM Clock Source.........................................................................................................................56 TM Interrupts...............................................................................................................................56 TM External Pins ........................................................................................................................56 TM Input/Output Pin Selection....................................................................................................56 Programming Considerations......................................................................................................57 Periodic Type TM – PTM .................................................................................... 58 Periodic TM Operation ...............................................................................................................58 Periodic Type TM Register Description ......................................................................................58 Periodic Type TM Operating Modes ...........................................................................................63 Analog to Digital Converter .............................................................................. 72 A/D Converter Overview.............................................................................................................72 A/D Converter Register Description............................................................................................73 A/D Converter Data Registers – SADOL, SADOH......................................................................73 A/D Converter Control Registers – SADC0, SADC1...................................................................73 A/D Converter Operation ............................................................................................................76 A/D Converter Reference Voltage...............................................................................................77 A/D Converter Input Signals........................................................................................................77 Conversion Rate and Timing Diagram........................................................................................78 Summary of A/D Conversion Steps ............................................................................................78 Programming Considerations......................................................................................................79 A/D Conversion Function............................................................................................................80 A/D Conversion Programming Examples....................................................................................80 Over Current Protection..................................................................................... 82 Over Current Protection Operation.............................................................................................82 Over Current Protection Control Registers.................................................................................83 Input Voltage Range....................................................................................................................86 Offset Calibration........................................................................................................................86 High Voltage Output........................................................................................... 87 Functional Description.................................................................................................................88 Protection Mechanism.................................................................................................................88 Control Registers........................................................................................................................88 I2C Interface......................................................................................................... 89 I2C Interface Operation ...............................................................................................................89 I2C Registers...............................................................................................................................91 I2C Bus Communication .............................................................................................................94 I2C Bus Start Signal ....................................................................................................................95 Slave Address ............................................................................................................................95 I2C Bus Read/Write Signal .........................................................................................................95 I2C Bus Slave Address Acknowledge Signal ..............................................................................95 I2C Bus Data and Acknowledge Signal ......................................................................................96 I2C Time-out Control....................................................................................................................97 Rev. 1.00 4 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Interrupts............................................................................................................. 98 Interrupt Registers.......................................................................................................................98 Interrupt Operation....................................................................................................................103 External Interrupt.......................................................................................................................104 Over Current Protection Interrupt..............................................................................................105 Time Base Interrupts.................................................................................................................105 I2C Interrupt...............................................................................................................................107 A/D Converter Interrupt.............................................................................................................107 LVD Interrupt.............................................................................................................................107 EEPROM Interrupt....................................................................................................................107 Multi-function Interrupt..............................................................................................................108 TM Interrupts.............................................................................................................................108 Interrupt Wake-up Function.......................................................................................................108 Programming Considerations....................................................................................................109 Low Voltage Detector – LVD............................................................................ 110 LVD Register............................................................................................................................. 110 LVD Operation........................................................................................................................... 111 Application Circuits.......................................................................................... 112 Instruction Set................................................................................................... 113 Introduction............................................................................................................................... 113 Instruction Timing...................................................................................................................... 113 Moving and Transferring Data................................................................................................... 113 Arithmetic Operations................................................................................................................ 113 Logical and Rotate Operation................................................................................................... 114 Branches and Control Transfer................................................................................................. 114 Bit Operations........................................................................................................................... 114 Table Read Operations............................................................................................................. 114 Other Operations....................................................................................................................... 114 Instruction Set Summary................................................................................. 115 Table Conventions..................................................................................................................... 115 Extended Instruction Set........................................................................................................... 117 Instruction Definition........................................................................................ 119 Extended Instruction Definition.................................................................................................128 Package Information........................................................................................ 135 16-pin SSOP (150mil) Outline Dimensions...............................................................................136 Rev. 1.00 5 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Features CPU Features • Operating voltage ♦♦ VCC: 12V (Maximum) ♦♦ fSYS=8MHz: 2.2V~5.5V • Up to 0.5μs instruction cycle with 8MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillator type ♦♦ Internal High Speed RC – HIRC ♦♦ Internal Low Speed 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 8MHz oscillator requires no external components • All instructions executed in 1~3 instruction cycles • Table read instructions • 115 powerful instructions • 6-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 2K×16 • RAM Data Memory: 64×8 • EEPROM Memory: 32×8 • Watchdog Timer function • 12 bidirectional I/O lines • Programmable I/O port source current for LED applications • Dual pin-shared external interrupts • Over Current Protection (OCP) function with interrupt • High Voltage Output (HVO) function • Level shift function • Multiple Timer Modules for time measure, input capture, compare match output, PWM output or single pulse output function • Dual Time-Base functions for generation of fixed time interrupt signals • 8-channel 12-bit resolution A/D converter • I2C Interface • Low voltage reset function • Low voltage detect function • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years • Package type: 16-pin SSOP Rev. 1.00 6 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU General Description The device is a Flash Memory A/D type 8-bit high performance RISC architecture microcontroller with a high voltage driver of up to 12V, which is specifically designed for power tool controller applications. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter, an over current protection function and a level shift function. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Easy communication with the outside world is provided using the internal fully integrated I2C interface, this popular interface which provides designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of various internal high and low oscillator functions is provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. This device contains a programmable I/O port source current function which is used to implement LED driving function. Also the inclusion of flexible I/O programming features, Time-Base functions along with many other features further enhance device functionality and flexibility for wide range of application possibilities. Block Diagram Low Voltage Dete�t Flas�/EEPRO� P�og�amming Ci��uit�y (OCDS/ICP) EEPRO� Data �emo�y Flas� P�og�am �emo�y Wat��dog Time� Low Voltage Dete�t RA� Data �emo�y Time Bases Reset Ci��uit 8-bit RISC �CU Co�e Inte��upt Cont�olle� Inte�nal RC Os�illato�s 1�-bit A/D Conve�te� I�C VCC Time� �odules Level S�ift Ove� Cu��ent P�ote�tion I/O HVO Rev. 1.00 7 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Pin Assignment PB0/INT1/PTP1 1 1� PA7/AN7/PTP1I PB1/PTP1B � 15 PA�/AN�/PTCK1 PB�/SDA � 14 PA5/AN5 PB�/SCL 4 1� PA4/AN4/INT0 HVO 5 1� PA�/VREF/AN� VCC � 11 PA�/ICPCK/PTP0I/AN�/OCDSCK VSS/AVSS/VSSH 7 10 PA1/OCPI/PTCK0/PTP0B/AN1 VDD/AVDD 8 9 PA0/ICPDA/PTP0/AN0/OCDSDA HT45F3630/HT45V3630 16 SSOP-A Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, the desired pin-shared function is determined by the corresponding software control bits. 2. The OCDSDA and OCDSCK pins are supplied for the OCDS dedicated pins and as such only available for the HT45V3630 device which is the OCDS EV chip for the HT45F3630 device. Pin Description With the exception of the power pins and some relevant transformer control pins, all pins on the device can be referenced by their Port name, e.g. PA0, PA1 etc., which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Pin Name PA0/ICPDA/PTP0/ AN0/OCDSDA PA1/OCPI/PTCK0/ PTP0B/AN1 PA2/OCDSCK/ ICPCK/PTP0I/AN2 PA3/VREF/AN3 Rev. 1.00 Function OPT I/T O/T PA0 PAPU PAWU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. ICPDA — ST CMOS ICP address/data PTP0 PAS0 — CMOS PTM0 output AN0 PAS0 AN OCDSDA — ST CMOS OCDS address/data - for EV chip only. PA1 PAPU PAWU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — Descriptions ADC input channel 0 OCPI PAS0 AN — OCP input PTCK0 PAS0 ST — PTM0 clock input PTP0B PAS0 — AN1 PAS0 AN PA2 PAPU PAWU PAS0 ST OCDSCK — ST CMOS PTM0 inverting output — ADC input channel 1 CMOS General purpose I/O. Register enabled pull-up and wake-up. — OCDS clock - for EV chip only. ICPCK — ST — ICP clock PTP0I PAS0 ST — PTM0 capture input AN2 PAS0 AN — ADC input channel 2 PA3 PAPU PAWU PAS0 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. VREF PAS0 AN — ADC and OCP (DAC) reference voltage input AN3 PAS0 AN — ADC input channel 3 8 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Pin Name PA4/AN4/INT0 PA5/AN5 PA6/AN6/PTCK1 Function OPT I/T O/T Descriptions PA4 PAPU PAWU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. up. AN4 PAS1 AN — ADC input channel 4 INT0 PAS1 INTEG INTC0 ST — External Interrupt 0 input PA5 PAPU PAWU PAS1 ST AN5 PAS1 AN PA6 PAPU PAWU PAS1 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. — ADC input channel 5 CMOS General purpose I/O. Register enabled pull-up and wake-up. AN6 PAS1 AN — ADC input channel 6 PTCK1 PAS1 ST — PTM1 clock input PA7 PAPU PAWU PAS1 ST AN7 PAS1 AN — ADC input channel 7 PTP1I PAS1 ST — PTM1 capture input PB0 PBPU PBS0 ST INT1 PBS0 INTEG INTC0 ST PTP1 PBS0 — CMOS PTM1 output PB1 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. PTP1B PBS0 — CMOS PTM1 inverting output PB2 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. SDA PBS0 ST NMOS I2C data line PB3 PBPU PBS0 ST CMOS General purpose I/O. Register enabled pull-up. SCL PBS0 ST NMOS I2C clock line HVO HVO — — VCC VCC — PWR — Level shift positive power input PA7/AN7/PTP1I PB0/INT1/PTP1 PB1/PTP1B PB2/SDA PB3/SCL VDD/AVDD* VSS/AVSS/VSSH** CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS General purpose I/O. Register enabled pull-up. — External Interrupt 1 input PWR Level shift output VDD — PWR — Digital positive power supply AVDD — PWR — Analog positive power supply VSS — PWR — Digital negative power supply AVSS — PWR — Analog negative power supply VSSH — PWR — High voltage device negative power supply Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt Trigger input; CMOS: CMOS output; NMOS: NMOS output; AN: Analog signal; *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin and VSSH is the high voltage device ground pin. The AVSS pin and VSSH pin are bonded together internally with VSS. Rev. 1.00 9 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Absolute Maximum Ratings Supply Voltage for VCC. ....................................................................................................... VDD to 12V Supply Voltage for VDD.......................................................................................VSS-0.3V to VSS +6.0V Input Voltage......................................................................................................VSS-0.3V to VDD +0.3V Storage Temperature.......................................................................................................-50°C to 125°C Operating Temperature..................................................................................................... -40°C to 85°C IOL Total......................................................................................................................................... 80mA IOH Total........................................................................................................................................ -80mA Total Power Dissipation............................................................................................................. 500mW Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Symbol Parameter Test Conditions Conditions VDD Min. Typ. Max. Unit V VDD Operating Voltage (HIRC) — fSYS=fHIRC=8MHz 2.2 — 5.5 VDD Operating Voltage (LIRC) — fSYS=fLIRC=32kHz 2.2 — 5.5 V Operating Current (HIRC) 3V No load, all peripherals off, 5V fSYS=fHIRC=8MHz — 0.8 1.2 mA — 1.6 2.4 mA Operating Current (LIRC) 3V No load, all peripherals off, 5V fSYS=fLIRC=32kHz — 10 20 μA — 30 50 μA IDD ISTB IOH Rev. 1.00 3V Standby Current (SLEEP Mode) 5V Standby Current (SLEEP Mode) 5V 3V 3V No load, all peripherals off, WDT off No load, all peripherals off, WDT on Standby Current (IDLE0 Mode) 5V Standby Current (IDLE1 Mode, HIRC) 3V No load, all peripherals off, fSUB on, 5V fSYS=fHIRC=8MHz No load, all peripherals off, fSUB on — 0.2 0.8 μA — 0.5 1 μA — 1.5 3 μA — 3 5 μA — 3 5 μA — 5 10 μA — 360 500 μA — 600 800 μA VOH=0.9VDD, SLEDC[m+1, m]=00B 3V (m=0 or 2 or 4) -0.7 1.5 — mA 5V VOH=0.9VDD, SLEDC[m+1, m]=00B (m=0 or 2 or 4) -1.5 2.9 — mA 3V VOH=0.9VDD, SLEDC[m+1, m]=01B (m=0 or 2 or 4) -1.3 2.5 — mA 5V VOH=0.9VDD, SLEDC[m+1, m]=01B (m=0 or 2 or 4) -2.5 5.1 — mA 3V VOH=0.9VDD, SLEDC[m+1, m]=10B (m=0 or 2 or 4) -1.8 3.6 — mA 5V VOH=0.9VDD, SLEDC[m+1, m]=10B (m=0 or 2 or 4) -3.6 7.3 — mA 3V VOH=0.9VDD, SLEDC[m+1, m]=11B (m=0 or 2 or 4) -4.0 8 — mA 5V VOH=0.9VDD, SLEDC[m+1, m]=11B (m=0 or 2 or 4) -8.0 16 — mA Source Current for I/O Ports 10 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Symbol VIL Parameter Input Low Voltage for I/O Ports VIH Input High Voltage for I/O Ports IOL Sink Current for I/O Port RPH Pull-high Resistance for I/O Ports ILEAK Input Leakage Current VOH Output High Voltage for I/O Ports VOL Output Low Voltage for I/O Ports Test Conditions Min. Typ. Max. Unit — 0 — 0 — 1.5 V — 0.2VDD 5V — V 3.5 — 5 — — V 0.8VDD — VDD V 3V VOL=0.1VDD 16 32 — mA 5V VOL=0.1VDD 32 64 — mA VDD Conditions 5V — 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ 5V VIN=VDD or VIN=VSS — — ±1 μA 3V IOH=-5.5mA 2.7 — — V 5V IOH=-11mA 4.5 — — V 3V IOL=16mA — — 0.3 V 5V IOL=32mA — — 0.5 V A.C. Characteristics Ta=25°C Symbol Test Conditions Parameter VDD 2.2V~ fSYS=fLIRC=32kHz 5.5V fSYS System Clock (LIRC) fLIRC Low Speed Internal RC Oscillator (LIRC) — tRSTD System Reset Delay Time (Power-on Reset, LVR Hardware Reset, LVR Software Reset, WDT Software Reset) System Reset Delay Time (WDT Time-Out Hardware Cold Reset) — System Start-up Timer Period (Wake-up from Power Down Mode and fSYS off) tSST Conditions System Start-Up Timer Period (Slow Mode ↔ Normal Mode) System Start-Up Timer Period (Wake-Up From Power Down Mode and fSYS on) Min. Typ. Max. Unit — 32 — kHz 3V Ta=25°C -10% 32 +10% kHz 5V Ta=25°C -10% 32 +10% kHz — 25 50 100 ms — 8.3 16.7 33.3 ms — fSYS=fHIRC~fHIRC/64 16 — — tHIRC — fSYS=fLIRC 2 — — tLIRC — fHIRC off → on (HIRCF=1) 16 — — tHIRC — fSYS=fHIRC~fHIRC/64 2 — — tHIRC — fSYS=fLIRC 2 — — tLIRC 0 — — tH System Start-Up Timer Period (WDT Time-out Hardware Cold Reset) — — tINT External Interrupt Minimum Pulse Width — — 10 — — μs tTCK PTCKn Input Pin Minimum Pulse Width — — 0.3 — — μs tTPI PTPnI Input Pin Minimum Pulse Width — — 0.3 — — μs tEERD EEPROM read time — — — — 4 tSYS tEEWR EEPROM write time — — — 2 4 ms Rev. 1.00 11 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU HIRC Characteristics Symbol fHIRC Frequency Accuracy Trimmed at VDD=3V Test Conditions Parameter VDD High Speed Internal RC Oscillator (HIRC) Conditions Min. Typ. Max. Unit 3V Ta=25°C -2% 8 +2% MHz 3V Ta=0°C ~ 70°C -5% 8 +5% MHz 2.2V~5.5V Ta=0°C ~ 70°C -7% 8 +7% MHz 2.2V~5.5V Ta=-40°C ~ 85°C -10% 8 +10% MHz Frequency Accuracy Trimmed at VDD=5V Symbol fHIRC Test Conditions Parameter VDD High Speed Internal RC Oscillator (HIRC) Conditions Min. Typ. Max. Unit 5V Ta=25°C -2% 8 +2% MHz 5V Ta=0°C ~ 70°C -5% 8 +5% MHz 2.2V~5.5V Ta=0°C ~ 70°C -7% 8 +7% MHz 2.2V~5.5V Ta=-40°C ~ 85°C -10% 8 +10% MHz I2C A.C. Characteristics Symbol Parameter I2C Standard Mode (100kHz) fSYS Frequency fI2C I2C Fast Mode (400kHz) fSYS Frequency Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. — No clock debounce 2 — — MHz — 2 system clock debounce 4 — — MHz — 4 system clock debounce 8 — — MHz — No clock debounce 5 — — MHz — 2 system clock debounce 10 — — MHz — 4 system clock debounce 20 — — MHz A/D Converter Electrical Characteristics Symbol Unit Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage — — 2.7 — 5.5 V VADI Input Voltage — — 0 — VREF V VREF Reference Voltage — 2 — VDD V — — ±3 LSB — — ±4 LSB — 1 2 mA DNL INL Differential Nonlinearity Integral Nonlinearity — 3V VREF=VDD, tADCK=0.5μs 5V VREF=VDD, tADCK=0.5μs 3V VREF=VDD, tADCK=10μs 5V VREF=VDD, tADCK=10μs 3V VREF=VDD, tADCK=0.5μs 5V VREF=VDD, tADCK=0.5μs 3V VREF=VDD, tADCK=10μs 5V VREF=VDD, tADCK=10μs 3V No load, tADCK=0.5μs 5V No load, tADCK=0.5μs IADC Additional Current for A/D Converter Enable — 1.5 3 mA tADCK Clock Period — — 0.5 — 10 μs tON2ST A/D Converter On-to-Start Time — — 4 — — μs tADS Sampling Time — — — 4 — tADCK tADC Conversion Time (Include A/D Sample and Hold Time) — — — 16 — tADCK Rev. 1.00 12 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LVD/LVR Electrical Characteristics Ta=25°C Symbol VLVR VLVD ILVRLVDBG tLVDS Parameter Low Voltage Reset Voltage Low Voltage Detection Voltage Operating Current Test Conditions Min. Typ. Max. Unit Conditions VDD — LVR enable, voltage select 2.1V -5% — LVR enable, voltage select 2.55V -5% 2.55 +5% 2.1 +5% — LVR enable, voltage select 3.15V -5% 3.15 +5% V — LVR enable, voltage select 3.8V -5% 3.8 +5% — LVD enable, voltage select 2.0V -5% 2.0 +5% — LVD enable, voltage select 2.2V -5% 2.2 +5% — LVD enable, voltage select 2.4V -5% 2.4 +5% — LVD enable, voltage select 2.7V -5% 2.7 +5% — LVD enable, voltage select 3.0V -5% 3.0 +5% — LVD enable, voltage select 3.3V -5% 3.3 +5% — LVD enable, voltage select 3.6V -5% 3.6 +5% — LVD enable, voltage select 4.0V -5% 4.0 +5% 3V LVD enable, LVR enable, VBGEN=0 — — 15 μA 5V LVD enable, LVR enable, VBGEN=0 — 20 25 μA 3V LVD enable, LVR enable, VBGEN=1 — — 150 μA 5V LVD enable, LVR enable, VBGEN=1 — 180 200 μA V — For LVR enable, VBGEN=0, LVD off → on — — 15 μs — For LVR disable, VBGEN=0, LVD off → on — — 150 μs LVDO Stable Time ILVR Additional Current for LVR Enable — LVD disable, VBGEN=0 — — TBD μA ILVD Additional Current for LVD Enable — LVR disable, VBGEN=0 — — TBD μA Reference Voltage Characteristics Ta=25°C Symbol Parameter Test Conditions VDD Conditions — Min. Typ. Max. Unit VBG Bandgap Reference Voltage — -5% 1.04 +5% V tBGS VBG Turn On Stable Time — No load — — 150 μs IBG Additional Current for Bandgap Reference Enable — LVR disable, LVD disable — — TBD μA Note: The VBG voltage is used as the A/D converter internal signal input. Rev. 1.00 13 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Over Current Protection Electrical Characteristics Ta=25°C Symbol IOCP VOS_CMP VHYS VCM_CMP VOS_OPA VCM_OPA VOR Ga DNL INL Rev. 1.00 Parameter Test Conditions Hysteresis Comparator Common Mode Voltage Range OPA Input Offset Voltage OPA Common Mode Voltage Range OPA Maximum Output Voltage Range PGA Gain Accuracy Differential Nonlinearity Integral Nonlinearity Min. Typ. Max. Unit 3V OCPEN[1:0]=01B, DAC VREF=2.5V — — 625 μA 5V OCPEN[1:0]=01B, DAC VREF=2.5V — 730 1250 μA 3V Without calibration (OCPCOF[4:0]=10000B) -15 — 15 mV 5V Without calibration (OCPCOF[4:0]=10000B) -15 — 15 mV mV Operating Current Comparator Input Offset Voltage Conditions VDD 3V With calibration -4 — 4 5V With calibration -4 — 4 mV 3V — 20 40 60 mV 5V — 20 40 60 mV 3V — VSS — VDD-1.4 V 5V — VSS — VDD-1.4 V 3V Without calibration (OCPOOF[5:0]=100000B) -15 — 15 mV 5V Without calibration (OCPOOF[5:0]=100000B) -15 — 15 mV 3V With calibration -4 — 4 mV 5V With calibration -4 — 4 mV 3V — VSS — VDD-1.4 V 5V — VSS — VDD-1.4 V 3V — VSS+0.1 — VDD-0.1 V 5V — VSS+0.1 — VDD-0.1 V -5 — 5 % 3V All gain 5V All gain -5 — 5 % 3V DAC VREF=VDD — — ±1 LSB 5V DAC VREF=VDD — — ±1 LSB 3V DAC VREF=VDD — — ±1.5 LSB 5V DAC VREF=VDD — — ±1.5 LSB 14 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU High Voltage Output Characteristics Ta=25°C Symbol Test Conditions Parameter Min. Conditions VDD — Typ. Max. Unit VIN Input Voltage — VDD — 12 V IOH Source Current for HVO Pin — VOH=0.9 × VIN, VIN=10V -100 — — mA IOL Sink Current for HVO Pin — VOL=0.1 × VIN, VIN=10V 100 — — mA tR HVO Output Rising Time — VIN=10V — — 0.5 μs tF HVO Output Falling Time — VIN=10V — — 0.5 μs Power-on Reset Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Raising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms tPOR RRPOR VDD VPOR Rev. 1.00 15 Time March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of the device take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one or two cycles for most of the standard or extended instructions respectively. The exceptions to this are branch or call instructions which need one more cycle. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. Os�illato� Clo�k (System Clo�k) P�ase Clo�k T1 P�ase Clo�k T� P�ase Clo�k T� P�ase Clo�k T4 P�og�am Counte� Pipelining PC PC+1 PC+� Fet�� Inst. (PC) Exe�ute Inst. (PC-1) Fet�� Inst. (PC+1) Exe�ute Inst. (PC) Fet�� Inst. (PC+�) Exe�ute Inst. (PC+1) System Clocking and Pipelining Rev. 1.00 16 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. 1 �OV A�[1�H] � CALL DELAY � CPL [1�H] 4 : 5 : � DELAY: NOP Fet�� Inst. 1 Exe�ute Inst. 1 Fet�� Inst. � Exe�ute Inst. � Fet�� Inst. � Flus� Pipeline Fet�� Inst. � Exe�ute Inst. � Fet�� Inst. 7 Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demands a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High Byte PCL Register PC10~PC8 PCL7~PCL0 Program Counter The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly; however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.00 17 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 6 levels and neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P�og�am Counte� Top of Sta�k Sta�k Level 1 Sta�k Level � Sta�k Pointe� Sta�k Level � Bottom of Sta�k Sta�k Level � : : : P�og�am �emo�y Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA, LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA, LAND, LANDM, LOR, LORM, LXOR, LXORM, LCPL, LCPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC, LRR, LRRA, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC • Increment and Decrement INCA, INC, DECA, DEC, LINCA, LINC, LDECA, LDEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI, LSNZ, LSZ, LSZA, LSIZ, LSIZ, LSDZ, LSDZA Rev. 1.00 18 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 2K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. 0000H 0004H 00�CH 07FFH Reset Inte��upt Ve�to�s 1� bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the corresponding table read instruction such as “TABRD [m]” or “TABRDL [m]” respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors, the data can be retrieved from the program memory using the corresponding extended table read instruction such as “LTABRD [m]” or “LTABRDL [m]” respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Rev. 1.00 19 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU The accompanying diagram illustrates the addressing data flow of the look-up table. P�og�am �emo�y Add�ess Last Page o� TBHP Registe� TBLP Registe� Data 1� bits Registe� TBLH Use� Sele�ted Registe� Hig� Byte Low Byte Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “0700H” which refers to the start address of the last page within the 2K Program Memory of the microcontroller. The table pointer low byte register is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “0706H” or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address specified by TBLP and TBHP if the “TABRD [m]” or “LTABRD [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRD [m]” or “LTABRD [m]” instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or the page that tbhp pointed mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “0706H” transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “0705H” transferred to ; tempreg2 and TBLH in this example the data “1AH” is ; transferred to tempreg1 and data “0FH” to register tempreg2 : : org 0700h ; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.00 20 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU In Circuit Programming – ICP The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Programming Serial Data/Address ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM Data Memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, taking control of the ICPDA and ICPCK pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W�ite� Conne�to� Signals �CU P�og�amming Pins W�ite�_VDD VDD ICPDA PA0 ICPCK PA� W�ite�_VSS VSS * * To ot�e� Ci��uit Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. Rev. 1.00 21 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU On Chip Debug Support – OCDS There is an EV chip named HT45V3630 which is used to emulate the HT45F3630 device. The EV chip device also provides an “On-Chip Debug” function to debug the real MCU device during the development process. The EV chip and the real MCU device are almost functionally compatible except for “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output Pin Description OCDSCK OCDSCK On-Chip Debug Support Clock input VDD VDD Power Supply VSS VSS Ground Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Categorized into two types, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory is subdivided into several sectors, all of which are implemented in 8-bit wide RAM. Each of the Data Memory Sector is categorized into two types, the special Purpose Data Memory and the General Purpose Data Memory. The Special Purpose Data Memory registers are accessible in sector 0, with the exception of the EEC register at address 40H, which is only accessible in sector 1. Switching between the different Data Memory sectors is achieved by setting the Memory Pointers to the correct value. The start address of the Data Memory is the address 00H. Special Purpose Data Memory Sector: Address 0: 00H~7FH 1: 40H General Purpose Data Memory Capacity Sector: Address 64×8 0: 80H~BFH 00H Spe�ial Pu�pose Data �emo�y EEC at 40H in Se�to� 1 7FH 80H Gene�al Pu�pose Data �emo�y Se�to� 0 BFH Data Memory Structure Rev. 1.00 22 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU General Purpose Data Memory There are 64 bytes of general purpose data memory which are arranged in 80H~BFH of Sector 0. All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value “00H”. 00H Se�to� 0 IAR0 Se�to� 1 �9H Se�to� 0 IICC0 01H �P0 �AH IICC1 0�H IAR1 �BH IICD 0�H �P1L �CH IICA 04H �P1H �DH IICTOC 05H ACC �EH INTC0 0�H PCL �FH INTC1 07H TBLP �0H INTC� 08H TBLH �1H �FI0 09H TBHP ��H �FI1 0AH STATUS ��H PSCR IAR� �4H �5H TB0C TB1C 0DH �P�L ��H WDTC 0EH �P�H �7H PT�0C0 0FH RSTFC �8H PT�0C1 10H PB �9H PT�0DL 11H PBC �AH PT�0DH 1�H PBPU PBS0 �BH �CH PT�0AL PT�0AH 14H PA �DH PT�0RPL 15H PAC �EH PT�0RPH 1�H PAPU �FH 17H PAWU 40H 18H 19H PAS0 PAS1 41H 4�H EED 1AH SCC 4�H PT�1C0 PT�1C1 0BH 0CH 1�H Se�to� 1 EEC EEA 1BH HIRCC 44H 1CH SADOL 45H PT�1DL 1DH SADOH 4�H PT�1DH 1EH SADC0 47H PT�1AL 1FH �0H SADC1 SLEDC 48H 49H PT�1AH PT�1RPL �1H INTEG 4AH PT�1RPH ��H LVRC 4BH HVOC ��H LVDC 4CH HVOPC �4H OCPC0 4DH �5H ��H OCPC1 OCPDA �7H OCPOCAL �8H OCPCCAL 7FH : Unused� �ead as 00H Special Purpose Data Memory Rev. 1.00 23 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with the MP1L/MP1H register pair and IAR2 register together with the MP2L/MP2H register pair can access data from any Data Memory Sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers will return a result of “00H” and writing to the registers will result in no operation. Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L, MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example 1 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h ; setup size of block mov block, a mov a, offset adres1; Accumulator loaded with first RAM address mov mp0, a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: Rev. 1.00 24 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Indirect Addressing Program Example 2 data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a, 04h; setup size of block mov block, a mov a, 01h; setup the memory sector mov mp1h, a mov a, offset adres1 ; Accumulator loaded with first RAM address mov mp1l, a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1L inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Direct Addressing Program Example using extended instructions data .section ´data´ temp db ? code .section at 0 ´code´ org 00h start: lmov a, [m] ; move [m] data to acc lsub a, [m+1] ; compare [m] and [m+1] data snz c; [m]>[m+1]? jmp continue; no lmov a, [m] ; yes, exchange [m] and [m+1] data mov temp, a lmov a, [m+1] lmov [m], a mov a, temp lmov [m+1], a continue: Note: here “m” is a data memory address located in any data memory sectors. For example, m=1F0H, it indicates address 0F0H in Sector 1. Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Rev. 1.00 25 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the SC flag, CZ flag, zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. • CZ is the operational result of different flags for different instructions. Refer to register definitions for more details. • SC is the result of the “XOR” operation which is performed by the OV flag and the MSB of the current instruction operation result. Rev. 1.00 26 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR x x 0 0 x x x x “x” unknown Bit 7SC: XOR operation result - performed by the OV flag and the MSB of the instruction operation result. Bit 6CZ: Operational result of different flags for different instructions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.00 27 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU EEPROM Data Memory This device contains an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 32×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and a data register in Sector 0 and a single control register in Sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Sector 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Sector 1, can be read from or written to indirectly using the MP1L/MP1H or MP2L/MP2H Memory Pointer and Indirect Addressing Register, IAR1/IAR2. Because the EEC control register is located at address 40H in Sector 1, the MP1L or MP2L Memory Pointer must first be set to the value 40H and the MP1H or MP2H Memory Pointer high byte set to the value, 01H, before any operations on the EEC register are executed. Register Name Bit 7 6 5 4 3 2 1 0 EEA — — — EEA4 EEA3 EEA2 EEA1 EEA0 EED EED7 EED6 EED5 EED4 EED3 EED2 EED1 EED0 EEC — — — — WREN WR RDEN RD EEPROM Register List EEA Register Bit 7 6 5 4 3 2 1 0 Name — — — EEA4 EEA3 EEA2 EEA1 EEA0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as “0” Bit 4~0EEA4~EEA0: Data EEPROM address Data EEPROM address bit 4 ~ bit 0 Rev. 1.00 28 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU EED Register Bit 7 6 5 4 3 2 1 0 Name EED7 EED6 EED5 EED4 EED3 EED2 EED1 EED0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0EED7~EED0: Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD cannot be set high at the same time in one instruction. The WR and RD cannot be set high at the same time. Rev. 1.00 29 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register is located in Sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM interrupts are enabled and the stack is not full, a jump to the associated EEPROM Interrupt vector will take place. When the interrupt is serviced, the EEPROM interrupt request flag, DEF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. More details can be obtained in the Interrupt section. Rev. 1.00 30 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register, MP1H or MP2H, could be normally cleared to zero as this would inhibit access to Sector 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR MP1H MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.00 ; user defined address ; user defined data ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set WREN bit, enable write operations ; start Write Cycle - set WR bit — executed immediately ; after set WREN bit ; check for write cycle end ; disable EEPROM read/write 31 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Internal High Speed RC HIRC 8MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, one high speed oscillator and one low speed oscillator. The high speed oscillator is the internal 8MHz RC oscillator. The low speed oscillator is the internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected. The frequency of the slow speed or high speed system clock is also determined using CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. fH fH/� Hig� Speed Os�illato� HIRCEN fH/4 fH/8 HIRC IDLE0 SLEEP P�es�ale� fH/1� fSYS fH/�� fH/�4 Low Speed Os�illato� LIRC fLIRC fSUB IDLE� SLEEP CKS�~CKS0 fSUB fLIRC System Clock Configurations Rev. 1.00 32 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. It requires no external pins for its operation. Internal 32kHz Oscillator – LIRC The internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency fH or low frequency fSUB source, and is selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock can be sourced from the HIRC oscillator. The low speed system clock source can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Rev. 1.00 33 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU fH fH/� Hig� Speed Os�illato� HIRCEN fH/4 fH/8 HIRC IDLE0 SLEEP P�es�ale� fH/1� fSYS fH/�� fH/�4 Low Speed Os�illato� LIRC fLIRC CKS�~CKS0 fSUB IDLE� SLEEP fSUB fSYS fPSC fSYS/4 P�es�ale� Time Bases fSUB TB1[�:0] TB0[�:0] CLKSEL[1:0] fLIRC WDT fLIRC LVR Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator can be stopped to conserve the power or continue to oscillate to provide the clock source, fH ~ fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit. System Operation Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP, DLE0, IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU NORMAL SLOW Register Setting fSYS FHIDEN FSIDEN CKS2~CKS0 On x x 000~110 fH ~ fH/64 On x x 111 fSUB IDLE0 Off 0 1 IDLE1 Off 1 1 IDLE2 Off 1 0 SLEEP Off 0 0 000~110 Off 111 On xxx On 000~110 On 111 Off xxx Off fH fSUB On fLIRC On On On On Off On On On On On On Off On Off Off On/Off (1) On/Off (2) “x”: Don’t care Note: 1. The fH clock will be switched on or off by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock can be switched on or off which is controlled by the WDT function being enabled or disabled in the SLEEP mode. Rev. 1.00 34 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from the LIRC oscillator. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW mode, the fH clock will be switched on or off by configuring the corresponding oscillator enable bit HIRCEN. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. However the fLIRC clock can still continue to operate if the WDT function is enabled, the fLIRC clock will be stopped too, if the Watchdog Timer function is disabled. IDLE0 Mode The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions. IDLE1 Mode The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched off but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Rev. 1.00 35 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Control Register The registers, SCC and HIRCC, are used to control the system clock and the corresponding oscillator configurations. SCC Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — — — FHIDEN FSIDEN R/W R/W R/W R/W — — — R/W R/W POR 0 0 0 — — — 0 0 Bit 7~5CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4~2 Unimplemented, read as “0” Bit 1FHIDEN: High frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. Bit 0FSIDEN: Low frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively. If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. HIRCC Register Bit 7 6 5 Name — — R/W — — POR — — Bit 7~2 4 3 2 1 0 — — — — HIRCF HIRCEN — — — — R/W R/W — — — — 0 1 Unimplemented, read as “0” Bit 1HIRCF: HIRC oscillator stable flag 0: HIRC unstable 1: HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable. Bit 0HIRCEN: HIRC oscillator enable control 0: Disable 1: Enable Rev. 1.00 36 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register. NORMAL fSYS=fH~fH/�4 fH on CPU �un fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU �un fSYS on fH on/off SLEEP HALT inst�u�tion exe�uted CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off IDLE0 HALT inst�u�tion exe�uted CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE2 HALT inst�u�tion exe�uted CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off Rev. 1.00 37 IDLE1 HALT inst�u�tion exe�uted CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode CKS�~CKS0 = 111 SLOW Mode FHIDEN=0� FSIDEN=0 HALT inst�u�tion is exe�uted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT inst�u�tion is exe�uted IDLE2 Mode Rev. 1.00 38 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to “000”~“110” and then the system clock will respectively be switched to fH~ fH/64. However, if fH is not used in SLOW mode and thus switched off, it will take some time to reoscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HIRCF bit in the HIRCC register. The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. SLOW Mode CKS�~CKS0 = 000~110 NORMAL Mode FHIDEN=0� FSIDEN=0 HALT inst�u�tion is exe�uted SLEEP Mode FHIDEN=0� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE0 Mode FHIDEN=1� FSIDEN=1 HALT inst�u�tion is exe�uted IDLE1 Mode FHIDEN=1� FSIDEN=0 HALT inst�u�tion is exe�uted IDLE2 Mode Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT” instruction in the application program with both the FHIDEN and FSIDEN bit in SCC register equal to “0”. In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and stopped. Rev. 1.00 39 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in SCC register equal to “0” and the FSIDEN bit in SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be stopped and the application program will stop at the “HALT” instruction, but the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and stopped. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The fH and fSUB clocks will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and stopped. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the “HALT” instruction in the application program with the FHIDEN bit in the SCC register equal to “1” and the FSIDEN bit in the SCC register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The fH clock will be on but the fSUB clock will be off and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag PDF will be set, and WDT timeout flag TO will be cleared. • The WDT will be cleared and resume counting if the WDT function is enabled. If the WDT function is disabled, the WDT will be cleared and stopped. Rev. 1.00 40 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to the device which has different package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched off. However, when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow When the device executes the “HALT” instruction, the PDF flag will be set to 1. The PDF flag will be cleared to 0 if the device experiences a system power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT overflow, a Watchdog Timer reset will be initiated and the TO flag will be set to 1. The TO flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 41 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal clock, fLIRC, which is in turn supplied by the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable and reset MCU operation. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function software control 10101: Disable 01010: Enable Others: Reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after 2~3 fLIRC clock cycles and the WRF bit in the RSTFC register will be set high. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fLIRC 001: 210/fLIRC 010: 212/fLIRC 011: 214/fLIRC 100: 215/fLIRC 101: 216/fLIRC 110: 217/fLIRC 111: 218/fLIRC These three bits determine the division ratio of the watchdog timer source clock, which in turn determines the time-out period. Rev. 1.00 42 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LVRF LRF WRF R/W — — — — — R/W R/W R/W POR — — — — — x 0 0 “x” unknown Bit 7~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVR Control register software reset flag Described elsewhere. Bit 0WRF: WDT Control register software reset flag 0: Not occur 1: Occurred This bit is set high by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device after 2~3 fLIRC clock cycles. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B Disable 01010B Enable Any other values Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT. Rev. 1.00 43 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC Registe� WE4~WE0 bits Reset �CU CLR “CLR WDT” Inst�u�tion “HALT” Inst�u�tion LIRC fLIRC 8-stage Divide� fLIRC/�8 WS�~WS0 WDT P�es�ale� 8-to-1 �UX WDT Time-out Watchdog Timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally. Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all I/O ports will be first set to inputs. VDD Powe�-on Reset tRSTD SST Time-out Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart Rev. 1.00 44 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the RSTFC register will also be set high. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the LVD/LVR characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the LVS7~LVS0 bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise or software setting, the LVR will reset the device after 2~3 fLIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set high. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. LVR tRSTD + tSST Inte�nal Reset Note: tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: MCU reset (register is reset to POR value). When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after the low voltage condition keeps more than a tLVR time. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined LVR values above, will also result in the generation of an MCU reset. The reset operation will be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value. • RSTFC Register Bit 7 6 5 4 3 2 1 0 Name — — — — — LVRF LRF WRF R/W — — — — — R/W R/W R/W POR — — — — — x 0 0 “x” unknown Bit 7~3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set high when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Rev. 1.00 45 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Bit 1LRF: LVR Control register software reset flag 0: Not occur 1: Occurred This bit is set high if the LVRC register contains any non-defined LVR voltage register values. This in effect acts like a software-reset function. This bit can only be cleared to zero by the application program. Bit 0WRF: WDT Control register software reset flag Described elsewhere. Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as LVR reset except that the Watchdog time-out flag TO will be set high. WDT Time-out tRSTD + tSST Inte�nal Reset Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the A.C. Characteristics for tSST details. WDT Time-out tSST Inte�nal Reset WDT Time-out Reset during Sleep or IDLE Mode Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset Reset Conditions u u LVR reset during Normal or SLOW Mode operation 1 u WDT time-out reset during Normal or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.00 Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack 46 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Register Rev. 1.00 Power On Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) uuuu uuuu IAR0 0000 0000 0000 0000 MP0 0000 0000 0000 0000 uuuu uuuu IAR1 0000 0000 0000 0000 uuuu uuuu MP1L 0000 0000 0000 0000 uuuu uuuu MP1H 0000 0000 0000 0000 uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- -xxx ---- ---- STATUS xx00 xxxx xx1u uuuu u u 11 u u u u IAR2 0000 0000 0000 0000 uuuu uuuu MP2L 0000 0000 0000 0000 uuuu uuuu MP2H 0000 0000 0000 0000 uuuu uuuu RSTFC ---- -x00 ---- -uuu ---- -uuu -uuu -uuu PB - - - - 1111 - - - - 1111 ---- uuuu PBC - - - - 1111 - - - - 1111 ---- uuuu PBPU ---- 0000 ---- 0000 ---- uuuu PBS0 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 uuuu uuuu PAPU 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 uuuu uuuu PAS0 0000 0000 0000 0000 uuuu uuuu PAS1 0000 0000 0000 0000 uuuu uuuu SCC 000- --00 000- --00 uuu- --uu HIRCC ---- --01 ---- --01 ---- --uu SADOL (ADRFS=0) xxxx ---- xxxx ---- xxxx ---- SADOL (ADRFS=1) xxxx xxxx xxxx xxxx xxxx xxxx SADOH (ADRFS=0) xxxx xxxx xxxx xxxx uuuu uuuu SADOH (ADRFS=1) ---- xxxx ---- xxxx ---- uuuu SADC0 0000 0000 0000 0000 uuuu uuuu SADC1 0000 0000 0000 0000 uuuu uuuu SLEDC --00 0000 --00 0000 --uu uuuu INTEG ---- 0000 ---- 0000 ---- uuuu LVRC 0101 0101 0101 0101 uuuu uuuu LVDC --00 0000 --00 0000 --uu uuuu OCPC0 0000 ---0 0000 ---0 uuuu ---u OCPC1 --00 0000 --00 0000 --uu uuuu OCPDA 0000 0000 0000 0000 uuuu uuuu OCPOCAL 0010 0000 0010 0000 uuuu uuuu OCPCCAL 0001 0000 0001 0000 uuuu uuuu IICC0 ---- 000- ---- 000- ---- uuu- 47 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Register Power On Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) IICC1 1000 0001 1000 0001 uuuu uuuu IICD xxxx xxxx xxxx xxxx uuuu uuuu IICA 0000 000- 0000 000- uuuu uuu- IICTOC 0000 0000 0000 0000 uuuu uuuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 uuuu uuuu MFI0 --00 --00 --00 --00 --uu --uu MFI1 --00 --00 --00 --00 --uu --uu PSCR ---- --00 ---- --00 ---- --uu TB0C 0--- -000 0--- -000 u--- -uuu TB1C 0--- -000 0--- -000 u--- -uuu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu PTM0C0 0000 0--- 0000 0--- uuuu u--- PTM0C1 0000 0000 0000 0000 uuuu uuuu PTM0DL 0000 0000 0000 0000 uuuu uuuu PTM0DH ---- --00 ---- --00 ---- --uu PTM0AL 0000 0000 0000 0000 uuuu uuuu PTM0AH ---- --00 ---- --00 ---- --uu PTM0RPL 0000 0000 0000 0000 uuuu uuuu PTM0RPH ---- --00 ---- --00 ---- --uu PTM1C0 0000 0--- 0000 0--- uuuu u--- PTM1C1 0000 0000 0000 0000 uuuu uuuu EEA ---0 0000 ---0 0000 ---u uuuu EED 0000 0000 0000 0000 uuuu uuuu PTM1DL 0000 0000 0000 0000 uuuu uuuu PTM1DH ---- --00 ---- --00 ---- --uu PTM1AL 0000 0000 0000 0000 uuuu uuuu PTM1AH ---- --00 ---- --00 ---- --uu PTM1RPL 0000 0000 0000 0000 uuuu uuuu PTM1RPH ---- --00 ---- --00 ---- --uu HVOC ---- 0000 ---- 0000 ---- uuuu HVOPC ---- 0000 ---- 0000 ---- uuuu EEC ---- 0000 ---- 0000 ---- uuuu Note: “u” stands for unchanged “x” stands for unknown “-” stands for unimplemented Rev. 1.00 48 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PB. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU4 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC5 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PBPU0 PBPU — — — — PBPU3 PBPU2 PBPU1 PB — — — — PB3 PB2 PB1 PB0 PBC — — — — PBC3 PBC2 PBC1 PBC0 I/O Register List Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PBPU, and are implemented using weak PMOS transistors. Note that the pull-high resistor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high resistors cannot be enabled. PAPU Register Bit 7 6 5 4 3 2 1 0 Name PAPU7 PAPU4 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAPU7~PAPU0: Port A bit 7 ~ bit 0 Pull-high Control 0: Disable 1: Enable Rev. 1.00 49 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PBPU Register Bit 7 6 5 4 3 2 1 0 Name — — — — PBPU3 PBPU2 PBPU1 PBPU0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~0PBPU3~PBPU0: Port B bit 3 ~ bit 0 Pull-high Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0PAWU7~PAWU0: Port A bit 7~bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PBC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 PAC5 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PAC7~PA0: Port A bit 7 ~ bit 0 Input/Output Control 0: Output 1: Input Rev. 1.00 50 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PBC Register Bit 7 6 5 4 3 2 1 0 Name — — — — PBC3 PBC2 PBC1 PBC0 R/W — — — — R/W R/W R/W R/W POR — — — — 1 1 1 1 Bit 7~4 Unimplemented, read as “0” Bit 3~0PBC3~PBC0: Port B bit 3 ~ bit 0 Input/Output Control 0: Output 1: Input I/O Port Source Current Control The device supports different source current driving capability for each I/O port. With the corresponding selection register, SLEDC, each I/O port can support four levels of the source current driving capability. Users should refer to the D.C. characteristics section to select the desired source current for different applications. SLEDC Register Bit 7 6 5 4 3 2 1 0 Name — — SLEDC5 SLEDC4 SLEDC3 SLEDC2 SLEDC1 SLEDC0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5~4SLEDC5~SLEDC4: PB3~PB0 source current selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) Bit 3~2SLEDC3~SLEDC2: PA7~PA4 source current selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) Bit 1~0SLEDC1~SLEDC0: PA3~PA0 source current selection 00: Source current=Level 0 (min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (max.) Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. Rev. 1.00 51 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. The device includes Port “x” output function selection register “n”, labeled as PxSn, which can select the desired functions of the multi-function pin-shared pins. The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Bit Register Name 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 Pin-shared Function Selection Registers List PAS0 Register Bit 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PAS07~PAS06: PA3 Pin-Shared function selection 00: PA3 01: VREF for OCP DAC input reference voltage 10: VREF for ADC and OCP DAC input reference voltage 11: AN3 Bit 5~4PAS05~PAS04: PA2 Pin-Shared function selection 00: PA2/PTP0I 01: PA2/PTP0I 10: PA2/PTP0I 11: AN2 Bit 3~2PAS03~PAS02: PA1 Pin-Shared function selection 00: PA1/PTCK0 01: PTP0B 10: OCPI 11: AN1 Bit 1~0PAS01~PAS00: PA0 Pin-Shared function selection 00: PA0 01: PTP0 10: PA0 11: AN0 Rev. 1.00 52 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PAS1 Register Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PAS17~PAS16: PA7 Pin-Shared function selection 00: PA7/PTP1I 01: PA7/PTP1I 10: PA7/PTP1I 11: AN7 Bit 5~4PAS15~PAS14: PA6 Pin-Shared function selection 00: PA6/PTCK1 01: PA6/PTCK1 10: PA6/PTCK1 11: AN6 Bit 3~2PAS13~PAS12: PA5 Pin-Shared function selection 00: PA5 01: PA5 10: PA5 11: AN5 Bit 1~0PAS11~PAS10: PA4 Pin-Shared function selection 00: PA4/INT0 01: PA4/INT0 10: PA4/INT0 11: AN4 PBS0 Register Bit 7 6 5 4 3 2 1 0 Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6PBS07~PBS06: PB3 Pin-Shared function selection 00: PB3 01: SCL 10: PB3 11: PB3 Bit 5~4PBS05~PBS04: PB2 Pin-Shared function selection 00: PB2 01: SDA 10: PB2 11: PB2 Bit 3~2PBS03~PBS02: PB1 Pin-Shared function selection 00: PB1 01: PTP1B 10: PB1 11: PB1 Bit 1~0PBS01~PBS00: PB0 Pin-Shared function selection 00: PB0/INT1 01: PTP1 10: PB0/INT1 11: PB0/INT1 Rev. 1.00 53 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. VDD Cont�ol Bit Data Bus D W�ite Cont�ol Registe� Q Pull-�ig� Registe� Sele�t Weak Pull-up CK Q S C�ip Reset I/O pin Read Cont�ol Registe� Data Bit D W�ite Data Registe� Q CK Q S � U X Read Data Registe� System Wake-up wake-up Sele�t PA only Generic Input/Output Structure VDD Cont�ol Bit Data Bus W�ite Cont�ol Registe� C�ip Reset Read Cont�ol Registe� D A/D Input Po�t Data Bit Q CK Q S Read Data Registe� Weak Pull-up CK Q S D W�ite Data Registe� Q Pull-�ig� Registe� Sele�t � U X Analog Input Sele�to� To A/D Conve�te� SACS�~SACS0 A/D Input/Output Structure Rev. 1.00 54 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PBC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PB, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The general features of the Periodic type TM are described here with more detailed information provided in the Periodic TM section. Introduction The device contains two Periodic type TMs having a reference name of PTM0 and PTM1. The common features to the Periodic TMs will be described in this section and the detailed operation will be described in the corresponding sections. The main features of the PTM are summarised in the accompanying table. Function PTM Timer/Counter √ I/P Capture √ Compare Match Output √ PWM Channels 1 Single Pulse Output 1 PWM Alignment Edge PWM Adjustment Period & Duty Duty or Period TM Function Summary TM Operation The Periodic type TMs offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.00 55 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU TM Clock Source The clock source which drives the main counter in the TM can originate from various sources. The selection of the required clock source is implemented using the PTnCK2~PTnCK0 bits in the PTMn control registers. The clock source can be a ratio of the system clock fSYS or the internal high clock fH, the fSUB clock source or the external PTCKn pin. The PTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Periodic Type TMs have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs has two TM input pin, with the label PTCKn and PTPnI. The PTMn input pin, PTCKn, is essentially a clock source for the PTMn and is selected using the PTnCK2~PTnCK0 bits in the PTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The PTCKn input pin can be chosen to have either a rising or falling active edge. The PTCKn pin is also used as the external trigger input pin in single pulse output mode for the PTMn. The other PTMn input pin, PTPnI, is the capture input whose active edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the PTnIO1~PTnIO0 bits in the PTMnC1 register. There is another capture input, PTCKn, for PTMn capture input mode, which can be used as the external trigger input source except the PTPnI pin. The TMs each have two output pins, PTPn and PTPnB. The PTPnB is the inverted signal of the PTPn output. The TM output pins can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external PTPn or PTPnB output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. PTM0 PTM1 Input Output Input Output PTCK0, PTP0I PTP0, PTP0B PTCK1, PTP1I PTP1, PTP1B TM External Pins TM Input/Output Pin Selection Selecting to have a TM input/output or whether to retain its other shared function is implemented using the relevant pin-shared function selection registers, with the corresponding selection bits in each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. PTCKn CCR �aptu�e input PT�n CCR output PTPnI PTPn PTPnB PTM Function Pin Control Block Diagram (n=0 or 1) Rev. 1.00 56 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing the register is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named PTMnAL and PTMnRPL, using the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. PT�n Counte� Registe� (Read only) PT�nDL PT�nDH 8-bit Buffe� PT�nAL PT�nAH PT�n CCRA Registe� (Read/W�ite) PT�nRPL PT�nRPH PT�n CCRP Registe� (Read/W�ite) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte PTMnAL or PTMnRPL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte PTMnAH or PTMnRPH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.00 ♦♦ Step 1. Read data from the High Byte PTMnDH, PTMnAH or PTMnRPH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte PTMnDL, PTMnAL or PTMnRPL ––This step reads data from the 8-bit buffer. 57 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with two external input pins and can drive two external output pins. CCRP 10-bit Compa�ato� P fSYS/4 000 fSYS fH/1� fH/�4 fSUB 001 fSUB 101 PT�nPF Inte��upt PTnOC b0~b9 010 011 10-bit Count-up Counte� 100 110 PTCKn Compa�ato� P �at�� PTnON PTnPAU Counte� Clea� PTnCCLR b0~b9 111 PTnCK�~PTnCK0 10-bit Compa�ato� A Output Cont�ol Pola�ity Cont�ol Pin Cont�ol PTn�1� PTn�0 PTnIO1� PTnIO0 PTnPOL PxSn 0 1 Compa�ato� A �at�� PTPnB PT�nAF Inte��upt PTnIO1� PTnIO0 PTnCAPTS Edge Dete�to� 0 CCRA PTPn PxSn Pin Cont�ol 1 PTPnI Periodic Type TM Block Diagram (n=0 or 1) Periodic TM Operation The Periodic Type TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 10-bit wide. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTMn interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control more than one output pin. All operating setup conditions are selected using relevant internal registers. Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA value and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 — — — PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON PTMnC1 PTnM1 PTnM0 PTnIO1 PTMnDL D7 D6 D5 D4 D3 D2 D1 D0 PTMnDH — — — — — — D9 D8 D0 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR PTMnAL D7 D6 D5 D4 D3 D2 D1 PTMnAH — — — — — — D9 D8 PTMnRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMnRPH — — — — — — D9 D8 10-bit Periodic TM Register List (n=0 or 1) Rev. 1.00 58 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7PTnPAU: PTMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4PTnCK2~PTnCK0: Select PTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCKn rising edge clock 111: PTCKn falling edge clock These three bits are used to select the clock source for the PTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3PTnON: PTMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTMn. Setting the bit high enables the counter to run, clearing the bit disables the PTMn. Clearing this bit to zero will stop the counter from counting and turn off the PTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTMn is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTMn output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Rev. 1.00 Unimplemented, read as “0” 59 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PTMnC1 Register Bit 7 6 5 4 3 Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTnPOL PTnCAPTS PTnCCLR Bit 7~6PTnM1~PTnM0: Select PTMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTMn. To ensure reliable operation the PTMn should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the PTMn output pin control must be disabled. Bit 5~4PTnIO1~PTnIO0: Select PTMn external pin PTPn or PTPnI/PTCKn function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTPnI or PTCKn 01: Input capture at falling edge of PTPnI or PTCKn 10: Input capture at falling/rising edge of PTPnI or PTCKn 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTMn is running. In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a compare match occurs from the Comparator A. The PTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTMn output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs. After the PTMn output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the PTnIO1 and PTnIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed when the PTMn is running. Rev. 1.00 60 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Bit 3PTnOC: PTMn PTPn Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTMn output pin. Its operation depends upon whether PTMn is being used in the Compare Match Output Mode or in the PWM Mode/Single Pulse Output Mode. It has no effect if the PTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTMn output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2PTnPOL: PTMn PTPn Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTPn output pin. When the bit is set high the PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTMn is in the Timer/Counter Mode. Bit 1PTnCAPTS: PTMn Capture Trigger Source Selection 0: From PTPnI pin 1: From PTCKn pin Bit 0PTnCCLR: Select PTMn Counter clear condition 0: PTMn Comparator P match 1: PTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM Mode, Single Pulse or Capture Input Mode. PTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn Counter Low Byte Register bit 7 ~ bit 0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0D9~D8: PTMn Counter High Byte Register bit 1 ~ bit 0 PTMn 10-bit Counter bit 9 ~ bit 8 Rev. 1.00 61 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn CCRA Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRA bit 7 ~ bit 0 PTMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 2 1 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0D9~D8: PTMn CCRA High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRA bit 9 ~ bit 8 PTMnRPL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn CCRP Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRP bit 7 ~ bit 0 PTMnRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0D9~D8: PTMn CCRP High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRP bit 9 ~ bit 8 Rev. 1.00 62 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Periodic Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTMn output pin, will change state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTMn output pin. The way in which the PTMn output pin changes state are determined by the condition of the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The PTMn output pin can be selected using the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1 and PTnIO0 bits are zero then no pin change will take place. Rev. 1.00 63 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Counter Value Counte� ove�flow CCRP > 0 Counte� �lea�ed by CCRP value CCRP=0 0x�FF CCRP > 0 PTnCCLR = 0; PTnM[1:0] = 00 Counte� Resta�t Resume CCRP Pause CCRA Stop Time PTnON PTnPAU PTnPOL CCRP Int. Flag PT�nPF CCRA Int. Flag PT�nAF PT�n O/P Pin Output pin set to initial Level Low if PTnOC=0 Output not affe�ted by PT�nAF flag. Remains Hig� until �eset by PTnON bit Output Toggle wit� PT�nAF flag He�e PTnIO [1:0] = 11 Toggle Output sele�t Note PTnIO [1:0] = 10 A�tive Hig� Output sele�t Output Inve�ts w�en PTnPOL is �ig� Output Pin Reset to Initial value Output �ont�olled by ot�e� pin-s�a�ed fun�tion Compare Match Output Mode − PTnCCLR=0 (n=0 or 1) Note: 1. With PTnCCLR=0 a Comparator P match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge Rev. 1.00 64 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Counter Value PTnCCLR = 1; PTnM[1:0] = 00 CCRA = 0 Counte� ove�flow CCRA > 0 Counte� �lea�ed by CCRA value 0x�FF CCRA=0 Resume CCRA Pause Stop Counte� Resta�t CCRP Time PTnON PTnPAU PTnPOL No PT�nAF flag gene�ated on CCRA ove�flow CCRA Int. Flag PT�nAF CCRP Int. Flag PT�nPF PT�n O/P Pin PT�nPF not gene�ated Output pin set to initial Level Low if PTnOC=0 Output does not ��ange Output Toggle wit� PT�nAF flag He�e PTnIO [1:0] = 11 Toggle Output sele�t Output not affe�ted by PT�nAF flag. Remains Hig� until �eset by PTnON bit Note PTnIO [1:0] = 10 A�tive Hig� Output sele�t Output Inve�ts w�en PTnPOL is �ig� Output Pin Reset to Initial value Output �ont�olled by ot�e� pin-s�a�ed fun�tion Compare Match Output Mode − PTnCCLR=1 (n=0 or 1) Note: 1. With PTnCCLR=1 a Comparator A match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. A PTMnPF flag is not generated when PTnCCLR=1 Rev. 1.00 65 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively. The PWM function within the PTMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the PTnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The PTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTMn, PWM Mode, Edge-aligned Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA — If fSYS=12MHz, PTMn clock source select fSYS/4, CCRP=512 and CCRA=128, The PTMn PWM output frequency=(fSYS/4)/512=fSYS/2048=5.8594kHz, duty=128/(2×256)=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.00 66 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Counter Value PTnM[1:0] = 10 Counte� �lea�ed by CCRP Counte� Reset w�en PTnON �etu�ns �ig� CCRP Pause Resume Counte� Stop if PTnON bit low CCRA Time PTnON PTnPAU PTnPOL CCRA Int. Flag PT�nAF CCRP Int. Flag PT�nPF PT�n O/P Pin (PTnOC=1) PT�n O/P Pin (PTnOC=0) PW� Duty Cy�le set by CCRA PW� Pe�iod set by CCRP Output �ont�olled by ot�e� pin-s�a�ed fun�tion PW� �esumes ope�ation Output Inve�ts W�en PTnPOL = 1 PWM Output Mode (n=0 or 1) Note: 1. Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTnIO[1:0]=00 or 01 4. The PTnCCLR bit has no influence on PWM operation Rev. 1.00 67 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Single Pulse Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter can only be reset back to zero when the PTnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR bit is not used in this Mode. S/W Command SET“PTnON o� ” CCRA Leading Edge CCRA T�ailing Edge PTnON bit 0 1 PTnON bit 1 0 PTCKn Pin T�ansition S/W Command CLR“PTnON” o� CCRA Compa�e �at�� PTPn Output Pin Pulse Widt� = CCRA Value Single Pulse Generation (n=0 or 1) Rev. 1.00 68 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Counter Value PTnM[1:0] = 10 ; PTnIO[1:0] = 11 Counte� stopped by CCRA Counte� Reset w�en PTnON �etu�ns �ig� CCRA Pause Counte� Stops by softwa�e Resume CCRP Time PTnON Softwa�e T�igge� Auto. set by PTCKn pin Softwa�e T�igge� Clea�ed by CCRA mat�� PTCKn pin Softwa�e Softwa�e T�igge� Clea� Softwa�e T�igge� PTCKn pin T�igge� PTnPAU PTnPOL CCRP Int. Flag PT�nPF No CCRP Inte��upts gene�ated CCRA Int. Flag PT�nAF PT�n O/P Pin (PTnOC=1) PT�n O/P Pin (PTnOC=0) Output Inve�ts w�en PTnPOL = 1 Pulse Widt� set by CCRA Single Pulse Mode (n=0 or 1) Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCKn pin or by setting the PTnON bit high 4. A PTCKn pin active edge will automatically set the PTnON bit high 5. In the Single Pulse Mode, PTnIO[1:0] must be set to “11” and cannot be changed. Rev. 1.00 69 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPnI or PTCKn pin which is selected using the PTnCAPTS bit in the PTMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPnI or PTCKn pin the present value in the counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of what events occur on the PTPnI or PTCKn pin, the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.00 70 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Counter Value PTnM[1:0] = 01 Counte� �lea�ed by CCRP Counte� Stop Counte� Reset CCRP YY Resume Pause XX Time PTnON PTnPAU A�tive edge A�tive edge A�tive edge PT�n Captu�e Pin PTPnI o� PTCKn CCRA Int. Flag PT�nAF CCRP Int. Flag PT�nPF XX CCRA Value PTnIO [1:0] Value 00 - Rising edge YY XX 01 - Falling edge 10 - Bot� edges YY 11 - Disable Captu�e Capture Input Mode (n=0 or 1) Note: 1. PTnM[1:0]=01 and active edge set by the PTnIO[1:0] bits 2. A PTMn Capture input pin active edge transfers the counter value to CCRA 3. PTnCCLR bit not used 4. No output function – PTnOC and PTnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 71 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview This device contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, the Bandgap reference voltage VBG and the Over Current Protection analog output signal OCPAO, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the SAINS2~SAINS0 bits together with the SACS3~SACS0 bits. When the external analog signal is to be converted, the corresponding pin-shared control bits should first be properly configured and then desired external channel input should be selected using the SAINS2~SAINS0 and SACS3~SACS0 bits. Note that when the internal analog signal is to be converted, the pin-shared control bits should also be properly configured except the SAINS and SACS bit fields. More detailed information about the A/D input signal is described in the “A/D Converter Control Registers” and “A/D Converter Input Signals” sections respectively. External Input Channels Internal Signals Channel Select Bits 8: AN0~AN7 2: VBG, OCPAO SAINS2~SAINS0, SACS3~SACS0 The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. Pin-s�a�ed Sele�tion AVDD fSYS SACKS�~SACKS0 AN0 AN1 ÷ �N SAVRS1~SAVRS0 (N=0~7) A/D Clo�k AN� AN� VREF ADCEN A/D Refe�en�e Voltage SADOL A/D Data SADOH Registe�s A/D Conve�te� AN4 AN5 AN� AN7 ADBZ START SACS�~SACS0 AVSS ADRFS ADCEN VBG OCPAO SAINS�~SAINS0 A/D Converter Structure Rev. 1.00 72 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU A/D Converter Register Description Overall operation of the A/D converter is controlled using several registers. A read only register pair exists to store the A/D converter data 12-bit value. The remaining two registers are control registers which setup the operating and control function of the A/D converter. Register Name Bit 7 6 5 4 3 2 1 0 SADOL(ADRFS=0) D3 D2 D1 D0 — — — — SADOL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 SADOH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 SADOH(ADRFS=1) — — — — D11 D10 D9 D8 SADC0 START ADBZ SACS3 SACS2 SACS1 SACS0 SADC1 SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0 ADCEN ADRFS A/D Converter Register List A/D Converter Data Registers – SADOL, SADOH As this device contains an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as SADOH, and a low byte register, known as SADOL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the SADC0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. Note that A/D data registers contents will be unchanged if the A/D converter is disabled. ADRFS 0 1 SADOH 7 6 D11 D10 0 0 5 4 D9 D8 0 0 SADOL 3 2 1 0 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Data Registers A/D Converter Control Registers – SADC0, SADC1 To control the function and operation of the A/D converter, two control registers known as SADC0 and SADC1 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. As the device contains only one actual analog to digital converter hardware circuit, each of the external or internal analog signal inputs must be routed to the converter. The SACS3~SACS0 bits in the SADC0 register are used to determine which external channel input is selected to be converted. The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the internal analog signal or external analog channel input. The relevant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pinshared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input. Rev. 1.00 73 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU SADC0 Register Bit 7 6 5 4 3 2 1 0 Name START ADBZ ADCEN ADRFS SACS3 SACS2 SACS1 SACS0 R/W R/W R R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7START: Start the A/D conversion 0→1→0: Start This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6ADBZ: A/D converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is used to indicate whether the A/D conversion is in progress or not. When the START bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5ADCEN: A/D converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/D converter. If the bit is set low, then the A/D converter will be switched off reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair known as SADOH and SADOL will be unchanged. Bit 4ADRFS: A/D converter data format select 0: A/D converter data format → SADOH=D[11:4]; SADOL=D[3:0] 1: A/D converter data format → SADOH=D[11:8]; SADOL=D[7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Bit 3~0SACS3~SACS0: A/D converter external analog channel input select 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000~1111: Non-existed channel, the input will be floating if selected Rev. 1.00 74 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU SADC1 Register Bit 7 6 5 4 3 2 1 0 Name SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~5SAINS2~SAINS0: A/D converter input signal select 000: External input — External analog channel input 001: Internal input — Internal Bandgap reference voltage, VBG 010: Internal input — Internal OCPAO signal 011, 100: Reserved, connected to ground 101~111: External input — External analog channel input Care must be taken if the SAINS2~SAINS0 bits are set from “001” to “010” to select the internal analog signal to be converted. When the internal analog signal is selected to be converted, the external input pin must never be selected as the A/D input signal by properly setting the SACS3~SACS0 bits with a value from 1000 to 1111. Otherwise, the external channel input will be connected together with the internal analog signal. This will result in unpredictable situations such as an irreversible damage. Bit 4~3SAVRS1~SAVRS0: A/D converter reference voltage select 00: VREF pin 01: Internal A/D converter power, AVDD 1x: VREF pin These bits are used to select the A/D converter reference voltage. Care must be taken if the SAVRS1~SAVRS0 bits are set to “01” to select the internal A/D converter power as the reference voltage source. When the internal A/D converter power is selected as the reference voltage, the VREF pin cannot be configured as the reference voltage input by properly configuring the corresponding pin-shared function control bits. Otherwise, the external input voltage on VREF pin will be connected to the internal A/D converter power. Bit 2~0SACKS2~SACKS0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These three bits are used to select the clock source for the A/D converter. Rev. 1.00 75 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU A/D Converter Operation The START bit in the SADC0 register is used to start the AD conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The ADBZ bit in the SADC0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register. Although the A/D clock source is determined by the system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, as the system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000, 001 or 111. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tADCK) SACKS[2:0] = 000 (fSYS) SACKS[2:0] = 001 (fSYS/2) SACKS[2:0] = 010 (fSYS/4) SACKS[2:0] = 011 (fSYS/8) SACKS[2:0] = 100 (fSYS/16) SACKS[2:0] = 101 (fSYS/32) SACKS[2:0] = 110 (fSYS/64) SACKS[2:0] = 111 (fSYS/128) 1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs * 2MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 4MHz 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 8MHz 125ns * 250ns * 500ns 1μs 2μs 4μs 8μs 16μs * fSYS A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADCEN bit in the SADC0 register. This bit must be set high to power on the A/D converter. When the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D converter function is not being used. Rev. 1.00 76 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU A/D Converter Reference Voltage The reference voltage supply to the A/D converter can be supplied from the positive power supply pin, AVDD, or from an external reference source supplied on pin VREF. The desired selection is made using the SAVRS1 and SAVRS0 bits. When the SAVRS bit field is set to “01”, the A/D converter reference voltage will come from the AVDD pin. Otherwise, if the SAVRS bit field is set to any other value except “01”, the A/D converter reference voltage will come from the VREF pin. As the A/D converter and OCP D/A converter external reference voltage come from the same VREF pin, when the VREF pin is selected as the A/D converter reference voltage pin, the OCP D/A converter reference voltage selection bit OCPVRS should be also properly configured except the pin-shared function control bits to avoid functional abnormity. However, if the internal A/D converter power is selected as the reference voltage, the VREF pin must not be configured as the reference voltage input function for the A/D converter to avoid the internal connection between the VREF pin to A/D converter power AVDD. The analog input values must not be allowed to exceed the value of the selected reference voltage, AVDD or VREF. The following table shows how to properly select reference voltage for the A/D converter or OCP D/A converter. ADC Reference Voltage Selection OCP DAC Reference Voltage Selection SAVRS[1:0] OCPVRS PAS07~PAS06 AVDD AVDD 01 0 Others except “10” AVDD VREF 01 1 01 VREF AVDD Others except “01” 0 10 VREF VREF Others except “01” 1 10 A/D Converter Input Signals All the external A/D analog channel input pins are pin-shared with the I/O pins as well as other functions. The corresponding control bits for each A/D external input pin in the PAS0 and PAS1 register determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the pin is setup to be as an A/D analog channel input, the original pin functions will be disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the pin-shared function control bits enable an A/D input, the status of the port control register will be overridden. There are two internal analog signals derived from the Bandgap reference voltage or Over Current Protection analog output signal, which can be connected to the A/D converter as the analog input signal by configuring the SAINS2~SAINS0 bits. If the external channel input is selected to be converted, the SAINS2~SAINS0 bits should be set to “000” and the SACS3~SACS0 bits can determine which external channel is selected. If the internal analog signal is selected to be converted, the SACS3~SACS0 bits must be configured with a value from 1000 to 1111 to switch off the external analog channel input. Otherwise, the internal analog signal will be connected together with the external channel input. This will result in unpredictable situations. Rev. 1.00 77 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU SAINS[2:0] 000, 101~111 SACS[3:0] Input Signals 0000~0111 Description AN0~AN7 External pin analog input 1000~1111 — Non-existed channel, input is floating. 1000~1111 VBG Internal Bandgap reference voltage 010 1000~1111 OCPAO 011, 100 1000~1111 — 001 Internal Over Current Protection analog output signal Reserved, connected to ground. A/D Converter Input Signal Selection Conversion Rate and Timing Diagram A complete A/D conversion contains two parts, data sampling and data conversion. The data sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is defined as tADC are necessary. Maximum single A/D conversion rate=A/D clock period / 16 The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. tON�ST ADCEN off on off A/D sampling time tADS A/D sampling time tADS Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion on START ADBZ SACS[�:0] (SAINS[�:0]=000) End of A/D �onve�sion 0011B A/D ��annel swit�� End of A/D �onve�sion 0010B tADC A/D �onve�sion time Sta�t of A/D �onve�sion 0000B tADC A/D �onve�sion time 0001B tADC A/D �onve�sion time A/D Conversion Timing – External Channel Input Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits SACKS2~SACKS0 in the SADC1 register. • Step 2 Enable the A/D by setting the ADCEN bit in the SADC0 register to one. Rev. 1.00 78 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU • Step 3 Select which signal is to be connected to the internal A/D converter by correctly configuring the SAINS2~SAINS0 bits. Select the external channel input to be converted, go to Step 4. Select the internal analog signal to be converted, go to Step 5. • Step 4 If the A/D input signal comes from the external channel input selecting by configuring the SAINS bit field, the corresponding pins should be configured as A/D input function by configuring the relevant pin-shared function control bits. The desired analog channel then should be selected by configuring the SACS bit field. After this step, go to Step 6. • Step 5 Before the A/D input signal is selected to come from the internal analog signal by configuring the SAINS bit field, the corresponding external input pin must be switched to a non-existed channel input by setting the SACS3~SACS0 bits with a value from 1000 to 1111. The desired internal analog signal then can be selected by configuring the SAINS bit field. After this step, go to Step 6. • Step 6 Select the reference voltage source by configuring the SAVRS1~SAVRS0 bits in the SADC1 register. • Step 7 Select A/D converter output data format by setting the ADRFS bit in the SADC0 register. • Step 8 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance. • Step 9 The A/D conversion procedure can now be initialized by setting the START bit from low to high and then low again. • Step 10 If A/D conversion is in progress, the ADBZ flag will be set high. After the A/D conversion process is complete, the ADBZ flag will go low and then the output data can be read from SADOH and SADOL registers. Note: When checking for the end of the conversion process, if the method of polling the ADBZ bit in the SADC0 register is used, the interrupt enable step above can be omitted. Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by clearing bit ADCEN to 0 in the SADC0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. Rev. 1.00 79 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU A/D Conversion Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the AVDD or VREF voltage, this gives a single bit analog input value of AVDD or VREF divided by 4096. 1 LSB=(AVDD or VREF) ÷ 4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage=A/D output digital value × (AVDD or VREF) ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the AVDD or VREF level. 1.5 LSB FFFH FFEH FFDH A/D Conversion Result 0�H 0.5 LSB 0�H 01H 0 1 � � 409� 4094 4095 409� AVDD o� VREF 409� Analog Input Voltage Ideal A/D Transfer Function A/D Conversion Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Rev. 1.00 80 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Example: using an ADBZ polling method to detect the end of conversion clr ADE; disable ADC interrupt mova,03H mov SADC1,a ; select fSYS/8 as A/D clock set ADCEN mov a,03h ; setup PAS0 to configure pin AN0 mov PAS0,a mova,20h mov SADC0,a ; enable and connect AN0 channel to A/D converter : start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register :: jmp start_conversion ; start next A/D conversion Example: using the interrupt method to detect the end of conversion clr ADE; disable ADC interrupt mova,03H mov SADC1,a ; select fSYS/8 as A/D clock set ADCEN mov a,03h ; setup PAS0 to configure pin AN0 mov PAS0,a mova,20h mov SADC0,a ; enable and connect AN0 channel to A/D converter Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE ; enable ADC interrupt set EMI ; enable global interrupt :: ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory :: mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register :: EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.00 81 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Over Current Protection The device includes an over current protection function which provides a protection mechanism for applications. To prevent the battery charge or load current from exceeding a specific level, the current on the OCP pin is converted to a relevant voltage level according to the current value using the OCP operational amplifier. It is then compared with a reference voltage generated by an 8-bit D/A converter. When an over current event occurs, an OCP interrupt will be generated if the corresponding interrupt control is enabled. VREF OCPEN[1:0] OCPI AVDD OCPDA[7:0] � U X 8-bit DAC S1 S� R1 (R1 = 4K) fSYS OCPCHY OCPCOUT S4 S0 S� OCPVRS - C�P + + OPA - Deboun�e OCPO OCPINT OCPDEB[�:0] R� OCPAO (To A/D inte�nal input) G[�:0] Over Current Protection Circuit Over Current Protection Operation The illustrated OCP circuit is used to prevent the input current from exceeding a reference level. The current on the OCP pin is converted to a voltage and then amplified by the OCP operational amplifier with a programmable gain from 1 to 50 selected by the G2~G0 bits in the OCPC1 register. This is known as a Programmable Gain Amplifier or PGA. This PGA can also be configured to operate in the non-inverting, inverting or input offset calibration mode determined by the OCPEN1 and OCPEN0 bits in the OCPC0 register. After the current is converted and amplified to a specific voltage level, it will be compared with a reference voltage provided by an 8-bit DAC. The 8-bit DAC power can be AV DD or V REF, selected by the OCPVRS bit in the OCPC0 register. The comparator output, OCPCOUT, will first be filtered with a certain de-bounce time period selected by the OCPDEB2~OCPDEB0 bits in the OCPC1 register. Then a filtered OCP digital comparator output, OCPO, is obtained to indicate whether an over current condition occurs or not. The OCPO bit will be set to 1 if an over current condition occurs. Otherwise, the OCPO bit is zero. Once an over current event occurs, i.e., the converted voltage of the OCP input current is greater than the reference voltage, the corresponding interrupt will be generated if the relevant interrupt control bit is enabled. Rev. 1.00 82 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Over Current Protection Control Registers Overall operation of the over current protection is controlled using several registers. One register is used to provide the reference voltages for the over current protection circuit. There are two registers used to cancel out the operational amplifier and comparator input offset. The remaining two registers are control registers which control the OCP function, D/A converter reference voltage select, PGA gain select, comparator de-bounce time together with the hysteresis function. Bit Register Name 7 6 5 4 3 2 1 0 OCPC0 OCPEN1 OCPEN0 OCPVRS OCPCHY — — — OCPO OCPC1 — — G2 G1 G0 OCPDA D7 D6 D5 D4 D3 OCPDEB2 OCPDEB1 OCPDEB0 D2 D1 D0 OCPOCAL OCPOOFM OCPORSP OCPOOF5 OCPOOF4 OCPOOF3 OCPOOF2 OCPOOF1 OCPOOF0 OCPCCAL OCPCOUT OCPCOFM OCPCRSP OCPCOF4 OCPCOF3 OCPCOF2 OCPCOF1 OCPCOF0 OCP Register List OCPC0 Register Bit Name 7 6 5 4 OCPEN1 OCPEN0 OCPVRS OCPCHY 3 2 1 0 — — — OCPO R/W R/W R/W R/W R/W — — — R POR 0 0 0 0 — — — 0 Bit 7~6OCPEN1~OCPEN0: OCP function operating mode selection 00: OCP function is disabled, S1and S3 on, S0 and S2 off 01: Non-inverting mode, S0 and S3 on, S1 and S2 off 10: Inverting mode, S1 and S2 on, S0 and S3 off 11: Calibration mode, S1 and S3 on, S0 and S2 off Bit 5OCPVRS: OCP DAC reference voltage selection 0: From AVDD 1: From VREF Bit 4OCPCHY: OCP Comparator hysteresis function control 0: Disable 1: Enable Bit 3~1 Unimplemented, read as “0” Bit 0OCPO: OCP digital output bit 0: The monitored source current is not over 1: The monitored source current is over Rev. 1.00 83 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU OCPC1 Register Bit 7 6 5 4 3 Name — — G2 G1 G0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 2 1 0 OCPDEB2 OCPDEB1 OCPDEB0 Unimplemented, read as “0” Bit 5~3G2~G0: PGA R2/R1 ratio selection 000: Unity gain buffer (non-inverting mode) or R2/R1=1(inverting mode) 001: R2/R1=5 010: R2/R1=10 011: R2/R1=15 100: R2/R1=20 101: R2/R1=30 110: R2/R1=40 111: R2/R1=50 These bits are used to select the R2/R1 ratio to obtain various gain values for inverting and non-inverting mode. The calculating formula of the PGA gain for the inverting and non-inverting mode is described in the “Input Voltage Range” section. Bit 2~0OCPDEB2~OCPDEB0: OCP output filter debounce time selection 000: Bypass, without debounce 001: (1~2) × tDEB 010: (3~4) × tDEB 011: (7~8) × tDEB 100: (15~16) × tDEB 101: (31~32) × tDEB 110: (63~64) × tDEB 111: (127~128) × tDEB Note: tDEB=1/fSYS OCPDA Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: OCP DAC output voltage control bits OCP DAC Output=(DAC reference voltage/256) × D[7:0] Rev. 1.00 84 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU OCPOCAL Register Bit Name 7 6 5 4 3 2 1 0 OCPOOFM OCPORSP OCPOOF5 OCPOOF4 OCPOOF3 OCPOOF2 OCPOOF1 OCPOOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 0 0 0 0 Bit 7OCPOOFM: OCP Operational Amplifier Input Offset Calibration Mode Enable control 0: Input Offset Calibration Mode Disabled 1: Input Offset Calibration Mode Enabled This bit is used to control the OCP operational amplifier input offset Calibration function. The OCPEN1 and OCPEN0 bits must first be set to “11” and then the OCPOOFM bit must be set to 1 followed by the OCPCOFM bit being setting to 0, then the operational amplifier input offset Calibration mode will be enabled. Refer to the “Operational Amplifier Input Offset Calibration” section for the detailed offset Calibration procedures. Bit 6OCPORSP: OCP Operational Amplifier Input Offset Voltage Calibration Reference selection 0: Select negative input as the reference input 1: Select positive input as the reference input Bit 5~0OCPOOF5~OCPOOF0: OCP Operational Amplifier Input Offset Voltage Calibration value This 6-bit field is used to perform the operational amplifier input offset Calibration operation and the value for the OCP operational amplifier input offset Calibration can be restored into this bit field. More detailed information is described in the “Operational Amplifier Input Offset Calibration” section. OCPCCAL Register Bit Name 7 6 5 4 3 2 1 0 OCPCOUT OCPCOFM OCPCRSP OCPCOF4 OCPCOF3 OCPCOF2 OCPCOF1 OCPCOF0 R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 1 0 0 0 0 Bit 7OCPCOUT: OCP Comparator Output, positive logic (read only) 0: Positive input voltage < Negative input voltage 1: Positive input voltage > Negative input voltage This bit is used to indicate whether the positive input voltage is greater than the negative input voltage when the OCP operates in the input offset Calibration mode. If the OCPCOUT is set to 1, the positive input voltage is greater than the negative input voltage. Otherwise, the positive input voltage is less than the negative input voltage. Bit 6OCPCOFM: OCP Comparator Input Offset Calibration Mode Enable control 0: Input Offset Calibration Mode Disabled 1: Input Offset Calibration Mode Enabled This bit is used to control the OCP comparator input offset Calibration function. The OCPEN1 and OCPEN0 bits must first be set to “11” and then the OCPCOFM bit must be set to 1 followed by the OCPOOFM bit being setting to 0, then the comparator input offset calibration mode will be enabled. Refer to the “Comparator Input Offset Calibration” section for the detailed offset calibration procedures. Bit 5OCPCRSP: OCP Comparator Input Offset Calibration Reference Input select 0: Select negative input as the reference input 1: Select positive input as the reference input Bit 4~0OCPCOF4~OCPCOF0: OCP Comparator Input Offset Calibration value This 5-bit field is used to perform the comparator input offset calibration operation and the value for the OCP comparator input offset calibration can be restored into this bit field. More detailed information is described in the “Comparator Input Offset Calibration” section. Rev. 1.00 85 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Input Voltage Range Together with different PGA operating modes, the input voltage on the OCP pin can be positive or negative for flexible operation. The PGA output for the positive or negative input voltage is calculated based on different formulas and described by the following. • For input voltages VIN > 0, the PGA operates in the non-inverting mode and the PGA output is obtained using the formula below: R2 VOUT = (1 + ) × VIN R1 • When the PGA operates in the non-inverting mode by setting the OCPEN[1:0] to “01” with unity gain select by setting the G[2:0] to “000”, the PGA will act as a unit-gain buffer whose output is equal to VIN. VOUT = VIN • For input voltages 0 >VIN >-0.4V, the PGA operates in the inverting mode and the PGA output is obtained using the formula below. Note that if the input voltage is negative, it cannot be lower than -0.4V which will result in current leakage. R2 VOUT = ‒ × VIN R1 Offset Calibration The OCP circuit has 4 operating modes controlled by OCPEN[1:0], one of them is calibration mode. In calibration mode, Operational amplifier and comparator offset can be calibrated. Operational Amplifier Input Offset Calibration Step 1. Set OCPEN[1:0]=11, OCPOOFM=1 and OCPCOFM=0, the OCP will operate in the operational amplifier input offset Calibration mode. Step 2. Set OCPOOF[5:0]=000000 and then read the OCPCOUT bit. Step 3. Increase the OCPOOF[5:0] value by 1 and then read the OCPCOUT bit. If the OCPCOUT bit state has not changed, then repeat Step 3 until the OCPCOUT bit state has changed. If the OCPCOUT bit state has changed, record the OCPOOF value as VOOS1 and then go to Step 4. Step 4. Set OCPOOF[5:0]=111111 and read the OCPCOUT bit. Step 5. Decrease the OCPOOF[5:0] value by 1 and then read the OCPCOUT bit. If the OCPCOUT bit state has not changed, then repeat Step 5 until the OCPCOUT bit state has changed. If the OCPCOUT bit state has changed, record the OCPOOF value as VOOS2 and then go to Step 6. Step 6. Restore the operational amplifier input offset calibration value VOOS into the OCPOOF[5:0] bit field. The offset Calibration procedure is now finished. V + VOOS2 Where VOOS = OOS1 2 Rev. 1.00 86 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Comparator Input Offset Calibration Step 1. Set OCPEN[1:0]=11, OCPCOFM=1 and OCPOOFM=0, the OCP will now operate in the comparator input offset calibration mode. S4 is on (S4 is used for calibration mode, in normal mode operation, it is off). Step 2. Set OCPCOF[4:0]=00000 and read the OCPCOUT bit. Step 3. Increase the OCPCOF[4:0] value by 1 and then read the OCPCOUT bit. If the OCPCOUT bit state has not changed, then repeat Step 3 until the OCPCOUT bit state has changed. If the OCPCOUT bit state has changed, record the OCPCOF value as VCOS1 and then go to Step 4. Step 4. Set OCPCOF[4:0]=11111 and then read the OCPCOUT bit. Step 5. Decrease the OCPCOF[4:0] value by 1 and then read the OCPCOUT bit. If the OCPCOUT bit state has not changed, then repeat Step 5 until the OCPCOUT bit state has changed. If the OCPCOUT bit state has changed, record the OCPCOF value as VCOS2 and then go to Step 6. Step 6. Restore the comparator input offset calibration value VCOS into the OCPCOF[4:0] bit field. The offset Calibration procedure is now finished. Where VCOS=VCOS1 + VCOS2 2 High Voltage Output The device contains a high voltage driver with level shift functions, which can be used to drive the external Power MOS. VCC VDD M U X PTP0 HVO OCPO VCC Level shift HVOOE VDD OE* VCC Level shift D* EN HV Output Control HVO HVODS HVOP0EN INT0 HVOP1EN HVOP2 P* H/W Protection Control HVOP2EN HVOPEN HVOP3 HVOP3EN Note: 1. “*” is the circuit node name and not the Special Function Register bit. 2. PTP0 acted as the control signal output High /Low (D) source. High Voltage Output Block Diagram Rev. 1.00 87 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Functional Description The high voltage output on the HVO pin is used to drive the external power MOS by the HVO bit high/low or using PTP0 output to control power MOS loads, the control methods can be selected by the HVODS bit. Protection Mechanism There is a protection mechanism provided for high voltage output. • If HVOPEN=0, whether the HVO pin is in a floating status or normally outputs as above described methods will be determined by the HVOOE bit. • If HVOPEN=1, when the control signal P trigger from low to high occurs, first the HVO and HVODS bits will be forced to be cleared to zero, the purpose is as follows. ♦♦ When OE=1, the HVO pin output status is low. When OE=0, the HVO pin output status is floating, where the OE value is decided by the HVOOE bit. Then the action of the HVOC register is determined by software. ♦♦ • If HVOPEN=1, but the control signal P trigger does not occur, then the HVO and HVODS bits will not be affected. Control Registers These two registers are used to control the overall operation of high voltage output. HVOC Register Bit 7 6 5 4 3 2 1 0 Name — — — — HVOPEN HVOOE HVODS HVO R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3HVOPEN: HVO pin H/W protection enable control 0: Disable 1: Enable Bit 2HVOOE: HVO pin output enable control 0: Output disable 1: Output enable Bit 1HVODS: HVO pin output data select 0: Output decide by HVO bit 1: Output decide by PTP0 Bit 0HVO: HVO pin output control 0: Output low 1: Output high Note: As the HVOOE and HVO bits are in the same register, when the HVOC register is configured, there is a system clock fSYS delay provided between the HVO pin output enable and data signals by hardware, to solve the problem due to these two signals are too closed. Rev. 1.00 88 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU HVOPC Register Bit 7 6 5 4 Name — — — — 3 2 1 0 HVOP3EN HVOP2EN HVOP1EN HVOP0EN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3HVOP3EN: HVOP3 H/W Protection control 0: Disable 1: Enable Bit 2HVOP2EN: HVOP2 H/W Protection control 0: Disable 1: Enable Bit 1HVOP1EN: INT0 H/W Protection control 0: Disable 1: Enable Bit 0HVOP0EN: OCPO H/W Protection control 0: Disable 1: Enable I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. VDD SDA SCL Devi�e Slave Devi�e �aste� Devi�e Slave I2C Master/Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For this device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. Rev. 1.00 89 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Data Bus I�C Data Registe� (IICD) fSYS SCL Pin SDA Pin HTX Deboun�e Ci��uit�y Add�ess Add�ess �at��–HAAS Compa�ato� Di�e�tion Cont�ol Data in �SB � U X IICDEB[1:0] I�C Add�ess Registe� (IICA) S�ift Registe� Read/W�ite Slave I�C Inte��upt SRW Data out �SB TXAK 8-bit Data T�ansfe� Complete–HCF T�ansmit/ Re�eive Cont�ol Unit Dete�t Sta�t o� Stop IICTOF Time-out Cont�ol fSUB IICTOEN HBB Add�ess �at�� I2C Block Diagram START signal f�om �aste� Send slave add�ess and R/W bit f�om �aste� A�knowledge f�om slave Send data byte f�om �aste� A�knowledge f�om slave STOP signal f�om �aste� The IICDEB1 and IICDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Debounce fSYS > 2 MHz fSYS > 5 MHz 2 system clock debounce fSYS > 4 MHz fSYS > 10 MHz fSYS > 8 MHz fSYS > 20 MHz 4 system clock debounce I C Minimum fSYS Frequency 2 Rev. 1.00 90 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I2C Registers There are three control registers associated with the I2C bus, IICC0, IICC1 and IICTOC, and one slave address register, IICA, together with one data register, IICD. Register Name Bit 7 6 5 4 3 2 1 0 IICC0 — — — — IICDEB1 IICDEB0 IICEN — IICC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK IICD D7 D6 D5 D4 D3 D2 D1 D0 IICA A6 A5 A4 A3 A2 A1 A0 — IICTOC IICTOEN IICTOF IICTOS5 IICTOS4 IICTOS3 IICTOS2 IICTOS1 IICTOS0 I2C Registers List IICD Register The IICD register is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register. After the data is received from the I2C bus, the microcontroller can read it from the IICD register. Any transmission or reception of data from the I2C bus must be made via the IICD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x”: unknown Bit 7~0D7~D0: I2C Data Buffer bit 7~bit 0 IICA Register The IICA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the IICA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the IICA register, the slave device will be selected. Bit 7 6 5 4 3 2 1 0 Name A6 A5 A4 A3 A2 A1 A0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR 0 0 0 0 0 0 0 — Bit 7~1A6~A0: I C slave address A6~A0 is the I2C slave address bit 6 ~ bit 0. 2 Bit 0 Rev. 1.00 Unimplemented, read as “0” 91 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I2C Control Registers There are two control registers for the I2C interface, IICC0 and IICC1. The register IICC0 is used to control the enable/disable function and to set the data transmission clock frequency. The IICC1 register contains the relevant flags which are used to indicate the I2C communication status. Another register, IICTOC, is used to control the I2C time-out function and described in the corresponding section. • IICC0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — IICDEB1 IICDEB0 IICEN — R/W — — — — R/W R/W R/W — POR — — — — 0 0 0 — Bit 7~4 Unimplemented, read as “0” Bit 3~2IICDEB1~IICDEB0: I2C Debounce Time Selection 00: No debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce Bit 1IICEN: I2C enable 0: Disable 1: Enable The bit is the overall on/off control for the I2C interface. When the IICEN bit is cleared to zero to disable the I2C interface, the SDA and SCL lines will lose their I2C function and the I2C operating current will be reduced to a minimum value. When the bit is high the I2C interface is enabled. If the IICEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Unimplemented, read as “0” • IICC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Below is an example of the flow of a two-byte I2C data transfer. First, I2C slave device receive a start signal from I2C master and then HCF bit is automatically cleared to zero. Second, I2C slave device finish receiving the 1st data byte and then HCF bit is automatically set to one. Third, user read the 1st data byte from IICD register by the application program and then HCF bit is automatically cleared to zero. Fourth, I2C slave device finish receiving the 2nd data byte and then HCF bit is automatically set to one and so on. Finally, I2C slave device receive a stop signal from I2C master and then HCF bit is automatically set to one. Rev. 1.00 92 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Bit 6HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to “0” when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Control 0: Disable 1: Enable This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. Rev. 1.00 93 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the IICC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and IICTOF bits to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer completion or I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set IICEN bit in the IICC0 register to “1” to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register IICA. • Step 3 Set the IICE interrupt enable bit of the interrupt control register to enable the I2C interrupt. Sta�t SET IICEN W�ite Slave Add�ess to IICA No I�C Bus Inte��upt=? Yes CLR IICE Poll IICF to de�ide w�en to go to I�C Bus ISR SET IICE Wait fo� Inte��upt Go to �ain P�og�am Go to �ain P�og�am I2C Bus Initialisation Flow Chart Rev. 1.00 94 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the IICC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the HAAS and IICTOF bits should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or I2C time-out. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register, or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the IICC1 register defines whether the master device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the IICC1 register should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the IICC1 register should be set to “0”. Rev. 1.00 95 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the IICD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the IICD register. If setup as a receiver, the slave device must read the transmitted data from the IICD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the IICC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. SCL Slave Add�ess Sta�t 1 0 1 SDA 1 0 1 SRW ACK 1 0 0 Data SCL 1 0 0 1 0 ACK 1 0 Stop 0 SDA S=Sta�t (1 bit) SA=Slave Add�ess (7 bits) SR=SRW bit (1 bit) �=Slave devi�e send a�knowledge bit (1 bit) D=Data (8 bits) A=ACK (RXAK bit fo� t�ansmitte�� TXAK bit fo� �e�eive�� 1 bit) P=Stop (1 bit) S SA SR � D A D A …… S SA SR � D A D A …… P Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register, or in the receive mode where it must implement a dummy read from the IICD register to release the I2C SCL line. I2C Communication Timing Diagram Rev. 1.00 96 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Sta�t No No No Yes HAAS=1? Yes HTX=1? Yes IICTOF=1? Yes SET IICTOEN CLR IICTOF No SRW=1? RETI Read f�om IICD to �elease SCL Line RETI Yes SET HTX CLR HTX CLR TXAK W�ite data to IICD to �elease SCL Line Dummy �ead f�om IICD to �elease SCL Line RETI RETI RXAK=1? No CLR HTX CLR TXAK W�ite data to IICD to �elease SCL Line Dummy �ead f�om IICD to �elease SCL Line RETI RETI I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, a time-out function is provided. If the clock source to the I2C is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts counting on an I2C bus “START” & “address match” condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out setup by the IICTOC register, then a time-out condition will occur. The time-out function will stop when an I2C “STOP” condition occurs. SCL Sta�t Slave Add�ess 1 SDA 0 1 1 0 1 SRW ACK 1 0 0 I�C time-out �ounte� sta�t Stop SCL 1 0 0 1 0 1 0 0 SDA I�C time-out �ounte� �eset on SCL negative t�ansition I2C Time-out Rev. 1.00 97 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU When an I2C time-out counter overflow occurs, the counter will stop and the IICTOEN bit will be cleared to zero and the IICTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out IICD, IICA, IICC0 No change IICC1 Reset to POR condition I2C Registers after Time-out The IICTOF flag can be cleared by the application program. There are 64 time-out periods which can be selected using bits in the IICTOC register. The time-out time is given by the formula: ((1~64) × 32) / fSUB This gives a range of about 1ms to 64ms. IICTOC Register Bit 7 6 5 4 3 2 1 0 Name IICTOEN IICTOF IICTOS5 IICTOS4 IICTOS3 IICTOS2 IICTOS1 IICTOS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7IICTOEN: I2C Time-out Control 0: Disable 1: Enable Bit 6IICTOF: Time-out flag (set by time-out and clear by software) 0: No time-out 1: Time-out occurred Bit 5~0IICTOS5~IICTOS0: Time-out Definition I2C time-out clock source is fSUB/32. I2C time-out time is given by: (IICTOS[5:0]+1) × (32/fSUB) Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0~INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, Time Base, LVD, EEPROM and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI1 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Rev. 1.00 98 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/disable bit or “F” for request flag. Function Global INTn Pin Multi-function A/D Converter Time Base LVD EEPROM I2C Over Current Protection PTM Enable Bit Request Flag Notes EMI INTnE MFnE ADE TBnE LVE DEE IICE OCPE PTMnPE PTMnAE — INTnF MFnF ADF TBnF LVF DEF IICF OCPF PTMnPF PTMnAF — n=0~1 n=0~1 — n=0~1 — — — — n=0~1 Interrupt Register Bit Naming Conventions Register Name Bit 7 6 5 4 3 2 1 0 INT0S0 INTEG — — — — INT1S1 INT1S0 INT0S1 INTC0 — INT1F OCPF INT0F INT1E OCPE INT0E EMI INTC1 TB1F TB0F MF1F MF0F TB1E TB0E MF1E MF0E INTC2 DEF LVF ADF IICF DEE LVE ADE IICE MFI0 — — PTM0AF PTM0PF — — PTM0AE PTM0PE MFI1 — — PTM1AF PTM1PF — — PTM1AE PTM1PE Interrupt Register Contents INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~2INT1S1~INT1S0: interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0INT0S1~INT0S0: interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Rev. 1.00 99 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — INT1F OCPF INT0F INT1E OCPE INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as “0” Bit 6INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 5OCPF: OCP interrupt request flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 2OCPE: OCP interrupt control 0: Disable 1: Enable Bit 1INT0E: INT0 interrupt control 0: Disable 1: Enable Bit 0EMI: Global interrupt control 0: Disable 1: Enable Rev. 1.00 100 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU INTC1 Register Bit 7 6 5 4 3 2 1 0 Name TB1F TB0F MF1F MF0F TB1E TB0E MF1E MF0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 6TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 5MF1F: Multi-function interrupt 1 request flag 0: No request 1: Interrupt request Bit 4MF0F: Multi-function interrupt 0 request flag 0: No request 1: Interrupt request Bit 3TB1E: Time Base 1 interrupt control 0: Disable 1: Enable Bit 2TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 1MF1E: Multi-function interrupt 1 control 0: Disable 1: Enable Bit 0MF0E: Multi-function interrupt 0 control 0: Disable 1: Enable Rev. 1.00 101 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU INTC2 Register Bit 7 6 5 4 3 2 1 0 Name DEF LVF ADF IICF DEE LVE ADE IICE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 6LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 5ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 4IICF: I2C interrupt request flag 0: No request 1: Interrupt request Bit 3DEE: Data EEPROM interrupt control 0: Disable 1: Enable Bit 2LVE: LVD interrupt control 0: Disable 1: Enable Bit 1ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 0IICE: I2C interrupt control 0: Disable 1: Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — PTM0AF PTM0PF — — PTM0AE PTM0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5PTM0AF: PTM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4PTM0PF: PTM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1PTM0AE: PTM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0PTM0PE: PTM0 Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.00 102 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU MFI1 Register Bit 7 6 5 4 3 2 1 0 Name — — PTM1AF PTM1PF — — PTM1AE PTM1PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5PTM1AF: PTM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4PTM1PF: PTM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as “0” Bit 1PTM1AE: PTM1 Comparator A match interrupt control 0: Disable 1: Enable Bit 0PTM1PE: PTM1 Comparator P match interrupt control 0: Disable 1: Enable Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P, Comparator A match or A/D conversion completion etc., the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. Rev. 1.00 103 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. xxF xxF xxE Legend Request Flag� no auto �eset in ISR Request Flag� auto �eset in ISR Inte��upt Name Request Flags Enable Bits �aste� Enable Vector Enable Bits INT0 Pin INT0F INT0E E�I 04H OCP OCPF OCPE E�I 08H INT1 Pin INT1F INT1E E�I 0CH Inte��upt Name Request Flags Enable Bits E�I auto disabled in ISR Hig� PT�0 P PT�0PF PT�0PE PT�0 A PT�0AF PT�0AE �. Fun�t. 0 �F0F �F0E E�I 10H PT�1 P PT�1PF PT�1PE �. Fun�t. 1 �F1F �F1E E�I 14H PT�1 A PT�1AF PT�1AE Time Base 0 TB0F TB0E E�I 18H Time Base 1 TB1F TB1E E�I 1CH I�C IICF IICE E�I �0H A/D ADF ADE E�I �4H LVD LVF LVE E�I �8H EEPRO� DEF DEE E�I �CH Inte��upts �ontained wit�in �ulti-Fun�tion Inte��upts P�io�ity Low Interrupt Structure External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the Rev. 1.00 104 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Over Current Protection Interrupt The OCP Interrupt is controlled by detecting the OCP input current. An OCP Interrupt request will take place when the OCP Interrupt request flag, OCPF, is set, which occurs when a large current is detected. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and OCP Interrupt enable bit, OCPE, must first be set. When the interrupt is enabled, the stack is not full and an over current is detected, a subroutine call to the OCP Interrupt vector, will take place. When the interrupt is serviced, the OCP Interrupt flag, OCPF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL1~CLKSEL0 bits in the PSCR register. TB0[�:0] TB0ON fPSC/�4 ~ fPSC/�11 fSYS fSYS/4 fSUB � U X fPSC CLKSEL[1:0] � U X Time Base 0 Inte��upt � U X Time Base 1 Inte��upt P�es�ale� fPSC/�8 ~ fPSC/�15 TB1ON TB1[�:0] Time Base Interrupt Rev. 1.00 105 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU PSCR Register Bit 7 6 5 4 3 2 Name — — — — — — R/W — — — — — — R/W R/W POR — — — — — — 0 0 3 2 1 0 Bit 7~2 1 0 CLKSEL1 CLKSEL0 Unimplemented, read as “0” Bit 1~0CLKSEL1~CLKSEL0: Prescaler clock source selection 00: fSYS 01: fSYS/4 1x: fSUB TB0C Register Bit 7 6 5 4 Name TB0ON — — — — TB02 TB01 TB00 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7TB0ON: Time Base 0 Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0” Bit 2~0TB02~TB00: Select Time Base 0 Time-out Period 000: 24/fPSC 001: 25/fPSC 010: 26/fPSC 011: 27/fPSC 100: 28/fPSC 101: 29/fPSC 110: 210/fPSC 111: 211/fPSC TB1C Register Bit 7 6 5 4 3 2 1 0 Name TB1ON — — — — TB12 TB11 TB10 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7TB1ON: Time Base 1 Control 0: Disable 1: Enable Bit 6~3 Unimplemented, read as “0” Bit 2~0TB12~TB10: Select Time Base 1 Time-out Period 000: 28/fPSC 001: 29/fPSC 010: 210/fPSC 011: 211/fPSC 100: 212/fPSC 101: 213/fPSC 110: 214/fPSC 111: 215/fPSC Rev. 1.00 106 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU I2C Interrupt An I2C Interrupt request will take place when the I2C Interrupt request flag, IICF, is set, which occurs when a byte of data has been received or transmitted by the I2C interface, I2C address match or I2C time-out. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, IICE, must first be set. When the interrupt is enabled, the stack is not full and any of these situations occurs, will take place. When the I2C Interface Interrupt is serviced, the interrupt request flag, IICF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. LVD Interrupt An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low Voltage Interrupt enable bit, LVE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the LVD interrupt request flag, LVF, will be also automatically cleared. EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the EEPROM interrupt request flag, DEF, will be also automatically cleared. Rev. 1.00 107 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Multi-function Interrupt Within this device there are two Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts will not be automatically reset and must be manually reset by the application program. TM Interrupts The Periodic Type TMs have two interrupts. All of the TM interrupts are contained within the Multifunction Interrupts. For each of the Periodic Type TMs there are two interrupt request flags PTMnPF and PTMnAF and two enable bits PTMnPE and PTMnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.00 108 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 109 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Low Voltage Detector – LVD The device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 Name R/W POR Bit 7~6 6 5 4 3 2 1 0 — — LVDO LVDEN VBGEN VLVD2 VLVD1 VLVD0 — — R R/W R/W R/W R/W R/W — — 0 0 0 0 0 0 Unimplemented, read as “0” Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3VBGEN: Bandgap Buffer Control 0: Disable 1: Enable Note that the Bandgap circuit is enabled when the LVD or LVR function is enabled or when the VBGEN bit is set to 1. Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.00 110 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is in the SLEEP mode, the low voltage detector will be disabled even if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. VDD VLVD LVDEN LVDO tLVDS LVD Operation The Low Voltage Detector also has its own interrupt, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt function to avoid mistake action. Rev. 1.00 111 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Application Circuits Battery Pack Input B+ HV LDO 5V HV B1 T 22μF 0.1µF 0.1µF 5V 100Ω B- 10kΩ AN1 8050 + VCC VDD/AVDD 1μF~ 10μF 11V VDD T 10μF 22Ω T Power Tool Controller VDD VSS/AVSS/VSSH PA0/ICPDA/AN0/PTP0 PA1/OCPI/PTCK0/PTP0B/AN1 B+ + PA2/ICPCK/PTPI/AN2 PA3/VREF/AN3 PA4/AN4/INT0 PA5/AN5 PA6/PTCK1/AN6 PA7/PTP1I/AN7 A - HVO 5 10Ω H level: VCC L level: VSS OCPI OCPI PB1/PTP1B PB2/SDA PB3/SCK 7 Battery Temp. Detection VDD 9 10 11 12 13 14 15 16 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN2 27kΩ 0.1µF Governor Position Detection B1 2Ω AN3 CMP OCP(SCP) PB0/INT1/PTP1 0.1µF ANx(INTERNEL) OPA INT 1 2 3 4 8 DAC 0.1µF 10kΩ Battery Voltage Detection Integrated OCP(SCP) HT45F3630 16SSOP Rev. 1.00 112 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 113 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 114 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract immediate data from ACC with Carry Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,x SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 115 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None None 2Note 2Note 2Note None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Table Read Operation TABRD [m] Read table (specific page) to TBLH and Data Memory TABRDL [m] Read table (last page) to TBLH and Data Memory ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and ITABRDL [m] Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 116 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 2 2Note 2 2Note 2 2Note 2 2Note 2Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 2 2 2 2Note 2Note 2Note 2Note 2 Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 2 2Note 2 2Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 2 2Note 2 2Note 2 2Note 2 2Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory 2 2Note None None Clear bit of Data Memory Set bit of Data Memory 2Note 2Note None None Arithmetic LADD A,[m] LADDM A,[m] LADC A,[m] LADCM A,[m] LSUB A,[m] LSUBM A,[m] LSBC A,[m] LSBCM A,[m] LDAA [m] Logic Operation LAND A,[m] LOR A,[m] LXOR A,[m] LANDM A,[m] LORM A,[m] LXORM A,[m] LCPL [m] LCPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement LINCA [m] LINC [m] LDECA [m] LDEC [m] Rotate LRRA [m] LRR [m] LRRCA [m] LRRC [m] LRLA [m] LRL [m] LRLCA [m] LRLC [m] Data Move LMOV A,[m] LMOV [m],A Bit Operation LCLR [m].i LSET [m].i Rev. 1.00 117 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Branch LSZ [m] LSZA [m] LSNZ [m] LSZ [m].i LSNZ [m].i LSIZ [m] LSDZ [m] LSIZA [m] LSDZA [m] Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if Data Memory is not zero Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note None None None None None None None None None 3Note 3Note 3Note None None None 3Note None 2Note 2Note 2Note 2 None None None None Table Read LTABRD [m] Read table to TBLH and Data Memory LTABRDL [m] Read table (last page) to TBLH and Data Memory LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and LITABRDL [m] Data Memory Miscellaneous LCLR [m] LSET [m] LSWAP [m] LSWAPA [m] Clear Data Memory Set Data Memory Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution. Rev. 1.00 118 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 119 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C Rev. 1.00 120 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None Rev. 1.00 121 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rev. 1.00 122 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rev. 1.00 123 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ SBC A, x Description Operation Affected flag(s) Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None Rev. 1.00 124 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ Rev. 1.00 125 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 126 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBLP and TBHP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRD [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 127 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC LADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC LADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC LADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC LAND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z LANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z LCLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None LCLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None Rev. 1.00 Add Data Memory to ACC 128 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LCPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z LCPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z LDAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C LDEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z LDECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z LINC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z LINCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 129 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LMOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None LMOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None LOR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z LORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z LRL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None LRLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None LRLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C LRLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rev. 1.00 130 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LRR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None LRRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None LRRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C LRRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C LSBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ LSBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Rev. 1.00 131 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LSDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None LSDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None LSET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None LSET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None LSIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None LSIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None LSNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Rev. 1.00 132 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LSNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m] ≠ 0 None LSUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ LSUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ LSWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None LSWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None LSZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None LSZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Rev. 1.00 133 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU LSZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None LTABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LTABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LITABRD [m] Description Operation Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LXOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z LXORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Rev. 1.00 134 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 135 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU 16-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.193 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. — A — 6.000 BSC B — 3.900 BSC — C 0.20 — 0.30 C’ — 4.900 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 136 March 03, 2016 HT45F3630 Power Tool Controller 8-Bit Flash MCU Copyright© 2016 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 137 March 03, 2016