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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300021-E-V10
FR FAMILY
32-BIT MICROCONTROLLER
MB91460 SERIES
START91460.ASM
APPLICATION NOTE
Start91460.asm
Revision History
Revision History
Date
2007-03-30
Issue
UMa
First draft
This document contains 29 pages.
MCU-AN-300021-E-V10
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© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (eg. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu
Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer´s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
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loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
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Contents
Contents
REVISION HISTORY.............................................................................................................. 2
WARRANTY AND DISCLAIMER ........................................................................................... 3
CONTENTS ............................................................................................................................ 4
1 INTRODUCTION................................................................................................................ 5
2 SETTINGS OF THE START91460.ASM ........................................................................... 6
2.1
Controller Device (DEVICE)...................................................................................... 6
2.2
Boot / Flash Security (BOOT_FLASH_SEC) ............................................................ 6
2.3
Stack Type and Stack Size (STACKUSE, …)........................................................... 7
2.3.1
STACKUSE................................................................................................. 7
2.3.2
STACK_RESERVE, STACK_SYS_SIZE, STACK_USR_SIZE .................. 7
2.3.3
STACK_FILL, STACK_PATTERN .............................................................. 8
2.4
Copy code from Flash to I-RAM (I_RAM) ................................................................. 8
2.5
Low-Level Library Interface (CLIBINIT)..................................................................... 9
2.6
C++ startup (CPLUSPLUS)....................................................................................... 9
2.7
Clock Configuration................................................................................................. 10
2.8
2.7.1
Clock Selection (CLOCKSPEED) ............................................................. 10
2.7.2
Select Clock Modulator (CLOMO, CMPR) ................................................ 11
External Bus Interface (EXTBUS) ........................................................................... 13
3 USER CLOCK SETTINGS (CLOCKSPEED == CLOCK_USER) ................................... 14
3.1
Clock source (CLOCKSOURCE, ENABLE_SUBCLOCK) ...................................... 15
3.2
PLL ratio (PLLSPEED)............................................................................................ 16
3.3
PLL Auto Gear-Up and –Down (DIV_G, MUL_G)................................................... 18
3.4
Clock divider (CPUCLOCK, PERCLOCK, EXTBUSCLOCK).................................. 20
3.5
CAN clock (PSCLOCKSOURCE, PSDVC, CANCLOCK) ....................................... 21
3.6
Voltage Regulator (REGULATORCTRL, REGULATORSEL) ................................. 23
3.7
Memory Controller (FLASHCONTROL, FLASHREADT, FLASHMWT2) ................ 25
4 SECTION AND DATA DECLARATION .......................................................................... 28
4.1
Default Sections ...................................................................................................... 28
4.2
Additional Sections.................................................................................................. 29
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Start91460.asm
Chapter 1 Introduction
1 Introduction
All C/C++-language applications need special startup code, which initializes all data areas
generated by the compiler and which performs a basic configuration of the microcontroller.
This document describes the startup file “start91460.asm” version 2.5 or later provided by
Fujitsu
Microelectronics Europe GmbH for the MB91460 series-microcontrollers.
Main Features of the Startup File “start91460.asm”:
- Configuration part for easy step by step set-up of the startup code
- Startup code for pre-setting of core and external bus registers
- Startup code for memory initialization according to FCC911-compiler sections
- Startup file is linkage order independent
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Chapter 2 Settings of the Start91460.asm
2 Settings of the Start91460.asm
The startup file has to be configured for the target system (hardware) and the application
software. The startup file provides several prepared settings, which have to be checked and
which have possibly to be changed. The header of the startup file contains information how
to find the lines containing the options to be checked. All lines with the comment extension
“<<<” were pointing to available settings.
In the following paragraphs all available settings are described.
2.1
Controller Device (DEVICE)
Set the target device the application is running in. This setting is used by the startup file to
check the availability of registers and to check the plausibility of settings.
Available settings for DEVICE:
- MB91464A
- MB91467B
- MB91467C
- MB91467D
- MB91469G
- MB91465K
- MB91463N
- MB91461R
- MB91467R
- MB91465X
- others
Note: This list will be adapted, depending on new devices
Note: The setting “others” should only be used for the case that desired device of the
MB91460 Series is not listed.
Example:
The target controller is the MB91F467DA. This requires the setting.
#set
2.2
DEVICE
MB91467D
; <<< select device
Boot / Flash Security (BOOT_FLASH_SEC)
The most flash devices have two flash and two boot security vectors. It is important to set
the four vectors correctly. Valid boot security vectors means that the build-in bootrom can
not be entered anymore.
Available settings for BOOT_FLASH_SEC:
- OFF: The security feature is switched off. The section SECURITY_VECTORS is reserved
and the vectors are set to 0xFFFFFFFF.
- ON: The security vectors are not set. But the section SECURITY_VECTORS is reserved.
The security vectors have to be set in the user application.
Note: This feature is not available for all devices of the MB91460 Series. The datasheet of
the target device lists the available features.
Note: If the device MB91469G is selected, the section SECURITY_VECTORS is located
from 0x24:8000 – 0x24:800F.
Note: If the ROMless device MB91461R is selected no section SECURITY_VECTORS is
reserved.
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Chapter 2 Settings of the Start91460.asm
Note: For all other devices, including “others” the section SECURITY_VECTORS is located
from 0x14:8000 – 0x14:800F.
Example:
The security feature of target controller should be disabled.
#set
2.3
BOOT_FLASH_SEC
OFF
; <<< BOOT and Flash Security Vector
Stack Type and Stack Size (STACKUSE, …)
2.3.1 STACKUSE
The setting STACKUSE specifies the stack type that is configured, when the application
main()-function is called. The devices of MB91460 Series provide two different types of
stack: system stack and user stack. The application can use either system stack only or it
can use both system stack and user stack.
System stack is always used for interrupt function. It is automatically selected, if hardware
interrupts are executed or if software interrupts are called. All stack operation of interrupt
handlers will work with the system stack.
Outside of interrupt handlers the pre-selected stack type is used. This is either user stack
(option USRSTACK) or system stack (option SYSSTACK). If SYSSTACK is set, only the
system stack area has to be prepared. All operation will work on the same stack. The
necessary safety margin has to be reserved for one stack only. SYSSTACK should be used,
if the necessary RAM consumption for stack has to be low. If USRSTACK is set, both
system stack and user stack have to be prepared. The necessary safety margin has to be
provided twice. USRSTACK should be used, if separated stack areas are necessary for
management reasons. This might be the case with schedulers, operating systems or other
applications.
Available settings for STACKUSE:
- USRSTACK
- SYSSTACK
Example:
The user stack should be used outside of interrupt handlers. This requires the setting.
#set
STACKUSE
USRSTACK
; <<< set active stack
2.3.2 STACK_RESERVE, STACK_SYS_SIZE, STACK_USR_SIZE
These settings specify the amount of bytes to be reserved for stacks. This value has to cover
all:
- parameters passed over stack
- return addresses for function calls
- local variables (except static)
- temporary data due to compiler optimization
- interrupt context on stacks
- safety margin
For estimating necessary stack size the compiler offers the “-INF stack” option. With it the
compiler generates stack information files (extension “stk”), which list the number of bytes
necessary to execute each function. These stack information files are already available for
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Chapter 2 Settings of the Start91460.asm
all library functions and can be found in the Lib\911\ subdirectory of the Softune Workbench
installation.
If the support tool “C-Analyzer” is installed, the additional tool “Musc” is able to collect these
data and to calculate the minimum stack size for the whole application.
Available settings for STACK_RESERVE:
- ON
- OFF
Note: If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this
module. Otherwise, they have to be reserved in other modules. If STACK_RESERVE
is OFF, the size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no
meaning.
Example:
A system stack size of 0x200-4 bytes and a user stack size of 0x400-4 bytes should be
reserved.
#set
;
STACK_RESERVE
ON
; <<< reserve stack area in
;
this module
#set
STACK_SYS_SIZE
0x200-4
; <<< byte size of System stack
#set
STACK_USR_SIZE
0x400-4
; <<< byte size of User stack
2.3.3 STACK_FILL, STACK_PATTERN
With theses settings the stacks can be filled with a specific pattern. Filling the stack with
pattern allows dynamically checking of the stack area, which had already been used.
Available settings for STACK_FILL:
- ON
- OFF
Note: If STACK_ STACK_FILL is OFF, the pattern definition STACK_PATTERN has no
meaning.
Example:
The stacks should be filled with the pattern 0x55AA6699.
#set
STACK_FILL
ON
#set
STACK_PATTERN
0x55AA6699 ; <<< the pattern to write to stack
2.4
; <<< fills the stack area with pattern
Copy code from Flash to I-RAM (I_RAM)
If this option is activated code located in the section IRAM is copied during startup from the
ROM to the instruction RAM. The code is linked for the instruction RAM. This is for example
useful for flash routines, which must be executed in the instruction RAM or for routines,
which should be run in the instruction RAM to benefit from the shorter wait states of the
instruction RAM.
The segment CODE has to be renamed to IRAM for the code, which should be copied the
the instruction RAM during the startup. To rename the segment CODE to IRAM, the
following pragma instruction can be used.
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Chapter 2 Settings of the Start91460.asm
#pragma segment CODE = IRAM
Available settings for I_RAM:
- ON
- OFF
Example:
The code in the segment IRAM should be copied to the instruction RAM during startup.
#set
;
2.5
I_RAM
ON
; <<< select if code
should be copied
in
section IRAM
Low-Level Library Interface (CLIBINIT)
The setting CLIBINI specifies whether the startup code has to call the stream initialization
function of the C-library.
The stream initialization is necessary only, if streamed IO-functions are used. These
functions (e.g. printf()) also require the definition of application specific low-level functions.
For more information refer to the compiler help.
Available settings for CLIBINIT:
- ON
- OFF
Example:
The stream initialization should not be done.
#set
2.6
CLIBINIT
OFF
; <<< select ext. libray usage
C++ startup (CPLUSPLUS)
In the C++ specifications, when external or static objects are used, a constructor must be
called followed by the main function. Because four-byte pointers to the main function are
stored in the EXT_CTOR_DTOR section, call a constructor sequentially from the lower
address of the four addresses in that section. If using C++ sources, activate this function to
create the section EXT_CTOR_DTOR.
Available settings for CPLUSPLUS:
- ON
- OFF
Example:
C++ is not used.
#set
CPLUSPLUS
OFF
© Fujitsu Microelectronics Europe GmbH
; <<< activate if c++ files are used
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Chapter 2 Settings of the Start91460.asm
2.7
Clock Configuration
2.7.1 Clock Selection (CLOCKSPEED)
There are different default configurations available, where all necessary settings for clocks
and the related registers are made. These configurations should not be changed. The
default settings include the settings for the flash access and the regulator configuration, too.
Beside these configurations, there is the possibility to define a user configuration.
Available settings for CLOCKSPEED:
- NO_CLOCK
clock registers are not set by the startup file.
- SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ means:
Main oscillation
= 32 kHz, PLL is not active
CPU clock (CLKB)
= 32 kHz
Peripheral clock (CLKP) = 32 kHz
Ext. bus clock (CLKT)
= 32 kHz
CAN clock (CLKCAN)
= 2 MHz, using main oszillation
- MAIN_4MHZ_CPU___2MHZ_PER__1MHZ_EXT__1MHZ_CAN__2MHZ means:
Main oscillation
= 4 MHz, PLL is not activated
CPU clock (CLKB)
= 2 MHZ
Peripheral clock (CLKP) = 1 MHZ
Ext. bus clock (CLKT)
= 1 MHZ
CAN clock (CLKCAN)
= 2 MHz, using main oszillation
- PLL_4MHZ__CPU__48MHZ_PER_16MHZ_EXT_24MHZ_CAN_16MHZ
Main oscillation
= 4 MHz, PLL is activated
CPU clock (CLKB)
= 48 MHZ
Peripheral clock (CLKP) = 16 MHZ
Ext. bus clock (CLKT)
= 24 MHZ
CAN clock (CLKCAN)
= 16 MHz, using PLLx
- PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ means:
Main oscillation
= 4 MHz, PLL is activated
CPU clock (CLKB)
= 64 MHZ
Peripheral clock (CLKP) = 16 MHZ
Ext. bus clock (CLKT)
= 32 MHZ
CAN clock (CLKCAN)
= 16 MHz, using PLLx
- PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_27MHZ_CAN_20MHZ
Main oscillation
= 4 MHz, PLL is activated
CPU clock (CLKB)
= 80 MHZ
Peripheral clock (CLKP) = 20 MHZ
Ext. bus clock (CLKT)
= 27 MHZ
CAN clock (CLKCAN)
= 20 MHz, using PLLx
- PLL_4MHZ__CPU__80MHZ_PER_20MHZ_EXT_40MHZ_CAN_20MHZ
Main oscillation
= 4 MHz, PLL is activated
CPU clock (CLKB)
= 80 MHZ
Peripheral clock (CLKP) = 20 MHZ
Ext. bus clock (CLKT)
= 40 MHZ
CAN clock (CLKCAN)
= 20 MHz, using PLLx
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Chapter 2 Settings of the Start91460.asm
- PLL_4MHZ__CPU__96MHZ_PER_16MHZ_EXT_48MHZ_CAN_16MHZ
Main oscillation
= 4 MHz, PLL is activated
CPU clock (CLKB)
= 96 MHZ
Peripheral clock (CLKP) = 16 MHZ
Ext. bus clock (CLKT)
= 48 MHZ
CAN clock (CLKCAN)
= 16 MHz, using PLLx
- PLL_4MHZ__CPU_100MHZ_PER_20MHZ_EXT_50MHZ_CAN_20MHZ
Main oscillation
= 4 MHz, PLL is activated
CPU clock (CLKB)
= 100 MHZ
Peripheral clock (CLKP) = 20 MHZ
Ext. bus clock (CLKT)
= 50 MHZ
CAN clock (CLKCAN)
= 20 MHz, using PLLx
- PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
Main oscillation
= 10 MHz, PLL is activated
CPU clock (CLKB)
= 60 MHZ
Peripheral clock (CLKP) = 20 MHZ
Ext. bus clock (CLKT)
= 30 MHZ
CAN clock (CLKCAN)
= 20 MHz, using PLLx
- PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ
Main oscillation
= 20 MHz, PLL is activated
CPU clock (CLKB)
= 60 MHZ
Peripheral clock (CLKP) = 20 MHZ
Ext. bus clock (CLKT)
= 30 MHZ
CAN clock (CLKCAN)
= 20 MHz, using PLLx
- CLOCK_USER means that the user configuration defined in the chapter 3.
Note: Not all frequencies are supported by every device. Please see the hardware manual.
Example:
The default configuration with a core frequency of 64 MHz should be selected.
#set
CLOCKSPEED
PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
2.7.2 Select Clock Modulator (CLOMO, CMPR)
The clock modulator is intended for the reduction of electromagnetic interference - EMI, by
spreading the spectrum of the clock signal over a wide range of frequencies.
Available settings for CLOMO:
- ON
- OFF
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Chapter 2 Settings of the Start91460.asm
Available settings for CMPR (CMPR):
- The available settings depend on the specific device. They are listed in the corresponding
data sheet. Below some values for the MB91F467DA are listed.
For the whole table and the latest inforomation, see the data sheet.
Modulation
Degree
(k)
1
1
1
2
1
1
2
1
1
1
2
3
1
1
1
1
2
2
3
4
1
1
1
1
2
2
3
4
…
Random No
CMPR
Base Clock
Fmin
Fmax
(N)
3
3
5
3
3
5
3
3
5
7
3
3
3
5
7
9
3
5
3
3
3
5
7
9
3
5
3
3
…
[hex]
026F
026F
02AE
046E
026F
02AE
046E
026F
02AE
02ED
046E
066D
026F
02AE
02ED
032C
046E
04AC
066D
086C
026F
02AE
02ED
032C
046E
04AC
066D
086C
…
[MHz]
84
80
80
80
76
76
76
72
72
72
72
72
68
68
68
68
68
68
68
68
64
64
64
64
64
64
64
64
…
[MHz]
76.1
72.6
68.7
68.7
69.1
65.3
65.3
65.5
62
58.8
62
58.8
62
58.7
55.7
53
58.7
53
55.7
53
58.5
55.3
52.5
49.9
55.3
49.9
52.5
49.9
…
[MHz]
93.8
89.1
95.8
95.8
84.5
90.8
90.8
79.9
85.8
92.7
85.8
92.7
75.3
80.9
87.3
95
80.9
95
87.3
95
70.7
75.9
82
89.1
75.9
89.1
82
89.1
…
Note: If the CLKCAN source is set either to main oscillator or to PLLx output then the clock
for the CAN is not influenced by the clock modulation. If the CLKCAN source is set
CPU clock (CLKB) then the clock for the CAN is also modulated if the clock
modulator is enabled.
Note: If the clock modulator is enabled, the wait states of the internal flash wait states must
be adapted to maximum frequency. Check the wait states settings in this case.
Note: This feature is not supported by every device. Check the data sheet if this feature is
available..
Example:
The clock modulator should be enabled and the value of the CMPR should be set to 0x026F.
#set
CLOMO
ON
; <<< Enable /disable clock modulator
#set
CMPR
0x026F
; <<< Ref. to the data sheet, CMPR
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Chapter 2 Settings of the Start91460.asm
2.8
External Bus Interface (EXTBUS)
If the external bus interface is used, it has to be configured properly. Please refer to the
hardware manual and the data sheet for detailed information. The startup file supports the
configuration of the external bus interface.
Available settings for EXTBUS:
- ON
The ext. bus interface is enabled and will be configured.
- OFF
The ext. bus interface is disabled. The port function registers are set
to general I/O. The registers of external bus interface will not be
touched by the startup file.
- DEFAULT
Neither the register nor the respective port function registers are
touched by the startup file.
Note: Not all devices support an external bus interface. The following devices do not offer
an external bus interface: MB91464A, MB91467C, MB91465K, MB91463N,
MB91465X.
Note: Be aware, that the device might startup in external bus mode by default after reset.
Example:
The external bus interface should be configured.
#set
EXTBUS
ON
; <<< Ext. Bus on/off
The startup file supports the configuration of the following registers, too.
- CSER
Chip Select Enable Register
- ASR0-7
Area Select Registers 0-7
- ACR0-7
Area Configuration Registers 0-7
- AWR0-7
Area Wait Registers 0-7
- MCRA
MEMORY SETTING REGISTER for extend type - A for SDRAM/FCRAM auto
- RCR
Refresh control register
- TCR
Pin/Timing Control Register
- CHER
Cache Enable Register
- PFR0 – 10 Port Function Register 0-7
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Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
Beside the default configurations with the settings for clocks and the related registers, there
is the possibility to define a user configuration for the settings. In the following the different
settings are explained. The following figure shows which part of the clock settings can be
configured in the start91460.asm.
Configurable in Start91460.asm
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
1/2
Main Clock SV
Main
Oscillator
Base Clock Φ
PLL Interface x1, x2, …x25
Cntr.
Logic
CLKPLL
4 MHz
Auto-Gear
0 CSVCR_
MSVE
Sub
Oscillator
Ext. Bus Clock
CLKT
1/G
1
PLL
Clock
Modulator
1
0
1/M
DIV1R
2
CMCR, CMPR
x CLKVCO
Divider /1 .. /16
0
1
CMCR_
FMOD
3
CLKR_
CLKS
Sub Clock SV
0
32 kHz
FB
0
1
Cntr.
Logic
CLKPLLFB
DIV0R
1/N
CPU Clock
CLKB
Multiplier
CSVCR_
SSVE
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
Peripheral Clock
CLKP
Divider /1 .. /16
Divider /1 .. /16
DIV0R
CSVCR_
SCKS
100 kHz
CSVCR
RC
Oscillator
0
CAN Clock
CANCLK
0
3
2 MHz
1
CSCFG_
RCSEL
Source Oscillation
1
Clock Supervisor
Base Clock Generator
Divider /1 .. /16
CANPRE_
CPCKS
Operating Clock Generator
CANPRE
CAN Clock Prescaler
Beside the clock settings the startup supports the settings for the voltage regulators and the
wait state settings of the internal flash, too. The clock modulator is not part of the user clock
settings, but part of the general settings.
The user clock settings can be found in the startup91460.asm in the chapter ”5.1
CLOCKSPEED == CLOCK_USER”.
MCU-AN-300021-E-V10
- 14 -
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.1
Clock source (CLOCKSOURCE, ENABLE_SUBCLOCK)
The clock source of the base clock can be configured in the following.
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
1/2
Main Clock SV
Main
Oscillator
Base Clock Φ
PLL Interface x1, x2, …x25
Cntr.
Logic
CLKPLL
4 MHz
Auto-Gear
0 CSVCR_
MSVE
Sub
Oscillator
PLL
1
DIV1R
2
0
1/M
Divider /1 .. /16
0
1
CMCR_
FMOD
3
CLKR_
CLKS
Sub Clock SV
0
FB
CLKPLLFB
0
1
Cntr.
Logic
DIV0R
1/N
CPU Clock
CLKB
Multiplier
CSVCR_
SSVE
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
Divider /1 .. /16
DIV0R
CSVCR_
SCKS
0
CAN Clock
CANCLK
0
3
2 MHz
Peripheral Clock
CLKP
Divider /1 .. /16
CSVCR
100 kHz
RC
Oscillator
Clock
Modulator
CMCR, CMPR
x CLKVCO
32 kHz
RC
Oscillator
Ext. Bus Clock
CLKT
1/G
1
1
CSCFG_
RCSEL
1
Divider /1 .. /16
CANPRE_
CPCKS
CANPRE
Available settings for CLOCKSOURCE:
- NOCLOCK
The clock register are not set by the startup code
- MAINCLOCK
MB91461R: Base clock frequency = ¼ of main clock
Others:
Base clock frequency = ½ of main clock
- MAINPLLCLOCK The PLL (programmable) is used as base clock
- SUBCLOCK
Te sub clock is selected as base clock
Available settings for ENABLE_SUBCLOCK:
- ON
Enable sub clock
- OFF
Sub clock is not enabled
Example:
The PLL should be used and the sub clock should not be enabled.
#set CLOCKSOURCE
MAINPLLCLOCK ;<<< Clocksource
#set ENABLE_SUBCLOCK OFF
© Fujitsu Microelectronics Europe GmbH
;<<< Subclock: ON/OFF
- 15 -
MCU-AN-300021-E-V10
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.2
PLL ratio (PLLSPEED)
The PLL multiplier can be configured individually, but there are recommended settings which
should be used. The table below gives some recommendations. Please check the data
sheet and the hardware manual for updated values.
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
1/2
Main Clock SV
Main
Oscillator
Base Clock Φ
PLL Interface x1, x2, …x25
Cntr.
Logic
CLKPLL
Auto-Gear
0 CSVCR_
MSVE
Sub
Oscillator
PLL
1
DIV1R
2
0
1/M
Divider /1 .. /16
0
1
CMCR_
FMOD
3
CLKR_
CLKS
Sub Clock SV
0
FB
0
1
Cntr.
Logic
CLKPLLFB
DIV0R
1/N
CPU Clock
CLKB
Multiplier
CSVCR_
SSVE
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
Divider /1 .. /16
DIV0R
CSVCR_
SCKS
0
CAN Clock
CANCLK
0
3
2 MHz
Peripheral Clock
CLKP
Divider /1 .. /16
CSVCR
100 kHz
RC
Oscillator
Clock
Modulator
CMCR, CMPR
x CLKVCO
32 kHz
RC
Oscillator
Ext. Bus Clock
CLKT
1/G
1
4 MHz
1
CSCFG_
RCSEL
1
Available settings for PLLSPEED:
- Main clock 4 MHz:
Name
Setting
PLLSPEED
PLLx3
0x0B02
PLLx4
0x0903
PLLx5
0x0704
PLLx6
0x0505
PLLx7
0x0306
PLLx8
0x0307
PLLx9
0x0308
PLLx10
0x0309
PLLx11
0x010A
PLLx12
0x010B
PLLx13
0x010C
PLLx14
0x010D
PLLx15
0x010E
PLLx16
0x010F
PLLx17
0x0110
PLLx18
0x0111
PLLx19
0x0112
PLLx20
0x0113
PLLx21
0x0114
Resulting Base
Clock
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
36 MHz
40 MHz
44 MHz
48 MHz
52 MHz
56 MHz
60 MHz
64 MHz
68 MHz
72 MHz
76 MHz
80 MHz
84 MHz
PLLx22
88 MHz
0x0115
MCU-AN-300021-E-V10
- 16 -
Divider /1 .. /16
CANPRE_
CPCKS
CANPRE
Remark
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
PLLx23
0x0116
92 MHz
PLLx24
0x0117
96 MHz
PLLx25
0x0118
100 MHz
- Main clock 10 MHz (MB91461R only):
Name
Setting
Resulting Base
PLLSPEED
Clock
PLL_10_MHzx2
0x0301
20 MHz
PLL_10_MHzx3
0x0302
30 MHz
PLL_10_MHzx4
0x0303
40 MHz
PLL_10_MHzx5
0x0104
50 MHz
PLL_10_MHzx6
0x0105
60 MHz
PLL_10_MHzx7
0x0106
70 MHz
- Main clock 10 MHz (MB91461R only):
Name
Setting
Resulting Base
PLLSPEED
Clock
PLL_20_MHzx2
0x0301
40 MHz
PLL_20_MHzx3
0x0302
60 MHz
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R,
MB91467D
Remark
Remark
Note: PLLSPEED corresponds to the registers PLLDIVM and PLLDIVN at the addresses
0x48Ch and 0x48Dh.
Note: Never exceed the maximum operation frequency. Check the corresponding data
sheet.
Example:
The PLL should be set to 4 MHz x 16 = 64 MHz.
#set PLLSPEED
0x010F
© Fujitsu Microelectronics Europe GmbH
;<<< 0x48Ch, 0x48Dh: PLLDIVM/N ;
- 17 -
64 MHz
MCU-AN-300021-E-V10
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.3
PLL Auto Gear-Up and –Down (DIV_G, MUL_G)
To avoid voltage drops and surges when switching the clock source from oscillator to high
frequency PLL/DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is
implemented with the PLL interface. The table below gives some recommendations. Please
check the data sheet and the hardware manual for updated values.
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
1/2
Main Clock SV
Main
Oscillator
Base Clock Φ
PLL Interface x1, x2, …x25
Cntr.
Logic
CLKPLL
Auto-Gear
0 CSVCR_
MSVE
Sub
Oscillator
PLL
1
DIV1R
2
0
1/M
Divider /1 .. /16
0
1
CMCR_
FMOD
3
CLKR_
CLKS
Sub Clock SV
0
FB
0
1
Cntr.
Logic
CLKPLLFB
DIV0R
1/N
CPU Clock
CLKB
Multiplier
CSVCR_
SSVE
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
Divider /1 .. /16
DIV0R
CSVCR_
SCKS
0
CAN Clock
CANCLK
0
3
2 MHz
Peripheral Clock
CLKP
Divider /1 .. /16
CSVCR
100 kHz
RC
Oscillator
Clock
Modulator
CMCR, CMPR
x CLKVCO
32 kHz
RC
Oscillator
Ext. Bus Clock
CLKT
1/G
1
4 MHz
1
CSCFG_
RCSEL
1
Divider /1 .. /16
CANPRE_
CPCKS
CANPRE
Available settings for DIV_G (PLLDIVG), MUL_G (PLLMULG):
- Main clock 4 MHz:
Name
Setting DIV_G
PLLx3
0x0F
PLLx4
0x0F
PLLx5
0x0F
PLLx6
0x0F
PLLx7
0x0F
PLLx8
0x0F
PLLx9
0x0F
PLLx10
0x0F
PLLx11
0x0F
PLLx12
0x0F
PLLx13
0x0F
PLLx14
0x0F
PLLx15
0x0F
PLLx16
0x0F
PLLx17
0x0F
PLLx18
0x0F
PLLx19
0x0F
PLLx20
0x0F
PLLx21
0x0F
Setting MUL_G
0x1F
0x1F
0x1B
0x17
0x17
0x17
0x17
0x17
0x0B
0x0B
0x0B
0x0F
0x0F
0x0F
0x0F
0x13
0x13
0x13
0x13
PLLx22
0x17
0x0F
MCU-AN-300021-E-V10
- 18 -
Remark
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
PLLx23
0x0F
0x17
PLLx24
0x0F
0x17
PLLx25
0x0F
0x17
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R
Not: MB91V460A, MB91464A,
MB91465K, MB91463N, MB91467R,
MB91467D
- Main clock 10 MHz (MB91461R only):
Name
Setting DIV_G Setting MUL_G
PLL_10_MHzx2
0x0F
0x1F
PLL_10_MHzx3
0x0B
0x1F
PLL_10_MHzx4
0x0B
0x1F
PLL_10_MHzx5
0x0B
0x1F
PLL_10_MHzx6
0x0B
0x1F
PLL_10_MHzx7
0x0B
0x1F
- Main clock 20 MHz (MB91461R only):
Name
Setting DIV_G Setting MUL_G
PLL_20_MHzx2
0x0B
0x1F
PLL_20_MHzx3
0x0B
0x1F
Remark
Remark
Note: DIV_G corresponds to the register PLLDIVG at the addresses 0x48Eh.
Note: MUL_G corresponds to the register PLLMULG at the addresses 0x48Fh.
Example:
The PLL should be set to 4 MHz x 16 = 64 MHz.
#set DIV_G
#set MUL_G
0x0F
0x0F
© Fujitsu Microelectronics Europe GmbH
;<<< 0x48Eh: PLLDIVG;
;<<< 0x48Fh: PLLMULG;
- 19 -
MCU-AN-300021-E-V10
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.4
Clock divider (CPUCLOCK, PERCLOCK, EXTBUSCLOCK)
The base clock can be divided for the different clock trees. There are clock divider for the
CPU clock (CLKB), the peripheral clock (CLKP) and the external bus interface clock (CLKT).
The divider can be configured independently.
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
1/2
Main Clock SV
Main
Oscillator
Base Clock Φ
PLL Interface x1, x2, …x25
Cntr.
Logic
CLKPLL
Auto-Gear
0 CSVCR_
MSVE
Sub
Oscillator
PLL
1
DIV1R
2
0
1/M
Divider /1 .. /16
0
1
CMCR_
FMOD
3
CLKR_
CLKS
Sub Clock SV
0
FB
0
1
Cntr.
Logic
CLKPLLFB
DIV0R
1/N
CPU Clock
CLKB
Multiplier
CSVCR_
SSVE
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
Divider /1 .. /16
DIV0R
CSVCR_
SCKS
0
CAN Clock
CANCLK
0
3
2 MHz
Peripheral Clock
CLKP
Divider /1 .. /16
CSVCR
100 kHz
RC
Oscillator
Clock
Modulator
CMCR, CMPR
x CLKVCO
32 kHz
RC
Oscillator
Ext. Bus Clock
CLKT
1/G
1
4 MHz
1
CSCFG_
RCSEL
1
Divider /1 .. /16
CANPRE_
CPCKS
CANPRE
Available settings for CPUCLOCK (DIV0R_B), PERCLOCK (DIV0R_P), EXTBUSCLOCK
(DIV1R_T):
Name
Setting
Remark
BASECLOCK_DIV1
0x00
clock = 1/1 base clock
BASECLOCK_DIV2
0x01
clock = 1/2 base clock
BASECLOCK_DIV3
0x02
clock = 1/3 base clock
BASECLOCK_DIV4
0x03
clock = 1/4 base clock
BASECLOCK_DIV5
0x04
clock = 1/5 base clock
BASECLOCK_DIV6
0x05
clock = 1/6 base clock
BASECLOCK_DIV7
0x06
clock = 1/7 base clock
BASECLOCK_DIV8
0x07
clock = 1/8 base clock
BASECLOCK_DIV9
0x08
clock = 1/9 base clock
BASECLOCK_DIV10
0x09
clock = 1/10 base clock
BASECLOCK_DIV11
0x0A
clock = 1/11 base clock
BASECLOCK_DIV12
0x0B
clock = 1/12 base clock
BASECLOCK_DIV13
0x0C
clock = 1/13 base clock
BASECLOCK_DIV14
0x0D
clock = 1/14 base clock
BASECLOCK_DIV15
0x0E
clock = 1/15 base clock
BASECLOCK_DIV16
0x0F
clock = 1/16 base clock
Note: CPUCLOCK corresponds to the register DIV0R_B at the addresses 0x486h.
Note: PERCLOCK corresponds to the register DIV0R_P at the addresses 0x486h.
Note: EXTBUSCLOCK corresponds to the register DIV1R_T at the addresses 0x487h.
Note: Never exceed the maximum operation frequency. Check the corresponding data
sheet.
MCU-AN-300021-E-V10
- 20 -
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
Example:
The base clock frequency is 64 MHz. The CPU clock should run with 64 MHz, the peripheral
with 16 MHz and the external bus clock with 32 MHz.
#set CPUCLOCK
#set PERCLOCK
#set EXTBUSCLOCK
3.5
0x00
0x03
0x01
;<<< 0x486h: DIV0R_B;
;<<< 0x486h: DIV0R_P;
;<<< 0x487h: DIV1R_T;
=> /1 ;
=> /4 ;
=> /2 ;
64 MHz
16 MHz
32 MHz
CAN clock (PSCLOCKSOURCE, PSDVC, CANCLOCK)
The CAN prescaler clock source and source clock divider can be configured in the following.
Main Oscillation
Sub Oscillation
RC Oscillation 100 kHz
Main Clock / 2
Sub Clock
1/2
Main Clock SV
Main
Oscillator
Base Clock Φ
PLL Interface x1, x2, …x25
Cntr.
Logic
CLKPLL
4 MHz
Auto-Gear
0 CSVCR_
MSVE
Sub
Oscillator
PLL
x CLKVCO
1
DIV1R
2
0
1/M
Divider /1 .. /16
0
1
CMCR, CMPR
0
FB
CLKPLLFB
0
1
Cntr.
Logic
CMCR_
FMOD
3
CLKR_
CLKS
DIV0R
1/N
CPU Clock
CLKB
Multiplier
CSVCR_
SSVE
PLLDIVM, PLLDIVG, PLLMULG, PLLCTRL
1
Divider /1 .. /16
DIV0R
CSVCR_
SCKS
0
CAN Clock
CANCLK
0
3
2 MHz
Peripheral Clock
CLKP
Divider /1 .. /16
CSVCR
100 kHz
RC
Oscillator
Clock
Modulator
Sub Clock SV
32 kHz
RC
Oscillator
Ext. Bus Clock
CLKT
1/G
1
1
CSCFG_
RCSEL
1
Divider /1 .. /16
CANPRE_
CPCKS
CANPRE
Available settings for PSCLOCKSOURCE (CANPRE):
- PSCLOCK_CLKB
The CLKB is the clock source for the CAN clock prescaler.
- PSCLOCK_PLL
The CLKVCO is the clock source for the CAN clock prescaler.
- PSCLOCK_MAIN
The main oscillation is the clock source for the CAN clock prescaler.
The following table shows the selectable prescaler source clock frequency depending on the
selectable PLL multiplier. The frequencies are only valid; if the settings for the PLL
multiplication are the ones, defined above.
- Main clock 4 MHz:
PLL Multiplier
PLLx3
PLLx4
PLLx5
PLLx6
PLLx7
PLLx8
PLLx9
PLLx10
PLLx11
PLLx12
PSCLOCK_CLKB
(CLKB)
12 MHz
16 MHz
20 MHz
24 MHz
28 MHz
32 MHz
36 MHz
40 MHz
44 MHz
48 MHz
© Fujitsu Microelectronics Europe GmbH
PSCLOCK_PLL
(CLKVCO)
144 MHz
160 MHz
160 MHz
144 MHz
112 MHz
128 MHz
144 MHz
160 MHz
88 MHz
96 MHz
- 21 -
PSCLOCK_MAIN
(Main Oszillation)
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
MCU-AN-300021-E-V10
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
PLLx13
PLLx14
PLLx15
PLLx16
PLLx17
PLLx18
PLLx19
PLLx20
PLLx21
PLLx22
PLLx23
PLLx24
PLLx25
52 MHz
56 MHz
60 MHz
64 MHz
68 MHz
72 MHz
76 MHz
80 MHz
84 MHz
88 MHz
92 MHz
96 MHz
100 MHz
104 MHz
112 MHz
120 MHz
128 MHz
136 MHz
144 MHz
152 MHz
160 MHz
168 MHz
176 MHz
184 MHz
192 MHz
200 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
4 MHz
- Main clock 10 MHz (MB91461R only):
PLL Multiplier
PSCLOCK_CLKB
(CLKB)
PLL_10_MHzx2
20 MHz
PLL_10_MHzx3
30 MHz
PLL_10_MHzx4
40 MHz
PLL_10_MHzx5
50 MHz
PLL_10_MHzx6
60 MHz
PLL_10_MHzx7
70 MHz
PSCLOCK_PLL
(CLKVCO)
160 MHz
120 MHz
160 MHz
100 MHz
120 MHz
140 MHz
PSCLOCK_MAIN
(Main Oszillation)
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
- Main clock 20 MHz (MB91461R only):
PLL Multiplier
PSCLOCK_CLKB
(CLKB)
PLL_20_MHzx2
40 MHz
PLL_20_MHzx3
60 MHz
PSCLOCK_PLL
(CLKVCO)
160 MHz
120 MHz
PSCLOCK_MAIN
(Main Oszillation)
20 MHz
20 MHz
Available settings for PSDVC (CANPRE_DVC):
- The devisor can be configured in the range of 1 to 16, with 0x0 means a devisor of 1 and
0xf a devisor of 16.
Available settings for CANCLOCK (CANCKD):
- Each can clock can be enabled or disabled independently, with ‘0’ the CAN clock can be
enabled and with ‘1’ the CAN clock can be disabled.
- B'0 0 0 0 0 0 0 0
| | | | | | | |
| | | | | | | |_____
| | | | | | |_______
| | | | | |_________
| | | | |___________
| | | |_____________
| | |_______________
| |_________________
|___________________
CAN 0
CAN 1
CAN 2
CAN 3
CAN 4
CAN 5
reserved (always ‘0’)
reserved (always ‘0’)
Not every CAN-Channel is supported by every device. Please check the data sheet.
Note: If the CLKCAN source is set either to main oscillator or to PLL output then the clock
for the CAN is not influenced by the clock modulation.
If the CLKCAN source is set core clock CLKB then the clock for the CAN is also
modulated (if the clock modulator is enabled).
MCU-AN-300021-E-V10
- 22 -
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
Note: For the maximum permitted frequency, please see the data sheet.
Note: If prescaler source is selected to PLL output: Even though it is possible to select no
division ratio (:1) for the divide-by-C counter it is not recommended. The resulting
output clock will have an odd clock duty ratio (direct PLL output can have up to 90:10
duty). Always select at least a division ratio > 1.
Example:
The PLL x output should be used as prescaler clock source, which has in this example 128
MHz. The prescaler should output 16 MHz. All CAN clocks should be enabled.
#set PSCLOCKSOURCE PSCLOCK_PLL ;<<< 0x4C0h: CANPRE;
=> PLLx ; 128 MHz
#set PSDVC
0x07
;<<< 0x4C0h: CANPRE_DVC; => /8
; 16 MHz
#set CANCLOCK
0x00
;<<< 0x4C1h: CANCKD; all CAN Clks enabled
3.6
Voltage Regulator (REGULATORCTRL, REGULATORSEL)
With the following settings the behavior of the main-regulator and sub-regulator in the device
modes can be configured. The main-regulator can be enabled and disabled independently
for Sub-run and STOP/RTC and the sub regulator output voltage for sub-run and STOP/RTC
can be controlled.
The settings may depend on the configuration of the PLL frequency, the wait state settings
of the internal flash interface, the device and the access type. Therefore it is necessary to
check the data sheet.
The following table shows the settings for the main and the flash regulator of MB91F469G
for flash read. Please check the latest data sheet for later information.
Core Clock (CLKB)
to 20 MHz
to 32 MHz
to 44 MHz
to 48 MHz
to 88MHz
to 100MHz
1.8 V Operation of
main regulator and Flash?
Yes
Yes
Yes
No
Yes
No
1.9 V Operation of
main regulator and Flash?
Yes
Yes
Yes
Yes
Yes
Yes
Available settings for REGULATORCTRL (REGCTR):
- B'0 0 0 0 0 0 0 0
| | | | | | | |
| | | | | | | |_____
| | | | | | |_______
| | | | | |_________
| | | | |___________
| | | |_____________
| | |_______________
| |_________________
|___________________
MAINDSBL
MAINKPEN
Reserved
Reserved
MSTBO (read only)
Reserved
Reserved
Reserved
BIT[7:5]:
Reserved
BIT[4]:
MSTBO - Main regulator Standby output flag. (read only)
© Fujitsu Microelectronics Europe GmbH
- 23 -
MCU-AN-300021-E-V10
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
BIT[3:2]:
Reserved
BIT[1]:
MAINKPEN - Main Regulator enable in STOP/RTC mode.
- 0 - Main regulator disabled in STOP/RTC mode [Initial value]
- 1 - Main regulator enabled in STOP/RTC mode
BIT[0]:
MAINDSBL - Main Regulator disable in Sub-run Mode.
- 0 - Main regulator enabled in Sub-run mode [Initial value]
- 1 - Main regulator disabled in Sub-run mode
Available settings for REGULATORSEL (REGSEL):
- B'0 0 0 0 0 0 0 0
| | | | | | | |
| | | | | | | |
| | | | | | | |_____
| | | | | | |_______
| | | | | |_________
| | | | |___________
| | | |_____________
| | |_______________
| |_________________
|___________________
SUBSEL0
SUBSEL1
SUBSEL2
SUBSEL3
MAINSEL
FLASHSEL
Reserved
Reserved
BIT[7:6]:
Reserved
BIT[5]:
FLASHSEL - Flash memory supply mode.
- 0 - Flash memory operation mode is 1.8V [Initial value]
- 1 - Flash memory operation mode is 1.9V
BIT[4]:
MAINSEL - Main Regulator supply mode.
- 0 - Main regulator operation mode is 1.8V [Initial value]
- 1 - Main regulator operation mode is 1.9V
BIT[3:0]:
SUBSEL[3:0] - Sub-regulator voltage level
- 0111 - 1.9V +/- 0.1V
- 0110 - 1.8V +/- 0.1V (initial)
- 0101 - 1.7V +/- 0.1V
- 0100 - 1.6V +/- 0.1V
- 0011 - 1.5V +/- 0.1V
- 0010 - 1.4V +/- 0.1V
- 0001 - 1.3V +/- 0.1V
- 0000 - 1.2V +/- 0.1V
Note: The set level of the Sub-regulator voltage is only be effective in case of Main
Regulator is switched off. Otherwise (with main regulator on) the default level is
applied internally by hardware to the Sub-Regulator (the register setting is not
changed in this case and will be applied next time the main regulator is switched off).
Example:
Main and flash operation mode should be 1.8 V and the sub regulator voltage should be set
to 1.8 V, too.
#set REGULATORCTRL
#set REGULATORSEL
MCU-AN-300021-E-V10
0x00
0x06
;<<< 0x4CFh: REGCTR;
;<<< 0x4CEh: REGSEL;
- 24 -
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
3.7
Memory Controller (FLASHCONTROL, FLASHREADT, FLASHMWT2)
The memory controller must be configured, depending on the core frequency and the target
device. The startup file allows configuring the registers FCHCR, FMWT and FMWT2.
The following table shows the settings for the MB91F469G for flash read. Please check the
latest data sheet for later information.
Core clock (CLKB)
to 20 MHz
to 32 MHz
to 44 MHz
to 48 MHz
to 88 MHz
to 100 MHz
ATD
0
0
0
0
1
1
ALEH
0
0
0
0
1
1
EQ
0
1
3
1
3
3
WEXH
-
WTC
1
2
3
2
4
4
The following table shows the settings for the MB91F467D for flash read. Please check the
latest data sheet for later information.
Core clock (CLKB)
to 24 MHz
to 48 MHz
to 96 MHz
ATD
0
0
1
ALEH
0
0
1
EQ
0
1
3
WEXH
0
0
0
WTC
1
2
4
Available settings for FLASHCONTROL (FCHCR):
- B'0000000000000000
||||||||||||||||
||||||||||||||||__
|||||||||||||||___
||||||||||||||____
|||||||||||||_____
||||||||||||______
|||||||||||_______
||||||||||________
|||||||||_________
||||||||__________
|||||||___________
||||||____________
|||||_____________
||||______________
|||_______________
||________________
|_________________
SZ0
bit
SZ1
bit
ENAB bit
LOCK bit
PFMC bit
PFEN bit
DBEN bit
FLUSH bit
TAGE bit
REN
bit
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BIT[9]:
REN - Non-cacheable area Range Enable
- 0 - FCHA1 defines address mask (default)
- 1 - FCHA1 defines second point for the non-cacheable address range from
FCHA0 to FCHA1
BIT[8]:
TAGE - TAG RAM access Enable
- 0 - Memory mapped TAG RAM access disabled (default)
- 1 - Memory mapped TAG RAM access enabled
BIT[7]:
FLUSH - Flush instruction cache entries
0 - Flushing the instruction cache entries has been completed
1 - Actually flushing the instruction cache entries
© Fujitsu Microelectronics Europe GmbH
- 25 -
MCU-AN-300021-E-V10
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
BIT[6]:
DBEN - Data Buffer Enable
- 0 - Buffering of read data is disabled (default)
- 1 - Buffering of read data is enabled
BIT[5]:
PFEN - PreFetch Enable
- 0 - Prefetch of instructions is disabled (default)
- 1 - Prefetch of instructions is enabled
BIT[4]:
PFMC - Prefetch Miss Cache enable
- 0 Standard cache algorithm (default)
- 1 Prefetch misses are cached only
BIT[3]:
LOCK - Global lock of cache entries
- 0 - Write of cache entries enabled (default)
- 1 - Writing of cache entries is disabled, the cache contents is locked
BIT[2]:
ENAB - Instruction cache enable
- 0 - The instruction cache is disabled (default)
- 1 - Enable the instruction cache
BIT[1:0]:
SZ[1:0] - Cache size configuration (only valid for MB91V460)
- 00 - 0kByte - Cache disabled
- 01 - 4kByte (1024 entries)
- 10 - 8kByte (2048 entries)
- 11 - 16kByte (4096 entries) (default)
Available settings for FLASHREADT (FMWT):
- B'0000000000000000
||||||||||||||||
||||||||||||||||__
|||||||||||||||___
||||||||||||||____
|||||||||||||_____
||||||||||||______
|||||||||||_______
||||||||||________
|||||||||_________
||||||||__________
|||||||___________
||||||____________
|||||_____________
||||______________
|||_______________
||________________
|_________________
EQ0
EQ1
EQ2
EQ3
ATD0
ATD1
ATD2
FRAM
WTC0
WTC1
WTC2
WTC3
WEXH0
WEXH1
WTP0
WTP1
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
bit
WTP[1:0]:
- Wait cycles for FLASH in page access
WEXH[1:0]:
- Minimum WEX High timing requirement
WTC[3:0]:
- Wait cycles for FLASH memory access
FRAM:
- Wait cycles for F-Bus general purpose RAM memory access
ATD[2:0]:
- Duration of the ATDIN signal for FLASH memory access
EQ[3:0]:
- Duration of the EQIN signal for FLASH memory access
MCU-AN-300021-E-V10
- 26 -
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 3 User Clock Settings (CLOCKSPEED == CLOCK_USER)
Available settings for FLASHMWT2 (FMWT2):
- B'00000000
||||||||
||||||||__
|||||||___
||||||____
|||||_____
||||______
|||_______
||________
|_________
ALEH[2:0]:
Reserved
ALEH2
ALEH1
ALEH0
Reserved
Reserved
Reserved
Reserved
- Duration of the ALEH time for FLASH memory access
Example:
The memory controller should be configured for the MB91F467D. The core frequency should
be 64 MHz.
#set FLASHCONTROL
#set FLASHREADT
#set FLASHMWT2
0x032
0xC413
0x10
© Fujitsu Microelectronics Europe GmbH
;<<< 0x7002h: FCHCR;
;<<< 0x7004h: FMWT;
;<<< 0x7006h: FMWT2;
- 27 -
MCU-AN-300021-E-V10
Start91460.asm
Chapter 4 Section and Data Declaration
4 Section and Data Declaration
The ANSI specification requires that global data are initialised. This has to be done by the
startup code. However, the compiler has to provide a mechanism to collect those data,
which have to be cleared (set to zero) and those data, which have to be pre-loaded with a
value. The FCC911S provides default sections, which contain dedicated groups of data. A
section is a unit that can be handled by the linker. It either contains initialised data or
reserved areas. All sections used in an application can be found in the linkage map after
linking project.
4.1
Default Sections
The compiler FCC911S has the following default sections
Section Type
Section Name
Type
Bondary
Alignment
[Byte]
Write
Initial Value
Code section
CODE
CODE
2
Disabled
Provided
Initialized section
INIT
DATA
4
Enabled
Provided
Constant section
CONST
CONST
4
Disabled
Provided
Data section
DATA
DATA
4
Enabled
Not Provided
I/O section
IO
IO
4
Enabled
Not Provided
Vector section
INTVECT
CONST
4
Disabled
Provided
C++ Init section
EXT_CTOR_DTOR
CONST
4
Disabled
Provided
Code section: The code section stores machine codes. This section corresponds to the
procedure section for the C language.
Initialized section: The initialized section stores the initial value attached variable area. For
the C language, this section corresponds to the area for external variables without the const
attribute, static external variables, and static internal variables. The ANSI specification
requires that global data are initialised. This is done during the startup code.
Constant section: The constant section stores the write-protected initial value attached
variable area. For the C language, this section corresponds to the area for const attribute
attached external variables, static external variables, and static internal variables.
Data section: The data section stores the area for variables without the initial value. For the
C language, this section corresponds to the area for external variables (including those
which are with the const attribute), static external variables, and static internal variables. The
ANSI specification requires that data section must be cleared. This is done during the startup
code.
I/O section: I/O section stores the area for the __io-qualified variables. For the C language,
this section corresponds to the area for __io-qualified external variables (including those
which are provided with the const attribute), static external variables, and static internal
variables. The default section name is IO.
Vector section: This section is where interrupt vector tables are stored. In C, a vector table is
generated only when its generation is specified in #pragma intvect. The default section name
is INTVECT.
C++ Init section: This section is where tables for indicating the entry of functions constituting
and destroying static objects are stored. It must be used at startup.
MCU-AN-300021-E-V10
- 28 -
© Fujitsu Microelectronics Europe GmbH
Start91460.asm
Chapter 4 Section and Data Declaration
4.2
Additional Sections
Beside the default sections, the startup defines, depending on the settings several
additional settings.
Section Type
Section Name
Type
Bondary
Alignmen
t [Byte]
Write
Initial Value
Start section
CODE_START
CODE
4
Disabled
Provided
System stack
SSTACK
DATA
4
Enabled
Not Provided
User stack
USTACK
DATA
4
Enabled
Not Provided
Security vectors
SECURITY_VECTORS
CODE
4
Disabled
Provided
Instruction RAM
Section
IRAM
CODE
4
Disabled
Provided
Start section: This section stores the startup.
System stack: This section is where the system stack is located. The size of the system
stack can be defined in the startup code.
User stack: This section is where the user stack is located. The size of the user stack can be
defined in the startup code.
Security vectors: This section stores the security vectors.
Instruction RAM Section: This section stores the code, which should be executed in the
IRAM.
© Fujitsu Microelectronics Europe GmbH
- 29 -
MCU-AN-300021-E-V10
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