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Fujitsu Microelectronics Europe
Application Note
MCU-AN-300054-E-V13
FR FAMILY
32-BIT MICROCONTROLLER
MB91460
I/O PORTS
APPLICATION NOTE
I/O PORTS
Revision History
Revision History
Date
2008-01-25
2008-03-20
2008-04-24
2009-09-27
Issue
V1.0, First release, MPi
V1.1, MSt some typos corrected
V1.2, Type in Title page corrected, MSt
V1.3, Added chapter “Using the same IO-port…” MHz
This document contains 20 pages.
MCU-AN-300054-E-V13
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© Fujitsu Microelectronics Europe GmbH
I/O PORTS
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (eg. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu
Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer´s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer´s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
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loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
-3-
MCU-AN-300054-E-V13
I/O PORTS
Contents
Contents
REVISION HISTORY.............................................................................................................. 2
WARRANTY AND DISCLAIMER ........................................................................................... 3
CONTENTS ............................................................................................................................ 4
1 INTRODUCTION................................................................................................................ 6
1.1
Key features .............................................................................................................. 6
2 THE I/O-PORT ................................................................................................................... 7
2.1
Block Diagram........................................................................................................... 7
2.2
Registers ................................................................................................................... 8
2.3
2.2.1
Port Input Enable (PORTEN) ........................................................................ 8
2.2.2
Port Data Register (PDR)............................................................................. 8
2.2.3
Data Direction Register (DDR) ..................................................................... 8
2.2.4
Port Data Register Direct Read (PDRD)....................................................... 9
2.2.5
(Extra) Port Input Level Register (PILR, EPILR) ........................................ 9
2.2.6
Port Output Drive Register (PODR) .............................................................. 9
2.2.7
Port Pull-up/Pull-down Enable and Control Register (PPER, PPCR)............ 9
2.2.8
(Extra) Port Function Register (PFR, EPFR) ................................................ 9
Input Mode .............................................................................................................. 10
2.3.1
Digital Port Input........................................................................................ 10
2.3.2
Resource Input.......................................................................................... 11
2.4
Configuring Pull-up or Pull-down resistor................................................................ 11
2.5
Output-mode ........................................................................................................... 12
2.5.1
Digital Port Output..................................................................................... 12
2.5.2
Resource Output ....................................................................................... 12
3 PORT INPUT / UNUSED PINS ........................................................................................ 13
3.1
Port Input / Unused Pins ......................................................................................... 13
4 TECHNICAL INFORMATION .......................................................................................... 14
4.1
Hysteresis Inputs..................................................................................................... 14
5 USING THE SAME I/O PORT SIMULTANEOUSLY AS IN- AND OUTPUT ................... 15
6 TIPS AND TRICKS .......................................................................................................... 17
6.1
Initial Value ............................................................................................................. 17
6.2
Bit Instructions ........................................................................................................ 17
6.3
RMW Instructions.................................................................................................... 17
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I/O PORTS
Contents
7 ADDITIONAL INFORMATION......................................................................................... 18
LIST OF FIGURES ............................................................................................................... 19
LIST OF TABLES................................................................................................................. 20
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
Chapter 1 Introduction
1 Introduction
The I/O-port functionality is the simplest peripheral function of the Fujitsu FR microcontroller.
Nevertheless, some details should be considered while programming. This application note
reflects the functionality and describes the different modes.
Please note that in this document each port number is given with the 2-digit placeholder “xy”.
“z” always means the bit position 0 – 7.
Example: “PDR02_D3” means Port 02 Bit 3.
1.1
Key features
•
Port direction settable
•
Global port enable for port inputs
•
Usage of I/O Port or Resource Pin 1/2, both states readable
•
Input can be disabled, if corresponding pin is unused
•
Internal pull-up/pull-down resistor can be enabled
•
Input level can be set to CMOS Hysteresis A (0307), CMOS Hysteresis B (0208),
Automotive Hysteresis and TTL
•
Output drive strength can be set
•
In STOP-HIZ state all pins are switched to input high impedance state
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I/O PORTS
Chapter 2 The I/O-port
2 The I/O-port
BASIC FUNCTIONALITY OF THE I/O PORTS
2.1
Block Diagram
Figure 2-1 shows the internal block diagram of an external I/O-pin.
Up to 8 I/O-pins may be encapsulated into one port and one register set. The registers are
described below.
Figure 2-1: I/O-port block diagram
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
Chapter 2 The I/O-port
2.2
Registers
2.2.1 Port Input Enable (PORTEN)
This registers globally enable the inputs.
Bit
No.
7-2
Name
Initial
Value
X
Explanation
Undefined
-
Bootloader
CPORTEN Communication
Port Enable
1
0
GPORTEN
Value
Operation
0
Reserved Bit , always write “0” to it
Inputs of bootloader
communication ports are disabled
Inputs of bootloader
communication ports are enabled
Inputs of all ports are disabled
Inputs of all ports are enabled
0
0
1
General Port
Enable
0
1
0
Table 2-1: PORTEN
2.2.2 Port Data Register (PDR)
This register contains the data bits, if the corresponding port acts as a simple digital output.
The contents are output, if the Port Direction Register is set to output mode.
Please note that a resource output control bit overwrites the PDR bit value.
PDRxy_Dz
0
1
Pin Function
Pin State Low (VSS)
Pin State High (VDD)
Table 2-2: PDR
The read value of PDR register depends on the following:
− The corresponding bit in DDR and PFR register
− The type of instruction used (Read/Read-modify-write)
The following table describes the above discussed behaviour:
PFR Value
DDR Value
0
0 (Input)
0
1 (Output)
Write
Writes the PDR
setting value, has no
effect on the pin
value
Writes the PDR
setting value to the
corresponding
external pins
PDR
Read
Read-modify-write
Reads the
sampled pin data
Always writes the
PDR setting value
Reads the PDR
register value
Always writes the
PDR setting value
Table 2-3: Reading PDR
2.2.3 Data Direction Register (DDR)
This register contains the bit information of the corresponding pins if they should act as input
or output.
DDRxy_Dz
0
1
Pin Function
Port Input
Port Output
Table 2-4: DDR
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I/O PORTS
Chapter 2 The I/O-port
2.2.4 Port Data Register Direct Read (PDRD)
This register samples the pin data with CLKP. It is read-only.
2.2.5 (Extra) Port Input Level Register (PILR, EPILR)
The input levels of each port can be programmed bit-wise using PILR and EPILR registers.
PILRxy_Dz
0
1
0
1
EPILRxy_Dz
0
0
1
1
Input Level
CMOS Hysteresis A (0307)
Automotive Hysteresis
TTL
CMOS Hysteresis B (0208)
VIL
0.3 VDD
0.5 VDD
0.8 V
0.2 VDD
VIH
0.7 VDD
0.8 VDD
2.1 V
0.8 VDD
Table 2-5: PILR, EPILR
2.2.6 Port Output Drive Register (PODR)
With these registers the strength of the output current of a pin can be adjusted to improve
the EMI behaviour. This setting does not limit the output drive to the given values. The
output must not exceed these values to guarantee the specified Output levels. See also
Datasheet of MB91F46x series.
PODRxy_Dz
0
1
Output Current
5 mA output drive
2 mA output drive
Table 2-6: PODR
2.2.7 Port Pull-up/Pull-down Enable and Control Register (PPER, PPCR)
These registers enable and connect an internal pull-up or pull-down resistor to a port pin.
PPERxy_Dz
0
1
1
PPCRxy_Dz
x
0
1
Pull-Up Resistor
Pull-up/ Pull-down Disabled
Pull-down is selected
Pull-up is selected
Table 2-7: PPER, PPCR
The nominal value for this pull-up resistor is 50 kΩ.
2.2.8 (Extra) Port Function Register (PFR, EPFR)
PFR along with EPFR configures the certain port as general purpose I/O or resource 1
(input/output) or resource 2 (input/output), if available. It should be noted that PFR is
available for all the ports where as EPFR is available for selected ports.
The following table gives an example of this.
PFR19_D2
0
1
1
EPFR19_D2
X
0
1
Pin Function
General Purpose I/O
SCK5 input/output
CK5 input
Table 2-8: PFR, EPFR
For more details please refer the hardware manual.
© Fujitsu Microelectronics Europe GmbH
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Chapter 2 The I/O-port
2.3
Input Mode
In general, if a pin should acts as a digital input, the PORTEN register should be set to 0x03
in order to globally enable the inputs
2.3.1 Digital Port Input
The following example shows the register configuration that needs to be done on MB91460
Series, if a pin should act as a digital input:
PFR19_D4 = 0;
DDR19_D4 = 0;
PORTEN = 0x03;
// Port 19 pin 4 as general purpose i/o
// data direction - input
// global port input enable
As shown above, first the PORTEN register should be set to 0x03. Then the corresponding
bit of PFR register should be set to 0 in order to configure port 19 pin 4 as general purpose
i/o and finally the corresponding bit of DDR register should be set to 0.
After configuring a pin as digital port input, the level of the input pin can be determined as
follows:
if ( 1 == PDR19_D4 )
{
// do something
}
else
{
// do something
}
// if pin high?
// pin low
Additionally the level of the input pin can also be read out via the PDRD register (2.2.4) as
follows:
if ( 1 == PDRD19_D4 )
{
// do something
}
else
{
// do something
}
// if pin high?
// pin low
Optionally the input level can be set via the PILR and EPILR registers (2.2.5) as follows:
PILR19_D4 = 1;
EPILR19_D4 = 1;
// set input detection level as CMOS hysterisis
// B(0208)
//
If the connected external source may change to high-Z state, please use an external pull-up
or –down resistor or configure the internal pull-up or pull-down resistor using PPER and PPCR
(2.2.7) registers.
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I/O PORTS
Chapter 2 The I/O-port
2.3.2 Resource Input
The following example shows the register configuration that needs to be done on MB91460
Series, if a pin should act as resource input (clock input for Free-run timer 4):
PFR19_D2 = 1;
EPFR19_D2 = 1;
PORTEN = 0x03;
// Port 19 pin 2 as resource function
// Port 19 pin 2 as CK4 input
// global port input enable
In addition too the above the ECLK bit of TCCS4 register should be set as 1 in order to select
the external clock for Free-run timer 4.
Optionally the input level can be set via the PILR and EPILR registers (2.2.5), if required
and also the pull-up or pull-down resistor can be configured using PPER and PPCR registers,
if required.
2.4
Configuring Pull-up or Pull-down resistor
All ports while in input-mode (digital input as well as resource input) have the possibility to
enable and configure an internal pull-up/pull-down resistor (about 50 kΩ) by programming
the PPER and PPCR (2.2.7).
It should be noted that the PPCR can only be changed while the corresponding bit of PPER 0
i.e. pull-up/pull-down disabled. If the PPCR is written with a different value while pull-up/pull
down enabled then the new PPCR setting would not be effective.
The following example code shows how to do the same:
. . .
. . .
PPER19_D4 = 0;
PPCR19_D4 = 0;
PPER19_D4 = 1;
PORTEN = 0x03;
//
//
//
//
disable pull-up/pull-down on port 19 pin 4
configure pull-down on port 19 pin 4
re-enable pull-down on port 19 pin 4
global port input enable
. . .
. . .
If the port-pin is used as an output, the values of corresponding bits of these registers have
no meaning and the pull-up/pull-down resistor is disabled.
Enabled pull-up resistors will be disabled while the microcontroller is in STOP-HIZ state.
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
Chapter 2 The I/O-port
2.5
Output-mode
2.5.1 Digital Port Output
The following example shows the register configuration that needs to be done on MB91460
Series, if a pin should act as a digital output:
PFR19_D4 = 0;
PDR19_D4 = 0;
DDR19_D4 = 1;
PORTEN = 0x03;
//
//
//
//
//
//
//
Port 19 pin 4 as general purpose i/o
clear output before setting the data direction,
this is required to guarantee the initial value
when the data direction is set as output
data direction - output
this configuration is required only if the external
pin status needs to be read via PDRD
Optionally the output current strength can be set by the PODR register (2.2.6) as follows:
PODR19_D4 = 1;
// 2mA output drive
2.5.2 Resource Output
The following example shows the register configuration that needs to be done on MB91460
Series, if a pin should act as resource output (output for Reload Timer 7):
PFR15_D7 = 1;
EPFR15_D7 = 1;
PORTEN = 0x03;
//
//
//
//
Port 15 pin 7 resource output
Port 15 pin 7 as TOT7 output
this configuration is required only if the external
pin status needs to be read via PDRD
Optionally the output current strength can be set by the PODR register (2.2.6).
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I/O PORTS
Chapter 3 Port Input / Unused Pins
3 Port Input / Unused Pins
How to connect Input Port Pins and how to proceed with unused Pins
3.1
Port Input / Unused Pins
It is strongly recommended not to leave the pins unconnected, while they are switched to
input and are enabled (by PORTEN register). In this case those pins can enter a so-called
floating state. This can cause a high ICC current, which is adverse to low power modes. Also
damage of the MCU may happen.
In such cases, it is highly recommended to use the internal pull-up/pull-down resistors.
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
Chapter 4 Technical information
4 Technical information
ELECTRICAL CHARACTERISTICS OF THE INPUT HYSTERESIS
4.1
Hysteresis Inputs
A hysteresis describes the behaviour of an input pin where the input level at which ‘1’ is
detected, and the level at which ‘0’ is detected are different.
The levels are described in chapter 2.2.5.
Kindly note that the power supply current i.e. the power consumption of the device may
increase, while the input voltage is within the hysteresis
ysteresis area, however the input current of
the I/O pin remains constant.
Detected
Level
1
Hysteresis
0
VI [V]
0V
Vil
VIH
5V
Input
current
Clamping diode
Leakage current
VI [V]
5V
Power supply
current
Clamping diode
VI [V]
Figure 4-1: Hysteresis
VIL
VIH
MCU-AN-300054-E-V13
5V
Port hysteresis input level (low-level) specified in the datasheet
Port hysteresis input level (high-level) specified in the datasheet
Real hysteresis area
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© Fujitsu Microelectronics Europe GmbH
I/O PORTS
Chapter 5 Using the same I/O port simultaneously as in- and output
5 Using the same I/O port simultaneously as in- and output
THIS CHAPTER EXPLAINS USING ONE PIN SIMULTANEOUSLY AS IN- AND OUTPUT
With the circuit shown in figure 6.1, enabled internal pull-up resistor, pin state set low and
some small considerations in the software it’s possible to use the same port simultaneously
as input and output – for polling the key button and driving a LED at the same pin.
If the port is used as output the LED is on. If the port is used as input the LED is off and the
key button’s status can be polled.
Vcc
LED
Internal pull-up
MCU pin
Key button
External circuit
MCU internal
GND
Figure 5-1: I/O-port example circuit
When the port direction is changed from output to input, the pin’s level becomes high. The
high-level is not reached immediately after the port’s DDR register is set to input.
Some minor parasitic capacities (~ 30 pF) caused by chip-internal capacities and by the
PCB are connected to the pin. These capacities are loaded via the internal pull-up (50 kΩ)
as soon as the port is set to input. The pin reaches high-level after a typical charging time of
1 to 2 µs.
Charging time: τ = R * C = 50 kΩ ∗ 30 pF = 1,5 us
Polling the port within this time may return a false value. As workaround we recommend to
implement a short delay loop after the port‘s direction is switched to input and before the port
polling is started. Figure 6.2 shows a code example for using port 29 pin 0 as in- and output.
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
Chapter 5 Using the same I/O port simultaneously as in- and output
void KeyLED_Init(void)
{
PFR29_D0 = 0;
/* Port 29 pin 0 as general purpose I/O */
PDR29_D0 = 0;
/* Preset Port 29 pin 0 pin state low (never output high */
/* this might cause shortcircuit if switch is pressed) */
PPER29_D0 = 0;
PPCR29_D0 = 1;
PPER29_D0 = 1;
/* disable pull-up/pull-down on port 29 pin 0*/
/* configure pull-up on port 29 pin 0*/
/* re-enable pull-up on port 29 pin 0*/
}
void LED_on(void)
{
DDR29_D0 = 1;
}
void LED_off(void)
{
DDR29_D0 = 0;
}
/* Switch Port 29 pin 0 to output */
/* Switch Port 29 pin 0 to input (never output high) */
unsigned char KeyPressed(void)
{
if (PDR29_D0 == 0)
return (1);
else
return (0);
/* return '1' in case that the key button is pressed */
}
void main(void)
{
...
KeyLED_Init();
LED_on();
/* switch the LED on */
for (delay=0; delay<500000; delay++) /* keep the LED on for some time delay */
__asm("\tNOP");
LED_off();
/* switch the LED off */
for (delay=0; delay<10; delay++)
__asm("\tNOP");
/* short delay to get pull-up resistor */
/* active */
while (!KeyPressed())
__asm("\tNOP");
/* wait until key button is pressed */
...
}
Figure 5-2: Example code
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© Fujitsu Microelectronics Europe GmbH
I/O PORTS
Chapter 6 Tips and Tricks
6 Tips and Tricks
THIS CHAPTER GIVES SOME HINTS ON USING I/O PORTS
6.1
Initial Value
Ensure that the port-data is defined before the pin-direction is changed to output. Otherwise
undefined data might be output to the I/O-pin, until PDR00 is written.
PDR00 = 0x00;
DDR00 = 0xFF;
6.2
// define initial value before port 0 is set to output
// set port 0 to output, after initial value is defined
Bit Instructions
Use byte-instructions which will be executed faster instead of using bit instructions since all
bit instructions are essentially read-modify-write instructions.
6.3
RMW Instructions
Accessing to the PDR register (2.2.2) via a read-modify-write instruction always returns the
contents of the register itself during read cycle (of the same read-modify-write instruction)
regardless of the DDR register setting.
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
Chapter 7 Additional Information
7 Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet page:
http://mcu.emea.fujitsu.com/
The software example related to this application note is:
91460_io
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
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© Fujitsu Microelectronics Europe GmbH
I/O PORTS
List of Figures
List of Figures
Figure 2-1: I/O-port block diagram ........................................................................................... 7
Figure 4-1: Hysteresis............................................................................................................ 14
Figure 5-1: I/O-port example circuit ....................................................................................... 15
Figure 5-2: Example code...................................................................................................... 16
© Fujitsu Microelectronics Europe GmbH
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I/O PORTS
List of Tables
List of Tables
Table 2-1: PORTEN................................................................................................................... 8
Table 2-2: PDR ......................................................................................................................... 8
Table 2-3: Reading PDR ........................................................................................................... 8
Table 2-4: DDR ......................................................................................................................... 8
Table 2-5: PILR, EPILR .......................................................................................................... 9
Table 2-6: PODR ....................................................................................................................... 9
Table 2-7: PPER, PPCR............................................................................................................. 9
Table 2-8: PFR, EPFR............................................................................................................... 9
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© Fujitsu Microelectronics Europe GmbH
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