2.1 MB

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16314-3E
32-Bit Microcontroller
CMOS
FR60 MB91307 Series
MB91306R/MB91307R
■ DESCRIPTION
The FUJITSU MICROELECTRONICS FR family of single-chip microcontrollers using a 32-bit high-performance
RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications
requiring high-capability, high-speed CPU processing. External bus access is assumed in order to support the
expanded address space accessible by the 32-bit CPU, and a 1K bytes cache memory plus large RAM are
provided for high-speed execution of CPU instructions.
This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX
and printer control that demand high-capability CPU processing power.
The MB91307 series is a FR60 family product based on the FR30/40 family CPU with enhanced bus access for
higher speed operation.
■ FEATURES
FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• Operating frequency 66MHz [with PLL: base frequency 16.5 MHz]
• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
• Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc.
• Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/
store instructions
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2005-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.11
MB91307 Series
• Easier assembler notation: register interlock function
• Built-in multiplier/instruction level support
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC, PS removal): 6 cycles, 16 priority levels
• Harvard architecture for simultaneous execution of program access and data access
• CPU hold 4-word queue allows advanced instruction fetch function
• 4G bytes expanded memory space enables linear access
• Instruction compatible with FR30/40 family
Bus Interface
• Operating frequency: Max 33 MHz
• 8- or 16-bit data output
• Built-in pre-fetch buffer
• Unused data/address pins can be used as general-0purpose input/output ports
• Fully independent 8-area chip select outputs, can be set in minimum 64K bytes units
• Interface support for many memory types
SRAM, ROM/Flash
Page mode flash ROM, page mode ROM interface
Burst mode flash ROM (select burst length 1, 2, 4, 8)
• Basic bus cycle: 2 cycles
• Programmable by area with automatic wait cycle generation to enable wait insert
• RDY input for external wait cycles
• DMA supports fly-by transfer with independent I/O wait control
Built-in RAM
• 128K bytes (MB91307R), 64K bytes (MB91306R)
• Accepts writing of data and instruction codes, enabling use as instruction RAM
Instruction cache
• 1K bytes capacity
• 2-way set associative
• 4-words (16 bytes) per set
• Lock function enables permanent program storage
• Areas not used for instruction cache can be used for RAM
DMAC (DMA controller)
• 5-channel (3-channel external-to-external)
• 3 transfer sources (external pin, internal peripheral, software)
• Addressing mode with 32-bit full address indication (increment, decrement, fixed)
• Transfer mode (demand transfer / burst transfer / step transfer / block transfer)
• Fly-by transfer support (3 channels between external I/O and external memory)
• Transfer data size selection 8/16/32-bit
Bit search module (using REALOS)
• Search the location of first "1" or "0" bit , or first changed bit from MSB in one word.
Reload timer (includes 1 channel for REALOS)
• 16-bit timer: 3 channels
• Internal clock multiplier choice of x2, x8, x32
(Continued)
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DS07-16314-3E
MB91307 Series
(Continued)
UART
• Full duplex double buffer
• 3-channel
• Parity/no parity selection
• Asynchronous (start-stop synchronized), CLK-synchronized communications selection
• Built-in exclusive baud rate timer
• External clock can be used as transfer clock
• Variety of error detection functions (parity, frame, overrun)
I2C interface
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transfer direction detection function
• Start condition repeat generator and detection function
• Bus error detection function
• 10-bit/7-bit slave address
• Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)
Interrupt controller
• Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0
• Interrupt from internal peripheral devices
• Programmable priority settings (16 levels) enabled, except for non-maskable interrupt
• Can be used for wake-up from stop mode
A/D converter
• 10-bit resolution, 4-channel
• Sequential comparator type, conversion time approx. 5.4 µs
• Conversion modes: single conversion mode, continuous conversion mode
• Startup source: software / external trigger / timer output signal
Other interval timers
• 16-bit timer with 3 channels (U-timer)
• Watchdog timer
I/O port
• Maximum 69 ports
Other features
• Built-in oscillator circuit for clock source, PLL multiplier selection enabled
• INIT reset pin
• Also included: watchdog timer reset, software reset
• Power-saving modes: stop mode, sleep mode supported
• Gear functions
• Built-in time base timer
• Packages: LQFP-120 (FPT-120P-M21) : MB91306R, MB91307R
: MB91V307R (Evaluation products)
• CMOS technology
: 0.25 µm : MB91V307R, 0.18 µm : MB91306R, MB91307R
• Supply voltage : MB91V307R : 3.3 V ± 0.3 V (built-in regulator 3.3 V → 2.5 V)
: MB91306R, MB91307R : 3.3 V ± 0.3 V, 1.8V ± 0.15 V dual power supplies
DS07-16314-3E
3
MB91307 Series
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
PA2/CS2
PA1/CS1
PA0/CS0
PB7/IORD
PB6/IOWR
VCC
X0
X1
VSS
PB5/DEOP1/DSTP1
PB4/DACK1
PB3/DREQ1
PB2/DEOP0/DSTP0
PB1/DACK0
PB0/DREQ0
MD2
MD1
MD0
PG2/DEOP2/DSTP2
PG1/DACK2
PG0/DREQ2
PH7/SCL
PH6/SDA
PH5/TOT2
PH4/TOT1 ∗
PH3/TOT0 ∗
VSS
PH2/SC2
PH1/SO2
PH0/SI2
■ PIN ASSIGNMENT
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PI5/SC1
PI4/SO1
PI3/SI1
PI2/SC0
PI1/SO0
PI0/SI0
VCC
PJ7/INT7/ATG
PJ6/INT6/TIN2
PJ5/INT5/TIN1
PJ4/INT4/TIN0
PJ3/INT3
PJ2/INT2
PJ1/INT1
PJ0/INT0
AN3
AN2
AN1
AN0
AVSS/AVRL
AVRH
AVCC
A24/P70
A23/P67
A22/P66
A21/P65
A20/P64
A19/P63
A18/P62
A17/P61
P26/D22
P27/D23
D24
D25
D26
D27
D28
D29
D30
D31
VSS
A00
A01
A02
A03
A04
A05
A06
A07
VCC
A08
A09
A10
A11
A12
A13
A14
A15
VSS
P60/A16
PA3/CS3
PA4/CS4
PA5/CS5
VCCI
PA6/CS6
PA7/CS7
P80/RDY
P81/BGRNT
P82/BRQ
RD
UUB/WR0
P85/ULB/WR1
NMI
VCCI
VSS
INIT
P90/SYSCLK
P91
P92/MCLK
P93
P94/LBA/AS
P95/BAA
P96
P97/WE
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
FPT-120P-M21
* : “L” level output after initialization and reset
4
DS07-16314-3E
MB91307 Series
■ PIN DESCRIPTIONS
Pin no.
85 to 92
Pin name
D16 to D23
I/O
circuit type
C
P20 to P27
Description
External data bus bit 16 to bit 23
Valid only in external bus 16-bit mode.
These pins can be used as ports in external bus 8-bit mode
93 to 100
D24 to D31
C
External data bus bit 24 to bit 31
102 to 109
A00 to A07
F
External address output bit0 to bit7
111 to 118
A08 to A15
F
External address output bit8 to bit15
120, 1 to 7
A16 to A23
P60 to P67
A24
8
P70
F
F
External address output bit16 to bit23
These pins can be used as ports according to setting
External data bus output bit24
This pin can be used as a port according to setting
9
AVCC
⎯
Power supply pin. Analog power supply for A/D converter
10
AVRH
⎯
A/D converter reference voltage supply
11
AVSS/AVRL
⎯
Power supply pin. Analog power supply for A/D converter
12 to 15
AN0 to AN3
D
A/D converter reference voltage supply. Analog input pin.
I
External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally
16 to 19
INT0 to INT3
PJ0 to PJ3
General purpose input/output port
Reload timer input. When the corresponding timer input is enabled, this
input is in use at all times, so that output from other functions must be
stopped unless used intentionally.
TIN0 to TIN2
20 to 22
I
INT4 to INT6
PJ4 to PJ6
General purpose input/output port
A/D converter external trigger input. When selected as an A/D start
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.
ATG
23
25
External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.
INT7
I
External interrupt input. When the corresponding external interrupt is enabled, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.
PJ7
General purpose input/output port
SI0
UART0 data input. When the UART0 channel is in input operation, this
input is in use at all times, so that output from other functions must be
stopped unless used intentionally.
F
PI0
General purpose input/output port.
SO0
UART0 data output. This function is valid when the UART0 data output
function setting is disabled.
26
F
PI1
General purpose input/output port. This function is valid when the
UART0 data output function setting is disabled.
(Continued)
DS07-16314-3E
5
MB91307 Series
Pin no.
Pin name
I/O
circuit type
SC0
27
28
F
General purpose input/output port. This function is valid when the
UART0 clock output function is disabled.
SI1
UART1 data input. When UART1 is set for input operation, this input is
in use at all times, so that output from other functions must be stopped
unless used intentionally.
F
PI3
General purpose input/output port.
SO1
UART1 data output. This function is enabled when the UART1 data output function setting is enabled.
F
PI4
General purpose input/output port. This function is valid when the
UART1 data output function setting is disabled.
SC1
UART1 clock input/output. The clock output is enabled when the UART1
clock output function setting is enabled.
30
F
PI5
General purpose input/output port. This function is valid when the
UART1 clock output function setting is disabled.
SI2
UART2 data input. When UART2 is set for input operation, this input is
in use at all times, so that output from other functions must be stopped
unless used intentionally.
F
PH0
General purpose input/output port.
SO2
UART2 data output. This function is enabled when the UART2 data output function setting is enabled.
32
F
PH1
General purpose input/output port This function is enabled when the
UART2 data output function setting is disabled.
SC2
UART2 clock input/output. The clock output is enabled when the UART2
clock output function setting is enabled.
33
F
PH2
TOT0
35
C
General purpose input/output port This function is enabled when the
UART2 clock output function is disabled.
Timer output port. This function is valid when the timer output setting is
enabled.
PH3
General purpose input/output port.This pin outputs an “L” level signal at
reset.
TOT1
Timer output port. This function is valid when the timer output setting is
enabled.
36
C
PH4
37
UART0 clock output. The clock output is valid when the UART0 clock
output function setting is enabled.
PI2
29
31
Description
TOT2
PH5
C
General purpose input/output port.This pin outputs an “L” level signal at
reset.
Timer output port. This function is valid when the timer output is enabled.
General purpose input/output port.
(Continued)
6
DS07-16314-3E
MB91307 Series
Pin no.
Pin name
SDA
38
39
I/O
circuit type
Q
General purpose input/output port.
SCL
I2C bus input/output port. This function is valid when I2C operation is enabled. When the I2C bus is in use, the port output must be set to Hi-Z
level. When the I2C bus is in use, this is an open drain pin.
Q
DREQ2
General purpose input/output port.
F
PG0
41
F
46
General purpose input/output port. This function is valid when the DMA
transfer request acknowledge output setting is enabled.
DEOP2
DMA external transfer end output. This function is valid when the DMA
external transfer end output setting is enabled.
DSTP2
F
MD2 to MD0
DREQ0
G
F
F
PB1
PB2
DMA external transfer request input. When selected as a DMA startup
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.
DMA external transfer request acknowledge output. This function is valid
when the DMA transfer request acknowledge output setting is enabled.
General purpose input/output port. This function is enabled when the
DMA transfer request acknowledge output setting is disabled.
DMA external transfer end output. This function is valid when the DMA
external transfer end output setting is enabled.
DEOP0
DSTP0
Mode pins 2 to 0. The setting of these two pins determines the basic
operating mode. They should be connected to Vcc or Vss.
General purpose input/output port.
DACK0
47
DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled.
General purpose input/output port. This function is valid when the DMA
external transfer end output selection and the DMA external transfer stop
input selection are disabled.
PB0
48
DMA external transfer request acknowledge output. This function is valid
when the DMA transfer request acknowledge output setting is enabled.
PG1
PG2
43 to 45
DMA external transfer request input. When selected as a DMA startup
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.
General purpose input/output port.
DACK2
42
I2C bus input/output port. This function is valid when I2C operation is enabled. When the I2C bus is in use, the port output must be set to Hi-Z
level. When the I2C bus is in use, this is an open drain pin.
PH6
PH7
40
Description
F
DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled.
General purpose input/output port. This function is valid when the DMA
external transfer end output selection and the DMA external transfer stop
input selection are disabled.
(Continued)
DS07-16314-3E
7
MB91307 Series
Pin no.
49
Pin name
DREQ1
I/O
circuit type
F
PB3
F
PB4
DSTP1
F
X1
54
X0
A
IOWR
F
56
DMA external transfer stop input. This function is valid when the DMA external transfer stop input setting is enabled.
Clock (oscillator) output
Clock (oscillator) input
Write strobe output for DMA fly-by transfer. This function is valid when
the DMA fly-by transfer write strobe output setting is enabled.
PB6
General purpose input/output port. This function is valid when the DMA
fly-by transfer write strobe output setting is disabled.
IORD
Read strobe output for DMA fly-by transfer. This function is valid when
the DMA fly-by transfer read strobe output setting is enabled.
F
57
PB7
General purpose input/output port. This function is valid when the DMA
fly-by transfer read strobe output setting is disabled.
CS0
Chip select output. This function is valid when the chip select 0 output
setting is enabled.
58
F
PA1
General purpose input/output port. This function is valid when the chip
select 0 output setting is disabled.
CS1
Chip select output. This function is valid when the chip select 1 output
setting is enabled.
59
F
PA1
General purpose input/output port. This function is valid when the chip
select 1 output setting is disabled.
CS2
Chip select output. This function is valid when the chip select 2 output
setting is enabled.
60
F
PA2
General purpose input/output port. This function is valid when the chip
select 2 output setting is disabled.
CS3
Chip select output. This function is valid when the chip select 3 output
setting is enabled.
61
F
PA3
8
General purpose input/output port. This function is enabled when the
DNA transfer request acknowledge output setting is disabled.
General purpose input/output port. This function is valid when the DMA
external transfer end output selection and the DMA external transfer stop
input selection are disabled.
PB5
53
DMA external transfer request acknowledge output. This function is valid
when the DMA transfer request acknowledge output setting is enabled.
DMA external transfer end output. This function is valid when the DMA
external transfer end output setting is enabled.
DEOP1
51
DMA external transfer request input. When selected as a DMA startup
source, this input is in use at all times, so that output from other functions
must be stopped unless used intentionally.
General purpose input/output port.
DACK1
50
Description
General purpose input/output port. This function is valid when the chip
select 3 output setting is disabled.
(Continued)
DS07-16314-3E
MB91307 Series
Pin no.
Pin name
I/O
circuit type
CS4
62
F
General purpose input/output port. This function is valid when the chip select 4 output setting is disabled.
CS5
Chip select output. This function is valid when the chip select 5 output setting is enabled.
F
PA5
VCCI
⎯
CS6
65
F
General purpose input/output port. This function is valid when the chip select 5 output setting is disabled.
Internal Power supply pin (1.8 V power supply) .
Chip select output. This function is valid when the chip select 6 output setting is enabled.
PA6
General purpose input/output port. This function is valid when the chip
select 6 output setting is disabled.
CS7
Chip select output. This function is valid when the chip select 7 output setting is enabled.
66
F
PA7
General purpose input/output port. This function is valid when the chip
select 7 output setting is disabled.
RDY
External ready signal input. This function is valid when the external ready
input setting is enabled.
67
C
P80
General purpose input/output port. This function is valid when the external ready input setting is disabled.
BGRNT
External bus open acknowledge output. This pin outputs an L level signal
when the external bus is open. This function is valid when the output setting is enabled.
F
68
P81
General purpose input/output port. This function is valid when the output
setting is disabled.
BRQ
External bus open request input. The input value is “1” when the external
bus is open. This function is valid when the input setting is enabled.
69
P
P82
70
RD
71
WR0
UUB
72
Chip select output. This function is valid when the chip select 4 output setting is enabled.
PA4
63
64
Description
WR1
ULB
P85
DS07-16314-3E
General purpose input/output port. This function is valid when the input
setting is disabled.
M
External bus read strobe output.
F
External bus write strobe output.
Upper side of the 16-bit SRAM input/output mask enable signal.
It is valid when the external bus is set to SRAM use. (WE/P97 function as
the write strobe.)
F
External bus write strobe output.
Lower side of the 16-bit SRAM input/output mask enable signal.
It is valid when the external bus is set to SRAM use. (WE/P97 function as
the write strobe.)
General purpose input/output port. This function is valid when the enable
output setting is disabled.
(Continued)
9
MB91307 Series
(Continued)
Pin no.
Pin name
I/O
circuit type
73
NMI
H
NMI request input
74
VCCI
H
Internal Power supply pin(1.8 V power supply)
76
INIT
B
External reset input
F
System clock output. This function is valid when the system clock output
setting is enabled. The clock signal output is at the same frequency as the
external bus operating frequency. Clock output halts in the stop mode or
the hardware standby mode.
SYSCLK
77
General purpose input/output port. This function is enabled when the system clock output setting is disabled.
P90
78
P91
F
MCLK
79
F
P92
80
P93
F
LBA
F
Memory clock output. Clock output halts in the sleep mode, the stop mode
or the hardware standby mode.
General purpose input/output port. This function is enabled when the
clock output setting is disabled.
General purpose input/output port.
Burst flash ROM address load output. This function is valid when the address load output setting is enabled.
P94
General purpose input/output port. This function is valid when the address
load output and address strobe output settings are disabled.
BAA
Burst flash ROM address advance output. This function is valid when the
address advance output setting is enabled.
P95
General purpose input/output port. This function is valid when the address
advance output and column address strobe output settings are disabled.
82
83
General purpose input/output port.
Address strobe output. This function is valid when the address strobe output setting is disabled.
AS
81
Description
P96
F
General purpose input/output port. This function is enabled when the column address strobe output setting is disabled.
WE
Write strobe output for 16-bit SRAM. This function is enabled when the
write strobe output setting is enabled.
P97
General purpose input/output port. This function is enabled when the write
strobe output setting is prohibited.
84
9
AVCC
⎯
A/D converter power supply
10
AVRH
⎯
A/D converter power supply
11
AVSS/AVRL
⎯
A/D converter power supply (GND)
24, 55,
110
VCC
⎯
Power supply pins
34, 52,
75, 101
VSS
⎯
Power supply pins (GND)
10
DS07-16314-3E
MB91307 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
clock input
• Oscillator feedback resistance
approx. 1 MΩ
X0
A
STANDBY
CONTROL
• CMOS hysteresis input
with pull-up resistance (25 kΩ)
B
digital input
• CMOS level input/output
with standby control
digital output
digital output
C
digital input
STANDBY CONTROL
• Analog input with switch
D
analog input
CONTROL
(Continued)
DS07-16314-3E
11
MB91307 Series
Type
Circuit
Remarks
digital output
• CMOS level output
• CMOS hysteresis input with
standby control
digital output
F
digital input
STANDBY CONTROL
• CMOS level input
without standby control
G
digital input
• CMOS hysteresis input without
standby control
H
digital input
digital output
I
• CMOS level input
• CMOS hysteresis input without
standby control
digital output
digital input
• CMOS level input
digital output
M
digital output
(Continued)
12
DS07-16314-3E
MB91307 Series
(Continued)
Type
Circuit
Remarks
digital output
• CMOS level input/output
with standby control
with pull-down resistance (25 kΩ)
digital output
P
CONTROL
digital input
STANDBY CONTROL
Open drain control
• Open drain output
CMOS hysteresis input with
standby control
digital output
Q
digital input
STANDBY CONTROL
DS07-16314-3E
13
MB91307 Series
■ HANDLING DEVICES
❍MB91307 Series
• Preventing Latchup
When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output
pins (other than medium- and high-withstand voltage pins), or to voltages lower than VSS, as well as when voltages
in excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. When
a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements.
In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
• Treatment of unused pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or
pull-down resistor.
• About power supply pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 mF between VCC and VSS near
this device.
• Notes on Power-ON/shut-down
Cautions to take when turning on/off VCCI (1.8-V internal power supply) and VSS (3.3-V external-pin power
supply)
Do not apply VSS (external) alone continuously (for over an indication of one minute) with VCCI (internal) disconnected not to cause a reliability problem with the LSI.
When VSS (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for
example, due to power supply noise.
When the power is turned on
VCCI (internal) → VSS (external) → Signal
When the power is turned off
Signal → VSS (external) → VCCI (internal)
• Precautions for use of stop mode
The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when
increased leak current (ICCH) in stop mode, or abnormal operation or power fluctuation due to noise while in
operating mode cause the regulator to stop, the internal 2.5 V power supply can ball below the voltage at which
operation is assured. Therefore it is necessary when using the internal regulator and stop mode to assure that
the external power supply does not fall below 3.3 V. And even if this should occur, the internal regulator can be
set to restart when a reset is applied. (In this case the oscillator stabilization wait period should also be set to
“L” level.)
14
DS07-16314-3E
MB91307 Series
• Sample use of Stop Mode with 3.3 V power supply
3.3 V
VCC
2.4 k
C
7.6 k
0.1 F
VSS
GND
• About crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that
X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to
the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.
• Treatment of NC pins
Any pins marked “NC” (not connected) must be left open.
• About mode pins (MD0 to MD2)
Mode pins (MD0 to MD2) should be connected directly to VCC or VSS .
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low.
• Operation at startup
Immediately after a power-on startup, always apply a reset initialization (INIT) at the INIT pin. Also, in order to
assure a wait period for the oscillator circuits to stabilize immediately after startup, be sure that the “L” level input
to the INIT pin continues for the required stabilization wait interval. (The INIT cycle for the INIT pin includes only
the minimum setting for the stabilization wait period.)
• Source oscillation input at startup
At power-on startup, always input a clock signal until the oscillator stabilization wait period is ended.
• Caution on operations during PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
• Precaution on using ports 6 and 7
If one of P60/A15 to P70/A24, which are shared for output of external bus interface addresses, is used as a port,
a grid voltage is applied to the port instantaneously when the status of another address output pin is changed.
Therefore, add resistors or capacitors to those ports to prevent application of the grid voltage.
DS07-16314-3E
15
MB91307 Series
• Clock control block
For “L” level input to the INIT pin, allow for the regulator settling time or oscillation settling time.
• Bit search module
The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible.
• Prefetch
When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).
Byte or halfword access results in wrong data read.
• Setting of external bus
The MB91307 series is guaranteed at an external bus frequency of 33 MHz. As the external bus is capable of
supporting 66 MHz for future enhancements, the initial value is the same rate as the base clock (determined by
the PLL setting) . The external bus is set to 66 MHz if you set the base clock to 66 MHz with the external-bus
base clock division setting register (DIVR1) containing the initial value. To change the base clock frequency, set
the external bus frequency not exceeding 33 MHz and set the new base clock frequency.
• MCLK and SYSCLK
MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either
depending on each application.
• I2C input/output pin
The SDA and SCL pins of the MB91307 series are pseudo open-drain pins with the P-ch transistor turned off
to prevent the “H” level from being output. As the circuit configuration has a diode added to the VCC side, therefore,
the communication voltage must be adjusted to the 3.3-V power supply of this model (pulled up to a voltage of
3.3 V) .
• Shared port function switching
To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are
switched depending on external bus settings.
• Pull-up control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot a guarantee the AC standard.
Even the port for which a pull-up resistor has been set is invalid in stop mode with HIZ = 1 or in hardware standby
mode.
• I/O port access
Byte access only for access to port
• Remarks for the external clock operation
When selecting the external clock, active X0 pin generally. Also simultaneously the opposite phase clock to X0
must be supplied to X1 pin. When using the clock along with STOP (oscillation stopped) mode, the X1 pin stops
when “H” is input in STOP mode. To prevent one output from competing against another, in this case, the stop
mode must not be used.
16
DS07-16314-3E
MB91307 Series
X0
X1
MB91307 series
Using external clock (normal)
Note : Stop mode (oscillation stop mode) cannot be used.
• Low-power consumption modes
• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the
TBCR, or time-base counter control register) and be sure to use the following sequence:
(LDI
#value_of_standby, R0)
(LDI
#_STCR, R12)
STB
R0, @R12
; Write to standby control register (STCR)
LDUB @R12, R0
; Read STCR for synchronous standby
LDUB @R12, R0
; Read STCR again for dummy read
NOP
; NOP x 5 for timing adjustment
NOP
NOP
NOP
NOP
Set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler
triggers the microcontroller to return from the standby mode.
• If you use the monitor debugger, follow the precautions below:
Do not set a breakpoint within the above array of instructions.
Do not single-step the above array of instructions.
• Current at power-on (only for MB91V307R)
About 300 mA of power supply current flows when the power is turned on with INIT set to 0.
Set INIT to 1 to stop the overcurrent flowing. After that, the overcurrent will not flow even if INIT is set to 0.
• Watchdog timer
The watchdog timer function of this model monitors that a program delays a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer countinues to operate until a reset takes
place.
An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under
a condition in which the CPU stops program execution.
Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT pin to cause a reset (INIT).
DS07-16314-3E
17
MB91307 Series
• Terminal and timing control register (TCR) (00000683H)
The terminal and timing control register (TCR) is a write-only register. Therefore, do not access TCR with a bit
manipulation instruction.
If you intend to disable sharing of the bus by writing “0” to Bit 7 (BREN bit) of TCR when the bit is “1”, be sure
to follow the procedure below. If the procedure is not followed, the device may hang up.
1. Write “0” to Bit 2 (BRQE bit) of the port 8 function register (PFR8).
2. Write “0” to Bit 7 (BREN bit) of TCR.
• RD/WR → CS hold extension cycle
Assume that use of the RD/WR → CS hold extension cycle is specified (Bit 0 of AWR is 1) for an
area for which the normal memory/IO access type is set (the TYPE3 to TYPE0 bits of ACR are
0xxx). Even in this case, the hold extension cycle might not be inserted when the operation and
settings are specified in a specific combination.
The hold extension cycle will not be inserted when the following conditions are met:
• Use of the RD/WR → CS hold extension cycle is specified.
(Bit 0 [W00 bit] of AWR is 1.)
• A normal memory/IO access type is set for the area.
(Bits 3 to 0 [TYPE3 to TYPE0 bits] of ACR are 0xxx.)
Note: The MB91307 series allows only this type to be set.
• Disuse of the address → CS delay cycle is specified.
(Bit 2 [W02 bit] of AWR is 0.)
• A setting (recovery enabled) other than 0 cycle is made for the write recovery cycle.
(Bits 5 and 4 [W05 and W04 bits] of AWR are other than 00.)
(Example: First word writing to an external bus 16-bit area)
• If an access is made to write data larger than the bus width to the relevant area under the above conditions,
the RD/WR-CS hold extension cycle is not inserted in any cycle other than the last cycle to write divisions of
the data. Therefore, the hold time becomes insufficient.
Note : This problem does not occur in the read cycle.
To use this function, make either of the following settings:
• Specify the use of the address → CS delay cycle.
(Set 1 for Bit 2 [W02 bit] of AWR.)
• Specify 0 cycle for the write recovery cycle.
(Set 00 for Bits 5 and 4 [W05 and W04 bits] of AWR.)
• Signed DIVIDE statement (DIVOS)
When the instruction immediately before the instruction of DIVOS is an instruction by which the memory access
is done, a correct calculation result might not be obtained.
This is generated under the following conditions.
• When the instruction performs memory accesses just before a DIVOS instruction.
Note : Instructions that performs relevant memory accesses (a total of 58 instructions)
ST Ri, @- R15
STB Ri, @Rj
STB Ri, @ (R14, disp8)
LDUH @ (R13, Rj), Ri
DMOVH @dir9, R13
18
ST Rs, @- R15
STB Ri, @ (R13, Rj)
LDUB @Rj, Ri
LDUB @ (R13, Rj), Ri
DMOVB @dir8, R13
ST PS, @- R15
DMOVB R13, @dir8
LD @ (R13, Rj), Ri
DMOV @dir10, R13
LD @ (R14, disp10), Ri
DS07-16314-3E
MB91307 Series
LDUH @ (R14, disp9), Ri
ANDH Rj, @Ri
EORB Rj, @Ri
DMOVB @R13+, @dir8
DMOVB @dir8, @R13+
LDUB @ (R14, disp8), Ri
ANDB Rj, @Ri
DMOV @R13+, @dir10
DMOV @dir10, @R13+
DMOV @R15+, @dir10
AND Rj, @Ri
ORB Rj, @Ri
DMOVH @R13+, @dir9
DMOVH @dir9, @R13+
DMOV @dir10, @- R15
• When full trace mode is specified as trace mode and the DIVOS and DIV1 instructions are not 4-byte aligned.
• Even if the DIVOS and DIV1 instructions are 4-byte aligned, perform a D-bus DMA transfer or specify the full
trace mode as trace mode if a breakpoint is set in the DIV1 instruction.
Avoid this notes as follows:
(1) Do not place an instruction that performs memory access before a DIVOS instruction.
(2) Do not perform a DMA transfer to the D-bus or set full trace mode as trace made when a DIVOS instruction
is specified.
To output the code for avoiding above (1) condition, specify "[email protected] 1" as the compiler option.
SOFTUNE compiler:
• In case of using the SOFTUNE V3: after the SOFTUNE compiler V30L07R07
• In case of using the SOFTUNE V5: after the SOFTUNE compiler V50L04
• In case of using the SOFTUNE V6: after the SOFTUNE compiler V60L01
• DMA demand transfer
In sleep mode, demand transfer is executed only once and processing does not go further. During normal
operation, the efficiency of demand transfers may seem to be lowered.
This action occurs only in demand transfers (it does not occur in DREQ edge detection mode or the like).
This is occurred in the following cases:
• A demand transfer by DMAC is performed in sleep mode.
- After a demand transfer is performed once, processing does not go further although DREQ is input
successively.
- A subsequent transfer is started if the device is released from sleep mode and an external bus operation
other than a DMA transfer occurs.
• A demand transfer by DMAC is performed during normal operation.
- After a demand transfer is performed once, a subsequent transfer is not performed until an external bus
access other than a DMA transfer occurs.
- A demand transfer does not progress while there is no external bus access because cache hitting is
performed continuously or internal ROM operation continues.
• A subsequent demand transfer is not started even if an external bus access for prefetching occurs.
Avoid this notes as follows:
• Do not perform a demand transfer by DMAC in sleep mode.
• Do not use sleep mode during a demand transfer by DMAC.
DS07-16314-3E
19
MB91307 Series
• R15 (General-purpose register)
If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and,
as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following
instructions:
AND
OR
EOR
XCHB
R15,@Rj
R15,@Rj
R15,@Rj
@Rj,R15
ANDH
ORH
EORH
R15,@Rj
R15,@Rj
R15,@Rj
ANDB
ORB
EORB
R15,@Rj
R15,@Rj
R15,@Rj
* : R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the
state of the S flag of the PS register.
Avoid this notes as follows:
• When programming any of the above 10 instructions by an assembler, specify a general-purpose register in
place of R15.
• Executing instructions on RAM
• If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005 FFF8H to
0005 FFFFH. (Instruction code prohibited area)
• Notes on the PS register
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the
microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs
operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as those in (1) above.
• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as that in (1) above.
• Notes on I-bus Memory
Do not access data in the instruction cache control register or the instruction cache RAM immediately before
the RETI instruction.
20
DS07-16314-3E
MB91307 Series
❍Unique to the evaluation chip MB91V307R
• Simultaneous occurrences of a software break and a user interrupt/NMI
When a software break and a user interrupt /NMI take place at the same time, the emulator debugger may cause
the following phenomena:
• The debugger stops pointing to a location other than the programmed breakpoints.
• The halted program is not re-executed correctly.
If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has
been used, avoid setting any break at the relevant location.
• Single-stepping the RETI instruction
If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being
executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
• Break function
• If the address of a current system stack pointer or an area that includes a stack pointer is specified as an
object address of a hardware break (including an event break), a break occurs after one instruction is executed.
The break occurs although the relevant user program does not include an actual data access instruction. To
avoid this problem, do not set the (word) access to an area that includes the address of a system stack pointer
as a target of a hardware break (including an event break).
• If an instruction that causes a wait is executed between an instruction to read a branch destination address
from memory and a branch instruction, an instruction alignment error occurs at a point where an instruction
alignment error cannot occur originally. Then, an ICE break (CPU error break) occurs, and execution of
instructions stops. Furthermore, even if an instruction break is set for the branch destination address at the
point where the above error occurs, a break might not occur.
Example: LD
LD
CALL
@R1,R0 ; read F-bus RAM
@R2,R3 ; read F-bus RAM
@R0
; An incorrect alignment error may occur or a break might not occur.
To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger
function setup.
To perform the instruction break correctly, do not specify use of a hardware break, but specify use of a software
break in debugger function setup.
• Trace mode
If the trace mode for debugging is set to full trace mode, which uses internal FIFO memory as the output buffer,
the current may increase or DMA access to the D-bus may be lost.
This is occurred if:
• A DMA transfer to the D-bus or standby mode occurs in full trace mode.
Use internal trace mode to avoid this note.
DS07-16314-3E
21
MB91307 Series
• Alignment error (emulator debugger)
Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed
between an instruction to read a branch destination address from memory and a branch instruction. Under these
conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur
originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown
break factor or a CPU error break is output.
Furthermore, even if an instruction break is set for the branch destination address at the point where the above
error occurs, a break might not occur.
This problem occurs if the following three types of instructions are executed successively:
(1) LD or DMOV instructions causing a wait (reading a branch destination address)
LD
@Rj,Ri
LDUH @Rj,RI
LD
@(R13,Rj)Ri
LDUH @(R13,Rj),Ri
LDUB @(R13,Rj),Ri
LD
@(R14,disp10),Ri LDUH @(R14,disp9),Ri LDUB @(R14,disp8),Ri
LD
@R15+,Ri
LD @R15+,Rs
LD @R15+,PS
DMOV @dir10,R13
DMOVH @dir9,R13
DMOVB @dir8,R13
(2) Instructions causing a wait (reading F-bus RAM or external memory)
(3) Branch instructions such as JMP @Ri, JMP: D @Ri, CALL @Ri, CALL: D @Ri, RET, and RET: D
Example:
[email protected],R0 ;read F-bus RAM
[email protected],R3 ;read F-bus RAM
CALL @R0
Avoid this note as follows:
Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed
between an instruction to read a branch destination address from memory and a branch instruction. Under these
conditions, an instruction alignment error occurs at a point where an instruction alignment error cannot occur
originally, an ICE break occurs, and execution of instructions stops. Then, a message indicating an unknown
break factor or a CPU error break is output.
Furthermore, even if an instruction break is set for the branch destination address at the point where the above
error occurs, a break might not occur.
Avoid this problem as follows:
• To avoid the incorrect alignment error as described above, turn off the alignment error function in debugger
function setup.
• To perform the instruction break correctly, set the break point in an address other than the branch destination
address.
• Operand break
A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.
22
DS07-16314-3E
MB91307 Series
■ BLOCK DIAGRAM
CPU Core
32
Instruction
cache
1K bytes
32
Bit search
DMAC
5 channels
Bus Converter
RAM*
32
External
memory
interface
32 16
Adapter
16
Clock control
UART
3 channels
U-TIMER
3 channels
I2C
1 channel
Interrupt
controller
External
interrupt
Reload
timer
3 channels
A/D
4 channels
Port
* : Internal RAM 128K bytes for MB91307R
64K bytes for MB91306R
DS07-16314-3E
23
MB91307 Series
■ CPU AND CONTROL BLOCK
Internal Architecture
The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set
intended for built-in applications.
1. Features
• Uses of RISC Architecture
Basic instruction set: 1 instruction to 1 cycle.
• 32-bit architecture
General-purpose registers: 32-bits × 16 registers
• 4G bytes linear memory space
• Built-in multipliers
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing
High-speed response (6 cycles)
Multiple interrupt support
Level masking functions (16 levels)
• Enhanced I/O operating instructions
Memory-to-memory transfer instructions
Bit processing instructions
• High code efficiency
Basic instruction length: 16 bits
• Low-power consumption
Sleep mode, stop mode
• Gear function
24
DS07-16314-3E
MB91307 Series
2. Internal Architecture
The FR family CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction
bus (I-bus) is connected to an on-chip instruction cache. a 32-bit ←→16-bit bus converter is connected to the
bus (F-bus) to provide an interface between the CPU and peripheral resources. The Harvard ←→ Princeton bus
converter is connected to the both the I-bus and D-bus as an interface between the CPU and bus controller.
FRex CPU
I-bus
D-bus
Instruction
cache
RAM
I address
32
I data
32
D address
32
D data
32
F address
32
F data
32
Harvard
Princeton
bus
converter
32 bit
16 bit
Bus converter
16
R-bus
Peripherals resource
DS07-16314-3E
X-bus
Bus controller
25
MB91307 Series
3. Programming Model
• Basic Programming Model
32 bits
[Default values]
XXXX XXXXH
R0
R1
General-purpose register
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplier result registers
MDH
⎯
ILM
⎯
SCR
CCR
MDL
26
DS07-16314-3E
MB91307 Series
4. Registers
• General Purpose Register
32 bits
[Default values]
R0
R1
XXXX XXXXH
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R 0 to R 15 are general-purpose registers. These registers can be used as accumulators for computation operations, or as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13: Virtual accumulator
R14: Frame pointer
R15: Stack pointer
Default values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
• PS (Program Status Register)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All bits not defined in the diagram are reserved bits with read value “0” at all times. Write access to these bits
is not enabled.
Bit position→ 31
20
16
⎯
10
0
8 7
⎯
ILM
SCR
CCR
PS Register
• CCR (Condition Code Register)
S
I
N
Z
V
C
7
6
5
4
3
2
1
0
[Default value]
⎯
⎯
S
I
N
Z
V
C
- - 00XXXXB
CCR Register
: Stack flag, cleared to “0” at reset.
: Interrupt flag, cleared to “0” at reset.
: Negative flag, default value at reset undefined.
: Zero flag, default value at reset undefined.
: Overflow flag, default value at reset undefined.
: Carry flag, default value at reset undefined.
DS07-16314-3E
27
MB91307 Series
• SCR (System Condition code Register)
10
9
8
[Default value]
D1
D0
T
XX0B
SCR Register
Stepwise division flags
These flags store interim data during execution of stepwise division.
Step trace trap flag
Indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
• ILM(Interrupt Level Mask Register)
20
19
18
17
16
[Default value]
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
ILM Register
This register stores interrupt level mask values, for use in level masking.
The register is initialized to value 15 (01111B) at reset.
• PC (Program Counter Registerr)
31
0
PC
[Default value]
XXXXXXXXH
PC Register
The program counter indicates the address of the instruction that is executing.
The default value at reset is undefined.
• TBR (Table Base Register)
31
0
TBR
[Default value]
000FFC00H
TBR Register
The table base register stores the starting address of the vector table used in EIT processing.
The default value at reset is 000FFC00H.
28
DS07-16314-3E
MB91307 Series
• RP (Return Pointer)
31
0
RP
[Default value]
XXXXXXXXH
RP Register
The return register stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to this PC register.
The default value at reset is undefined.
• SSP (System Stack Pointer)
31
0
SSP
[Default value]
00000000H
SSP Register
The SSP register is the system stack pointer.
When the S flag is “0,” this register functions as the R15 register.
The SSP register can also be explicitly specified.
This register is also used as a stack pointer to indicate the stack to which the PS and PC are removed when an
EIT occurs.
The default value at reset is 00000000H.
• USP (User Stack Pointer)
31
0
USP
[Default value]
XXXXXXXXH
USP Register
The USP register is the user stack pointer.
When the S flag is “1,” this register functions as the R15 register.
The USP register can also be explicitly specified.
The default value at reset is undefined.
This register cannot be used with RETI instructions.
• Multiply & Divide registers
31
0
MDH
MDL
Multiply & Divide Registers
The multiply and divide registers are each 32 bits in length.
The default value at reset is undefined.
DS07-16314-3E
29
MB91307 Series
■ SETTING MODE
In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating
mode.
1. Mode Pins
The three pins MD2, MD1, MD0 are used in mode vector fetch instructions, and also to make settings in test mode.
Mode pin
Mode name
Reset vector access area
Remarks
MD2 MD1 MD0
0
0
1
External ROM mode vector
External
Bus width is set by mode register.
2. Mode Register (MODR)
The mode data fetch instruction writes data to the address “0000 07FDH” called the mode data.
The area “0000 07FDH” is the mode register (MODR). When a setting is made to this register, the device will
operate the mode corresponding to that setting.
The mode register can only be set by a reset source at the INIT level. It is not possible to write to this register
from a user program.
Note : No data exists at the FR family mode register address (0000 07FFH).
< Detailed register description >
MODR
Address
0000 07FDH
7
6
5
4
3
2
1
0
0
0
0
0
0
ROMA
WTH1
WTH0
Default
XXXXXXXXB
Operating mode setting bits
[bit7 to bit3] Reserved bits
These bits should always be set to “00000.” If set to any other value, stable operation is not assured.
[bit2] ROMA (Internal RAM enable bit)
This bit indicates whether internal RAM is enabled.
ROMA
Function
Remarks
0
External ROM mode
The built-in RAM area functions as external area.
1
Internal RAM mode
The built-in RAM area is enabled.
The 128K bytes built-in RAM can be used.
[bit1, 0] WTH1, WTH0 (Bus width indicator bits)
In external bus mode, these bits determine the bus width setting.
In external bus mode, the value of these bits sets the DBW1, DBW0 bits in the ACR0 register (CS0 area).
WTH1
WTH0
Bus width
30
0
0
8-bit
0
1
16-bit
1
0
Setting prohibited
1
1
Setting prohibited
DS07-16314-3E
MB91307 Series
■ MEMORY SPACE
1. Memory Space
The FR family has 4G bytes (232 addresses) of logical address space with linear access from the CPU.
•Direct Addressing Areas
The following areas of address space are used for I/O operations.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The direct areas differ according to the size of the data accessed, as follows.
→ byte data access
: 000H to 0FFH
→ half word data access : 000H to 1FFH
→ word data access
: 000H to 3FFH
2. Memory Map
The following diagram illustrates memory space in this model.
MB91307R
MB91306R
MB91306R/MB91307R
Internal ROM
external bus mode
Internal ROM
external bus mode
External bus mode
I/O
I/O
0000 0000H
0000 0000H
I/O
0000 0400H
0000 0400H
I/O
I/O
Refer to I/O map
I/O
0001 0000H
0001 0000H
Access
prohibited
0004 0000H
0005 0000H
Direct addressing
area
Internal RAM
128K bytes
Access
prohibited
Access
prohibited
0004 0000H
Internal RAM
64K bytes
External area
0006 0000H
Access
prohibited
0006 0000H
Access
prohibited
0010 0000H
0010 0000H
External area
External area
External area
FFFF FFFFH
DS07-16314-3E
31
MB91307 Series
•Use of Built-in RAM
The MB91307R contains 128K bytes of internal RAM, and MB91306R contains 64K bytes of internal RAM. To
enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1).
Precautions for use of this model
• The reset vector is fixed at 000F FFFCH.
• For the MB91307R, the 128K bytes RAM area is from 0004 0000H to 0005 FFFFH and for the MB91306R, the
64K bytes RAM area is from 0004 0000H to 0004 FFFFH. The area from 0006 0000H to 000F FFFFH is access
prohibited.
• In order to use RAM the mode register must be set to internal ROM external bus mode.
• In internal ROM external bus mode the built-in RAM area can be used, but the vector area 000F FFXXH is an
internal area and cannot be accessed externally. Please refer to the following explanation.
• When placing instruction code in RAM, nothing should be placed in the last 8 bytes of the area 0005 FFF8H
to 0005 FFFFH. (This is an instruction code prohibited area.)
After mode setting
Internal ROM external bus mode
After reset release
0000 0000H
MB91307R
MB91306R
I/O
Direct addressing
area
I/O
I/O
I/O
Refer to I/O map
I/O
I/O
Access
prohibited
Access
prohibited
Access
prohibited
External area
Internal RAM
128K bytes
External area
Access
prohibited
External area
External area
0000 0400H
0001 0000H
0004 0000H
0005 0000H
Internal RAM
64K bytes
0006 0000H
Access
prohibited
0010 0000H
External area
FFFF FFFFH
: The shaded portion is an internal area.
After mode register setting the vector area is an internal area. Therefore before writing to the mode register
it is necessary to rewrite the TBR register so that the vector area is changed to an external area.
32
DS07-16314-3E
MB91307 Series
■ USER PROGRAM INITIALIZATION
The following sequence describes an example using built-in RAM.
For the MB91306R, only the internal RAM area is different but the setting is same.
1. Hardware Setting Conditions
MB91307 series
CS0
External
ROM
A19 to A1
1) Assume that 1M bytes of external ROM is placed beginning at 0010 0000H. Place the program at this location
in the linker. (The following description can apply to other addresses than this one as well.)
2) Connect addresses A19 to A1 (1M bytes) to ROM, other addresses will use CS0.
3) Set the mode pins (MD2, MD1, MD0) to external vectors.
4) Write the reset vector to 001F FFFCH. Likewise write the mode vector to 001F FFF8H.
2. Immediately After Reset Release
0000 0000H
MB91307 series
CS0
External
ROM
0004 0000H
External
ROM
FFFF FFFFH
1M bytes of ROM can
be viewed again on the
address map.
1) After reset release, the CPU will attempt to load a mode vector from 000F FFF8H, a reset vector from 000F
FFFCH, however because this will be an external vector, the CPU will have to go externally. However the
CS0 default value causes 1M bytes of external ROM to be repeated in external space, so that the mode
vector and the reset vector itself will load the contents written at 001F FFF8H and 001F FFFCH in external
ROM.
2) The branch destination is set in the linker to an address in the area 001X XXXXH, so that subsequent program execution will be in this area.
DS07-16314-3E
33
MB91307 Series
3. User Program Initialization Steps
0000 0000H
MB91307 series
CS0
External
ROM
0004 0000H
0010 0000H
External
ROM
001F FFFFH
FFFF FFFFH
1M bytes of ROM space
matches 1M bytes of the
address map.
1) Set the TBR register so that the interrupt table is 001F FFXXH, then perform initialization. This process also
includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X XXXXH. The
CS0 decoding result is the same before and after the setting, so that the CPU can continue to run programs
on external ROM.
2) If necessary, initialize the contents of RAM.
3) Now initialization is complete, and the application program can be executed.
34
DS07-16314-3E
MB91307 Series
■ I/O MAP
This map shows the correlation between areas of memory space and individual registers in peripheral resources.
[How to read the map]
Register
Address
000000H
+0
+1
+2
+3
PDR0 [R/W]
PDR1 [R/W]
PDR2 [R/W]
PDR3 [R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
T-unit
Port Data Register
Read/write attributes
Register default value after reset
Register name
(1-column registers at address 4n, 2-column registers at address 4n + 2…)
Left most register address
(for word access, the first column of the register contains the MSB end of the data)
Note: Default register bit values are indicated as follows:
“1” : Default value “1”
“0” : Default value “0”
“X” : Default value “X”
“-“ : No physical register at this location
DS07-16314-3E
35
MB91307 Series
Address
Register
+0
+1
000000H
⎯
⎯
000004H
⎯
⎯
PDR8 [R/W]
--X--XXX
000008H
PDR2 [R/W]
PDR7 [R/W]
XXXXXXXX
-------X
PDR9 [R/W]
PDRA [R/W]
PDRB [R/W]
XXXXXXX-
XXXXXXXX
XXXXXXXX
PDRG [R/W]
PDRH [R/W]
PDRI [R/W]
PDRJ [R/W]
-----XXX
XXX00XXX
---XXXXX
XXXXXXXX
000020H
to
00003CH
⎯
000048H
ENIR [R/W]
ELVR [R/W]
00000000
00000000
00000000
DICR [R/W]
HRCL [R/W]
-------0
0--11111
TMRLR [W]
XXXXXXXX XXXXXXXX
000058H
XXXXXXXX XXXXXXXX
000060H
000064H
000068H
DLYI/I-unit
TMR [R]
XXXXXXXX XXXXXXXX
Reload Timer 0
TMR [R]
XXXXXXXX XXXXXXXX
TMCSR [R/W]
⎯
Reload Timer 1
----0000 00000000
TMRLR [W]
XXXXXXXX XXXXXXXX
TMR [R]
XXXXXXXX XXXXXXXX
TMCSR [R/W]
⎯
00005CH
Ext int
----0000 00000000
TMRLR [W]
000054H
⎯
TMCSR [R/W]
⎯
R-bus
Port Data Register
Reserved
EIRR [R/W]
00004CH
000050H
T-unit
Port Data Register
⎯
⎯
000044H
Block
⎯
XXXXXXXX
000018H
to
00001CH
000040H
+3
PDR6 [R/W]
00000CH
000010H
+2
Reload Timer 2
----0000 00000000
SSR [R/W]
SIDR [R/W]
SCR [R/W]
SMR [R/W]
00001-00
XXXXXXXX
00000100
00--0-0-
UTIM [R] (UTIMR [W] )
DRCL [W]
UTIMC [R/W]
--------
0--00001
00000000 00000000
SSR [R/W]
SIDR [R/W]
SCR [R/W]
SMR [R/W]
00001-00
XXXXXXXX
00000100
00--0-0-
UART0
U-TIMER 0
UART1
(Continued)
36
DS07-16314-3E
MB91307 Series
Register
Address
+0
UTIM [R] (UTIMR [W] )
00006CH
000070H
+1
00000000 00000000
+2
+3
DRCL [W]
UTIMC [R/W]
--------
0--00001
SSR [R/W]
SIDR [R/W]
SCR [R/W]
SMR [R/W]
00001-00
XXXXXXXX
00000100
00--0-0-
UTIM [R] (UTIMR [W] )
DRCL [W]
UTIMC [R/W]
00000000 00000000
--------
0--00001
ADCR
ADCS
[R/W]
000074H
000078H
[R]
------XX XXXXXXXX
00000000 00000000
Block
U-TIMER 1
UART2
U-TIMER 2
A/D Converter
sequential comparator
00007CH
⎯
Reserved
000080H
⎯
Reserved
000084H
⎯
Reserved
000088H
⎯
Reserved
00008CH
⎯
Reserved
000090H
⎯
Reserved
000094H
IBCR [R/W]
IBSR [R/W]
00000000
00000000
000098H
00009CH
ITBA [R/W]
------00 00000000
ITMK [R/W]
ISMK [R/W]
ISBA [R/W]
01111111
00000000
IDAR [R/W]
ICCR [R/W]
IDBL [R/W]
00000000
0-011111
-------0
00----11 11111111
⎯
I2C interface
0000A0H
⎯
Reserved
0000A4H
⎯
Reserved
0000A8H
⎯
Reserved
0000ACH
⎯
Reserved
0000B0H
⎯
Reserved
(Continued)
DS07-16314-3E
37
MB91307 Series
Address
000200H
000204H
000208H
00020CH
000210H
000214H
000218H
00021CH
000220H
000224H
Register
+0
+1
+2
Block
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB4 [R/W]
00000000 00000000 00000000 00000000
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB4 [R/W]
00000000 00000000 00000000 00000000
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB4 [R/W]
00000000 00000000 00000000 00000000
DMAC
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB4 [R/W]
00000000 00000000 00000000 00000000
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
DMACB4 [R/W]
00000000 00000000 00000000 00000000
000228H
⎯
00022CH
to
00023CH
⎯
000240H
+3
DMACR [R/W]
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
DMAC
000244H
to
000274H
⎯
Reserved
000278H
⎯
Reserved
00027CH
⎯
Reserved
000280H
to
0002FCH
⎯
Reserved
(Continued)
38
DS07-16314-3E
MB91307 Series
Register
Address
+0
+1
000308H
to
0003E0H
ISIZE [R/W]
------00
⎯
0003E8H
to
0003ECH
Instruction Cache
Reserved
ICHRC [R/W]
⎯
0003E4H
Block
Reserved
⎯
000304H
0 - 000000
⎯
Instruction Cache
Reserved
BSD0 [W]
0003F0H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSD1 [R/W]
0003F4H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSDC [W]
0003F8H
Bit Search Module
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
BSRR [R]
0003FCH
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDRG [R/W]
DDRH [R/W]
DDRI [R/W]
DDRJ [R/W]
----000
00011000
--000000
00000000
⎯
000404H
000408H
⎯
00040CH
⎯
000410H
+3
⎯
000300H
000400H
+2
R-bus
Port Direction Register
PFRG [R/W]
PFRH [R/W]
PFRI [R/W]
----0000
0000000-
--00-00-
000414H
⎯
000418H
⎯
00041CH
⎯
000420H
to
00043CH
⎯
⎯
R-bus
Port Function Register
Reserved
(Continued)
DS07-16314-3E
39
MB91307 Series
Address
000440H
000444H
000448H
00044CH
000450H
000454H
000458H
00045CH
000460H
000464H
000468H
00046CH
Register
+0
+1
+2
+3
ICR00 [R/W]
ICR01 [R/W]
ICR02 [R/W]
ICR03 [R/W]
---11111
---11111
---11111
---11111
ICR04 [R/W]
ICR05 [R/W]
ICR06 [R/W]
ICR07 [R/W]
---11111
---11111
---11111
---11111
ICR08 [R/W]
ICR09 [R/W]
ICR10 [R/W]
ICR11 [R/W]
---11111
---11111
---11111
---11111
ICR12 [R/W]
ICR13 [R/W]
ICR14 [R/W]
ICR15 [R/W]
---11111
---11111
---11111
---11111
ICR16 [R/W]
ICR17 [R/W]
ICR18 [R/W]
ICR19 [R/W]
---11111
---11111
---11111
---11111
ICR20 [R/W]
ICR21 [R/W]
ICR22 [R/W]
ICR23 [R/W]
---11111
---11111
---11111
---11111
ICR24 [R/W]
ICR25 [R/W]
ICR26 [R/W]
ICR27 [R/W]
---11111
---11111
---11111
---11111
ICR28 [R/W]
ICR29 [R/W]
ICR30 [R/W]
ICR31 [R/W]
---11111
---11111
---11111
---11111
ICR32 [R/W]
ICR33 [R/W]
ICR34 [R/W]
ICR35 [R/W]
---11111
---11111
---11111
---11111
ICR36 [R/W]
ICR37 [R/W]
ICR38 [R/W]
ICR39 [R/W]
---11111
---11111
---11111
---11111
ICR40 [R/W]
ICR41 [R/W]
ICR42 [R/W]
ICR43 [R/W]
---11111
---11111
---11111
---11111
ICR44 [R/W]
ICR45 [R/W]
ICR46 [R/W]
ICR47 [R/W]
---11111
---11111
---11111
---11111
000470H
to
00047CH
000480H
000484H
000488H
to
0005FCH
⎯
RSRR [R/W]
STCR [R/W]
2
2
10000000 *
00110011 *
Interrupt Control unit
Interrupt Control unit
⎯
TBCR [R/W]
00XXXX00 *
1
CTBR [W]
XXXXXXXX
CLKR [R/W]
WPR [W]
DIVR0 [R/W]
DIVR1 [R/W]
00000000 *1
XXXXXXXX
00000011 *1
00000000 *1
⎯
Block
Clock Control unit
Reserved
*1: These registers have different default values at reset level. The value shown is the INIT level value.
*2: These registers have different default values at reset level. The value shown is the INIT level value from the INIT
pin.
(Continued)
40
DS07-16314-3E
MB91307 Series
Register
Address
+0
+1
000600H
⎯
⎯
000604H
⎯
⎯
000608H
+2
+3
DDR2 [R/W]
⎯
00000000
DDR6 [R/W]
DDR7 [R/W]
00000000
00000000
DDR8 [R/W]
DDR9 [R/W]
DDRA [R/W]
DDRB [R/W]
--0--000
00000000
00000000
00000000
⎯
⎯
PFR6 [R/W]
PFR7 [R/W]
11111111
-------1
000610H
⎯
⎯
000614H
⎯
⎯
PFR8 [R/W]
PFR9 [R/W]
PFRA [R/W]
PFRB1 [R/W]
--1--0--
1111111-
0-001101
00000000
00061CH
PFRB2 [R/W]
⎯
00------
000620H
⎯
000624H
⎯
000628H
to
00063FH
⎯
000648H
00064CH
000650H
000654H
T-unit
Port Function Register
Reserved
ASR0 [R/W]
ACR0 [R/W]
00000000 00000000
1111XX00 00000000
ASR1 [R/W]
ACR1 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
ASR2 [R/W]
ACR2 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
ASR3 [R/W]
ACR3 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
ASR4 [R/W]
ACR4 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
ASR5 [R/W]
ACR5 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
000640H
000644H
T-unit
Port Direction Register
⎯
00060CH
000618H
Block
T-unit
(Continued)
DS07-16314-3E
41
MB91307 Series
Address
000658H
00065CH
000660H
000664H
000668H
00066CH
Register
+0
+1
+2
ASR6 [R/W]
ACR6 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
ASR7 [R/W]
ACR7 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
AWR0 [R/W]
AWR1 [R/W]
011111111 11111111
XXXXXXXX XXXXXXXX
AWR2 [R/W]
AWR3 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
AWR4 [R/W]
AWR5 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
AWR6 [R/W]
AWR7 [R/W]
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
000670H
⎯
000674H
⎯
000678H
IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W]
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
T-unit
⎯
⎯
00067CH
000680H
+3
CSER [R/W]
CHER [R/W]
000000001
11111111
⎯
TCR [R/W]
00000000
000684H
⎯
000684H
to
0007F8H
⎯
Reserved
0007FCH
⎯
⎯
000800H
to
000AFCH
⎯
Reserved
000B00H
000B04H
ESTS0 [R/W] ESTS1 [R/W]
X0000000
ESTS2 [R]
⎯
XXXXXXXX
1XXXXXXX
ECTL0 [R/W] ECTL1 [R/W]
ECTL2 [W]
ECTL3 [R/W]
000X0000
00X00X11
0X000000
00000000
DSU
(Continued)
42
DS07-16314-3E
MB91307 Series
Register
Address
000B08H
+0
+1
+2
+3
ECNT0 [W]
ECNT1 [W]
EUSA [W]
EDTC [W]
XXXXXXXX
XXXXXXXX
XXX00000
0000XXXX
EWPT [R]
000B0CH
000B10H
⎯
00000000 00000000
EDTR0 [W]
EDTR1 [W]
XXXXXXXX XXXXXXXX
000B14H
to
000B1CH
000B20H
000B24H
000B28H
000B2CH
000B30H
000B34H
000B38H
000B3CH
000B40H
000B44H
000B48H
000B4CH
000B50H
Block
XXXXXXXX XXXXXXXX
⎯
EIA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA2 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA3 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA4 [W]
DSU
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA5 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA6 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIA7 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDTA [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EDTM [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOA0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOA1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EPCR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
(Continued)
DS07-16314-3E
43
MB91307 Series
(Continued)
Address
000B54H
000B58H
000B5CH
000B60H
000B64H
000B68H
000B6CH
000B70H
to
000FFCH
001000H
001004H
001008H
00100CH
001010H
001014H
001018H
00101CH
001020H
001024H
44
Register
+0
+1
+2
+3
Block
EPSR [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIAM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EIAM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOAM0/EODM0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DSU
EOAM1/EODM1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EOD1 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
⎯
Reserved
DMASA0 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA0 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA1 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA1 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA2 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMAC
DMADA2 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA3 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA3 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMASA4 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMADA4 [R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMAC
DS07-16314-3E
MB91307 Series
■ INTERRUPT SOURCES AND INTERRUPT VECTORS
Interrupt source
Interrupt number
Interrupt level
Offset TBR default address
Decimal
Hex
Reset
0
00
⎯
3FCH
000FFFFCH
Mode vector
1
01
⎯
3F8H
000FFFF8H
System reserved
2
02
⎯
3F4H
000FFFF4H
System reserved
3
03
⎯
3F0H
000FFFF0H
System reserved
4
04
⎯
3ECH
000FFFECH
System reserved
5
05
⎯
3E8H
000FFFE8H
System reserved
6
06
⎯
3E4H
000FFFE4H
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
INTE instruction
9
09
⎯
3D8H
000FFFD8H
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
Operand break trap
11
0B
⎯
3D0H
000FFFD0H
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
NMI requ
15
0F
15 (FH)
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART0(RX completed)
27
1B
ICR11
390H
000FFF90H
UART1(RX completed)
28
1C
ICR12
38CH
000FFF8CH
UART2(RX completed)
29
1D
ICR13
388H
000FFF88H
UART0(TX completed)
30
1E
ICR14
384H
000FFF84H
UART1(TX completed)
31
1F
ICR15
380H
000FFF80H
UART2(TX completed)
32
20
ICR16
37CH
000FFF7CH
DMAC0(end, error)
33
21
ICR17
378H
000FFF78H
(Continued)
DS07-16314-3E
45
MB91307 Series
Interrupt source
Interrupt number
Interrupt level
Offset TBR default address
Decimal
Hex
DMAC1(end, error)
34
22
ICR18
374H
000FFF74H
DMAC2(end, error)
35
23
ICR19
370H
000FFF70H
DMAC3(end, error)
36
24
ICR20
36CH
000FFF6CH
DMAC4(end, error)
37
25
ICR21
368H
000FFF68H
A/D
38
26
ICR22
364H
000FFF64H
IC
39
27
ICR23
360H
000FFF60H
System reserved
40
28
ICR24
35CH
000FFF5CH
System reserved
41
29
ICR25
358H
000FFF58H
System reserved
42
2A
ICR26
354H
000FFF54H
System reserved
43
2B
ICR27
350H
000FFF50H
U-TIMER0
44
2C
ICR28
34CH
000FFF4CH
U-TIMER1
45
2D
ICR29
348H
000FFF48H
U-TIMER2
46
2E
ICR30
344H
000FFF44H
Time base timer overflow
47
2F
ICR31
340H
000FFF40H
System reserved
48
30
ICR32
33CH
000FFF3CH
System reserved
49
31
ICR33
338H
000FFF38H
System reserved
50
32
ICR34
334H
000FFF34H
System reserved
51
33
ICR35
330H
000FFF30H
System reserved
52
34
ICR36
32CH
000FFF2CH
System reserved
53
35
ICR37
328H
000FFF28H
System reserved
54
36
ICR38
324H
000FFF24H
System reserved
55
37
ICR39
320H
000FFF20H
System reserved
56
38
ICR40
31CH
000FFF1CH
System reserved
57
39
ICR41
318H
000FFF18H
System reserved
58
3A
ICR42
314H
000FFF14H
System reserved
59
3B
ICR43
310H
000FFF10H
System reserved
60
3C
ICR44
30CH
000FFF0CH
System reserved
61
3D
ICR45
308H
000FFF08H
System reserved
62
3E
ICR46
304H
000FFF04H
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
System reserved (REALOS use)
64
40
⎯
2FCH
000FFEFCH
System reserved (REALOS use)
65
41
⎯
2F8H
000FFEF8H
System reserved
66
42
⎯
2F4H
000FFEF4H
System reserved
67
43
⎯
2F0H
000FFEF0H
System reserved
68
44
⎯
2ECH
000FFEECH
2
(Continued)
46
DS07-16314-3E
MB91307 Series
(Continued)
Interrupt source
Interrupt number
Interrupt level
Offset TBR default address
Decimal
Hex
System reserved
69
45
⎯
2E8H
000FFEE8H
System reserved
70
46
⎯
2E4H
000FFEE4H
System reserved
71
47
⎯
2E0H
000FFEE0H
System reserved
72
48
⎯
2DCH
000FFEDCH
System reserved
73
49
⎯
2D8H
000FFED8H
System reserved
74
4A
⎯
2D4H
000FFED4H
System reserved
75
4B
⎯
2D0H
000FFED0H
System reserved
76
4C
⎯
2CCH
000FFECCH
System reserved
77
4D
⎯
2C8H
000FFEC8H
System reserved
78
4E
⎯
2C4H
000FFEC4H
System reserved
79
4F
⎯
2C0H
000FFEC0H
Used by INT instructions
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
DS07-16314-3E
47
MB91307 Series
■ PERIPHERAL RESOURCES
1. Interrupt Controller
(1) Overview
The interrupt controller receives and processes arbitration of interrupts.
•Hardware Configuration
This module is configured from the following elements.
• ICR register
• Interrupt priority determination circuit
• Interrupt level and interrupt number (vector) generator
• Hold request cancellation request generator
•Principal Functions
This module primarily provides the following functions.
• NMI request / interrupt request detection
• Order of priority determination (according to level and number)
• Notification (to CPU) of interrupt level of source according to determination
• Notification (to CPU) of interrupt number of source according to determination
• Instruction (to CPU) to recover from stop mode when an interrupt other than NMI/interrupt level “11111” is
generated
• Generation of hold request cancellation requests to the bus master
48
DS07-16314-3E
MB91307 Series
(2) Register List
bit 7
6
5
4
3
2
1
0
Address : 00000440H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
Address : 00000441H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address : 00000442H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address : 00000443H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address : 00000444H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address : 00000445H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address : 00000446H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address : 00000447H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address : 00000448H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address : 00000449H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address : 0000044AH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address : 0000044BH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address : 0000044CH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address : 0000044DH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address : 0000044EH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address : 0000044FH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address : 00000450H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address : 00000451H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address : 00000452H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address : 00000453H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address : 00000454H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address : 00000455H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address : 00000456H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address : 00000457H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address : 00000458H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
Address : 00000459H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address : 0000045AH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address : 0000045BH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address : 0000045CH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address : 0000045DH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address : 0000045EH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address : 0000045FH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
R
R/W
R/W
R/W
R/W
(Continued)
DS07-16314-3E
49
MB91307 Series
(Continued)
bit 7
6
5
4
3
2
1
0
Address : 00000460H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
Address : 00000461H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
Address : 00000462H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
Address : 00000463H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
Address : 00000464H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
Address : 00000465H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
Address : 00000466H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
Address : 00000467H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
Address : 00000468H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
Address : 00000469H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
Address : 0000046AH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
Address : 0000046BH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
Address : 0000046CH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
Address : 0000046DH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
Address : 0000046EH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
Address : 0000046FH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
R
R/W
R/W
R/W
R/W
LVL4
LVL3
LVL2
LVL1
LVL0
R
R/W
R/W
R/W
R/W
Address : 00000045H
MHALTI
R/W
50
⎯
⎯
HRCL
DS07-16314-3E
MB91307 Series
(3) Block Diagram
WAKEUP (“1” when LEVEL ≠ 11111)
UNMI
Determine order of priority
LEVEL4 to LEVEL0
5
NMI
processing
LEVEL
determination
RI00
ICR00
VECTOR
determination
RI47
LEVEL,
VECTOR
generation
6
HLDREQ
cancel
request
MHALTI
VCT5 to VCT0
ICR47
(DLYIRQ)
R-bus
DS07-16314-3E
51
MB91307 Series
2. External Interrupt - NMI Control Block
(1) Overview
The External Interrupt-control block controls external interrupt requests input at the NMI and INT0 to INT7 pins.
The request level can be selected from “H,” “L,” “rising edge,” or “falling edge” detection (except for NMI).
(2) Register List
• External interrupt enable register (ENIR)
bit
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
• External interrupt source register (EIRR)
bit
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
• Request level setting register (ELVR)
bit
bit
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
(3) Block Diagram
R-bus
8
Interrupt
request
9
8
8
52
Interrupt enable register
Gate
Source F/F
Edge detection circuit
9
INT0 to INT7
NMI
Interrupt source register
Interrupt level setting register
DS07-16314-3E
MB91307 Series
3. REALOS Related Hardware
REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these
resources cannot be used by user programs.
• Delay Interrupt Module
(1) Overview
The delay interrupt module is a module that generates interrupts for task switching. This module can be used
with software instructions to generate and cancel interrupts to the CPU.
(2) Register List
Address :
bit
7
6
5
4
3
2
1
00000044H
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
DLYI
DICR
[R/W]
(3) Block Diagram
R-bus
Interrupt request
DS07-16314-3E
DLYI
53
MB91307 Series
• Bit Search Module
(1) Overview
Searches data written to input registers for “0” or “1” or change points, and outputs the value of the detected bits.
(2) Register List
bit 31
0
Address :
000003F0H
BSD0
0 detection data register
Address :
000003F4H
BSD1
1 detection data register
Address :
000003F8H
BSDC
Change point detection register
Address :
000003FCH
BSRR
Detection results register
(3) Block Diagram
D-bus
Input latch
Address
decoder
Detection
mode
1 detection data capture
Bit search circuit
Search results
54
DS07-16314-3E
MB91307 Series
4. 16-bit Reload Timer
(1) Overview
The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock
generation, and a control register.
For the input clock signal, a selection of three internal clock signals (peripheral clock multiplied by 2, 8, or 32)
or external clock is provided.
The output pin (TOUT) produces a toggle output waveform at every underflow in reload mode, and a square
wave indicating counting in progress in one-shot mode.
The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in
internal clock mode.
The external event count function can be used in reload mode or as a frequency multiplier in external clock mode.
The MB91306R/MB91307R contain 3 channels (0 to 2) of this timer.
(2) Register List
• Control status register (TMCSR)
bit
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
CSL1
CSL0
MOD2
MOD1
7
6
5
4
3
2
1
0
MOD0
⎯
OUTL
RELD
INTE
UF
CNTE
TRG
• 16-bit timer register (TMR)
15
0
• 16-bit reload register (TMRLR)
15
DS07-16314-3E
0
55
MB91307 Series
(3) Block Diagram
16
16-bit reload register
R-bus
8
Reload
RELD
16-bit down counter
OUTE
16
OUTL
2
OUT
CTL.
GATE
INTE
2
UF
IRQ
CSL1
Clock selector
CNTE
CSL0
Re-trigger
TRG
2
Port (TIN)
IN CTL.
EXCK
φ
φ
φ
21 23 25
Prescaler
clear
3
Port (TOT)
MOD2
MOD1
Internal clock
MOD0
3
56
DS07-16314-3E
MB91307 Series
5. U-TIMER (16 bit timer for UART baud rate generation)
(1) Overview
The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set
using the combination of chip operating frequency and U-TIMER reload value.
The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.
This device features a 3-channel built-in U-TIMER. By connecting two U-TIMER channels used as interval timers
in a cascade connection, it is possible to count intervals up to a maximum of 232 × φ.
The available case connections are channel 0 to channel 1, and channel 1 to channel 2.
(2) Register List
8 7
bit 15
0
UTIM
(R)
UTIMR
(W)
UTIMC
(R/W)
(3) Block Diagram
15
0
UTIMR (reload register)
Load
15
0
UTIM (timer)
Clock
Underflow
φ
(Peripheral clock)
control
MUX
Channel 0 only
f.f.
To UART
Under flow U-TIMER 1
DS07-16314-3E
57
MB91307 Series
6. UART
(1) Overview
The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing
the following features. This device features a 3-channel built-in UART.
•
•
•
•
•
•
•
•
•
Full duplex double buffer
Asynchronous (start-stop synchronized) or CLK synchronized transmission enabled
Supports multi-processor mode
Fully programmable baud rate
Built-in timer can be set to any desired baud rate (see U-TIMER description)
Independent baud rate setting from external clock enabled.
Error detection functions (parity, framing, overrun)
Transfer signal NRZ encoded
DMA transfer start from interrupt enabled
DMAC interrupt source cleared by write operation to DRCL register.
(2) Register List
8 7
bit 15
0
SCR
SMR
(R/W)
SSR
SIDR (R)/SODR (W)
(R/W)
DRCL
(W)
8 bit
8 bit
• Serial input register/Serial output registe (SIDR/SODR)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
• Serial status register (SSR)
7
6
5
4
3
2
1
0
PE
ORE
FRE
RDRF
TDRE
⎯
RIE
TIE
• Serial mode register (SMR)
7
6
5
4
3
2
1
0
MD1
MD0
⎯
⎯
CS0
⎯
SCKE
⎯
7
6
5
4
3
2
1
0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
• Serial control register (SCR)
• DRCL register (DRCL)
58
DS07-16314-3E
MB91307 Series
(3) Block Diagram
Control signal
RX interrupt
(to CPU)
SC (clock)
TX clock
From U-TIMER
Clock select
circuit
TX interrupt
(to CPU)
RX clock
External clock
SC
SI (receiving data)
RX control circuit
TX control circuit
Start bit detect
circuit
Sent start
circuit
Receiving bit
counter
Sending bit
counter
Receiving parity
counter
Sending parity
counter
SO (Sending data)
Receiving status
decision circuit
Receiving shifter
Sending shifter
Receiving
end
Sending
start
SIDR
SODR
DMA receiving
error signal
(to DMAC)
R-bus
MD1
MD0
SMR
register
CS0
SCKE
SOE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signal
DS07-16314-3E
59
MB91307 Series
7. A/D Converter (Sequential comparison type)
(1) Overview
This A/D converter is a module that coverts analog input voltages to digital values, and provides the following
features.
Minimum conversion time 5.4 µs/ch (at peripheral clock 33 MHz-CKLP)
Built-in sample & hold circuit
Resolution 10 bits (8-bit accuracy)
Analog input: 4 channels by program selection
Single conversion mode: Conversion on 1 select channel
Scan conversion mode: Select continuous multiple channels. Up to 4 channels can be selected by program.
Continuous conversion mode: Continuous conversion on selected channel
Stop conversion mode: 1-channel conversion then pause and wait until the next start is applied
(enables synchronized conversion start)
• DMA transfer start from interrupt enabled
• Start sources can be selected from software, external trigger (falling edge), reload timer (rising edge).
•
•
•
•
(2) Register List
• Control status register (ADCS)
bit
bit
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
⎯
7
6
5
4
3
2
1
0
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
• Data register (ADCR)
bit
bit
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(3) Block Diagram
AVCC
AVRH AVSS
Internal voltage generator
Sample & hold circuit
Data register (ADCR)
Channel decoder
R-bus
Input switch
Sequential comparison
register
AD control register
Timing generator
Peripheral clock
(CLKP)
Prescaler
ATG (External pin trigger)
Reload timer ch.1 (Internal connection)
(4) Precautions for Use:
When the A/D converter is started from an external trigger or internal timer, the ADCS register A/D start source
bits STS1, STS0 are set, and at this time the input values for the external trigger and internal timer should be
set to the inactive side. If these values are set to the active side, abnormal operation may result.
When setting the STS1, STS0 bits, set ATG = “1” input, reload timer (channel 1) = “0” output.
Note : If internal impedance is higher than the specified value, it may not be possible to obtain analog input
value sampling within the specified sampling time, so that proper results will not be obtained.
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MB91307 Series
8. I2C Interface
(1) Overview
The I2C interface operates as a master/slave device on the I2C bus at serial I/O ports with IC bus support. The
following features are provided.
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address/general call address detection function
• Transfer direction detection function
• Start condition repeat generation and detection function
• Bus error detection function
• 10-bit/7-bit master/slave addressing
• Compatible with standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)
• Transfer end interrupt/bus error interrupt generation
(2) Register List
• Bus Control Register (IBCR)
bit
Address : 000094H
Default value →
15
14
13
12
11
10
9
8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
ADT
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
TA9
TA8
⎯
⎯
⎯
⎯
⎯
⎯
R/W
0
R/W
0
7
6
5
4
3
2
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bus Status Register (IBSR)
Address : 000095H
Default value →
• 10-Bit Slave Address Register
Address : 000096H
Default value →
Address : 000097H
Default value →
(Continued)
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(Continued)
• 10-Bit Slave Address Mask Register (ITMK)
bit
Address : 000098H
15
14
13
12
11
10
9
8
ENTB
RAL
⎯
⎯
⎯
⎯
TM9
TM8
R/W
0
R
0
⎯
⎯
⎯
⎯
R/W
1
R/W
1
7
6
5
4
3
2
1
0
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
⎯
SA6
SA5
SA4
SA3
SA2
SA1
SA0
⎯
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Default value →
Address : 000099H
Default value →
• 7-Bit Slave Address Register (ISBA)
Address : 00009BH
Default value →
R/W
0
• 7-Bit Slave Address Mask Register (ISMK)
Address : 00009AH
Default value →
15
14
13
12
11
10
9
8
ENSB
SM6
SM5
SM4
SM3
SM2
SM1
SM0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
• Data Register (IDAR)
Address : 00009DH
Default value →
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
TEST
⎯
EN
CS4
CS3
CS2
CS1
CS0
W
0
⎯
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DBL
⎯
⎯
⎯
⎯
⎯
⎯
R/W
0
• Clock Control Register (ICCR)
Address : 00009EH
Default value →
• Clock Disable Register (IDBL)
Address : 00009FH
Default value →
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MB91307 Series
(3) Block Diagram
ICCR
I2 C operation enabled
EN
IDBL
Clock enabled
R-bus
DBL
ICCR
Clock divider 2
CS4
CS3
CS2
CS1
CS0
IBSR
2 3 4 5
Sync
32
Shift clock generator
Clock select 2 (1/12)
Shift clock
edge change timing
Bus busy
BB
Repeat start
RSC
LRB
Start - stop
condition detector
Last Bit
Error
TX/RX
TRX
First Byte
ADT
AL
Arbitration lost detector
IBCR
SCL
BER
BEIE
Interrupt request
SDA
IRQ
INTE
INT
IBCR
End
Start
SCC
Master
MSS
ACK OK
ACK
Start - stop
condition generator
GC-ACK OK
GCAA
IDAR
IBSR
Slave
AAS
Global call
Slave address
compare
GCA
ENTB
ISMK
RAL
ITBA
64
ITMK
ISBA
ISMK
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MB91307 Series
9. DMAC (DMA Controller)
(1) Overview
This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices.
DMA transfer controlled by this module increases system performance by enabling high speed transfer of many
types of data without going through the CPU.
•Hardware Configuration
This module is principally configured from the following units:
• Five independent DMA channels
• 5 channels independent access control circuit
• 32-bit address registers (reload enabled: 2 per channel)
• 16-bit transfer count registers (reload enabled: 2 per channel)
• 4-bit block count registers (1 per channel)
• External transfer request input pins: DREQ0,DREQ1,DREQ2 (ch.0, ch.1, ch.2 only)
• External transfer request acknowledge output pins: DACK0,DACK1,DACK2 (ch.0, ch.1, ch.2 only)
• DMA output completed pins: DEOP0,DEOP1,DEOP2 (ch.0, ch.1, ch.2 only)
• Fly-by transfer (memory to I/O, memory to memory) (ch.0, ch.1, ch.2 only)
• Two-cycle transfer
•Principal Functions
Data transfer using the DMAC module primarily involves the following functions:
• Supports independent data transfer on multiple channels (5 channels)
(1) Order of priority (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
(2) The order can be reversed between ch.0 and ch.1.
(3) DMAC startup sources
• Input from an external-only pin (edge detection/level detection, ch.0, ch.1, ch.2 only)
• Request from a built-in peripheral (shared interrupt request, including external interrupts)
• Software request (register write)
(4) Transfer modes
• Demand transfer / burst transfer / step transfer / block transfer
• Addressing mode 32-bit full address designation (increment/decrement/fixed)
(address increment can be specified up to -255 to +255)
• Data type, byte / half-word / word length
• Single-shot / reload selection available
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MB91307 Series
(2) Register Descriptions
(bit)
ch.0 Control/status register A
DMACA0 0000200 H
ch.0 Control/status register B
DMACB0 0000204 H
ch.1 Control/status register A
DMACA1 0000208 H
ch.1 Control/status register B
DMACB1 000020CH
ch.2 Control/status register A
DMACA2 0000210 H
ch.2 Control/status register B
DMACB2 0000214 H
ch.3 Control/status register A
DMACA3 0000218 H
ch.3 Control/status register B
DMACB3 000021CH
ch.4 Control/status register A
DMACA4 0000220 H
ch.4 Control/status register B
DMACB4 0000224 H
Overall control register
D M A C R 0000240 H
ch.0 Transfer source address register
DMASA0 0001000 H
31
24
23
16
15
08
07
00
ch.0 Transfer destination address register DMADA0 0001004H
ch.1 Transfer source address register
DMASA1 0001008 H
ch.1 Transfer destination address register DMADA1 000100CH
ch.2 Transfer source address register
DMASA2 0001010 H
ch.2 Transfer destination address register DMADA2 0001014H
ch.3 Transfer source address register
DMASA3 0001018 H
ch.3 Transfer destination address register DMADA3 000101CH
ch.4 Transfer source address register
DMASA4 0001020 H
ch.4 Transfer destination address register DMADA4 0001024H
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(3) Block Diagram
Counter
DMA transfer request to
bus controller
DMA start
source selection
circuit & request
acceptance
control
Selector
Write
back
Buffer
DTC two-stage register DTCR
Peripheral start request/stop
input
External pin start request/stop
input
Counter
DSS3 to DSS0
Buffer
Selector
ERIR, EDIR
Status
transition
circuit
Peripheral interrupt clear
DDNO register
Selector
SDAM, SASZ7 to SASZ0 SADR
Write back
Selector
Counter/buffer
Counter/buffer
address
DSAD two-stage register
MCLREQ
TYPE, MOD, WS
DMA controller
Access
IRQ4 to
IRQ0
X-bus
Selector
DDNO
Address counter
To bus
controller
Bus control block
BLK register
To interrupt controller
Bus control block
Read
Write
Read/write
control
Priority
circuit
DDAD two-stage register
DADM, DASZ7 to DASZ0 DADR
Write back
DMAC 5-channel Block Diagram
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MB91307 Series
10. External Interface
(1) Overview
The external interface controller controls the interface between the LSI’s internal bus and external memory or I/
O devices.
This section describes the functions of the external interface.
(2) Features
• Up to 32 bit-length (4G bytes space) address output.
• Connects directly to many external memory (8 bit/16 bit) devices, allows control of multiple access timings.
Asynchronous SRAM, asynchronous ROM/Flash memory (multiple write strobe type or byte enable type)
Page mode ROM/flash memory (2/4/8 page size enabled)
Burst ROM/Flash memory (MBM29BL160D/161D/162D etc.)
Address/data multiplexed bus (8 bit/16 bit width only)
Synchronous memory* (ASIC built-in memory etc.)
*: Does not connect to synchronous SRAM.
• 8 independent bank (chip select area) settings, each with corresponding chip select output available
Each area size can be set in multiples of 64K bytes (from 64K bytes to 2G bytes per chip select area).
Each area can be set in any desired area of logic address space (boundaries limited by area size).
• The following functions can be independently set for each chip select area.
Chip select area enable/disable (no access to prohibited areas)
Access timing type setting for each area, etc.
Detailed access timing settings (individual access type settings for wait cycle, etc.)
Data bus width setting (8 bit/16 bit)
Byte ordering endian setting* (big or little).
*: CS0 area available with big endian only.
Write prohibited setting (read-only areas)
Internal cache loading enable/disable settings
Pre-fetch function enable/disable settings
Maximum burst length setting (1,2,4,8)
• Different detailed timing settings for each access timing type
Different settings can be used for each chip select area even for the same access timing type.
Auto wait setting up to 15 cycles (asynchronous SRAM, ROM, Flash, I/O areas)
Bus cycle extension with external RDY input enabled (asynchronous SRAM, ROM, Flash, I/O areas)
First access wait and page wait settings enabled (burst, page mode ROM/FLASH areas)
Different idle, recovery cycles setup delay insertion etc. enabled
• Fly-by transfer with DMA enabled
Transfer between memory and I/O with 1 access
Memory wait cycle can be synchronized with I/O wait cycle during fly-by
Hold time can be obtained by delaying transfer source access only
Specific idle/recovery cycles can be set for fly-by transfer
• External bus arbitration using BRQ and BGRNT enabled
• Pins not used in external interface can be set for use as general purpose I/O ports
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(3) Block Diagram
Internal
address bus
Internal data
bus
32
32
External data bus
Write buffer
Switch
Read buffer
Switch
MUX
Data block
Address block
+1 or +2
External address bus
Address buffer
ASR
CS0 to CS7
ASZ
Comparator
External pin control block
RD
WR0, WR1
AS, BAA
All block control
Resisters &
controls
BRQ
BGRNT
RDY
(4) I/O Pins
These are the external interface pins. (Some pins have dual functions.)
< Normal bus interface >
A24 to A0, D31 to D16
CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7
AS, SYSCLK, MCLK
RD
WE, WR0 (UUB) , WR1 (ULB)
RDY, BRQ, BGRNT
< Memory interface >
MCLK
LBA ( = AS) , BAA*
*: For burst ROM, Flash use
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MB91307 Series
< DMA interface >
IOWR, IORD
DACK0, DACK1, DACK2
DREQ0, DREQ1, DREQ2
DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2
(5) Register List
Address
bit31
24 23
16 15
8 7
00000640H
ASR0
ACR0
00000644H
ASR1
ACR1
00000648H
ASR2
ASR2
0000064CH
ASR3
ACR3
00000650H
ASR4
ACR4
00000654H
ASR5
ACR5
00000658H
ASR6
ACR6
0000065CH
ASR7
ACR7
00000660H
AWR0
AWR1
00000664H
AWR2
AWR3
00000668H
AWR4
AWR5
0000066CH
AWR6
AWR7
0
00000670H
Reserved
Reserved
Reserved
Reserved
00000674H
Reserved
Reserved
Reserved
Reserved
00000678H
IOWR0
IOWR1
IOWR2
Reserved
0000067CH
Reserved
Reserved
Reserved
Reserved
00000680H
CSER
CHER
Reserved
TCR
00000684H
Reserved
Reserved
Reserved
Reserved
00000688H
Reserved
Reserved
Reserved
Reserved
0000068CH
Reserved
Reserved
Reserved
Reserved
•••
•••
•••
•••
•••
000007F8H
Reserved
Reserved
Reserved
Reserved
000007FCH Reserved
(MODR)
Reserved
Reserved
Reserved: This address is reserved, and should always be set to “0.”
MODR: Cannot be accessed from user programs.
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■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Min
Max
Unit
Remarks
Supply voltage*1
VCC
VSS − 0.5
VSS + 4.0
V
*2
Internal supply voltage
VCCI
VSS − 0.5
VSS + 2.2
V
*2
Analog supply voltage
AVCC
VSS − 0.5
VSS + 4.0
V
*3
Analog reference voltage
AVRH
VSS − 0.5
VSS + 4.0
V
*3
Input voltage*
VI
VSS − 0.3
VCC + 0.3
V
*8
Analog pin input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage*1
VO
VSS − 0.3
VCC + 0.3
V
*8
ICLAMP
− 2.0
2.0
mA
*7
Σ⏐ICLAMP⏐
⎯
20
mA
*7
IOL
⎯
10
mA
*4
“L” level average output current
IOLAV
⎯
8
mA
*5
“L” level maximum total output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*6
IOH
⎯
−10
mA
*4
“H” level average output current
IOHAV
⎯
−4
mA
*5
“H” level maximum total output current
ΣIOH
⎯
−50
mA
“H” level average total output current
ΣIOHAV
⎯
−20
mA
Power consumption
PD
⎯
750
mW
Operating temperature
TA
0
+70
°C
TSTG
⎯
+150
°C
1
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level average total output current
“H” level maximum output current
Storage temperature
*6
*1 : The parameter is based on VSS = AVSS = 0 V.
*2 : VCC must not be lower than VSS − 0.3 V.
*3 : AVCC and AVRH shall never exceed VCC + 0.3 V. Also AVRH shall never exceed AVCC.
*4 : Maximum output current determines the peak value of any one of the corresponding pins.
*5 : Average output current is defined as the value of the average current in 100 ms period at any one of the
corresponding pins.
*6 : Average total output current is defined as the value of the average current in 100 ms period at all of the
corresponding pins.
*7 : • Applicable to pins : P20 to P27, P60 to P67, P70, PJ0 to PJ7, PI0 to PI5, PH0 to PH7, PB0 to PB5, PA0 to
PA7, P80 to P82, P85, P90 to P97, AN0 to AN3
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
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MB91307 Series
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply is
provided from the pins, so that incomplete operation may result.
•Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
•Input/Output Equivalent circuits
Protective diode
VCC
+B input (0 V to 16 V)
Limiting
resistance
P-ch
N-ch
R
*8 : VI and VO must not exceed VCC + 0.3V. However if the maximum current to/from an input is limited by some
means with external components, the ICLAMP rating supersedes the VI rating.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Parameter
Symbol
Value
Unit
Min
Max
VCC
3.0
3.6
V
VCCI
1.65
1.95
V
Analog supply voltage
AVCC
VSS − 0.3
VSS + 3.6
V
Analog reference voltage
AVRH
AVSS
AVCC
V
TA
0
+70
°C
Supply voltage
Operating temperature
Remarks
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
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3. DC Characteristics
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
“H” level input
voltage
“L” level input
voltage
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
VIH
See note *
⎯
0.7 × VCC
⎯
VCC + 0.3
V
VHIS
Input pins
other than *
⎯
0.8 × VCC
⎯
VCC + 0.3
V
VIL
See note *
⎯
VSS
⎯
0.25 ×
VCC
V
VILS
Input pins
other than *
⎯
VSS
⎯
0.2 × VCC
V
“H” level output
voltage
VOH
D16 to D31
VCC = 3.0 V
A00 to A25
VCC − 0.5
IOH = − 4.0 mA
P6 to PH
⎯
VCC
V
“L” level output
voltage
VOL
D16 to D31
VCC = 3.0 V
A00 to A25
IOL = 8.0 mA
P6 to PH
VSS
⎯
0.4
V
D16 to D31
VCC = 3.6 V
A00 to A25
0.45 V<VI<VCC
P8 to PH
−5
⎯
+5
µA
Input leak
current
(Hi-Z output leak
current)
ILI
Pull-up resistance
RUP
INIT
VCC = 3.6 V
VI = 0.45 V
12
25
100
kΩ
RDOWN
P82/BRQ
VCC = 3.6 V
VI = 3.3 V
12
25
100
kΩ
Pull-down
resistance
ICC
Supply current
ICCS
VCC+VCCI(
ICCH
Input capacitance
CIN
Other than:
VCC
VSS
AVCC
AVSS
Remarks
Hysteresis
input
Hysteresis
input
fC = 16.5 MHz
VCC = 3.3 V
VCCI = 1.8 V
⎯
150
⎯
(4x
multiplied)
mA
66 MHz
operation
fC = 16.5 MHz
VCC = 3.3 V
VCCI = 1.8 V
⎯
50
⎯
mA Sleep mode
TA = 25 °C
VCC = 3.3 V
VCCI = 1.8 V
⎯
150
⎯
µA
⎯
5
15
pF
⎯
Stop mode
* : Pins without hysteresis input pins: D16 to D31, RDY, BRQ, INIT
74
DS07-16314-3E
MB91307 Series
4. AC Characteristics
(1) Clock Timing Standards
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
fC
X0
X1
Clock cycle time
tC
X0
X1
Clock frequency (2)
fC
Clock frequency (3)
Clock cycle time
Parameter
Condition
Value
Unit
Remarks
Min
Max
12.5
16.5
MHz
⎯
60.6
ns
X0
X1
10
33
MHz
fC
X0
X1
10
33
MHz
tC
X0
X1
40
100
ns
Input clock pulse width
PWH
PWL
X0
X1
16
⎯
ns
Input clock rise, fall time
tCR
tCF
X0
X1
⎯
8
ns
fCP
0.78*2
66
MHz CPU system
fCPP
0.78*2
33
MHz Peripheral system
fCPT
*2
33
Clock frequency (1)
Internal operating clock frequency
⎯
⎯
0.78
Self oscillation (x1/2
frequency input)
External clock
(tCR + tCF)
MHz External bus system
15.2
*2
1280
ns
CPU system
tCPP
30.3
1280*2
ns
Peripheral system
tCPT
30.3
1280*2
ns
External bus system
tCP
Internal operating clock cycle time
⎯
⎯
PLL system*1
(self oscillation
16.5MHz,multiplied
x4,maximum internal
operation 66MHz)
*1 : When using the PLL, the clock frequency should be around 12.5 to 16.5 MHz.
*2 : The values shown represent a minimum clock frequency of 12.5 MHz input at the X0 pin, using the oscillator
circuit PLL and a gear ratio of 1/16.
DS07-16314-3E
75
MB91307 Series
• Clock timing measurement conditions:
tC
0.8 VCC
Output pin
0.2 VCC
C = 50 pF
PWL
PWH
tCR
tCF
• Warranted operating range
Power supply
VCC (V)
Warranted operating temperature:
(TA =0 °C to +70 °C)
VCC= 3.0 V to 3.6 V
fCPP is represented by the shaded area
1.95
1.65
0 0.78
33
66
fCP / fCPP
(MHz)
Internal clock
• External/internal clock setting range
Internal clock
(MHz)
fCP,
fCPT
66
fCPP
33
CPU, external bus systems
Peripheral system
16.5
4:4
2:2
1:2
CPU: Divided ratio for peripherals
Notes : • When using the PLL, the external clock input should be around 16.5 MHz.
• Set PLL oscillator stabilization time > 300 µs.
• The internal clock gear setting should be within the values shown in (1) clock timing standards.
76
DS07-16314-3E
MB91307 Series
(2) Clock Output Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Symbol
Pin
name
Cycle time
tCYC
MCLK,
SYSCLK
MCLK↑→MCLK↓
SYSCLK↑→SYSCLK↓
tCHCL
MCLK,
SYSCLK
MCLK↓→MCLK↑
SYSCLK↓→SYSCLK↑
tCLCL
MCLK,
SYSCLK
Parameter
Conditions
⎯
Value
Unit
Remarks
Min
Max
tCPT
⎯
ns
*1
1/2 × tCYC − 3
1/2 × tCYC + 3
ns
*2
1/2 × tCYC − 3
1/2 × tCYC + 3
ns
*3
tCYC
tCHCL
MCLK,
SYSCLK
tCLCH
VOH
VOH
VOL
*1 : tCYC represents the frequency of one clock cycle including the gear period.
*2 : The values shown represent standards for × 1 gear period.
For gear period settings of 1/2, 1/4, 1/8, use the following formula replacing n with the value 1/2, 1/4, 1/8
respectively.
(1/2 × 1/n) × tCYC − 10
*3 : The values shown represent standards for × 1 gear period.
Note : tCPT indicates the internal operating clock time. See “ (1) Clock Timing Standards”.
DS07-16314-3E
77
MB91307 Series
(3) Reset and Hardware Standby Input Standards
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Hardware standby input time
INIT input time
(power-on)
INIT input time
(other than power-on)
Symbol
Pin
name
tHSTL
VCCI
tINTL
Conditions
INIT
⎯
Value
Unit
Min
Max
tCP × 5
⎯
ns
*
⎯
ns
tCP × 5
⎯
ns
Remarks
tRSTL, tHSTL, tINTL
HST
INIT
0.2 VCC
* : INIT input time (at power-on)
Ceramic oscillator : φ × 215 or greater recommended
Crystal oscillator : φ × 221 or greater recommended
φ
: Power on → X0/X1 period × 2
Note : tCP indicates the clock cycle time. See “ (1) Clock Timing Standards”.
78
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MB91307 Series
(4) Normal Bus Access Read/Write Operation
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Condition
CS0 to CS7 setup
tCSLCH
CS0 to CS7 hold
tCSHCH
MCLK, SYSCLK,
CS0 to CS7
⎯
Address setup
tASCH
Address hold
Valid address →
valid data input time
Value
Unit Remarks
Min
Max
3
⎯
ns
3
tCYC/2 + 6
ns
MCLK, SYSCLK,
A23 to A00
3
⎯
ns
tCHAX
MCLK, SYSCLK,
A23 to A00
3
tCYC/2 + 6
ns
tAVDV
A23 to A00,
D31 to D16
⎯
3/2 ×
tCYC − 11
ns
⎯
6
ns
tCHWH
MCLK, SYSCLK,
WR0 to WR1
⎯
6
ns
WR0 to WR1 minimum pulse
width
tWLWH
WR0 to WR1
tCYC − 3
⎯
ns
Data setup → WRx↑
tDSWH
tCYC
⎯
ns
WRx↑ → data hold time
tWHDX
WR0 to WR1,
D31 to D16
5
⎯
ns
⎯
6
ns
⎯
6
ns
⎯
tCYC − 10
ns
10
⎯
ns
0
⎯
ns
WR0 to WR1 delay time
RD delay time
RD↓ → valid data input time
tCHWL
tCHRL
tCHRH
⎯
MCLK, SYSCLK,
RD
tRLDV
RD,
D31 to D16
Data setup → RD↑time
tDSRH
RD↑ → data hold time
tRHDX
RD minimum pulse width
tRLRH
RD
tCYC − 3
⎯
ns
AS setup
tASLCH
3
⎯
ns
AS hold
tASHCH
MCLK, SYSCLK,
AS
3
⎯
ns
*
*
* : To extend bus time by automatic wait insertion or RDY input, add to this value (tCYC × number of extended cycles).
Note : tCYC indicates the cycle time. See “ (2) Clock Output Timing”.
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MB91307 Series
tCYC
BA1
MCLK,
SYSCLK
VOH
VOH
VOH
tASLCH
tASHCH
VOH
VOH
AS
LBA
VOL
tCSLCH
CS0 to CS7
tCSHCH
VOH
VOL
tASCH
A23 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRL
tCHRH
tRLRH
RD
VOH
VOL
tRHDX
tRLDV
tDSRH
tAVDV
D31 to D16
VOH
VOL
tCHWL
VOH
VOL
tCHWH
tWLWH
VOH
WR0 to WR1
VOL
tDSWH
D31 to D16
80
VOH
VOL
Write
tWHDX
VOH
VOL
DS07-16314-3E
MB91307 Series
(5) Ready Input Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Condition
RDY setup time →
MCLK↑, SYSCLK↑
tRDYS
MCLK, SYSCLK,
RDY
MCLK↑, SYSCLK↑
RDY hold time
tRDYH
MCLK, SYSCLK,
RDY
Value
Unit
Min
Max
⎯
10
⎯
ns
⎯
0
⎯
ns
Remarks
tCYC
VOH
MCLK,
SYSCLK
VOH
VOL
VOL
tCHASL
tRDYS
tRDYH
tRDYS tRDYH
RDY
Wait applied
VOH
VOL
VOH
VOL
RDY
Wait not applied
VOH
VOH
VOL
DS07-16314-3E
VOL
81
MB91307 Series
(6) Hold Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
tCHBGL
MCLK, SYSCLK,
BGRNT
BGRNT delay time
tCHBGH
Pin floating
→ BGRNT↓time
tXHAL
BGRNT↑ → valid time
tHAHV
Condition
⎯
BGRNT
Value
Unit
Min
Max
3
13.5
ns
3
13.5
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Remarks
Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes.
tCYC
MCLK,
SYSCLK
VOH
VOH
VOH
VOH
BRQ
tCHBGH
tCHBGL
BGRNT
VOH
VOL
tHXAL
tHAHV
Pins
Hi-Z
82
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MB91307 Series
(7) UART Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol Pin name
Condition
Value
Min
Max
Unit
Serial clock cycle time
tSCYC
SC0 to SC2
8 tCPP
⎯
ns
SCLK↓ → SOUT delay time
tSLOV
SC0 to SC2,
SO0 to SO2
−80
80
ns
Valid SIN → SCLK↑
tIVSH
100
⎯
ns
SCLK↑ → valid SIN hold time
tSHIX
SC0 to SC2,
SI0 to SI2
60
⎯
ns
Serial clock “H” pulse width
tSHSL
SC0 to SC2
4 tCPP
⎯
ns
Serial clock “L” pulse width
tSLSH
SC0 to SC2
4 tCPP
⎯
ns
SCLK↓ → SOUT delay time
tSLOV
SC0 to SC2,
SO0 to SO2
⎯
150
ns
Valid SIN → SCLK↑
tIVSH
60
⎯
ns
SCLK↑ → valid SIN hold time
tSHIX
60
⎯
ns
Internal
SC0 to SC2, shift clock
mode
SI0 to SI2
External
shift clock
SC0 to SC2,
mode
SI0 to SI2
SC0 to SC2,
SI0 to SI2
Remarks
Notes: • Above ratings are for operation in CLK synchronized mode.
• tCPP is the cycle time of the peripheral system clock.
• Internal Shift Clock Mode
tSCYC
VOH
SC0, SC1
VOL
tSLOV
VOL
VOH
VOL
SO0, SO1
tSHIX
tIVSH
VOH
VOL
VOH
VOL
SI0, SI1
• External Shift Clock Mode
tSLSH
tSHSL
VOH
SC0, SC1
VOL
VOL
VOL
tSLOV
SO0, SO1
VOH
VOL
tIVSH
SI0, SI1
DS07-16314-3E
VOH
VOL
tSHIX
VOH
VOL
83
MB91307 Series
(8) Timer Clock Input Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
TIN0 to TIN2
⎯
Value
Min
Max
2 tCYCP
⎯
Unit
Remarks
ns
Note: tCYCP is the cycle time of the peripheral system clock.
TIN0 to TIN2
tTIWL
tTIWH
(9) Trigger Input Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
A/D startup trigger input time
Symbol Pin name
tATGX
Condition
⎯
ATG
Value
Min
Max
5 tCYCP
⎯
Unit
Remarks
ns
Note: tCYCP is the cycle time of the peripheral system clock.
tATGX
ATG
84
DS07-16314-3E
MB91307 Series
(10) DMA Controller Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
DREQ input pulse width
tDRWH
DSTP input pulse width
DACK delay time
DEOP delay time
IORD delay time
IOWR delay time
DS07-16314-3E
Condition
Value
Unit
Min
Max
DREQ 0 to DREQ2
5 tCYC
⎯
ns
tDSWH
DSTP 0 to DSTP2
5 tCYC
⎯
ns
tCLDL
MCLK, SYSCLK,
DACK0 to DACK2
⎯
6
⎯
6
⎯
6
⎯
6
⎯
6
⎯
6
⎯
6
⎯
6
tCLDH
tCLEL
tCLEH
tCLIRL
tCLIRH
tCLIWL
tCLIWH
MCLK, SYSCLK,
DEOP 0 to DEOP2
MCLK, SYSCLK
MCLK, SYSCLK
⎯
Remarks
ns
ns
ns
ns
85
MB91307 Series
tCYC
BA1
BA2
VOH
MCLK,
SYSCLK
VOH
VOL
VOL
VOL
tCLDL
tCLDH
VOH
DACK0 to DACK2
VOL
tCLEL
tCLEH
VOH
DEOP0 to DEOP2
VOL
tCLIRL
tCLIRH
VOH
IORD
VOL
tCLIWL
tCLIWH
VOH
IOWR
VOL
tDRWH
VOH
DREQ0 to DREQ2
VOL
tDSWH
DSTP0 to DSTP2
86
VOH
VOL
DS07-16314-3E
MB91307 Series
(11) I2C Timing
(VCCI = 1.65 V to 1.95 V, VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Condition
Standard mode
High-speed mode*4
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
⎯
0.6
⎯
µs
SCL clock “L” width
tLOW
4.7
⎯
1.3
⎯
µs
SCL clock “H” width
tHIGH
4.0
⎯
0.6
⎯
µs
Repeat “start” condition setup time
SCL ↑ → SDA ↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
µs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT
250
⎯
100
⎯
ns
“Stop” condition setup time
SCL ↑ → SDA ↑
tSUSTO
4.0
⎯
0.6
⎯
µs
tBUS
4.7
⎯
1.3
⎯
µs
SCL clock frequency
(Repeat) “start” condition hold time
SDA ↓ → SCL ↓
Bus free time between “stop” and
“start” conditions
R = 1.0 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the resource clock to at least 6 MHz.
SDA
tSUDAT
tLOW
tBUS
tHDSTA
SCL
tHDSTA
DS07-16314-3E
tHDDAT
tHIGH
tSUSTA
tSUSTO
87
MB91307 Series
5. A/D Converter Electrical Characteristics
(VCCI = 1.65 V to 1.95 V, VCC = +3.0 V to +3.6 V, VSS = AVSS = 0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Resolution
⎯
Total error
Value
Unit
Min
Typ
Max
⎯
⎯
10
10
BIT
⎯
⎯
⎯
⎯
± 4.5
LSB
Linear error
⎯
⎯
⎯
⎯
± 3.0
LSB
Differential linear error
⎯
⎯
⎯
⎯
± 2.5
LSB
Zero transition voltage
VOT
AN0 to AN3
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
4.5 LSB
V
Full scale transition voltage
VFST
AN0 to AN3
AVRH −
4.5 LSB
AVRH −
1.5 LSB
AVRH +
4.5 LSB
V
Conversion time
⎯
⎯
5.4 *1
⎯
⎯
µs
Analog port input current
IAIN
AN0 to AN3
⎯
0.1
10
µA
Analog input voltage
VAIN
AN0 to AN3
AVss
⎯
AVRH
V
⎯
AVRH
AVss
⎯
AVCC
V
⎯
600
⎯
µA
⎯
⎯
10 *2
µA
⎯
600
⎯
µA
⎯
⎯
10 *
⎯
⎯
5
Reference voltage
IA
Supply current
IAH
Reference voltage supply current
Inter-channel variation
AVCC
IR
AVRH
IRH
⎯
AN0 to AN3
2
µA
LSB
*1 : At VCC = AVCC = 3.0 V to 3.6 V, VCCI = 1.65 V to 1.95 V peripheral clock 33 MHz.
*2 : Current in CPU stop mode with A/D converter not operating (at VCC = AVCC = AVRH = 3.6 V, VCCI = 1.95 V)
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
Note : The values are reference values.
88
MB91307R/306R
MB91V307R
R
C
5.0 kΩ (Max) 15 pF (Max)
8.1 kΩ (Max) 10 pF (Max)
DS07-16314-3E
MB91307 Series
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the operating frequency or decrease the external impedance
so that the sampling time is longer than the minimum value.
• The relationship between external impedance and minimum sampling time
External impedance = 0 kΩ to 20 kΩ
100
90
80
70
60
50
40
30
20
10
0
MB91V307R
External impedance [kΩ]
External impedance [kΩ]
External impedance = 0 kΩ to 100 kΩ
MB91307R
MB91306R
0
5
10
15
20
25
30
Minimum sampling time [µs]
35
20
18
16
14
12
10
8
6
4
2
0
MB91V307R
MB91307R
MB91306R
0
1
2
3
4
5
6
7
8
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As | AVRH - AVSS | becomes smaller, values of relative errors grow larger.
DS07-16314-3E
89
MB91307 Series
• Definition of A/D Converter Terms
• Resolution
Indicates the ability of the A/D converter to discriminate analog variation
• Linear error
Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s
zero transition point (00 0000 0000←→00 0000 0001) and full scale transition point (11 1111 1110←→11
1111 1111)
• Differential linear error
Expresses the deviation of the logical value of input voltage required to create a variation of 1 LSB in output
code.
[Differential linear error]
[Linear Error]
3FFH
Actual variation
Theoretical variation
3FEH
N−1
3FDH
VFST
(measured
value)
VNT
(measured
value)
004H
003H
Actual variation
Digital output
Digital output
{1 LSB × (N − 1) + VTO}
N−2
V(N − 1)T
(measured
value)
N−1
Actual variation
VNT
(measured value)
002H
Theoretical values
001H
N−2
Actual variation
VTO (measured value)
AVSS/AVRL
AVRH
AVSS/AVRL
AVRH
Analog input
Analog input
=
Linear error in digital output N
Differential linear error in digital output N =
1 LSB =
1 LSB” =
VFST − VOT
1022
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
[LSB]
V (N + 1) T − VNT
1 LSB
[LSB]
−1
[V]
AVRH − AVRL
1024
[V]
(theoretical value)
VOT : Voltage at which the digital output transitions from “000”H to “001”H.
VFST : Voltage at which the digital output transitions from “3FE”H to “3FF”H.
VNT : Voltage at which the digital output transitions from (N-1) to N.
90
DS07-16314-3E
MB91307 Series
• Total error
Expresses the difference between actual and theoretical values as error, including zero transition error, fullscale error, and linearity error.
[Total error]
3FFH
Actual variation
1.5 LSB
3FEH
{1 LSB × (N − 1) + 0.5 LSB
Digital output
3FDH
VNT
(measured
value)
004H
003H
Actual variation
002H
theoretical value
001H
0.5 LSB
AVSS/AVRL
AVRH
Analog input
VNT − {1 LSB” × (N − 1) + 0.5 LSB”}
[LSB]
1 LSB”
VOT” (theoretical value) = AVRL + 0.5 LSB” [V]
Total error in digital output N =
VFST” (theoretical value) = AVRH − 1.5 LSB” [V]
VNT : Voltage at which digital output transitions from (N-1) to N.
DS07-16314-3E
91
MB91307 Series
■ EXAMPLE CHARACTERISTICS
(1) Sample output voltage characteristics (TA = +25 °C)
Sample output “H” voltage (VOH) characteristics
Sample output “L” voltage (VOL) characteristics
0.4
Output voltage (V)
Output voltage (V)
3.6
3.4
3.2
3.0
2.8
0.3
0.2
0.1
0.0
3.0
3.2
3.4
3.6
3.0
Supply voltage (V)
3.2
3.4
3.6
Supply voltage (V)
(2) Sample input voltage characteristics (TA = +25 °C)
Sample input “H”/“L” level characteristics (CMOS)
Sample input “H”/“L” level characteristics (hysteresis)
3.0
2.0
VIH
VIL
1.0
Input voltage (V)
Input voltage (V)
3.0
VIH
2.0
1.0
VIL
0.0
0.0
3.0
3.2
3.4
3.6
Supply voltage (V)
3.0
3.2
3.4
3.6
Supply voltage (V)
(3) Sample supply current characteristics
Sample supply current (ICC) characteristics
(TA = +25 °C, 66 MHz)
Sample supply current (ICC) characteristics
(VCC = 3.3 V, 66 MHz)
200
Supply current (mA)
Supply current (mA)
200
150
100
50
0
150
100
50
0.0
3.0
3.2
3.4
3.6
Supply voltage (V)
0
25
70
Temperature ( °C)
(Continued)
92
DS07-16314-3E
MB91307 Series
(Continued)
Sample sleep current (ICCS) characteristics
(VCC = 3.3 V, 33 MHz)
50
50
Supply current (mA)
Supply current (mA)
Sample sleep current (ICCS) characteristics
(TA = +25 °C, 33 MHz)
40
30
20
40
30
20
0
3.0
3.2
3.4
3.6
Supply voltage (V)
Sample A/D supply current (IA) characteristics
(TA = +25 °C, 33 MHz)
Sample A/D reference current (IR) characteristics
(TA = +25 °C, 33 MHz)
500
Supply current (µA)
500
Supply current (µA)
25
70
Temperature ( °C)
400
300
200
3.0
400
300
200
3.0
3.2
3.4
3.6
Supply voltage (V)
3.2
3.4
3.6
Supply voltage (V)
(4) Port resistance characteristics
Sample pull-up resistance characteristics
(TA = +25 °C)
Sample pull-down resistance characteristics
(TA = +25 °C)
30
Resistance (kΩ)
Resistance (kΩ)
30
25
20
15
25
20
15
3.0
3.2
3.4
3.6
Supply voltage (V)
DS07-16314-3E
3.0
3.2
3.4
3.6
Supply voltage (V)
93
MB91307 Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91306RPFV
MB91307RPFV
120-pin, Plastic LQFP
(FPT-120P-M21)
Lead-free package
MB91V307RCR
135-pin, Ceramic PGA
(PGA-135C-A02)
For development tool use
94
DS07-16314-3E
MB91307 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
60
91
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
"A"
31
1
30
0.50(.020)
0.22±0.05
(.009±.002)
0.08(.003)
M
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5
C
2002 FUJITSU LIMITED F120033S-c-4-4
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16314-3E
95
MB91307 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
10
■ PIN DESCRIPTIONS
Pin name : Changed the description of P91 and P93
31
■ MEMORY SPACE
2. Memory Map
Changed Internal RAM capacity of MB91306R.
128 K → 64 K
■ PERIPHERAL RESOURCES
4. 16-bit Reload Timer
55, 60
7. A/D Converter (Sequential comparison
type)
Changed the operating clock name of peripheral resources
machine clock → peripheral clock
61
7. A/D Converter (Sequential comparison
type)
Changed the channel of the reload timer in Note
channel 2 → channel 1
66
9. DMAC (DMA Controller)
(2) Register Descriptions
Changed the register name of DMADA0 to DMADA4.
Transfer source → Transfer destination
75
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
Changed the value of the external bus system in “(1) Clock
Timing Standards”.
Internal operating clock frequency (max) 66 → 33
Internal operating clock cycle time (min) 15.2 → 30.3
88
5. A/D Converter Electrical Characteristics
Changed the items of “Zero transition voltage” and “Full
scale transition voltage”.
Parameter : transition error → transition voltage
Unit : LSB → V
Value : value → AVSS ± value LSB
Value : AVRH ± value → AVRH ± value LSB
Changed the operating clock name of peripheral resources
machine clock → peripheral clock
The vertical lines marked in the left side of the page show the changes.
96
DS07-16314-3E
MB91307 Series
MEMO
DS07-16314-3E
97
MB91307 Series
MEMO
98
DS07-16314-3E
MB91307 Series
MEMO
DS07-16314-3E
99
MB91307 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
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#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
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http://emea.fujitsu.com/microelectronics/
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
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206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
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property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
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