2.6 MB

The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16502-5E
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91301 Series
MB91302A/V301A
■ DESCRIPTION
The MB91301 series are a line of microcontrollers based on a 32-bit RISC CPU core (FR family) , incorporating
a variety of I/O resources and a bus control mechanism for embedded control that requires the processing of a
high-performance, fast CPU as well as an SDRAM interface that can connect SDRAM directly to the chip.
The large address space supported by the 32-bit CPU addressing means that operation is primarily based on
external bus access although instruction cache memory of 4 Kbytes and RAM of 4 Kbytes (for data) are included
for high-speed execution of CPU instructions.
The MB91302A and MB91V301A are FR60 products based on the FR30/40 CPU with enhanced bus access for
higher speed operation. The device specifications include a D/A converter to facilitate motor control and are ideal
for use in DVD players that support fly-by transfer.
■ FEATURES
The MB91301 series is a line of ICs with various programs embedded in internal ROM.
ROM variation
Product name
Built-in the real
Built-in IPL
time OS version (Internal Program Loader) version
User ROM
version
Without ROM
version
MB91302A
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.10
MB91301 Series
1. FR CPU
• 32-bit RISC, load/store architecture, 5-stage pipeline
• 68 MHz internal operating frequency (Max) [external (Max) 68 MHz] (when using PLL with base frequency
(Max) = 17 MHz)
• General purpose registers : 32 bits×16
• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle
• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
• Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store
instructions
• Easier assembler coding : Register interlock function
• Branch instructions with delay slots : Reduced overhead time in branch executions
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
2. Bus interface
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating frequency : Max 68 MHz (when using SDRAM)
Full 24-bit address output (16 Mbytes memory space)
8-bit, 16-bit or 32-bit data input/output
Built-in pre-fetch buffer
Unused data and address pins can be used as general-purpose input/output ports.
Eight fully independent chip select outputs, can be set in minimum 64 Kbytes units.
Supports the following memory interfaces
Asynchronous SRAM, asynchronous ROM/Flash
Page mode ROM/Flash ROM (selectable page size = 1, 2, 4, or 8)
Burst mode ROM/Flash ROM (MBM29BL160D/161D/162D)
SDRAM (FCRAM Type, CAS Latency 1 to 8, 2/4 bank products.)
Address/Data multiplex bus (only 8/16-bit width)
Basic bus cycle : 2 cycles
Automatic wait cycle generation function can insert wait cycles, independently programmable for each memory
area.
RDY input for external wait cycles
Endian setting of byte ordering (Big/Little)
CS0 area only for big endian
Prohibition setting of write (only for Read)
Permission/prohibition setting of fetch into built-in cache
Permission/prohibition setting of prefetch function
DMA supports fly-by transfer with independent I/O wait control
External bus arbitration can be used using BRQ and BGRNT.
3. Built-in memory
• 4 Kbytes DATA RAM
• ROM: 4 Kbytes (MB91302A)
(Continued)
2
DS07-16502-5E
MB91301 Series
4. Instruction cache
•
•
•
•
•
Size : 4 Kbytes
2-way set associative
128 blocks/way, 4 entries/block
Lock function enables program code to be made cache-resident
Areas not used for instruction cache can be used as instruction RAM
5. DMAC (DMA Controller)
•
•
•
•
•
•
•
5-channel (2-channel external-to-external)
3 transfer triggers : External pin, internal peripheral, software
Capable of selecting an internal peripheral as a transfer source freely for each channel
Addressing using 32-bit full addressing mode (increment, decrement, fixed)
Transfer modes : Demand transfer, burst transfer, step transfer, or block transfer
Supports fly-by transfer (between external I/O and memory)
Selectable transfer data size : 8, 16, or 32-bit
6. Bit search module
• Searches words from MSB for position of first 1/0 bit value change
7. Reload Timers
• 16-bit timer : 3 channels
• Internal clock : 2 clock cycle resolution, divide by 2/8/32 selective
8. UART
•
•
•
•
•
•
•
•
Full duplex, double buffer UART
Independent 3 channels
Data length : 7 bits to 9 bits (without parity) , 6 bits to 8 bits (with parity)
Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
Multi-processor mode
Built-in 16-bit timer (U-TIMER) as a baud rate generator to generate arbitrary baud rates
External clock can be used as transfer clock
Variety of error detection functions (parity, frame, overrun)
9. Interrupt controller
• External interrupt input : 1 non-maskable interrupt pin and 8 normal interrupt pins (INT0 to INT7)
• Internal internal resources : UART, DMAC, A/D, U-TIMER, Delay interrupt, I2C, Free-run timer, Input capture
• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. A/D converter
•
•
•
•
•
10-bit resolution, 4 channels
Successive approximation type, conversion time : 4.1 μs at 34 MHz
Built-in sample and hold circuit
Conversion modes : Single conversion mode, scan conversion mode and repeat conversion mode selectable
Conversion triggers : Software, external trigger and built-in timer selectable
11. I2C interface
• Internal 2-channels master/slave transmit/receive
• Internal arbitration function, clock synch function
12. Free-run timer
• 16-bit : 1channel
(Continued)
DS07-16502-5E
3
MB91301 Series
(Continued)
13. Input capture
• 4 channels
14. Other interval timers
• 16-bit timer : 3 channels (U-TIMER)
• PPG timer : 4 channels
• Watchdog timer : 1 channel
15. Other features
• Reset resources : watchdog timer/software reset/external reset (INIT pin)
• Power-saving modes : Stop mode, sleep mode
• Clock control
Gear function : Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals.
You can select one of the 16 gear clock factors of 1/1 to 1/16. PLL multiplication can also be selected. Note,
however, that peripherals operate at a maximum of 34 MHz.
• CMOS technology : 0.25 μm
• Power supply (analog power supply): 3.3 V ± 0.3 V (internal regulator used)
■ PRODUCT LINEUP
MB91302A
MB91V301A
Type
Mask ROM product
(for volume production)
Evaluation version
(For evaluation and development)
RAM
4 Kbytes
(only for data)
16 Kbytes
(data 8 KB+8 KB)
ROM
4 Kbytes
ROM has non-ROM model, the optimal real time
OS internal model*1, and the IPL (Internal Program
Loader) internal model*2 by adding the user ROM
model.
8 Kbytes (RAM)
DSU
⎯
DSU4
LQFP-144
(0.4 mm pitch)
PGA-179
Package
*1 : The Fujitsu product of real time OS REALOS/FR by conforming to the μITRON 3.0 is stored and optimized
with the MB91302A.
*2 : The ROM stores the IPL (Internal Program Loader) . Loading various programs can be executed from the
external system by the internal UART/SIO. Using this function, for example, writing on board to the Flash
memory connected to the external can be executed.
4
DS07-16502-5E
MB91301 Series
■ PIN ASSIGNMENTS
• MB91302A
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DEOP1/PPG1/PB5
DACK1/TRG1/PB4
DREQ1/PB3
DEOP0/PB2
DACK0/PB1
DREQ0/PB0
C
VSS
TIN2/TRG3/PH2
TIN1/PPG3/PH1
TIN0/PH0
TRG0/PJ7
PPG0/PJ6
SCK1/PJ5
SOT1/PJ4
SIN1/PJ3
SCK0/PJ2
SOT0/PJ1
SIN0/PJ0
VCC
INT7/SCK2/PG7
INT6/SOT2/PG6
INT5/SIN2/PG5
INT4/ATG/PG4/FRCK
INT3/PG3/ICU3
INT2/PG2/ICU2
INT1/PG1/ICU1
INT0/PG0/ICU0
AVSS/AVRL
AN0
AN1
AN2
AN3
AVR
AVRH
AVCC
P91/MCLKE
P92/MCLK
P93
P94/SRAS/LBA/AS
P95/SCAS/BAA
P96/SWE/WR
VSS
VCC
A00
A01
A02
A03
A04
A05
A06
A07
VSS
VCC
A08
A09
A10
A11
A12
A13
A14
A15
VSS
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20/SDA0
P65/A21/SCL0
P66/A22/SDA1
P67/A23/SCL1
VCC
P13/D11
P14/D12
P15/D13
P16/D14
P17/D15
VSS
VCC
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
VSS
VCC
D24
D25
D26
D27
D28
D29
D30
D31
VSS
VCC
P80/RDY
P81/BGRNT
P82/BRQ
RD
DQMUU/WR0(UUB)
P85/DQMUL/WR1(ULB)
P86/DQMLU/WR2(LUB)
P87/DQMLL/WR3(LLB)
P90/SYSCLK
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
D10/P12
D09/P11
D08/P10
VCC
VSS
D07/P07
D06/P06
D05/P05
D04/P04
D03/P03
D02/P02
D01/P01
D00/P00
VCC
VSS
CS7/PA7
CS6/PA6
CS5/PPG2/PA5
CS4/TRG2/PA4
CS3/PA3
CS2/PA2
CS1/PA1
CS0/PA0
VCC
NMI
INIT
MD2
MD1
MD0
VCC
VSS
X1
X0
VCC
IORD/PB7
IOWR/PB6
(TOP VIEW)
(FPT-144P-M12)
DS07-16502-5E
5
MB91301 Series
• MB91V301A
(TOP VIEW)
INDEX
1
5
178
174
172
168
165
161
160
156
155
151
150
145
142
140
2
7
179
177
173
169
166
162
157
154
149
148
144
139
134
133
3
10
4
2
176
171
167
163
159
153
147
143
138
137
132
129
4
15
9
3
180
175
170
164
158
152
146
141
135
131
128
127
5
16
13
8
6
1
136
130
126
124
123
6
20
14
12
11
125
122
121
120
7
21
19
18
17
119
118
117
116
8
25
22
24
23
113
114
112
115
9
26
27
28
29
107
108
109
111
10
30
31
32
35
101
102
104
110
11
33
34
36
40
46
91
96
98
103
106
12
37
38
41
45
51
56
62
68
74
80
85
90
93
99
105
13
39
42
47
48
53
57
63
69
73
77
81
86
92
94
100
14
43
44
49
54
58
59
64
67
72
76
79
83
87
89
97
15
50
52
55
60
61
65
66
70
71
75
78
82
84
88
95
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
(PGA-179C-A03)
6
DS07-16502-5E
MB91301 Series
• MB91V301A Pin No. Table
No.
PIN
Pin Name
No.
PIN
Pin Name
No.
PIN
Pin Name
1
E5
N.C.
31
B10
VSS
61
E15
A07
2
C3
P13/D11
32
C10
VCC
62
G12
VSS
3
C4
VSS
33
A11
P80/RDY
63
G13
VCC
4
B3
VCC
34
B11
P81/BGRNT
64
G14
A08
5
A1
P14/D12
35
D10
P82/BRQ
65
F15
A09
6
D5
P15/D13
36
C11
RD
66
G15
A10
7
A2
P16/D14
37
A12
DQMUU/WR0 (UUB)
67
H14
A11
8
C5
P17/D15
38
B12
P85/DQMUL/WR1
(ULB)
68
H12
A12
9
B4
VSS
39
A13
P86/DQMLU/WR2
(LUB)
69
H13
A13
10
A3
VCC
40
D11
P87/DQMLL/WR3
(LLB)
70
H15
A14
11
D6
P20/D16
41
C12
VSS
71
J15
A15
12
C6
P21/D17
42
B13
VCC
72
J14
VSS
13
B5
P22/D18
43
A14
P90/SYSCLK
73
J13
VCC
14
B6
P23/D19
44
B14
P91/MCLKE
74
J12
P60/A16
15
A4
P24/D20
45
D12
P92/MCLK
75
K15
P61/A17
16
A5
P25/D21
46
E11
P93
76
K14
P62/A18
17
D7
P26/D22
47
C13
VSS
77
K13
P63/A19
18
C7
P27/D23
48
D13
VCC
78
L15
SDA0/P64/A20
19
B7
VSS
49
C14
P94/SRAS/LBA/AS
79
L14
SCL0/P65/A21
20
A6
VCC
50
A15
P95/SCAS/BAA
80
K12
SDA1/P66/A22
21
A7
D24
51
E12
P96/SWE/WR
81
L13
SCL1/P67/A23
22
B8
D25
52
B15
VSS
82
M15
VCC
23
D8
D26
53
E13
VCC
83
M14
VCC
24
C8
D27
54
D14
A00
84
N15
EWR3
25
A8
VSS
55
C15
A01
85
L12
EWR2
26
A9
VCC
56
F12
A02
86
M13
EWR1
27
B9
D28
57
F13
A03
87
N14
EWR0
28
C9
D29
58
E14
A04
88
P15
ECS
29
D9
D30
59
F14
A05
89
P14
EMRAM
30
A10
D31
60
D15
A06
90
M12
ICD3
(Continued)
DS07-16502-5E
7
MB91301 Series
(Continued)
No.
PIN
8
Pin Name
No.
PIN
Pin Name
No.
PIN
Pin Name
91
L11
ICD2
121
P6
SOT0/PJ1
151
L1
VCC
92
N13
ICD1
122
N6
SCK0/PJ2
152
J4
INIT
93
N12
ICD0
123
R5
SIN1/PJ3
153
J3
NMI
94
P13
VSS
124
P5
SOT1/PJ4
154
J2
VSS
95
R15
VCC
125
M6
SCK1/PJ5
155
K1
VCC
96
M11
BREAK
126
N5
PPG0/PJ6
156
J1
CS0/PA0
97
R14
ICLK
127
R4
TRG0/PJ7
157
H2
CS1/PA1
98
N11
ICS2
128
P4
TIN0/PH0
158
H4
CS2/PA2
99
P12
ICS1
129
R3
TIN1/PPG3/PH1
159
H3
CS3/PA3
100
R13
ICS0
130
M5
TIN2/TRG3/PH2
160
H1
CS4/TRG2/PA4
101
M10
TRST
131
N4
VSS
161
G1
CS5/PPG2/PA5
102
N10
C
132
P3
C
162
G2
CS6/PA6
103
P11
AVCC
133
R2
DREQ0/PB0
163
G3
CS7/PA7
104
P10
AVRH
134
P2
DACK0/PB1
164
G4
VSS
105
R12
AVR
135
M4
DEOP0/PB2
165
F1
VCC
106
R11
AN3
136
L5
DREQ1/PB3
166
F2
D00/P00
107
M9
AN2
137
N3
DACK1/TRG1/PB4 167
F3
D01/P01
108
N9
AN1
138
M3
DEOP1/PPG1/PB5 168
E1
D02/P02
109
P9
AN0
139
N2
IOWR/PB6
169
E2
D03/P03
110
R10
AVSS/AVRL
140
R1
IORD/PB7
170
F4
VSS
111
R9
INT0/PG0/ICU0
141
L4
VCC
171
E3
VCC
112
P8
INT1/PG1/ICU1
142
P1
VSS
172
D1
D04/P04
113
M8
INT2/PG2/ICU2
143
L3
X0
173
D2
D05/P05
114
N8
INT3/PG3/ICU3
144
M2
X1
174
C1
D06/P06
115
R8
INT4/ATG/PG4/FRCK
145
N1
VSS
175
E4
D07/P07
116
R7
INT5/SIN2/PG5
146
K4
VCC
176
D3
VSS
117
P7
INT6/SOT2/PG6
147
K3
MD0
177
C2
VCC
118
N7
INT7/SCK2/PG7
148
L2
MD1
178
B1
D08/P10
119
M7
VCC
149
K2
MD2
179
B2
D09/P11
120
R6
SIN0/PJ0
150
M1
VCC
180
D4
D10/P12
DS07-16502-5E
MB91301 Series
■ PIN DESCRIPTIONS
• Except for Power supply, GND, and Tool pins
Pin no.
MB91302A
MB91V301A
166 to 169,
172 to 175
132 to 139
142 to 144,
1 to 5
178 to 180, 2,
5 to 8
8 to 15
11 to 18
Pin name
I/O circuit
type
D00 to D07
J
21 to 24,
27 to 30
Can be used as ports in 8-bit or 16-bit external bus
mode.
D08 to D15
External data bus bits 8 to 15.
It is available in the external bus mode.
J
P10 to P17
D16 to D23
J
D24 to D31
29
30
33
C
J
32
External ready input. The pin has this function when
external ready input is enabled.
BGRNT
Acknowledge output for external bus release.
Outputs "L" when the external bus is released. The
pin has this function when output is enabled.
J
P81
General purpose input/output port. The pin has this
function when output is disabled for external bus
release acknowledge.
BRQ
External bus release request input. Input "1" to
request release of the external bus. The pin has this
function when input is enabled.
35
37
External data bus bits 24 to 31.
It is available in the external bus mode.
General purpose input/output port. The pin has this
function when external ready input is disabled.
34
36
External data bus bits 16 to 23.
It is available in the external bus mode.
P80
J
P82
31
Can be used as ports in 8-bit or 16-bit external bus
mode.
Can be used as ports in 8-bit external bus mode.
RDY
28
External data bus bits 0 to 7. It is available in the
external bus mode.
P00 to P07
P20 to P27
18 to 25
Function
RD
WR0/ (UUB) /
DQMUU
General purpose input/output port. The pin has this
function when the external bus release request
input is disabled.
C
External bus read strobe output.
C
External bus write strobe output. When WR is used
as the write strobe, this becomes the byte-enable
pin (UUB).
Select signal (DQMUU) of D31 to D24 at using of
SDRAM.
(Continued)
DS07-16502-5E
9
MB91301 Series
Pin no.
MB91302A
MB91V301A
Pin name
I/O circuit
type
WR1/ (ULB) /
DQMUL
33
34
35
36
J
38
General purpose input/output port. The pin has this
function when the external bus write-enable output
is disabled.
WR2/ (LUB) /
DQMLU
External bus write strobe output. The pin has this
function when WR2 output is enabled. When WR is
used as the write strobe, this becomes the byteenable pin (LUB). Select signal (DQMLU) of D08 to
D05 at using of SDRAM.
J
39
P86
General purpose input/output port. The pin has this
function when the external bus write-enable output
is disabled.
WR3/ (LLB) /
DQMLL
External bus write strobe output. The pin has this
function when WR3 output is enabled. When WR is
used as the write strobe, this becomes the byteenable pin (LLB). Select signal (DQMLL) of D07 to
D00 at using of SDRAM.
J
40
P87
General purpose input/output port. The pin has this
functions when the external bus write-enable output
is disabled.
SYSCLK
System clock output. The pin has this function when
system clock output is enabled. This outputs the
same clock as the external bus operating frequency.
(Output halts in stop mode.)
43
C
General purpose input/output port. The pin has this
function when system clock output is disabled.
MCLKE
40
P91
Clock enable signal for memory.
J
MCLK
38
45
C
46
P93
General purpose input/output port. The pin has this
function when clock enable output is disabled.
Memory clock output. The pin has this function
when memory clock output is enabled. This outputs
the same clock as the external bus operating
frequency. (Output halts in sleep mode.)
General purpose input/output port. The pin has this
function when memory clock output is disabled.
P92
39
External bus write strobe output. The pin has this
function when WR1 output is enabled. When WR is
used as the write strobe, this becomes the byteenable pin (ULB). Select signal (DQMUL) of D23 to
D16 at using of SDRAM.
P85
P90
37
Function
C
General purpose input/output port.
(Continued)
10
DS07-16502-5E
MB91301 Series
Pin no.
MB91302A
MB91V301A
40
41
42
Pin name
51
Function
AS
Address strobe output. The pin has this function
when ASE bit of port function register 9 is enabled
“1”.
LBA
Address strobe output for burst flash ROM. The pin
has this function when ASE bit of port function
register 9 is enabled “1”.
49
50
I/O circuit
type
J
SRAS
RAS single for SDRAM. This pin has this function
when ASE bit of port function register 9 is enabled
“1”.
P94
General purpose input/output port. The pin has this
function when ASE bit of port function register 9 is
"0" general purpose port.
BAA
Address advance output for burst Flash ROM. The
pin has this function when BAAE bit of port function
register (PFR9) is enabled.
SCAS
J
CAS signal for SDRAM. This pin has this function
when BAAE bit of port function register (PFR9) is
enabled.
P95
General purpose input/output port. The pin has this
function when BAAE bit of port function register is
general purpose port.
WR
Memory write strobe output. This pin has this
function when WRXE bit of port function register is
enabled.
SWE
J
Write output for SDRAM. This pin has this function
when WRXE bit of port function register is enabled.
General purpose input/output port. This pin has this
function when WRXE bit of port function register is
general purpose port.
P96
45 to 52
54 to 61
A00 to A07
C
External address bits 0 to 7.
55 to 62
64 to 71
A08 to A15
C
External address bits 8 to 15.
A16 to A19
64 to 67
74 to 77
J
P60 to P63
External address bits 16 to 19. It is available in
external bus mode.
Can be used as ports when external address bus is
not used.
(Continued)
DS07-16502-5E
11
MB91301 Series
Pin no.
MB91302A
MB91V301A
Pin name
I/O circuit
type
Data input pin for I2C bus function. This function is
enable when typical operation of I2C is enable. The
port output must remains off unless intentionally
turned on. (Open drain output) (This function is only
for MB91302A, MB91V301A.)
SDA0
68
A20
External address bus bit 20.
This function is enable during prohibited I2C
operation and using external bus.
P64
General-purpose I/O port.
This function is enable during prohibited I2C and
nonused external address bus.
78
T
CLK input pin for I2C bus function. This function is
enable when typical operation of I2C is enable. The
port output must remains off unless intentionally
turned on. (open drain output) (This function is only
for MB91302A, MB91V301A.)
SCL0
69
A21
External address bus bit 21.
This function is enable during prohibited I2C
operation and using external bus.
P65
General-purpose I/O port.
This function is enable during prohibited I2C and
nonused external address bus.
79
T
DATA input pin for I2C bus function. This function is
enable when typical operation of I2C is enable. The
output must remains off unless intentionally turned
on. (open drain output) (This function is only for
MB91302A, MB91V301A.)
SDA1
70
Function
A22
External address bus bit 20.
This function is enable during prohibited I2C
operation and using external bus.
P66
General-purpose I/O port.
This function is enable during prohibited I2C and
nonused external address bus.
80
T
(Continued)
12
DS07-16502-5E
MB91301 Series
Pin no.
MB91302A MB91V301A
Pin name
I/O circuit
type
SCL1
71
81
T
A23
P67
76 to 79
106 to 109
AN3 to AN0
D
INT0 to INT3
81 to 84
111 to 114
PG0 to PG3
V
ICU0 to ICU3
INT4
85
115
ATG
V
PG4
FRCK
INT5
86
116
V
SIN2
PG5
DS07-16502-5E
Function
CLK input pin for I2C bus function. This function is
enable when typical operation of I2C is enable. The
port output must remains off unless intentionally
turned on. (open drain output) (This function is only
for MB91302A, MB91V301A.)
External address bus bit 21.
This function is enable during prohibited I2C
operation and using external bus.
General-purpose I/O port.
This function is enable during prohibited I2C
operation and nonused external address bus.
Analog input pins.
External interrupt inputs. These inputs are used continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
General purpose input/output ports.
Input capture input pins. These inputs are used continuously when selected as input capture inputs. In
this case, do not output to these ports unless
doing so intentionally.
External interrupt input. These inputs are used
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
External trigger input for A/D converter. This input is
used continuously when selected as the A/D
converter start trigger. In this case, do not output to
this port unless doing so intentionally.
General purpose input/output port.
External clock input pin for free-run timer. This input
is used continuously when selected as the external
clock input pin for the free-run timer. In this case, do
not output to this port unless doing so intentionally.
External interrupt input. These inputs are used
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do
not output to this port unless doing so intentionally.
General purpose input/output port.
(Continued)
13
MB91301 Series
Pin no.
MB91302A
MB91V301A
Pin name
I/O circuit
type
INT6
87
117
V
PG6
General purpose input/output port.
INT7
External interrupt input. This input is used
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
118
V
UART2 clock input/output pin. The pin has this
function when UART2 clock output is enabled.
SCK2
90
120
PG7
General purpose input/output port.
SIN0
UART0 data input pin. This input is used continuously
when UART0 is performing input. In this case, do not
output to this port unless doing so intentionally.
U
PJ0
91
121
SOT0
General purpose input/output port.
U
PJ1
92
93
122
123
SCK0
124
U
125
General purpose input/output port.
SIN1
UART1 data input pin. This input is used continuously
when UART1 is performing input. In this case, do not
output to this port unless doing so intentionally.
U
SOT1
General purpose input/output port.
U
SCK1
126
PPG0
PJ6
UART1 data output pin. The pin has this function
when UART1 data output is enabled.
General purpose input/output port.
U
PJ5
96
UART0 clock input/output pin. The pin has this
function when UART0 clock output is enabled.
PJ2
PJ4
95
UART0 data output pin. The pin has this function
when UART0 data output is enabled.
General purpose input/output port.
PJ3
94
External interrupt input. This input is used
continuously when the corresponding external
interrupt is enabled. In this case, do not output to
these ports unless doing so intentionally.
UART2 data output pin. The pin has this function
when UART2 data output is enabled.
SOT2
88
Function
UART1 clock input/output pin. The pin has this
function when UART1 clock output is enabled.
General purpose input/output port.
U
PPG timer output. This pin has this function when
PPG0 output is enabled.
General purpose input/output port.
(Continued)
14
DS07-16502-5E
MB91301 Series
Pin no.
MB91302A
MB91V301A
97
98
99
127
128
Pin name
TRG0
I/O circuit
type
U
General purpose input/output port.
TIN0
Reload timer input. This input is used continuously
when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so
intentionally.
J
PH0
General purpose input/output port.
TIN1
Reload timer input. This input is used continuously
when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so
intentionally.
129
J
PPG timer output. The pin has this function when
PPG3 output is enabled.
PH1
General purpose input/output port.
TIN2
Reload timer input. This input is used continuously
when the corresponding timer input is enabled. In
this case, do not output to this port unless doing so
intentionally.
130
J
TRG3
PH2
103
133
DREQ0
134
DACK0
J
105
135
PB2
External input for DMA transfer requests. This input
is used continuously when selected as a DMA
activation trigger. In this case, do not output to this
port unless doing so intentionally.
General purpose input/output port.
J
PB1
DEOP0
External trigger input for PPG timer. This input is
used continuously when the corresponding timer
input is enabled. In this case, do not output to this
port unless doing so intentionally.
General purpose input/output port.
PB0
104
External trigger input for PPG timer.
This input is used continuously when the
corresponding timer input is enabled. In this case, do
not output to this port unless doing so intentionally.
PJ7
PPG3
100
Function
External acknowledge output for DMA transfer
requests. The pin has this function when outputting
DMA transfer request acknowledgement is enabled.
General purpose input/output port.
J
Completion output for DMA external transfer. The
pin has this function when outputting DMA transfer
completion is enabled.
General purpose input/output port.
(Continued)
DS07-16502-5E
15
MB91301 Series
Pin no.
MB91302A
MB91V301A
Pin name
I/O circuit
type
DREQ1
106
107
136
J
General purpose input/output port. The pin has this
function when completion output and stop input are
disabled for DMA transfer.
DACK1
External acknowledge output for DMA transfer
requests. The pin has this function when outputting
DMA transfer request acknowledgement is enabled.
137
J
PB4
138
Completion output for DMA external transfer. The
pin has this function when outputting DMA transfer
completion is enabled.
J
PPG1
PB5
110
PPG timer output. The pin has this function when
PPG1 bit is enabled.
General purpose input/output port.
IOWR
139
External trigger input for PPG timer. This input is
used continuously when the corresponding timer
input is enabled. In this case, do not output to this
port unless doing so intentionally.
General purpose input/output port.
DEOP1
109
DMA External input for DMA transfer requests. This
input is used continuously when selected as a DMA
activation trigger. In this case, do not output to this
port unless doing so intentionally.
PB3
TRG1
108
Function
J
Write strobe output for DMA fly-by transfer. The pin
has this function when outputting a write strobe for
DMA fly-by transfer is enabled.
PB6
General purpose input/output port. The pin has this
function when outputting a write strobe for DMA
fly-by transfer is disabled.
IORD
Read strobe output for DMA fly-by transfer. The pin
has this function when outputting a read strobe for
DMA fly-by transfer is disabled.
140
J
PB7
General purpose input/output port. The pin has this
function when outputting a write strobe for DMA
fly-by transfer is disabled.
112
143
X0
A
Clock (oscillation) input.
113
144
X1
A
Clock (oscillation) output.
116 to 118
147 to 149
MD0 to MD2
G
Mode pins 0 to 2. The levels applied to these pins
set the basic operating mode. Connect VCC or VSS.
119
152
INIT
B
External reset input (Reset to initialize settings)
(“L” active)
120
053
NMI
M
NMI (Non Maskable Interrupt) input (“L” active)
(Continued)
16
DS07-16502-5E
MB91301 Series
(Continued)
Pin no.
MB91302A
MB91V301A
Pin name
I/O circuit
type
CS0
122
123
124
125
126
127
128
129
J
156
General purpose input/output port. The pin has this
function when chip select 0 output is disabled.
CS1
Chip select 1 output. The pin has this function when
chip select 1 output is enabled.
J
PA1
General purpose input/output port. The pin has this
function when chip select 1 output is disabled.
CS2
Chip select 2 output. The pin has this function when
chip select 2 output are enabled.
158
J
PA2
General purpose input/output port. The pin has this
function when chip select 2 output is disabled.
CS3
Chip select 3 output. The pin has this function when
chip select 3 output are enabled.
159
161
J
PA3
General purpose input/output port. The pin has this
function when chip select 3 output is disabled.
CS4
Chip select 4 output. The pin has this function when
chip select 4 output is enabled.
TRG2
J
External trigger input for PPG timer. This input is
used continuously when the corresponding timer
input is enabled. In this case, do not output to this
port unless doing so intentionally.
PA4
General purpose input/output port. The pin has this
function when chip select 4 output is disabled.
CS5
Chip select 5 output. The pin has this function when
chip select 5 output are enabled.
PPG2
J
PPG timer output. The pin has this function when
PPG2 bit is enabled.
PA5
General purpose input/output port. The pin has this
function when chip select 5 output and PPG timer
output are disabled.
CS6
Chip select 6 output. The pin has this function when
chip select 6 output is enabled.
162
J
PA6
General purpose input/output port. The pin has this
function when chip select 6 output are disabled.
CS7
Chip select 7 output. The pin has this function when
chip select 7 output are enabled.
163
J
PA7
DS07-16502-5E
Chip select 0 output. The pin has this function when
chip select 0 output is enabled.
PA0
157
160
Function
General purpose input/output port. The pin has this
function when chip select 7 output is disabled.
17
MB91301 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
• Oscillation feedback resistance
approx. 1 MΩ
X1
Clock input
A
X0
Standby control
• CMOS hysteresis input with pull-up
resistor
P-ch
P-ch
N-ch
B
Digital input
P-ch
N-ch
C
• CMOS level I/O with standby control
• IOL = 4 mA
Digital output
Digital output
Digital input
Standby control
•Analog input
With switch
P-ch
N-ch
D
Analog input
Control
(Continued)
18
DS07-16502-5E
MB91301 Series
Type
Circuit
Remarks
•CMOS level output
No standby control
P-ch
N-ch
G
Digital input
Pull-up control
P-ch
P-ch
Digital output
N-ch
• With Pull-up control
• CMOS level I/O
with standby control
• With Pull-up control
• IOL = 4 mA
Digital output
J
Digital input
Standby control
Pull-up control
P-ch
P-ch
Digital output
N-ch
• With Pull-up control
• CMOS level output
CMOS level hysteresis input
with standby control
• IOL = 4 mA
Digital output
K
Digital input
Standby control
Pull-up control
P-ch
P-ch
Digital output
N-ch
L
Digital output
• With Pull-up control
• CMOS level output
CMOS level hysteresis input
no standby control
• IOL = 4 mA
Digital input
• CMOS level hysteresis input
no standby control
P-ch
M
N-ch
Digital input
(Continued)
DS07-16502-5E
19
MB91301 Series
Type
Circuit
P-ch
Remarks
Digital output
• Output buffer
• CMOS level output
• IOL = 4 mA
N-ch
N
Digital output
O
Digital input
Digital input
P
• Input buffer
• CMOS level input
• Input buffer with pull-down
• Pull-down resistor value = 25 kΩ
approx. (Typ)
N-ch
• Input buffer with Pull-up
P-ch
Q
Digital input
P-ch
Digital output
• I/O buffer with pull-down
• CMOS level output
• IOL = 4 mA
N-ch
R
Digital output
N-ch
Digital input
P-ch
S
N-ch
Digital output
• I/O buffer
• CMOS level output
• IOL = 4 mA
Digital output
Digital input
(Continued)
20
DS07-16502-5E
MB91301 Series
(Continued)
Type
Circuit
P-ch
P-ch
N-ch
T
Remarks
Pull-up control
Digital output with
open-drain control
Digital output
• N-ch open-drain output
• CMOS level I/O with standby control
• Without pull-up control
• IOL = 4 mA
Digital input
P-ch
Digital output
N-ch
Digital output
U
• CMOS level output
• CMOS level hysteresis input
with standby control
• 5 V tolerant
• IOL = 4 mA
Digital input
P-ch
Digital output
V
N-ch
• CMOS level output
• CMOS level hysteresis input
with standby control
• 5 V tolerant
• IOL = 4 mA
Digital output
Digital input
DS07-16502-5E
21
MB91301 Series
■ HANDLING DEVICES
❍MB91301 series
• Operation at start-up
Always apply a settings initialization (INIT) to the INIT pin immediately after turning on the power.
Also, in order to provide a delay while the oscillator circuits stabilize immediately after start-up, maintain the “L”
level input to the INIT pin for the required stabilization delay time. (The initialization processing (INIT) triggered
by the INIT pin initializes the oscillation stabilization delay time to the minimum setting.)
• External clock input at start-up
At power-on start-up, always input a clock signal until the oscillation stabilization delay time is ended.
• Output indeterminate at power-on time
When the power is turned on, the output pin may remain indeterminate until the internal power supply becomes
stable.
• Built-in DC/DC regulator
This device has a built-in regulator, requiring 3.3 V input to the Vcc pin and a bypass capacitor of approximately
4.7 μF connected to the C pin for the regulator.
3.3 V
VCC
C
AVCC
4.7 μF
AVRH
AVR
0.05 μF
VSS
AVSS/AVRL
MB91301 series
VSS
GND
Note of built-in DC/DC regulator
• Note on use of the A/D converter
As the MB91301 series contains an A/D converter, be sure to supply power to AVcc at 3.3 V and insert a capacitor
of at least 0.05 μF between the AVR pin and the AVss/AVRL pin.
3.3 V
AVCC
AVRH
AVR
0.05 μF
AVSS/AVRL
MB91301 series
Note on Use of A/D Converter
22
DS07-16502-5E
MB91301 Series
• Preventing Latchup
When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output
pins, or to voltages lower than VSS, as well as when voltages in excess of rated levels are applied between VCC
and VSS, a phenomenon known as latchup can occur. When a latchup condition occurs, the supply current can
increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take
sufficient care to avoid exceeding maximum ratings.
• Power supply pins
Devices with multiple VCC and VSS supply pins are designed to prevent problems such as latchup occurring by
providing internal connections between pins at the same potential. However, in order to reduce unwanted
radiation, prevent abnormal operation of strobe signals due to a rise in ground level, and to maintain the total
output current ratings, all such pins should always be connected externally to power supply or ground. Also,
ensure that the impedance of the VCC and VSS connections to the power supply are as low as possible.
In addition, it is recommended that a bypass capacitor of approximately 0.1μF be connected between VCC and
VSS. Connect the capacitor close to the VCC and VSS pins.
• Crystal oscillators
Noise in proximity to the X0 and X1 pins can cause abnormal operation in this device. Printed circuit boards
should be designed so that the X0 and X1 pins, crystal (or ceramic) oscillator, and bypass capacitor connected
to ground are placed as close together as possible.
Also, to ensure stable operation, it is strongly recommended that the printed circuit board art work be designed
such that the X0 and X1 pins are surrounded by ground.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Treatment of NC and OPEN pins
Pins marked as "NC" or "OPEN" must be left open-circuit.
• Treatment of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistors.
• Mode pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode
due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is
as short as possible and the connection impedance is low.
• Remarks for External Clock Operation
When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to
X0 must be supplied to X1 pin. However, in this case the stop mode must not be used (because X1 pin stops
at “H” output in stop mode) .
When operating at 12.5 MHz or less, the microcontroller can be used with the clock signal supplied only to pin X0.
“Using an external clock (normal) and (12.5 MHz) ” shows examples of how the MB91301 uses the external clock.
DS07-16502-5E
23
MB91301 Series
X0
X1
MB91301 series
Note: Stop mode (oscillation stop mode) can not be used.
Using an external clock (normal)
X0
X1
MB91301 series
Using an external clock (12.5 MHz Max)
• Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
• Clock control block
For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time.
• Bit search module
The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only wordaccessible.
• I/O port access
Byte access only for access to port
• Shared port function switching
To switch a pin that also serves as a port, use the port function register (PFR). Note, however, that bus pins are
switched depending on external bus settings.
• D-bus memory
Do not set a code area in D-bus memory.
No instruction fetch is performed to the D-bus.
Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the
microcontroller to lose control.
Do not set a data area in I-bus memory.
24
DS07-16502-5E
MB91301 Series
• I-bus memory
Do not set a stack area or vector table in I-bus memory.
It may cause a hang during EIT processing (including RETI).
Recovery from the hang requires a reset.
Do not perform DMA transfer to I-bus memory.
• Low-power consumption modes
• To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the
TBCR, or time-base counter control register) and be sure to use the following sequence:
(LDI
#value_of_standby, R0)
(LDI
#_STCR, R12)
STB
R0, @R12
; Write to standby control register (STCR)
LDUB @R12, R0
; Read STCR for synchronous standby
LDUB @R12, R0
; Read STCR again for dummy read
NOP
; NOP x 5 for timing adjustment
NOP
NOP
NOP
NOP
• If you use the monitor debugger, follow the precautions below:
Do not set a breakpoint within the above array of instructions.
Do not single-step the above array of instructions.
• Prefetch
When accessing a prefetch-enabled little endian area, use word access only (access in 32 bits).
Byte or halfword access results in wrong data read.
• MCLK and SYSCLK
MCLK causes a stop in SLEEP/STOP mode while SYSCLK causes a stop only in STOP mode. Use either
depending on each application.
• Pull-up control
When function pins listed in the AC specifications (such as external bus control pins) have pull-up control,
enabling the pull-up resistor for a pin causes the actual pin load conditions to change. As all AC specifications
for this device were measured under the condition of pull-up resistors disabled, the values are not guaranteed
of AC specifications when pull-up resistors are enabled.
Even if the pull-up resistor is set to enabled for a pin, if the HIZ bit in the standby control register (STCR) specifies
setting output pins to high impedance during stop mode (HIZ = 1) , changing to stop mode (STOP = 1) causes
the pull-up resistor to be disabled.
DS07-16502-5E
25
MB91301 Series
• R15 (General purpose register)
When any of the following instructions is executed, the SSP* or USP* value is not used as R15, resulting in an
incorrect value written to memory.
AND
R15, @Ri
ANDH
R15, @Ri
ANDB R15, @Ri
OR
R15, @Ri
ORH
R15, @Ri
ORB
R15, @Ri
EOR
R15, @Ri
EORH
R15, @Ri
EORB R15, @Ri
XCHB @Rj, R15
* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending
on the status of the “S” flag as an SP flag. When coding the above ten instructions using an assembler,
specify a general-purpose register other than R15.
• RETI instruction
Please do not neither control register of the instruction cache nor the data access to RAM of the instruction
cache immediately before the instruction of RETI.
• Notes on the PS register
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the
microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs
operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as those in (1) above.
• The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as that in (1) above.
• A/D converter
When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged,
requiring the A/D converter to wait for at least 10 ms.
• Watchdog timer
The watchdog timer function of this model monitors that a program delays a reset within a certain period of time
and resets the CPU if the program fails to delay it, for example, because the program runs out of control. Once
the watchdog timer function is enabled, therefore, the watchdog timer continues to operate until a reset takes
place.
An exception, for example during stop, sleep and DMA transfer modes, is the automatic delaying of a reset under
a condition in which the CPU stops program execution.
Note, however, that a watchdog reset may not occur in the above state caused when the system runs out of
control. If this is the case, use the external INIT pin to cause a reset (INIT) .
26
DS07-16502-5E
MB91301 Series
❍Unique to the evaluation chip MB91V301A
• Tool reset
On an evaluation board, use the chip with INIT and TRST connected together.
• Simultaneous occurrences of a software break and a user interrupt/NMI
When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause
the following phenomena:
• The debugger stops pointing to a location other than the programmed breakpoints.
• The halted program is not re-executed correctly.
If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has
been used, avoid setting any break at the relevant location.
• Single-stepping the RETI instruction
If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly
after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant
interrupt routine becomes unnecessary, perform debugging with that interrupt disabled.
• Operand break
A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data
event break to access to the area containing the address of a system stack pointer.
• ICE startup sequence
When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area
being used before downloading. After turning on the power to the target, the states of the RD and WR0 to WR3
pins are undefined until you perform the above setting. Accordingly, include enabling pull-up as part of the startup
sequence. If using these pins as general-purpose ports, set as output ports to prevent conflict with the output
signals during the time the pin states are undefined.
External bus width
32 bit
16 bit
8 bit
RD
Pull-up
Pull-up
Pull-up
WR0
Pull-up
Pull-up
Pull-up
WR1(P85)
Pull-up
Pull-up
*
WR2(P86)
Pull-up
*
*
WR3(P87)
Pull-up
*
*
Pin name
* : Use as output ports.
DS07-16502-5E
27
MB91301 Series
• Configuration batch file
The example batch file below sets the mode vector and sets up the CS0 configuration register for the download
area. Use values appropriate to the hardware in the wait, timing, and other settings.
#--------------------------------------------------------# Set MODR (0x7fd) =Enable In memory+16 bit External Bus
set mem/byte 0x7fd=0x5
#--------------------------------------------------------# Set ASR0 (0x640) ; 0x0010_0000 - 0x002f_ffff
set mem/halfword 0x640=0x0010
#--------------------------------------------------------# Set ACR0 (0x642)
#
; ASZ [3:0]=0101:2 Mbytes
#
; DBW [1:0]=01:16 bit width, automatically set from
MODR
#
; BST [1:0]=00:1 burst (16 bit x 2)
#
; SREN=0:Disable BRQ
#
; PFEN=1:Enable Pre fetch buffer
#
; WREN=1:Enable Write operation
#
; LEND=0: Big endian
#
; TYPE [3:0]=0010:WEX: Disable RDY
set mem/harfword 0x642=0x5462
#--------------------------------------------------------# Set AWR0 (0x660)
#
; W15-12=0010:auto wait=2
#
; WR07, 06=01:RD, WR delay=1cycle
#
; W05, 04=01:WR->WR delay=1cycle (for WEX)
#
; W03 =1:MCLK->RD/WR delay=0.5cycle
#
;
:for async Memory
#
; W02 =0:ADR->CS delay=0
#
; W01 =0:ADR->RD/WR setup 0cycle
#
; W00 =RD/WR->ADR hold 0cycle
set mem/halfword 0x660=0x2058
#--------------------------------------------------------• Emulation memory
If SRAM as the emulation memory is built on target board, SRAM for be accessed by RD, WR signal, and +BYTE
control signal can not be used. (The external bus is initialized to the bus mode for accessing RD, WRn after reset.)
28
DS07-16502-5E
MB91301 Series
■ BLOCK DIAGRAM
• MB91302A, MB91V301A
FR CPU
Core
32
Instruction Cache
4 KB
32
DMAC
5 channels
Bit search module
MB91302A : RAM 4 KB
MB91V301A : RAM 8 KB (stack)
Bus
Converter
MB91302A : ROM 4 KB*
MB91V301A : RAM 8 KB
32
X0, X1
MD0 to MD2
INIT
16
32
Adapter
32
External memory
I/F
Clock
control
16
SIN0 to SIN2
SOT0 to SOT2
SCK0 to SCK2
8 channels
External interrupts
3 channels
UART
A23 to A00
D31 to D16
D15 to D00
RD, WR
WR0 to WR3
CS0 to CS7
RDY
BRQ
BGRNT
SYSCLK
MCLK
AS
MCLKE
Interrupt
controller
INT0 to INT7
NMI
DREQ0, DREQ1
DACK0, DACK1
DEOP0, DEOP1
IOWR
IORD
SDRAM I/F
4 channels
PPG timer
SRAS
SCAS
SWE
DQMUU, L
DQMLU,L
LBA
BAA
PPG0 to PPG3
TRG0 to TRG3
3 channels
U-TIMER
PORT I/F
AN0 to AN3
ATG
AVRH, AVCC
AVSS/AVRL
4 channels
A/D converter
TIN0 to TIN2
3 channels
Reload timer
2 channels
I2C I/F
Free Run Timer
4 channels
Input Capture
PORT
SDA0, SDA1
SCL0, SCL1
FRCK
ICU0 to ICU3
* : ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program
Loader) internal model by adding the user ROM model.
DS07-16502-5E
29
MB91301 Series
■ CPU
1. Memory Space
The FR family has 4 Gbytes (232 addresses) of logical address space with linear access from the CPU.
• Direct Addressing Areas
The following areas of address space are used for I/O operations.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The direct areas differ according to the size of the data accessed, as follows.
→ byte data access
: 000H to 0FFH
→ half word data access : 000H to 1FFH
→ word data access
: 000H to 3FFH
30
DS07-16502-5E
MB91301 Series
• Memory map
(MB91302A)
(Single chip
mode)
(MB91302A)
Internal ROM
External bus
mode
(MB91302A)
External ROM
External bus
mode
(MB91V301A)
Internal ROM
External bus mode
(MODR register at
ROAM = 1)
(MB91V301A)
External ROM
External bus
mode
0000 0000H
Direct
addre
ssing
area
I/O
Direct
addre
ssing
area
I/O
Direct
addre
ssing
area
I/O
Direct
addre
ssing
area
I/O
I/O
Direct
addre
ssing
area
I/O
see
“■I/O
MAP”
I/O
0000 0400H
see
“■I/O
MAP”
I/O
I/O
0001 0000H
0003 E000H
0003 F000H
0004 0000H
I/O
I-RAM ∗
Access
prohibited
Access
prohibited
Access
prohibited
Internal
RAM
4 Kbytes
Internal
RAM
4 Kbytes
Internal
RAM
4 Kbytes
1
I-RAM ∗
1
Access
prohibited
Access
prohibited
000F E000H
Internal
ROM
4 Kbytes*2
Access
prohibited
External
area
I/O
I-RAM ∗
1
I-RAM ∗
1
Access
prohibited
Access
prohibited
Internal
RAM
8 Kbytes
Internal
RAM
8 Kbytes
Access
prohibited
External
area
External
area
External
area
Internal
RAM
8 Kbytes
emulation
000F F000H
Internal
ROM
4 Kbytes*2
see
“■I/O
MAP”
I/O
Internal
RAM
8 Kbytes
External
area
0004 2000H
0006 0000H
000E 0000H
I/O
see
“■I/O
MAP”
I/O
I-RAM ∗
1
0002 0000H
see
“■I/O
MAP”
I/O
0010 0000H
External
area
External
area
External
area
FFFF FFFFH
MB91302A has non-ROM model, the optimal real time OS internal model, and the IPL (Internal program Loader)
internal model by adding the user ROM model.
*1 : On specific area between 10000H and 2000H, 4 Kbytes RAM can be used.
Refer to “■INSTRUCTION CACHE”.
*2 : The real time OS internal model stores the real time OS kernel. The program loader internal model stores
the program loader.
Note : Internal ROM emulation : only MB91V301A
Note : Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see “■MODE
SETTINGS”.)
DS07-16502-5E
31
MB91301 Series
2. Registers
The FR family has two types of registers: application-specific registers in the CPU and general purpose registers
in memory.
• Dedicated registers
Program counter (PC)
Program status (PS)
Table base register (TBR)
Return pointer (RP)
System stack pointer (SSP)
User stack pointer (USP)
Multiplication and division
result register (MDH/MDL)
: 32-bit register. Stores the current instruction address.
: 32-bit register. Contains the register pointer and condition code.
: Stores the top address of the vector table used by the EIT (exception/interrupt/
trap) function.
: Stores the subroutine return address.
: Points to the system stack area.
: Points to the user stack area.
: 32-bit registers used for multiplication and division.
Initial value
32 bit
PC
Program counter
PS
Program status
XXXX XXXXH
Table base register
000F FC00H
Return pointer
XXXX XXXXH
SSP
System stack pointer
0000 0000H
USP
User stack pointer
XXXX XXXXH
MDH
Multiplication and division
result register
XXXX XXXXH
TBR
RP
MDL
XXXX XXXXH
• PC (Program Counter)
The PC is the program counter and stores the address of the currently executing instruction.
31
0
PC
PC
• Table base register (TBR)
The TBR is the table base register and stores the top address of the vector table used by the EIT function.
31
0
TBR
TBR
32
DS07-16502-5E
MB91301 Series
• Return pointer (RP)
The RP is the return pointer and stores the subroutine return address.
31
0
RP
RP
• System stack pointer (SSP)
The SSP is the system stack pointer and functions as R15 when the S flag is “0”.
31
0
SSP
SSP
• User stack pointer (USP)
The USP is the user stack pointer and functions as R15 when the S flag is “1”.
31
0
USP
USP
• Multiplication and division result register (MDH/MDL)
MDH/MDL : 32-bit registers used for multiplication and division.
MDH
: Remainder
MDL
: Quotient
31
0
MDH
MDL
Multiplication and division result register
DS07-16502-5E
33
MB91301 Series
• Program status (PS)
This register holds the program status and is divided into the ILM, SCR, and CCR.
Bit position→ 31
20
16
10
⎯
0
8 7
⎯
ILM
SCR
CCR
PS
• Condition code register (CCR)
S flag
: Specifies which stack pointer to use as R15.
I flag
: Enables or disables user interrupt requests.
N flag
: Indicates the sign when an operation result is represented as a “2” complement integer.
Z flag
: Indicates whether an operation result is “0”.
V flag
: Indicates whether an overflow occurred for an operation result when the operation operand is
represented as a “2” complement integer.
C flag
: Indicates whether an operation resulted in a borrow or a carry from the most significant bit.
7
6
5
4
3
2
1
0
Initial Value
⎯
⎯
S
I
N
Z
V
C
- - 00XXXXB
CCR
• System condition code register (SCR)
D1, D0 flags : Stores intermediate data for stepwise multiplication operations.
T flags
: A flag specifying whether the step trace trap function is enabled or not.
10
9
8
Initial Value
D1
D0
T
XX0B
SCR
• Interrupt level mask register (ILM)
ILM4 to ILM0 : This register stores the interrupt level mask value. The value in the ILM register is used as
the level mask. Only interrupt requests to the CPU that have an interrupt level that is higher
than the level specified in ILM are accepted.
20
19
18
17
16
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt Level
0
0
0
0
0
0
High
•••
↑
15
(Medium)
•••
↓
31
Low
•••
0
1
0
0
0
•••
1
1
1
1
1
Initial Value
01111B
ILM
34
DS07-16502-5E
MB91301 Series
■ GENERAL PURPOSE REGISTERS
General purpose registers R0 to R15 are used by the CPU. The registers are used as the accumulator and
memory access pointers for CPU operations.
32-bit
R0
Initial Value
XXXX XXXXH
R1
R12
R13
AC (Accumulator)
R14
FP (Frame Pointer)
XXXX XXXXH
R15
SP (Stack Pointer)
0000 0000H
The following three registers are treated as having special meanings to enhance the operation of some instructions.
R13 : Virtual accumulator (AC)
R14 : Frame pointer (FP)
R15 : Stack pointer (SP)
The values of R0 to R14 after a reset are undefined. R15 is initialized to 0000 0000H (SSP value) .
DS07-16502-5E
35
MB91301 Series
■ MODE SETTINGS
In the FR family, the mode is set by the mode pins (MD2, MD1, and MD0) and mode register (MODR).
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.
Mode Pins
Reset vector access
Mode name
area
MD2 MD1 MD0
Remarks
0
0
0
Internal ROM vector mode
Internal
Single-chip mode*
0
0
1
External ROM vector mode
External
The bus width is specified by the
mode register.
Values other than those listed in the table are prohibited.
* : Single chip mode is able to set only MB91302A.
2. Mode Register (MODR)
• Details of mode register (MODR)
The data written to the mode register by the mode vector fetch operation (see “3.11.3 reset sequences”) is
called the mode data.
After the data is set to the mode register (MODR), the device operates with the operating mode specified by
this data. The mode register is set by all types of reset. The register cannot be written to by user programs.
<Details of mode register (MODR) >
Operation mode setting bits
Initial Value
bit
Address
23
22
21
20
19
18
17
16
⎯
⎯
⎯
⎯
⎯
ROMA
WTH1
WTH0
W
W
W
XXXXXXXXB
<Details of mode data>
Operation mode setting bits
Initial Value
bit
Address
31
30
29
28
27
26
25
24
⎯
⎯
⎯
⎯
⎯
ROMA
WTH1
WTH0
W
W
W
XXXXXXXXB
Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000”.
Operation is not guaranteed when any value other than “00000” is set.
36
DS07-16502-5E
MB91301 Series
• Operating mode
Bus mode
Single chip
Internal ROM external bus
Access mode
32-bit bus width
16-bit bus width
External ROM external bus
8-bit bus width
• Bus mode
The bus mode controls the operations of internal ROM and the external access function. It is specified with
the mode setting pins (MD2, MD1, and MD0) and the ROMA bit in mode data.
• Access mode
The access mode controls the external data bus width. It is specified with the WTH1 and WTH0 bits in the
mode register and the DBW1 and DBW0 bits in area configuration registers 0 to 7 (ACR0 to ACR7).
• Bus Modes
The FR family has three bus modes: bus mode 0 (single-chip mode), bus mode 1 (internal-ROM, external-bus
mode), and bus mode 2 (external-ROM, external-bus mode).
The MB91V301A supports only bus mode 2 (external-ROM, external-bus mode).
See “1. Memory Space” in ■CPU for details.
• Bus mode0 (single chip mode) (only MB91302A)
The internal I/O, 4 Kbytes D-bus RAM, 32 Kbytes F-bus RAM (FRAM) and 96 Kbytes F-bus ROM are valid,
while access to any other areas is invalid under this mode. The function of external pin is peripheral or generalpurpose port. The pin can not be used as the bus pin.
• Bus mode 1 (internal ROM external bus mode)
The internal I/O, D-bus RAM, F-bus RAM (FRAM) and F-bus ROM are valid, and access to areas where
external access is enabled will access external space under this mode. A part of an external terminal functions
as a bus terminal.
• Bus mode 2 (External-ROM, external-bus mode)
This mode enables internal I/O and D-bus RAM, in which any access is access to external space. Some
external pins serve as bus pins.
DS07-16502-5E
37
MB91301 Series
■ I/O MAP
This shows the location of the various peripheral resource registers in the memory space.
[How to read the table]
Address
000000H
Register
+0
+1
+2
Block
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
T-unit
Port Data Register
Read/write attribute, Access type
(B : Byte, H : Half-word, W : Word)
Initial value after a reset
Register name (Address of column 1 register is 4n, address of column
2 register is 4n+2, etc.)
Location of left-most register (When using word access,
the register in column 1 is in the MSB side of the data.)
Note : Initial values of register bits are represented as follows :
“1” : Initial value“1”
“0” : Initial value“0”
“X” : Initial value“X”
“-” : No physical register at this location
38
DS07-16502-5E
MB91301 Series
Register
Address
+0
+1
+2
+3
000000H
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
⎯
000004H
⎯
⎯
PDR6 [R/W] B
XXXXXXXX
⎯
000008H
PDR8 [R/W] B
XXXXXXXX
PDR9 [R/W] B
- XXXXXXX
PDRA [R/W] B
XXXXXXXX
PDRB [R/W] B
XXXXXXXX
⎯
PDRJ [R/W] B
XXXXXXXX
T-unit
Port Data
Register
⎯
00000CH
000010H
Block
PDRG [R/W] B
XXXXXXXX
PDRH [R/W] B
- - - - - XXX
000014H
to
00003CH
⎯
R-bus
Port Data
Register
Reserved
000040H
EIRR [R/W] B, H, W ENIR [R/W] B, H, W
00000000
00000000
ELVR [R/W] B, H, W
00000000
Ext int
000044H
DICR [R/W] B, H, W HRCL [R/W] B, H, W
-------0
0 - - 11111
⎯
DLYI/I-unit
000048H
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R/W] B, H, W
- - XX0000 00000000
000050H
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
000054H
⎯
TMCSR1 [R/W] B, H, W
- - XX0000 00000000
000058H
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R/W] B, H, W
- - XX0000 00000000
000060H
000064H
000068H
00006CH
SIDR0 [R]
SCR0 [R/W] B, H, W SMR0 [R/W] B, H, W
SSR0 [R/W] B, H, W
SODR0 [W] B, H, W
00000100
00 - - 0 - 0 00001000
XXXXXXXX
UTIM0 [R] H, W (UTIMR0 [W] H, W)
00000000 00000000
DRCL0 [W] B
--------
UTIMC0 [R/W] B
0 - - 00001
SIDR1 [R]
SCR1 [R/W] B, H, W SMR1 [R/W] B, H, W
SSR1 [R/W] B, H, W
SODR1 [W] B, H, W
00000100
00 - - 0 - 0 00001000
XXXXXXXX
UTIM1 [R] H, W (UTIMR1 [W] H, W )
00000000 00000000
DRCL1 [W] B
--------
UTIMC1 [R/W] B
0 - - 00001
Reload
Timer 0
Reload
Timer 1
Reload
Timer 2
UART0
U-TIMER 0
UART1
U-TIMER 1
(Continued)
DS07-16502-5E
39
MB91301 Series
Address
000070H
Register
+0
+1
UTIM2 [R] H, W (UTIMR2 [W] H, W )
00000000 00000000
000078H
ADCR [R] B, H, W
000000XX XXXXXXXX
ADCR0 [R] B, H, W
XXXXXXXX
IBCR0 [R/W] B, H, W
00000000
ADCR2 [R] B, H, W
XXXXXXXX
Reserved
ITBA0 [R, R/W] B, H, W
00000000 00000000
ISBA0 [R, R/W]
B, H, W
00000000
IDAR0 [R/W] B, H, W
00000000
ICCR0 [R, W, R/W]
B, H, W
00011111
IDBL0 [R, R/W]
B, H, W
00000000
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0000A0H
0000A4H
0000A8H
to
0000B0H
⎯
IBCR1 [R/W] B, H, W
00000000
IBSR1 [R] B, H, W
00000000
IDAR1 [R/W] B, H, W
00000000
ICCR1 [R, W, R/W]
B, H, W
00011111
IDBL1 [R, R/W]
B, H, W
00000000
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0000BCH
⎯
0000C0H
0000C4H
Reserved
ITBA1 [R, R/W] B, H, W
00000000 00000000
ISBA1 [R, R/W]
B, H, W
00000000
ITMK1 [R, R/W] B, H, W
00111111 11111111
I2C
interface0
Reserved
ISMK1 [R/W] B, H, W
01111111
0000B8H
U-TIMER 2
A/D
Converter
ADCR3 [R] B, H, W Sequential
Comparator
XXXXXXXX
ISMK0 [R/W] B, H, W
01111111
00009CH
UART2
ADCS [R/W] B, H, W
00000000 00000000
IBSR0 [R] B, H, W
00000000
ITMK0 [R, R/W] B, H, W
00111111 11111111
0000C8H
to
0000D0H
UTIMC2 [R/W] B
0 - - 00001
⎯
000098H
0000B4H
DRCL2 [W] B
--------
ADCR1 [R] B, H, W
XXXXXXXX
000080H
to
000090H
000094H
Block
+3
SIDR2 [R]
SCR2 [R/W] B, H, W SMR2 [R/W] B, H, W
SSR2 [R/W] B, H, W
SODR2 [W] B, H, W
00000100
00 - - 0 - 0 00001000
XXXXXXXX
000074H
00007CH
+2
I2C
interface1
Reserved
⎯
⎯
0000D4H
TCDT [R/W] H, W
00000000 00000000
0000D8H
IPCP1 [R/W] H, W
XXXXXXXX_XXXXXXXX
⎯
⎯
⎯
TCCS [R/W] B, H, W 16 bit Free
00000000
Run Timer
IPCP0 [R/W] H, W
XXXXXXXX_XXXXXXXX
16 bit Input
Capture
(Continued)
40
DS07-16502-5E
MB91301 Series
Address
Register
+0
+1
0000DCH
IPCP3 [R/W] H, W
XXXXXXXX_XXXXXXXX
0000E0H
⎯
+3
IPCP2 [R/W] H, W
XXXXXXXX_XXXXXXXX
ICS23 [R/W] B, H, W
00000000
0000E4H
to
000114H
000118H
+2
⎯
ICS01 [R/W] B, H, W
00000000
⎯
GCN10 [R/W] H
00110010 00010000
000120H
PTMR0 [R] H
11111111 11111111
000124H
PDUT0 [W] H, W
XXXXXXXX XXXXXXXX
000128H
PTMR1[R] H
11111111 11111111
00012CH
PDUT1 [W] H, W
XXXXXXXX XXXXXXXX
000130H
PTMR2 [R] H
11111111 11111111
000134H
PDUT2 [W] H, W
XXXXXXXX XXXXXXXX
000138H
PTMR3[R] H
11111111 11111111
00013CH
PDUT3 [W] H, W
XXXXXXXX XXXXXXXX
16 bit
Input
capture
Reserved
⎯
GCN20 [R/W] B
00000000
⎯
000011CH
Block
PPG timer
Reserved
PCSR0 [W] H, W
XXXXXXXX XXXXXXXX
PCNH0 [R/W] B
00000000
PCNL0 [R/W] B
000000X0
PCSR1 [W] H, W
XXXXXXXX XXXXXXXX
PCNH1 [R/W] B
00000000
PCNL1 [R/W] B
000000X0
PCSR2 [W] H, W
XXXXXXXX XXXXXXXX
PCNH2 [R/W] B
00000000
PCNL2 [R/W] B
000000X0
PCSR3 [W] H, W
XXXXXXXX XXXXXXXX
PCNH3 [R/W] B
00000000
000140H
to
0001FCH
⎯
000200H
DMACA0 [R/W] B, H, W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B, H, W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B, H, W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
PCNL3 [R/W] B
000000X0
PPG0
PPG1
PPG2
PPG3
Reserved
DMAC
(Continued)
DS07-16502-5E
41
MB91301 Series
Address
Register
+0
+1
+2
Block
+3
000214H
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B, H, W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B, H, W*1
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
⎯
Reserved
000240H
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
000244H
to
000300H
⎯
Reserved
ISIZE [R/W] B, H, W
- - - - - - 10
⎯
000304H
000308H
to
0003E0H
⎯
ICHCR [R/W] B, H, W
0 - 000000
0003E8H
to
0003EFH
⎯
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DDRG [R/W] B
00000000
DDRH [R/W] B
- - - - - 000
I-Cache
Reserved
⎯
0003E4H
000400H
DMAC
I-Cache
Reserved
⎯
Bit Search
Module
DDRJ [R/W] B
00000000
R-bus Data
Direction
Register
(Continued)
42
DS07-16502-5E
MB91301 Series
Register
Address
+0
+1
000404H
to
00040CH
000410H
+2
+3
⎯
PFRG [R/W] B
00 - - - - - -
PFRH [R/W] B
------0-
000414H
to
00041CH
Reserved
⎯
PFRJ [R/W] B
- 000 - 00 -
⎯
⎯
000420H
PCRH [R/W] B
- - - - - 000
Block
R-bus Port
Function
Register
Reserved
⎯
⎯
000424H
to
00043CH
⎯
000440H
ICR00 [R/W] B, H, W ICR01 [R/W] B, H, W ICR02 [R/W] B, H, W ICR03 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000444H
ICR04 [R/W] B, H, W ICR05 [R/W] B, H, W ICR06 [R/W] B, H, W ICR07 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000448H
ICR08 [R/W] B, H, W ICR09 [R/W] B, H, W ICR10 [R/W] B, H, W ICR11 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
00044CH
ICR12 [R/W] B, H, W ICR13 [R/W] B, H, W ICR14 [R/W] B, H, W ICR15 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000450H
ICR16 [R/W] B, H, W ICR17 [R/W] B, H, W ICR18 [R/W] B, H, W ICR19 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000454H
ICR20 [R/W] B, H, W ICR21 [R/W] B, H, W ICR22 [R/W] B, H, W ICR23 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000458H
ICR24 [R/W] B, H, W ICR25 [R/W] B, H, W ICR26 [R/W] B, H, W ICR27 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
00045CH
ICR28 [R/W] B, H, W ICR29 [R/W] B, H, W ICR30 [R/W] B, H, W ICR31 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000460H
ICR32 [R/W] B, H, W ICR33 [R/W] B, H, W ICR34 [R/W] B, H, W ICR35 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000464H
ICR36 [R/W] B, H, W ICR37 [R/W] B, H, W ICR38 [R/W] B, H, W ICR39 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000468H
ICR40 [R/W] B, H, W ICR41 [R/W] B, H, W ICR42 [R/W] B, H, W ICR43 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
R-bus
Pull-up
Resistance
Control
Register
Reserved
Interrupt
Controller
(Continued)
DS07-16502-5E
43
MB91301 Series
Address
00046CH
Register
+0
+1
⎯
000480H
RSRR [R, R/W]
B, H, W
10000000 (INIT)
- 0 - XX - 00 (INIT)
XXX - - X00 (RST)
000484H
CLKR [R/W] B, H, W
- 000 - 000 (INIT)
- XXX - XXX (RST)
STCR [R/W] B, H, W
TBCR [R/W] B, H, W
001100 - 1 (INIT)
00XXX - 00 (INIT)
0011XX - 1 (INIT)
00XXX - XX (RST)
00X1XX - X (RST)
⎯
000488H
to
0005FCH
CTBR [W] B, H, W
XXXXXXXX (INIT)
XXXXXXXX (RST)
DIVR0 [R/W] B, H, W DIVR1 [R/W] B, H, W
00000011 (INIT)
0000 - - - - (INIT)
XXXX - - - - (RST)
XXXXXXXX (RST)
⎯
DDR0 [R/W] B
00000000
DDR1 [R/W] B
00000000
⎯
000604H
000608H
Block
+3
ICR44 [R/W] B, H, W ICR45 [R/W] B, H, W ICR46 [R/W] B, H, W ICR47 [R/W] B, H, W
- - - 11111
- - - 11111
- - - 11111
- - - 11111
000470H
to
00047CH
000600H
+2
DDR8 [R/W] B
00000000
DDR9 [R/W] B
- 0000000
00060CH
⎯
000610H
⎯
DDR2 [R/W] B
00000000
⎯
DDR6 [R/W] B
00000000
⎯
DDRA [R/W] B
00000000
DDRB [R/W] B
00000000
⎯
⎯
PFR6 [R/W] B
11111111
PFR61 [R/W] B
- - - - 0000
000618H
PFR8 [R/W] B
111 - - 0 - -
PFR9 [R/W] B
- 0000111
PFRA1 [R/W] B
11111111
PFRB1 [R/W] B
00000000
00061CH
PFRB2 [R/W] B
000 - - - 00
⎯
PFRA2 [R/W] B
--0-----
⎯
000620H
PCR0 [R/W] B
00000000
PCR1 [R/W] B
00000000
PCR2 [R/W] B
00000000
⎯
PCR6 [R/W] B
00000000
⎯
PCRA [R/W] B
00000000
PCRB [R/W] B
00000000
⎯
000628H
00062CH
PCR8 [R/W] B
00000000
PCR9 [R/W] B
- 000 - - 0 -
Clock
Control
unit
Reserved
000614H
000624H
Interrupt
Controller
T-unit
Data
Direction
Register
T-unit
Port
Function
Register
T-unit
Pull-up
Resistance
Control
Register
⎯
(Continued)
44
DS07-16502-5E
MB91301 Series
Register
Address
+0
+1
000630H
to
00063CH
+2
+3
⎯
Reserved
000640H
ASR0 [R/W] H, W
00000000 00000000
ACR0 [R/W] H, W
1111XX00 00000000
000644H
ASR1 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR5 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR6 [R/W] B, H, W
XXXXXXXX XXXXXXXX
00065CH
ASR7 [R/W] H, W
XXXXXXXX XXXXXXXX
ACR7 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000660H
AWR0 [R/W] B, H, W
01111111 11111011
AWR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR5 [R/W] B, H, W
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR7 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000670H
MCRA [R/W] B, H, W MCRB [R/W] B, H, W
XXXXXXXX
XXXXXXXX
⎯
T-unit
⎯
000674H
000678H
Block
IOWR0 [R/W] B, H, W IOWR1 [R/W] B, H, W IOWR2 [R/W] B, H, W
XXXXXXXX
XXXXXXXX
XXXXXXXX
⎯
⎯
00067CH
000680H
CSER [R/W] B, H, W CHER [R/W] B, H, W
00000001
11111111
000684H
RCR [R/W] B, H, W
00XXXXXX XXXX0XXX
TCR [R/W] B, H, W
00000000 (INIT)
0000XXXX (RST)
⎯
⎯
(Continued)
DS07-16502-5E
45
MB91301 Series
Address
Register
+0
+1
00068CH
to
0007F8H
0007FCH
+2
Block
+3
⎯
Reserved
MODR [W] *2
XXXXXXXX
⎯
000800H
to
000AFCH
⎯
T-unit
⎯
Reserved
000B00H
ESTS0 [R/W] B
X0000000
ESTS1 [R/W] B
XXXXXXXX
ESTS2 [R] B
1XXXXXXX
⎯
000B04H
ECTL0 [R/W] B
0X000000
ECTL1 [R/W] B
00000000
ECTL2 [W] B
000X0000
ECTL3 [R/W] B
00X00X11
000B08H
ECNT0 [W] B
XXXXXXXX
ECNT1 [W] B
XXXXXXXX
EUSA [W] B
XXX00000
EDTC [W] B
0000XXXX
000B0CH
EWPT [R] H
00000000 00000000
ECTL4 [R] ([R/W]) B ECTL5 [R] ([R/W]) B
- 0X00000
- - - - 000X
000B10H
EDTR0 [W] H
XXXXXXXX XXXXXXXX
EDTR1 [W] H
XXXXXXXX XXXXXXXX
000B14H
to
000B1CH
⎯
000B20H
EIA0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B24H
EIA1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B28H
EIA2 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B2CH
EIA3 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B30H
EIA4 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B34H
EIA5 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B38H
EIA6 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B3CH
EIA7 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B40H
EDTA [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B44H
EDTM [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DSU
(Evaluation
chip only)
(Continued)
46
DS07-16502-5E
MB91301 Series
Address
Register
+0
+1
+2
000B48H
EOA0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B4CH
EOA1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B50H
EPCR [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B54H
EPSR [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B58H
EIAM0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B5CH
EIAM1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B60H
EOAM0/EODM0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B64H
EOAM1/EODM1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B68H
EOD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B6CH
EOD1 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000B70H
to
000FFCH
⎯
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
Block
DSU
(Evaluation
chip only)
Reserved
DMAC
(Continued)
DS07-16502-5E
47
MB91301 Series
(Continued)
Address
Register
+0
+1
+2
+3
Block
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
001028H
to
001FFCH
⎯
Reserved
*1 : Byte access is not permitted for the lower 16 bits of DMAC0 to DMAC4 (DTC15 to DTC0) .
*2 : This register is accessed through mode vector fetch; it cannot be accessed in normal mode.
48
DS07-16502-5E
MB91301 Series
■ INTERRUPT VECTORS
Interrupt No.
10
16
Interrupt
level*1
Offset
TBR default
address*2
RN
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
⎯
Operand break trap
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (FH)
fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
6
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
7
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
11
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
12
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
UART0 (RX completed)
27
1B
ICR11
390H
000FFF90H
0
UART1 (RX completed)
28
1C
ICR12
38CH
000FFF8CH
1
UART2 (RX completed)
29
1D
ICR13
388H
000FFF88H
2
UART0 (TX completed)
30
1E
ICR14
384H
000FFF84H
3
UART1 (TX completed)
31
1F
ICR15
380H
000FFF80H
4
UART2 (TX completed)
32
20
ICR16
37CH
000FFF7CH
5
Interrupt
(Continued)
DS07-16502-5E
49
MB91301 Series
Interrupt No.
10
16
Interrupt
level*1
Offset
TBR default
address*2
RN
DMAC0 (end, error)
33
21
ICR17
378H
000FFF78H
⎯
DMAC1 (end, error)
34
22
ICR18
374H
000FFF74H
⎯
DMAC2 (end, error)
35
23
ICR19
370H
000FFF70H
⎯
DMAC3 (end, error)
36
24
ICR20
36CH
000FFF6CH
⎯
DMAC4 (end, error)
37
25
ICR21
368H
000FFF68H
⎯
A/D
38
26
ICR22
364H
000FFF64H
15
PPG0
39
27
ICR23
360H
000FFF60H
13
PPG1
40
28
ICR24
35CH
000FFF5CH
14
PPG2
41
29
ICR25
358H
000FFF58H
⎯
PPG3
42
2A
ICR26
354H
000FFF54H
⎯
System reserved
43
2B
ICR27
350H
000FFF50H
⎯
U-TIMER0
44
2C
ICR28
34CH
000FFF4CH
⎯
U-TIMER1
45
2D
ICR29
348H
000FFF48H
⎯
U-TIMER2
46
2E
ICR30
344H
000FFF44H
⎯
Time base timer overflow
47
2F
ICR31
340H
000FFF40H
⎯
I C I/F0
48
30
ICR32
33CH
000FFF3FH
⎯
I2C I/F1
49
31
ICR33
338H
000FFF38H
⎯
System reserved
50
32
ICR34
334H
000FFF34H
⎯
System reserved
51
33
ICR35
330H
000FFF30H
⎯
16 bit Free Run Timer
52
34
ICR36
32CH
000FFF2CH
⎯
ICU0 (load)
53
35
ICR37
328H
000FFF28H
⎯
ICU1 (load)
54
36
ICR38
324H
000FFF24H
⎯
ICU2 (load)
55
37
ICR39
320H
000FFF20H
⎯
ICU3 (load)
56
38
ICR40
31CH
000FFF1CH
⎯
System reserved
57
39
ICR41
318H
000FFF18H
⎯
System reserved
58
3A
ICR42
314H
000FFF14H
⎯
System reserved
59
3B
ICR43
310H
000FFF10H
⎯
System reserved
60
3C
ICR44
30CH
000FFF0CH
⎯
System reserved
61
3D
ICR45
308H
000FFF08H
⎯
System reserved
62
3E
ICR46
304H
000FFF04H
⎯
Delay interrupt bit
63
3F
ICR47
300H
000FFF00H
⎯
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
System reserved
66
42
⎯
2F4H
000FFEF4H
⎯
Interrupt
2
(Continued)
50
DS07-16502-5E
MB91301 Series
(Continued)
Interrupt No.
10
16
Interrupt
level*1
Offset
TBR default
address*2
RN
System reserved
67
43
⎯
2F0H
000FFEF0H
⎯
System reserved
68
44
⎯
2ECH
000FFEECH
⎯
System reserved
69
45
⎯
2E8H
000FFEE8H
⎯
System reserved
70
46
⎯
2E4H
000FFEE4H
⎯
System reserved
71
47
⎯
2E0H
000FFEE0H
⎯
System reserved
72
48
⎯
2DCH
000FFEDCH
⎯
System reserved
73
49
⎯
2D8H
000FFED8H
⎯
System reserved
74
4A
⎯
2D4H
000FFED4H
⎯
System reserved
75
4B
⎯
2D0H
000FFED0H
⎯
System reserved
76
4C
⎯
2CCH
000FFECCH
⎯
System reserved
77
4D
⎯
2C8H
000FFEC8H
⎯
System reserved
78
4E
⎯
2C4H
000FFEC4H
⎯
System reserved
79
4F
⎯
2C0H
000FFEC0H
⎯
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
Interrupt
*1 : ICRs are registers built in the interrupt controller to set interrupt levels for individual interrupt requests.
The ICRs are provided for the different interrupt levels.
*2 : The TBR is the register holding the start address of the EIT vector table.
The TBR value and the offset value preset for each EIT source are added together to be the vector address.
Note: The 1 Kbyte area from the TBR address is the EIT vector area.
The vector size is 4 bytes and the relationship between vector number and vector address is expressed as
follows:
Vctadr
= TBR + vctofs
= TBR + (3FCH − 4 × vct)
vctadr : vector address
vctofs : vector offset
vct
: vector number
DS07-16502-5E
51
MB91301 Series
■ INSTRUCTION CACHE
The instruction cache is a fast local memory for temporary storage. Once an instruction code is accessed from
external slower memory, the instruction cache holds the instruction code inside to increase the speed of accessing the same code from then on.
By setting the RAM mode, the instruction cache data RAM is made directly read/write-accessible by software.
• Configuration
• FR family’s basic instruction length : Two bytes
• Block layout : Two-way set associative
• Blocks : 128 blocks per way
16 bytes per block ( = 4 sub-blocks)
4 bytes per sub-block ( = 1 bus access unit)
• Instruction Cache Configuration
4 bytes
4 bytes
4 bytes
4 bytes
4 bytes
I3
I2
I1
I0
Cash tag
Sub
block 3
Sub
block 2
Sub
block 1
Sub
block 0
block 0
Cash tag
Sub
block 3
Sub
block 2
Sub
block 1
Sub
block 0
block 127
Cash tag
Sub
block 3
Sub
block 2
Sub
block 1
Sub
block 0
block 0
Cash tag
Sub
block 3
Sub
block 2
Sub
block 1
Sub
block 0
block 127
Way 1
128 block
Way 2
128 block
52
DS07-16502-5E
MB91301 Series
• Instruction Cache Tags
Way 1
31
9
Address tag
8
Vacancy
7
6
5
4
3
2
1
0
SBV3
SBV2
SBV1
SBV0
TAGV
Vacancy
LRU
ETLK
2
1
Way 2
31
9
Address tag
8
Vacancy
7
6
5
4
3
SBV3
SBV2
SBV1
SBV0
TAGV
Vacancy
0
ETLK
[bit31 to bit9] Address tag
The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding
block.
For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the
following equation:
IA = address tag × 29 + i × 24 + k × 22
The address tag is used to check for a match with the instruction address requested for access by the CPU. The
CPU and cache behave as follows depending on the result of the tag check:
• When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within
the cycle.
• When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data
loaded by external access at the same time.
[bit7 to bit4] SBV3 to SBV0 : Sub-block validation
When SBVn contains "1", the corresponding sub-block holds the current instruction data at the address located
by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).
[bit3] TAGV : Tag validation bit
This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is
invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)
[bit1] LRU (only in way 1)
This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the
last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1
is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.
[bit0] ETLK : Entry lock
This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is
set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid
sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to
external memory takes place after losing one cycle used for evaluating the cache miss.
DS07-16502-5E
53
MB91301 Series
Control Registers
• Cache Size Register (ISIZE)
bit
Address : 00000307H
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
SIZE1
SIZE0
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
Initial value
- - - - - - 10B
• Instruction Cache Control Register (ICHCR)
The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache.
Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow.
bit
Address : 000003E7H
Address
00010000 H
00010200 H
00010400 H
00010600 H
00010800 H
00010FFFH
00014000 H
00014200 H
00014400 H
00014600 H
00014800 H
00014FFFH
00018000 H
00018200 H
00018400 H
00018600 H
00018800 H
00018FFFH
0001C000H
0001C200H
0001C400H
0001C600H
0001C800H
0001CFFFH
TAG RAM
00010000 H
00010004 H
00010008 H
0001000CH
00010010 H
00010014 H
54
Cache off
RAM off
7
6
5
4
3
2
1
0
RAM
⎯
GBLK
ALFL
EOLK
ELKR
FLSH
ENAB
R/W
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Cache off
RAM on
Cache 4 K
RAM off
Cache 4 K Cache 2 K
RAM on
RAM off
TAG1
TAG1
Initial value
0 - 000000B
Cache 2 K Cache 1 K
RAM on
RAM off
Cache
RAM on
TAG1
TAG1
<TAG1>
<TAG1>
<TAG1>
<TAG1>
<TAG1>
<TAG1>
<TAG1>
<TAG1>
TAG2
TAG2
TAG2
<TAG2>
<TAG2>
<TAG2>
TAG2
<TAG2>
<TAG2>
<TAG2>
<TAG2>
IRAM1
$RAM1
$RAM1
$RAM1
<TAG2>
IRAM1
<IRAM1>
<IRAM1>
<$RAM1>
IRAM2
IRAM2
$RAM2
<IRAM2>
<IRAM2>
IRAM1
IRAM1
IRAM1
IRAM1
<IRAM1>
<$RAM1>
<IRAM1>
<$RAM1>
$RAM2
<$RAM2>
IRAM2
IRAM2
IRAM2
IRAM2
<IRAM2>
<$RAM2>
<IRAM2>
<$RAM2>
$RAM1 ⋅⋅⋅Cache RAM (way1)
TAG1 ⋅⋅⋅TAG RAM (way1)
$RAM2 ⋅⋅⋅Cache RAM (way2)
TAG2 ⋅⋅⋅TAG RAM (way2)
<> ⋅⋅⋅Mirror area
RAM on/off⋅⋅⋅RAM bit = I/O
Cache RAM
←Entry at address 00x
00018000 H
00018004 H
←Mirror of 00x
←Entry at address 00x
←Mirror of 00x
$RAM2
00018008 H
0001800C H
00018010 H
00018014 H
IRAM1 ⋅⋅⋅I-bus RAM (way1)
IRAM1 ⋅⋅⋅I-bus RAM (way2)
Instruction at address 000 (SBV0)
Instruction at address 004 (SBV1)
Instruction at address 008 (SBV2)
Instruction at address 00C (SBV3)
Instruction at address 010 (SBV0)
Instruction at address 014 (SBV1)
⋅⋅⋅
DS07-16502-5E
MB91301 Series
Address
000H
200H
400H
600H
000H
200H
400H
600H
Cache 4 K
$RAM1
$RAM1
IRAM1
$RAM2
$RAM2
ROMA = 0
00100000 H
Cache 1 K
$RAM1
(ROM absent)
Address
00000000 H
00010000 H
00020000 H
00030000 H
00040000 H
Cache 2 K
IRAM2
Direct area
IRAM
IRAM
DS07-16502-5E
$RAM2
IRAM2
IRAM2
(Even the D-bus RAM area is cashed, when it is
transferred to the IA-Bus.)
Internal ROM/RAM area should be cached.
Internal
memory
Cache area
FFFFFFFFH
IRAM1
ROMA = 1
(ROM present)
Direct area
Cache area
IRAM1
Cache off
Each chip-select area can be set as a non-cache
area.
55
MB91301 Series
■ PERIPHERAL RESOURCES
1. External Bus Interface Controller
• External Bus Interface Controller Features
• Maximum output address width = 32-bit (4 Gbytes memory space)
• Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the
controller can support multiple devices with different access timings.
Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byteenable access)
Page mode ROM/FLASH memory (2, 4, or 8 page size)
Burst mode ROM/FLASH memory
Address/data multiplexed bus (8-bit or 16-bit width only)
Synchronous memory (built-in ASIC memory, etc.)
Note: Synchronous SRAM cannot be directly connected.
• Memory can be divided into eight independent banks (chip select areas) with a separate chip select output
for each bank.
The size of each area can be set in 64 Kbytes increments (the size of each chip select area can range from
64 Kbytes to 2 Gbytes)
Each area can be located anywhere in the physical address space (subject to boundary limitations based on
the area size)
• The following functions can be set independently for each chip select area :
Chip select area enable/disable (Access is not performed to disabled areas)
Setting of an access timing type to support each type of memory (For SDRAM, only the CS6 and CS7 areas
can be connected.)
Detailed access timing settings (wait cycles and similar settings for each access type)
Data bus width (8-bit, 16-bit, 32-bit)
Byte-ordering setting (big or little endian)
Note: The CS0 area must be big endian.
Write-prohibit setting (read-only areas)
Enable or disable loading into built-in cache
Enable or disable prefetch function
Maximum burst length setting (1, 2, 4, 8)
• Different detailed timing settings can be set for each timing type
Even for the same type, different settings can be used for each chip select area.
Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas)
The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O
areas)
Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas)
Idle cycles, recovery cycles, setup delays, and similar can be inserted.
Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM area)
Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh timings (SDRAM
area)
• DMA supports fly-by transfer
Transfer between memory and I/O can be performed by a single access.
Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer.
Hold times can be maintained by extending access to the data source only.
Separate idle and recovery cycle settings can be specified for use in fly-by transfer.
• Supports external bus arbitration using BRQ and BGRNT.
• Pins not used by the external interface can be set as general purpose I/O ports.
56
DS07-16502-5E
MB91301 Series
• Block Diagram
Internal
address bus
32
Internal
data bus
32
External data bus
write buffer
switch
read buffer
switch
MUX
DATA BLOCK
ADDRESS BLOCK
+1 or +2
External address
bus
address buffer
ASR
CS0 to CS7
ASZ
comparator
SRAS, SCAS,
SWE, MCLKE,
DQMUU, DQMUL,
DQMLU, DQMLL
SDRAM control
RCR
under flow
refresh counter
External pin controller
All block control
registers
&
control
DS07-16502-5E
RD
WR0, WR1,
WR2, WR3,
AS, BAA
BRQ
BGRNT
RDY
57
MB91301 Series
• I/O pin
External interface pin (Some pins are general purpose pins.)
The following shows I/O pins of each interface.
• Normal bus interface
A23 to A00, D31 to D00 (AD15 to AD00)
CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7
AS, SYSCLK, MCLK,
RD
WR, WR0 (UUB) , WR1 (ULB) , WR2 (ULB) , WR3 (LLB) ,
RDY, BRQ, BGRNT
• Memory interface
MCLK, MCLKE
MCLKI (for SDRAM)
LBA ( = AS) , BAA (for burst ROM/FLASH)
SRAS, SCAS, SWE ( = WR) (for SDRAM)
DQMUU, DQMUL, DQMLU, DQMLL (for SDRAM ( = WR0, WR1, WR2, WR3) )
• DMA interface
IOWR, IORD
DACK0, DACK1
DREQ0, DREQ1
DEOP0, DEOP1
58
DS07-16502-5E
MB91301 Series
• Register List
31
24 23
16 15
8 7
ASR0
ACR0
ASR1
ACR1
ASR2
ACR2
ASR3
ACR3
ASR4
ACR4
ASR5
ACR5
ASR6
ACR6
ASR7
ACR7
AWR0
AWR1
AWR2
AWR3
AWR4
AWR5
AWR6
AWR7
MCRA
MCRB
IOWR0
IOWR1
CSER
CHER
RCR
0
Area select registers 0 to 7 (ASR0 to ASR7)
Area configuration registers 0 to 7 (ACR0 to ACR7)
Area weight register (AWR0 to AWR7)
TCR
Memory setting register
(For SDRAM/FCRAM auto-precharge OFF mode) (MCRA)
Memory setting register
(For FCRAM auto-precharge ON mode) (MCRB)
DMAC I/O wait registers (IOWR0 and IOWR1)
Chip-select area enable register (CSER)
Cache fetch enable register (CHER)
Terminal and timing control register (TCR)
Refresh control register (RCR)
(MODR)
Notes : • Reserved indicates a reserved register. When writing, always set to “0”.
• The MODR register cannot be accessed by the user program.
DS07-16502-5E
59
MB91301 Series
2. I/O Ports
MB91301 series pins can be used as I/O ports when not set for use by the external bus interface or the various
peripheral I/O functions.
• I/O port (with pull-up resistor) block diagram
PDR read
Port Bus
Peripheral input
0
Pull-up resistor
(approx. 25 kΩ)
1
Peripheral output
PDR
Pin
1
0
PFR
DDR
PCR
PCR = 0 : No pull-up resistor
PCR = 1 : Use pull-up resistor
PDR : Port Data Register
DDR : Data Direction Register
PFR : Port Function Register
PCR : Pull-up Control Register
Note : For port output, the pull-up resistor is disabled irrespective of the setting.
I/O ports with pull-up resistors have the following registers :
• PDR (Port Data Register)
• DDR (Data Direction Register)
• PFR (Port Function Register)
• PCR (Pull-up Control Register)
I/O ports have three following modes
• When port is in input mode (PFR = 0 & DDR = 0)
PDR read : Reads the level of the corresponding external pin.
PDR write : Writes the value to the PDR.
• When port is in output mode (PFR = 0 & DDR = 1)
PDR read : Reads the PDR value.
PDR write : Outputs the PDR value to the corresponding external pin.
• When port is in peripheral output mode (PFR = 1 & DDR = X)
PDR
: Reads the value of the corresponding peripheral output.
PDR write : Writes the value to the PDR.
60
DS07-16502-5E
MB91301 Series
Notes : • Use byte access to access ports.
• The external bus function has priority for port 0 to port A when these are used as external bus pins.
Accordingly, writing to the DDR has no effect on the pin input/output setting while the pins are operating
as external bus pins. The value set in the DDR becomes meaningful when the PFR register is modified
to set the pins as general purpose ports.
• In stop mode (HIZ = 0), the pull-up resistor control register setting is used.
• In stop mode (HIZ = 1), the pull-up resistor control register (PCR) setting is ignored during hardware
standby.
• Using pull-up resistors is prohibited when these pins are used as external bus pins. In this case, do not
write “1” to the corresponding bit in the pull-up resistor control register (PCR).
DS07-16502-5E
61
MB91301 Series
• Port Data Register (PDR)
PDR0
7
6
5
4
3
2
1
0
Initial value
Address : 00000000H
P07
P06
P05
P04
P03
P02
P01
P00
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
P17
P16
P15
P14
P13
P12
P11
P10
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
XXXXXXXXB
PDR1
Address : 00000001H
PDR2
Address : 00000002H
PDR6
Address : 00000006H
PDR8
Address : 00000008H
PDR9
Address : 00000009H
PDRA
Address : 0000000AH
PDRB
Address : 0000000BH
PDRG
Address : 00000010H
PDRH
Address : 00000011H
PDRJ
Address : 00000013H
Initial value
XXXXXXXXB
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
XXXXXXXXB
P87
P86
P85
P84
P83
P82
P81
P80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
⎯
P96
P95
P94
P93
P92
P91
P90
- XXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
Initial value
XXXXXXXXB
Initial value
- - - - - XXXB
Initial value
XXXXXXXXB
• PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the I/O data registers for the I/O pots.
• The corresponding DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG, DDRH and DDRJ and PFR6 to PFRJ
registers control input/output.
• P00 to P07, P10 to P17 and P20 to P27 do not have a PFR (port function register).
62
DS07-16502-5E
MB91301 Series
• Data Direction Register (DDR)
DDR0
Address : 00000600H
DDR1
Address : 00000601H
DDR2
Address : 00000602H
DDR6
Address : 00000606H
DDR8
Address : 00000608H
DDR9
Address : 00000609H
DDRA
Address : 0000060AH
DDRB
Address : 0000060BH
DDRG
Address : 00000400H
DDRH
Address : 00000401H
DDRJ
Address : 00000403H
7
6
5
4
3
2
1
0
Initial value
P07
P06
P05
P04
P03
P02
P01
P00
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
P17
P16
P15
P14
P13
P12
P11
P10
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
P27
P26
P25
P24
P23
P22
P21
P20
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
P67
P66
P65
P64
P63
P62
P61
P60
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
P87
P86
P85
P84
P83
P82
P81
P80
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
⎯
P96
P95
P94
P93
P92
P91
P90
- 0000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
- - - - - 000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Initial value
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG, DDRH and DDRJ control the direction (input or output) of each
bit in the corresponding port.
When PFR = 0 DDR = 0 : Port input
DDR = 1 : Port output
When PFR = 1 DDR = 0 : Peripheral input
DDR = 1 : Peripheral output
DS07-16502-5E
63
MB91301 Series
• Pull-up Resistor Control Register (PCR)
Address :
Address :
PCR0
bit
00000620H
PCR1
bit
00000621H
Address :
PCR2
bit
00000622H
Address :
PCR6
bit
00000626H
Address :
PCR8
bit
00000628H
Address :
Address :
Address :
Address :
PCR9
bit
00000629H
PCRA
bit
0000062AH
PCRB
bit
0000062BH
PCRH
bit
00000421H
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
P96
P95
P94
⎯
⎯
P91
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
PH2
PH1
PH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
Initial value
00000000B
Initial value
00000000B
Initial value
00000000B
Initial value
00000000B
Initial value
- 000 - - 0 -B
Initial value
00000000B
Initial value
00000000B
Initial value
- - - - - 000B
PCR0 to PCR2, PCR6, PCR8 to PCRB , and PCRH control the pull-up resistors for the corresponding port.
PCR = 0 : No pull-up resistor
PCR = 1 : Use pull-up resistor
64
DS07-16502-5E
MB91301 Series
• Port Function Register (PFR)
Address :
Address :
PFR6
bit
00000616H
7
6
5
4
3
2
1
0
A23E
A22E
A21E
A20E
A19E
A18E
A17E
A16E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4
3
2
1
0
⎯
⎯
BRQE
⎯
⎯
PFR8
bit
7
6
5
00000618H
WR3XE WR2XE WR1XE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
WRXE
BAAE
ASXE
⎯
R/W
R/W
R/W
R/W
R/W
Address :
PFR9
bit
00000619H
Address :
PFRA1
bit
7
6
5
4
3
2
1
0
0000061AH
CS7XE CS6XE CS5XE CS4XE CS3XE CS2XE CS1XE CS0XE
Address :
PFRB1
bit
0000061BH
Address :
PFRB2
bit
0000061CH
Address :
PFRA2
bit
0000061EH
Address :
PFRG
bit
00000410H
Address :
Address :
Address :
PFRH
bit
00000411H
PFRJ
bit
00000413H
PFR61
bit
00000617H
MCKE MCKEE
R/W
R/W
SYSE
Initial value
11111111B
Initial value
111 - - 0 - -B
Initial value
- 0000111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DES1
AK12
AK11
AK10
DES0
AK02
AK01
AK00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DRDE
DWRE
PPE1
⎯
⎯
⎯
AKH1
AKH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
⎯
PPE2
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
SCE2
SOE2
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
PPE3
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
PPE0
SCE1
SOE1
⎯
SCE0
SOE0
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
TEST1
TEST0
I2CE1
I2CE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
11111111B
Initial value
00000000B
Initial value
000 - - - 00B
Initial value
- - 0 - - - - -B
Initial value
00 - - - - - -B
Initial value
- - - - - - 0 -B
Initial value
- 000 - 00 -B
Initial value
- - - - 0000 B
PFR6, PFR8 to PFRB, PFRA2, PFRG, PFRH and PFRJ control the output for the corresponding external bus
interface or peripheral output bit.
Always write "0" to unused bits in the PFR.
DS07-16502-5E
65
MB91301 Series
3. Interrupt Controller
The interrupt controller receives and processes interrupts.
• Hardware Configuration
The interrupt controller consists of the following :
• ICR register
• Interrupt priority determination circuit
• Interrupt level and interrupt number (vector) generator
• Hold request removal request generator
• Principal Functions
The main functions of the interrupt controller are as follows :
• Detect NMI and interrupt requests
• Prioritize interrupts (according to level and number)
• Notify interrupt level of selected interrupt request (to CPU)
• Notify interrupt number of selected interrupt request (to CPU)
If an NMI or interrupt request with an interrupt level other than "11111B" occurs, notify recovery from stop mode
(to CPU)
• Generate hold request removal requests to the bus master
• Block Diagram
UNMI
WAKEUP
(“1”
when
LEVEL
11111
(“1”
when
LEVEL
≠ ≠11111
B) B)
Determine
order
priority
Determine
order
ofof
priority
NMI
NMI
processing
processing
5
LEVEL
LEVEL
determination
determination
RI00
ICR00
VECTOR
VECTOR
6
determination
determination
LEVEL4 to LEVEL0
LEVEL,
LEVEL,
VECTOR
VECTOR
generageneration
tion
HLDREQ
HLDREQ
removal
removal
request
request
MHALTI
VCT5 to VCT0
ICR47
RI47
(DLYIRQ)
R-bus
66
DS07-16502-5E
MB91301 Series
• Register List
bit
7
6
5
4
3
2
1
0
Address : 00000440H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR00
Address : 00000441H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
Address : 00000442H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
Address : 00000443H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
Address : 00000444H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
Address : 00000445H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
Address : 00000446H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
Address : 00000447H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
Address : 00000448H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
Address : 00000449H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
Address : 0000044AH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
Address : 0000044BH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
Address : 0000044CH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
Address : 0000044DH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
Address : 0000044EH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
Address : 0000044FH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
Address : 00000450H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
Address : 00000451H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
Address : 00000452H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
Address : 00000453H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
Address : 00000454H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
Address : 00000455H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
Address : 00000456H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
Address : 00000457H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
Address : 00000458H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
Address : 00000459H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
Address : 0000045AH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
Address : 0000045BH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
Address : 0000045CH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
Address : 0000045DH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
Address : 0000045EH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
Address : 0000045FH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
(Continued)
DS07-16502-5E
67
MB91301 Series
(Continued)
bit
7
6
5
4
3
2
1
0
Address : 00000460H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR32
Address : 00000461H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
Address : 00000462H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
Address : 00000463H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
Address : 00000464H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
Address : 00000465H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
Address : 00000466H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
Address : 00000467H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
Address : 00000468H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
Address : 00000469H
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
Address : 0000046AH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
Address : 0000046BH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
Address : 0000046CH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
Address : 0000046DH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
Address : 0000046EH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
Address : 0000046FH
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
MHALTI
⎯
⎯
LVL4
LVL3
LVL2
LVL1
LVL0
HRCL
Address :
68
0000045H
DS07-16502-5E
MB91301 Series
4. External Interrupt/NMI Control Block
The external interrupt control block controls external interrupt requests input to the NMI and INT0 to INT7 pins.
The interrupt trigger level can be selected from "H", "L", "rising edge", or "falling edge" (except for NMI).
• Block Diagram
R-bus
8
Interrupt enable register
9
Interrupt
request
Gate
8
Edge detection circuit
Request F/F
9
INT0 to INT7
NMI
Interrupt request register
8
Interrupt level setting register
• Register List
External interrupt enable register (ENIR)
bit
7
6
5
EN7
EN6
EN5
External interrupt request register (EIRR)
bit
15
14
13
ER7
ER6
Request level setting register (ELVR)
bit
15
14
bit
DS07-16502-5E
ER5
4
3
2
1
0
EN4
EN3
EN2
EN1
EN0
12
11
10
9
8
ER4
ER3
ER2
ER1
ER0
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
69
MB91301 Series
5. Delay Interrupt Module
The delay interrupt module is used to generate interrupts for task switching.
This module can be used to generate and cancel interrupts to the CPU via software.
• Block Diagram
R-bus
DLYI
Interrupt request
• Register List
Delay interrupt control register (DICR)
bit
70
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DLYI
DS07-16502-5E
MB91301 Series
6. PPG Timer
The PPG timer can output highly precise PWM waveforms efficiently.
The MB91301 series contains four channels of PPG timer.
• Features of the PPG Timer
• Each channel consists of a 16-bit down counter, a 16-bit data register with cycle setting buffer, a 16-bit compare
register with duty setting buffer, and pin control section.
• The count clocks for the 16-bit down counter can be selected from the following four types :
Internal clock φ, φ/4, φ/16, φ/64
• The counter is initialized to “FFFFH” at a reset or counter borrow.
• Each channel has a PPG output.
• Register outline
Cycle setting register: Reload data register with buffer
Duty setting register: Compare register with buffer
Transfer from the buffer takes place upon a counter borrow.
• Pin control overview
A duty match sets the pin control section to 1. (Preferential)
A counter borrow resets it to 0.
The output value fix mode is available, which can each output all "L" (or "H").
A polarity can also be specified.
• An interrupt request can be generated at a combination of the following events :
Activation of the PPG timer
Counter borrow (cycle match)
Duty match
Counter borrow (cycle match) or duty match
DMA transfer can be initiated by the above interrupt request.
• It is possible to set the simultaneous activation of two or more channels by means of software or another
interval timer.
Restarting during operation can also be set.
• The request level to be detected can be selected from among "rising edge", "falling edge", and "both edges".
DS07-16502-5E
71
MB91301 Series
• Block diagram
16-bit reload timer
ch.0
16-bit reload timer
ch.1
General control
register 2
General
control
register 1
(resource select)
4
4
External TRG0 to TRG3
TRG input
PPG timer ch.0
PPG0
TRG input
PPG timer ch.1
PPG1
TRG input
PPG timer ch.2
PPG2
TRG input
PPG timer ch.3
PPG3
• Block diagram for 1 channel
PCSR
PDUT
Prescaler
1/1
1/4
1 / 16
1 / 64
Clock
cmp
Load
16-bit down counter
Start
Borrow
PPG mask
S
Peripheral clock
PPG output
Q
R
Enable
TRG input
72
Edge
detection
Soft trigger
Interrupt
selection
Conversion
bit
IRQ
DS07-16502-5E
MB91301 Series
• Register List
bit 15
7
0
General control register 10
GCN10
GCN20
PTMR0
ch.0 timer register
PCSR0
ch.0 cycle setting register
PDUT0
ch.0 duty setting register
PCNL0
PCNH0
ch.1 timer register
PCSR1
ch.1 cycle setting register
PDUT1
ch.1 duty setting register
PCNL1
ch.1 control status register
PTMR2
ch.2 timer register
PCSR2
ch.2 cycle setting register
PDUT2
ch.2 duty setting register
PCNL2
PCNH2
DS07-16502-5E
ch.0 control status register
PTMR1
PCNH1
PCNH3
General control register 20
ch.2 control status register
PTMR3
ch.3 timer register
PCSR3
ch.3 cycle setting register
PDUT3
ch.3 duty setting register
PCNL3
ch.3 control status register
73
MB91301 Series
7. 16-Bit Reload Timer
The 16-bit timer consists of a 16-bit down-counter, 16-bit reload register, prescaler for generating the internal
count clock, and a control register.
The clock source can be selected from three internal clock signals (machine clock divided by 2, 8, or 32) or the
external event.
The interrupt can be used to initiate DMA transfer.
The MB91301 series has three 16-bit reload timer channels.
• Block Diagram
16
16-bit reload register (TMRLR)
7
Reload
16
16-bit down counter (TMR) UF
RELD
Count enable
OUT
CTL.
R-bus
Re-trigger
INTE
UF
IRQ
CNTE
Clock selector
CSL1
TRG
CSL0
EXCK
3
φ
φ
φ
21 23 25
Prescaler
clear
IN CTL.
3
MOD0
MOD1
CLKP input
External
trigger
selection
External trigger input (TI)
MOD2
3
74
DS07-16502-5E
MB91301 Series
• Register List
Control status register (TMCSR)
bit
15
14
bit
13
12
11
10
9
8
CSL1
CSL0
MOD2
MOD1
⎯
⎯
⎯
⎯
7
6
5
4
3
2
1
0
MOD0
⎯
OUTL
RELD
INTE
UF
CNTE
TRG
16-bit timer register (TMR)
bit 15
0
16-bit reload register (TMRLR)
bit 15
0
DS07-16502-5E
75
MB91301 Series
8. U-TIMER (16 bit timer for UART baud rate generation)
The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set
using the combination of the chip operating frequency and U-TIMER reload value.
The U-TIMER can also be used as an interval timer by generating an interrupt from a count underflow event.
The MB91301 series has three U-TIMER channels. When used as an interval timer, two U-TIMER channels can
be connected in cascade for a maximum count interval of up to 232 × φ.
Cascade connection is only available for ch0 and ch1 or ch0 and ch2.
• Block Diagram
15
0
UTIMR (reload register)
load
15
0
UTIM (timer)
clock
underflow
φ (CLKP)
(Peripheral clock)
control
MUX
ch.0 only
f.f.
to UART
under flow U-TIMER 1
76
DS07-16502-5E
MB91301 Series
• Register List
8 7
15
0
UTIM
UTIMR
UTIMC
• U-TIMER (UTIM)
Address
bit
000064H (ch.0)
00006CH (ch.1)
000074H (ch.2)
15
14
2
1
0
b15
b14
b2
b1
b0
R
R
R
R
R
Initial value
00000000 00000000B
UTIM contains the timer value. Use a 16-bit transfer instruction to access the register.
Reload register (UTIMR)
Address
bit
15
000064H (ch.0)
b15
00006CH (ch.1)
W
000074H (ch.2)
14
2
1
0
b14
b2
b1
b0
W
W
W
W
Initial value
00000000
00000000B
UTIMR is the register that contains the value to be reloaded to UTIM when UTIM causes an underflow.
Use a 16-bit transfer instruction to access the register.
DS07-16502-5E
77
MB91301 Series
9. UART
The UART is a serial I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission.
The MB91301 series has three UART channels.
• UART Features
• Full duplex double buffer
• Asynchronous (start-stop synchronized) or CLK synchronized transmission
• Supports multi-processor mode
• Fully programmable baud rate
The internal timer can be set to any desired baud rate (see “8. U-TIMER” description)
• Variable baud rate can be input from an external clock.
• Error detection functions (parity, framing, overrun)
• Transmission signal format is NRZ
• The interrupt can be used to initiate DMA transfer.
• The DMAC interrupt can be cleared by writing to the DRCL register.
78
DS07-16502-5E
MB91301 Series
• Block Diagram
Control signal
RX interrupt
(to CPU)
SCK (clock)
From U-TIMER
Clock
selection
circuit
TX interrupt
(to CPU)
TX clock
RX clock
External clock
SCK
SI (Receive data)
RX control circuit
TX control circuit
Start bit detect
circuit
TX start
circuit
Receive bit
counter
Send bit
counter
Receive parity
counter
Send parity
counter
SO (Send data)
Receive status
decision circuit
RX shifter
TX shifter
RX
complete
TX start
SIDR
SODR
Receive error
signal for DMA
(to DMAC)
R-bus
MD1
MD0
SMR
register
CS0
SCKE
SCR
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control
signal
DS07-16502-5E
79
MB91301 Series
• Register List
8 7
15
0
SCR
SMR
(R/W)
SSR
SIDR (R)/SODR (W)
(R/W)
DRCL
(W)
8-bit
8-bit
Serial input data register
Serial output data register (SIDR/SODR)
bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
6
5
4
3
2
1
0
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
7
6
5
4
3
2
1
0
MD1
MD0
⎯
⎯
CS0
⎯
SCKE
⎯
Serial status register (SSR)
7
bit
PE
Serial mode register (SMR)
bit
Serial control register (SCR)
7
bit
6
5
4
3
2
1
0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DRCL register (DRCL)
bit
80
DS07-16502-5E
MB91301 Series
10. A/D Converter (Successive Approximation Type)
The A/D converter converts analog input voltages to digital values.
• A/D Converter Features
• Peripheral clock (CLKP) 140 clock cycle
• Minimum conversion time 4.1 μs/ch (for machine clock 34 MHz = CLKP)
• Built-in sample & hold circuit
• Resolution = 10-bit
• 4 channel program-selectable analog inputs
Single conversion mode : Convert 1 specified channel
Scan conversion mode : Continuous conversion of multiple channels. Conversion can be specified for up
to 4 channels.
• Single, continuous, and stop conversion operation is supported.
Single conversion mode
: Convert specified channel then stop.
Continuous conversion mode : Perform continuous conversion for the selected channel.
Stop conversion mode
: Perform conversion for one channel, then wait for the next activation trigger
(synchronizes the conversion start timing)
• DMA transfer can be initiated by an interrupt.
• Selectable conversion activation trigger: Software, external trigger (falling edge), or reload timer (rising edge)
DS07-16502-5E
81
MB91301 Series
• Block Diagram
AVCC
AVRH AVSS
AVR
Internal voltage
generator
Input switch
Sample & hold circuit
AN1
AN2
Successive
approximation register
AN3
Data register
(ADCR : 10 bit)
R-bus
AN0
Upper 8 bit COPY
Data register
(ADCR0 to ADCR7 : 8bit)
Channel decoder
A/D control register
(ADCS)
Timing generation circuit
Machine clock
φ (CLKP)
Prescaler
ATG (External pin trigger)
Reload timer ch.2
(internal connection)
• Register List
Control status register (ADCS)
bit
bit
15
14
13
12
11
10
9
8
BUSY
INT
INTE
CRF
STS1
STS0
STRT
⎯
7
6
5
4
3
2
1
0
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data register (ADCR)
bit
bit
Conversion result register (ADCR0 to ADCR3)
bit
82
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DS07-16502-5E
MB91301 Series
11. DMAC (DMA Controller)
The DMA controller is used to perform DMA (direct memory access) transfer on the FR family device.
Using DMA transfer under the control of the DMA controller improves system performance by enabling data to
be transferred at high speed independently of the CPU.
• Hardware Configuration
• Independent DMA channels × 5 channels
• 5-channel independent access control circuits
• 32-bit address register (Supports reloading : 2 per channel)
• 16-bit transfer count register (Supports reloading : 1 per channel)
• 4-bit block count register (1 per channel)
• External transfer request input pins : DREQ0, DREQ1 (ch.0, ch.1 only)
• External transfer request acknowledge output pins : DACK0, DACK1 (ch.0, ch.1 only)
• DMA completion output pins : DEOP0, DEOP1 (ch.0, ch.1 only)
• fly-by transfer (memory to I/O , I/O to memory) (ch.0, ch.1 only)
• Two-cycle transfer
• Main Functions of the DMA Controller
• Supports independent data transfer for multiple channels (5 channels)
(1) Priority order (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
(2) Order can be reversed for ch.0 and ch.1
(3) DMAC activation triggers
• Input from dedicated external pin (edge detection/level detection, ch.0, ch.1 only)
• Request from built-in peripheral (shared interrupt request, including external interrupts)
• Software request (register write)
(4) Transfer modes
• Demand transfer, burst transfer, step transfer, or block transfer
Addressing mode: Full 32-bit address (increment/decrement/fixed)
(address increment can be in the range −255 to +255)
• Data type : byte/half-word/word
• Single-shot or reload operation selectable
DS07-16502-5E
83
MB91301 Series
• Block Diagram
Counter
DTC two-stage register DTCR
DMA
start trigger
selection
circuit & request
acknowledge
control
Counter
Buffer
Selector
Read/write
control
address
DSS [3:0]
Priority
circuit
Selector
BLK register
DDNO register
External pin start
request/Stop input
IRQ
[4:0]
To interrupt controller
ERIR, EDIR
Status
transition
circuit
Clear peripheral interrupt
DSAD two-stage register
MCLREQ
TYPE, MOD, WS
DMA control
Selector
Counter buffer
Counter buffer
Access
Address counter
DDNO
SDAM, SASZ [7:0] SADR
Write back
Selector
Bus control block
To bus
controller
Read
Write
Peripheral start request/
Stop input
X-bus
Selector
Write
back
Buffer
Bus control block
DMA transfer
request to bus
controller
DDAD two-stage register
DADM, DASZ [7:0] DADR
Write back
5-channel DMAC block diagram
84
DS07-16502-5E
MB91301 Series
• Register List
ch.0 control status
register A DMACA0 0000200H
register B DMACB0 0000204H
ch.1 control status
register A DMACA1 0000208H
ch.1 control status
register B DMACB1 000020CH
ch.2 control status
register A DMACA2 0000210H
ch.2 control status
register B DMACB2 0000214H
ch.3 control status
register A DMACA3 0000218H
ch.3 control status
register B DMACB3 000021CH
ch.4 control status
register A DMACA4 0000220H
ch.4 control status
register B DMACB4 0000224H
ch.0 control status
Overall control register
DMACR 0000240H
ch.0 transfer source address register
DMASA0 0001000H
ch.0 transfer destination address register
DMADA0 0001004H
ch.1 transfer source address register
ch.1 transfer destination address register
ch.2 transfer source address register
ch.2 transfer destination address register
ch.3 transfer source address register
ch.3 transfer destination address register
ch.4 transfer source address register
ch.4 transfer destination address register
DS07-16502-5E
bit 31
24 23
16 15
8 7
0
bit 31
24 23
16 15
8 7
0
DMASA1 0001008H
DMADA1 000100CH
DMASA2 0001010H
DMADA2 0001014H
DMASA3 0001018H
DMADA3 000101CH
DMASA4 0001020H
DMADA4 0001024H
85
MB91301 Series
12. I2C Interface
I2C interface is the serial I/O port that support INTER IC BUS and functions as the master/slave device on the
I2C bus. It has the features below.
• Master/slave transmission and reception
• Arbitration function
• Clock synchronization
• Slave address/general call address detection function
• Forwarding direction detection function
• The function of generating/detecting repeat “START” conditions.
• Bus error detection function
• 10-bit/7-bit slave address
• Control slave address receiving at the master mode
• For support multiple slave address
• Can be interrupt at transmitting or bus mirror
• For normal mode (Max 100 Kbps) /fast mode (Max 400 Kbps)
86
DS07-16502-5E
MB91301 Series
• Block Diagram (1 ch)
ICCR
I2C operating enable
EN
IDBL
DBL
Clock enable
CLKP
ICCR
Clock dividing 2
CS4
CS3
CS2
CS1
CS0
IBSR
BB
RSC
LRB
2345
32
Clock select 2 (1/12)
Bus busy
Repeat start
Last Bit
Shift clock
generation
Shift clock edge
change timing
Start/stop condition
detection
Transmission/
reception
TRX
Error
First Byte
ADT
Arbitration lost
detection
AL
R-bus
Sync
IBCR
BER
SCL0/1
BEIE
Interrupt request
IRQ
INTE
SDA0/1
INT
IBCR
SCC
MSS
ACK
GCAA
End
Start
Master
ACK enable
Start/stop condition
generation
GC-ACK enable
IDAR
IBSR
AAS
Slave
Global call
GCA
Slave address
comparison
ISMK
FNSB
ITMK
ENTB
RAL
ITBA
DS07-16502-5E
ITMK
ISBA
ISMK
87
MB91301 Series
• Register List
• Bus control register (IBCR0/IBCR1)
Address :
000094H/0000B4H
15
14
13
12
11
10
9
8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Initial value = >
0
0
• Bus status register (IBSR0/IBSR1)
Address :
000095H/0000B5H
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
ADT
R
R
R
R
R
R
R
R
0
0
0
0
0
Initial value = >
0
0
0
• 10-bit slave address register (ITBA0/ITBA1)
Address :
000096H/0000B6H
Initial value = >
Address :
000097H/0000B7H
Initial value = >
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
TA9
TA8
R
R
R
R
R
R
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
(Continued)
88
DS07-16502-5E
MB91301 Series
(Continued)
• 10-bit slave address mask register (ITMK0/ITMK1)
Address :
000098H/0000B8H
Initial value = >
Address :
000099H/0000B9H
15
14
13
12
11
10
9
8
ENTB
RAL
⎯
⎯
⎯
⎯
TM9
TM8
R/W
R
R
R
R
R
R/W
R/W
0
0
1
1
1
1
1
1
7
6
5
4
3
2
1
0
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
Initial value = >
1
1
• 7-bit slave address register (ISBA0/ISBA1)
Address :
00009BH/0000BBH
7
6
5
4
3
2
1
0
⎯
SA6
SA5
SA4
SA3
SA2
SA1
SA0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Initial value = >
0
0
0
• 7-bit slave address mask register (ISMK0/ISMK1)
Address :
00009AH/0000BAH
15
14
13
12
11
10
9
8
ENSB
SM6
SM5
SM4
SM3
SM2
SM1
SM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
Initial value = >
0
•Data register (IDAR0/IDAR1)
Address :
00009DH/0000BDH
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Initial value = >
0
0
•Clock control register (ICCR0/ICCR1)
Address :
00009EH/0000BEH
15
14
13
12
11
10
9
8
TEST
⎯
EN
CS4
CS3
CS2
CS1
CS0
W
R
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
Initial value = >
0
0
•Clock disable register (IDBL0/IDBL1)
Address :
00009FH/0000BFH
Initial value = >
DS07-16502-5E
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DBL
R
R
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
89
MB91301 Series
13. 16-bit Free Run Timer
16-bit free-run timer consists of a 16-bit up counter and a control status register.
The timer count value is used as the base timer of output compare and input capture.
• The count clock can be selected from four different clocks.
• Can be generated the interrupt by the counter over-flow.
• Setting the mode enables initialization of counter through compare-match operation with the value of the
compare clear register0 in the output compare.
90
DS07-16502-5E
MB91301 Series
•Block Diagram
Interrupt
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
φ
Prescaler
F-bus
FRCK
Clock selector
16-bit Free run Timer
(TCDT)
Clock
To internal circuit (T15 to T00)
Comparator0
•Register List
DS07-16502-5E
15
14
13
12
11
10
9
8
Timer data register (upper)
T15
T14
T13
T12
T11
T10
T9
T8
(TCDT)
7
6
5
4
3
2
1
0
Timer data register (lower)
T07
T06
T05
T04
T03
T02
T01
T00
(TCDT)
7
6
5
4
3
2
1
0
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Timer control status register
(lower)
(TCCS)
91
MB91301 Series
14. Input Capture
This module has a function that detects a rising edge, falling edge or both edges and holds a value of the
16-bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.
The input capture consist of input capture and control registers.
Each input capture have the corresponded external input pins.
• The valid edge of the external input can be selected from three types :
Rising edge
Falling edge
Both edges
• It can generate an interrupt when it detects the valid edge of the external input.
92
DS07-16502-5E
MB91301 Series
•Block Diagram
16-bit timer count value (T15 to T00)
R-bus
Capture data register
ch (0, 2)
ICU0, ICU2
input pin
Edge detection
EG11
EG10
EG01
EG00
EG31
EG30
EG21
EG20
16-bit timer count value (T15 to T00)
Capture data register
ch (1, 3)
ICU1, ICU3
input pin
Edge detection
ICP1
ICP0
ICE1
ICE0
ICP3
ICP2
ICE3
ICE2
Interrupt
Interrupt
DS07-16502-5E
93
MB91301 Series
•Register List
94
15
14
13
12
11
10
9
8
Input capture data register (upper)
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
(IPCP)
7
6
5
4
3
2
1
0
Input capture data register (lower)
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
(IPCP)
7
6
5
4
3
2
1
0
Capture control register
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
(ICS23)
7
6
5
4
3
2
1
0
Capture control register
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
(ICS01)
DS07-16502-5E
MB91301 Series
15. Clock Generation Control
The internal operating clock is generated as follows in MB91301 series.
• Source clock selection : Selects the clock source.
• Base clock generation : The base clock is generated by dividing the source clock by 2 or using a PLL.
• Generation in each internal block : The base clock is divided to generate the operating clock for each block.
DS07-16502-5E
95
MB91301 Series
• Block Diagram
[Clock generator]
Stop control
External bus clock
division
Selector
Peripheral clock
division
Selector
R-bus
CPU clock division
Selector
DIVR0, 1 register
CPU clock
(CLKB)
Peripheral clock
(CLKP)
External bus
clock (CLKT)
CLKR register
X1
tion
circuit
Internal interrupt
Internal reset
Selector
X0
OscillaPLL
1/2
[Stop/sleep
controller]
Stop state
STCR register
State
transition
control
circuit
SLEEP state
Reset F/F
Internal reset (RST)
Reset F/F
Internal reset (INIT)
[Reset circuit]
INIT pin
RSRR register
[Watchdog controller]
Watchdog F/F
Timebase counter
CTBR register
Count clock
Selector
TBCR register
Interrupt enable
96
Overflow detection F/F
Timebase timer
interrupt request
DS07-16502-5E
MB91301 Series
• Register List
• RSRR : Reset initiation register/Watchdog timer control register
bit
15
14
13
12
11
10
9
8
INIT
⎯
WDOG
⎯
SRST
⎯
WT1
WT0
R
R
R
R
R
R
R/W
R/W
Initial value (INIT pin)
1
0
0
0
0
0
0
0
Initial value (INIT)
−
0
−
X
X
−
0
0
Initial value (RST)
X
X
X
−
−
X
0
0
7
6
5
4
3
2
1
0
STOP
SLEEP
HIZ
SRST
OS1
OS0
⎯
OSCD1
R/W
R/W
R/W
R/W
R/W
R/W
⎯
R/W
Initial value (INIT pin)
0
0
1
1
0
0
−
1
Initial value (INIT)
0
0
1
1
X
X
−
1
Initial value (RST)
0
0
X
1
X
X
−
X
15
14
13
12
11
10
9
8
TBIF
TBIE
TBC2
TBC1
TBC0
⎯
R/W
R/W
R/W
R/W
R/W
⎯
R/W
R/W
Initial value (INIT)
0
0
X
X
X
−
0
0
Initial value (RST)
0
0
X
X
X
−
X
X
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Initial value (INIT)
X
X
X
X
X
X
X
X
Initial value (RST)
X
X
X
X
X
X
X
X
14
13
12
11
10
9
8
Address : 00000480H
• STCR : Standby control register
bit
Address : 00000481H
• TBCR : Timebase counter control register
bit
Address : 00000482H
SYNCR SYNCS
• CTBR : Timebase counter clear register
bit
Address : 00000483H
• CLKR : Clock source control register
bit
Address : 00000484H
15
⎯
PLL1S2 PLL1S1 PLL1S0
⎯
PLL1EN CLKS1
CLKS0
⎯
R/W
R/W
R/W
⎯
R/W
R/W
R/W
Initial value (INIT)
−
0
0
0
−
0
0
0
Initial value (RST)
−
X
X
X
−
X
X
X
(Continued)
DS07-16502-5E
97
MB91301 Series
(Continued)
• DIVR0 : Base clock division setting register 0
bit
15
14
13
12
11
10
9
8
B3
B2
B1
B0
P3
P2
P1
P0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value (INIT)
0
0
0
0
0
0
1
1
Initial value (RST)
X
X
X
X
X
X
X
X
Address : 00000486H
• DIVR1 : Base clock division setting register 1
bit
7
6
5
4
3
2
1
0
T3
T2
T1
T0
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
⎯
⎯
⎯
⎯
Initial value (INIT)
0
0
0
0
−
−
−
−
Initial value (RST)
X
X
X
X
−
−
−
−
Address : 00000487H
− : Changes depending on what triggered the reset.
× : Not initialized
98
DS07-16502-5E
MB91301 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0 V)
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.5
VSS + 4.0
V
*1
AVCC
VSS − 0.5
VSS + 4.0
V
*2
AVRH,
AVRL
VSS − 0.5
AVCC
V
*2
Input voltage
VI
VSS − 0.3
VCC + 0.3
V
Analog pin input voltage
VIA
VSS − 0.3
AVCC + 0.3
V
Output voltage
VOH
VSS − 0.3
VCC + 0.3
V
“L” level maximum output
current
IOL
⎯
10
mA
*3
“L” level average output current
IOLAV
⎯
8
mA
*4
“L” level total maximum output
current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*5
IOH
⎯
−10
mA
*3
“H” level average output current
IOHAV
⎯
−4
mA
*4
“H” level total maximum output
current
ΣIOH
⎯
−50
mA
ΣIOHAV
⎯
−20
mA
Power consumption
PD
⎯
1000
mW
Operating temperature
Ta
0
+70
°C
TSTG
−50
+150
°C
Supply voltage
Analog supply voltage
Analog reference voltage
“L” level total average output
current
“H” level maximum output
current
“H” level total average output
current
Storage temperature
*5
*1 : VCC must not be lower than VSS − 0.3 V.
*2 : AVCC, AVRH and AVRL should not exceed VCC+0.3 V, including at power-on. AVRH and AVRL should not exceed
AVCC. Also AVRL should not exceed AVRH.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output current is the average current for a single pin over a period of 100ms.
*5 : The total average output current is the average current for all pins over a period of 100ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-16502-5E
99
MB91301 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0 V)
Parameter
Supply voltage
Analog supply voltage
Analog reference voltage
Operating temperature
Symbol
Value
Unit
Min
Max
VCC
3.0
3.6
V
AVCC
VSS + 3
3.6
V
AVRH
AVSS
AVCC
V
AVRL
AVSS
AVRH
V
Ta
0
+70
°C
Remarks
Normal operation
<Notes on turning the power on>
The maximum power rising slope (ΔV/Δt) must be 0.05 V/μs when the 3 V power supply is turned on.
It takes about 100 μs until the 2.5 V power supply becomes stable after the 3 V power supply becomes stable.
Keep INIT input during that interval.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
100
DS07-16502-5E
MB91301 Series
3. DC Characteristics
(VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
VIH
Non-hysteresis input pin
⎯
2.0
⎯
VCC + 0.3
V
VIHS
Hysteresis
input pin
⎯
0.8 × VCC
⎯
VCC + 0.3
V
VIL
Non-hysteresis input pin
⎯
VSS
⎯
0.8
V
VILS
Hysteresis
input pin
⎯
VSS
⎯
0.2 × VCC
V
“H” level output
voltage
VOH
All output pins
VCC = 3.0 V
VCC − 0.4
IOH = −4.0 mA
⎯
VCC
V
“L” level output
voltage
VOL
All output pins
VCC = 3.0 V
IOL = 4.0 mA
VSS
⎯
0.4
V
VCC = 3.6 V
All input pins* 0.45 V < VI <
VCC
−5
⎯
+5
μA
With pins Pull- VCC = 3.6 V
up settings VI = 0.45 V
10
25
120
kΩ
“H” level input
voltage
“L” level input
voltage
Input leak
current
(Hi-Z output
leak current)
Pull-up
resistance
ILI
RUP
Hysteresis input
Hysteresis input
fC = 17 MHz
VCC = 3.6 V
⎯
120
150
When operating at :
CLKB : 68 MHz
mA CLKT : 68 MHz
CLKP : 34 MHz
(×4 multiplier)
ICCS
fC = 17 MHz
VCC = 3.6 V
⎯
50
90
When sleeping at :
mA CLKP : 34 MHz
in sleep mode
ICCH
Ta = +25 °C
VCC = 3.6 V
⎯
200
700
μA In stop mode
⎯
⎯
5
15
pF
ICC
Power supply
current
Input
capacitance
Remarks
VCC
CIN
Except for
VCC
VSS
AVCC
AVSS
AVRH
AVR
* : Excludes X0, X1, pins with internal pull-up resistor (INIT, TRST), and pins with a pull-up resistor set by PCR.
DS07-16502-5E
101
MB91301 Series
4. AC Characteristics
(1) Clock Timing Ratings
(VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Sym- Pin
bol name
Parameter
fC
X0,
X1
Clock cycle time
tC
X0,
X1
Clock frequency (2)
fC
X0,
X1
Clock frequency (1)
Value
Condition
⎯
fCPP
Internal operation clock
cycle time
⎯
⎯
Remarks
Max
12.5
17
MHz
⎯
58.8
ns
10
34
MHz
0.78*
68
MHz CPU
⎯
fCP
Internal operation clock
frequency
Unit
Min
Using PLL
(When operating at max internal frequency (68 MHz) =
17 MHz self-oscillation with
×4 PLL)
Self-oscillation (1/2 division
input)
0.78*
34
MHz Peripherals
fCPT
0.78*
68
MHz External bus
tCP
14.7
1280*
ns
CPU
29.4
1280*
ns
Peripherals
14.7
1280*
ns
External bus
tCPP
⎯
⎯
tCPT
* : Values are for minimum clock frequency (12.5 MHz) input to X0, oscillation circuit uses PLL, and gear ratio = 1/16.
• Conditions for measuring the clock timing ratings
tC
0.8 VCC
Output pin
C = 50 pF
• Warranted operation range
VCC (V)
Power supply
Warranted operation range (Ta = 0 °C to +70 °C)
fCPP is represented by the shaded area.
3.6
3.0
0 0.78
34
68
fCP / fCPP
(MHz)
Internal operation clock
102
DS07-16502-5E
MB91301 Series
• External/internal clock setting range
fcp, fCPT
MHz
70
68
4 multiplier (CPU)
5 multiplier (CPU)
60
50
3 multiplier (CPU)
48
40
fCPP
34
4 multiplier, 2 divide
(CPU, peripheral)
5 multiplier, 2 divide
(CPU, peripheral)
30
3 multiplier, 2 divide
(CPU, peripheral)
4 multiplier, 3 divide
(CPU, peripheral)
24
22.7
5 multiplier, 3 divide
(CPU, peripheral)
20
17
4 multiplier, 4 divide
(CPU, peripheral)
10
1/2 divide
5
0
0
PLL
10
12.5
20
17
fc
MHz
30
34
Notes : • If using the PLL, input an external clock in the range 12.5 MHz to 17 MHz.
• Allow a PLL oscillation stabilization time > 300 μs.
• Set the gear ratio for the internal clock to be within the values shown in the “(1) Clock Timing Ratings”
table.
DS07-16502-5E
103
MB91301 Series
(2) Clock Output Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Symbol
Pin name
Cycle time
tCYC
SYSCLK,
MCLK
SYSCLK↑→SYSCLK↓
tCHCL
SYSCLK,
MCLK
SYSCLK↓→SYSCLK↑
tCLCH
SYSCLK,
MCLK
Parameter
Value
Condition
⎯
Unit
Remarks
Min
Max
tCPT
⎯
ns
*1
1 tCYC−2.35
2
1 tCYC+2.65
2
ns
*2
1 tCYC−2.35
2
1 tCYC+2.65
2
ns
*3
tCYC
tCHCL
SYSCLK
MCLK
tCLCH
VOH
VOH
VOL
*1 : tCYC is the frequency of one clock cycle after gearing.
*2 : The following ratings are for the gear ratio set to × 1.
For the ratings when the gear ratio is set to between 1/2, 1/4 and 1/8, substitute 1/2, 1/4 or 1/8 for n in the
following equation.
Min : (1 / 2 × 1 / n) × tCYC − 2.35
Max : (1 / 2 × 1 / n) × tCYC + 2.65
*3 : The following rating are for the gear ratio set to × 1.
Min : (1 / 2 × 1 / n) × tCYC − 2.35
Max : (1 / 2 × 1 / n) × tCYC + 2.65
(3) Reset and Tool Reset Input Ratings
(VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Condition
INIT input time (at power-on)
INIT input time
( other than at power-on)
tINTL
INIT,
TRST
⎯
INIT input time
(recovery from stop)
Value
Unit
Min
Max
20 + α
⎯
μs
tCP × 5
⎯
ns
20 + α
⎯
μs
Remarks
tINTL
INIT
TRST
104
0.2 VCC
DS07-16502-5E
MB91301 Series
(4) Normal Bus Access Read/Write Operation
(VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
CS0 to CS7 setup
tCSLCH
CS0 to CS7 hold
tCHCSH
Pin name
Condition
SYSCLK,
CS0 to CS7
Value
Unit Remarks
Min
Max
3
⎯
ns
3
tCYC / 2 + 4
ns
tASCH
SYSCLK,
A23 to A00
3
⎯
ns
tASWL
WR0 to WR3,
A23 to A00
4
⎯
ns
tASRL
RD, A23 to A00
5
⎯
ns
tCHAX
SYSCLK,
A23 to A00
3
tCYC / 2 + 4
ns
tWHAX
WR0 to WR3,
A23 to A00
tCYC / 2 − 5
⎯
ns
tRHAX
RD, A23 to A00
tCYC / 2 − 7
⎯
ns
Valid address→
Valid data input time
tAVDV
A23 to A00,
D31 to D00
⎯
3 / 2×tCYC −
11
ns
WR0 to WR3 delay time
tCHWL
⎯
6
ns
WR0 to WR3 delay time
tCHWH
SYSCLK, WR,
WR0 to WR3
⎯
6
ns
WR0 to WR3 minimum pulse
width
tWLWH
tCYC − 5
⎯
ns
Data setup
→WRx↑
tDSWH
tCYC
⎯
ns
WRx↑→
Data hold time
tWHDX
WR,
WR0 to WR3,
D31 to D00
5
⎯
ns
RD delay time
tCHRL
⎯
6
ns
RD delay time
tCHRH
SYSCLK,
RD
⎯
10
ns
RD↓→
Valid data input time
tRLDV
⎯
tCYC − 10
ns
Data setup
→RD↑ time
tDSRH
10
⎯
ns
RD↑→
Data hold time
tRHDX
0
⎯
ns
RD minimum pulse width
tRLRH
RD
tCYC − 5
⎯
ns
AS setup
tASLCH
tCYC / 2 − 6
⎯
ns
AS hold
tCHASH
SYSCLK,
AS
3
⎯
ns
UUB/ULB/LUB/LLB set up
tBLCH
tCYC / 2 − 6
⎯
ns
UUB/ULB/LUB/LLB hold
tCHBH
SYSCLK, UUB/
ULB/LUB/LLB
3
⎯
ns
Address setup
Address hold
WR,
WR0 to WR3
RD,
D31 to D00
⎯
*
*
* : When the bus is delayed by automatic wait insertion or RDY input, add (tCYC × number of wait cycles) to the rated
values.
DS07-16502-5E
105
MB91301 Series
tCYC
BA1
MCLK
SYSCLK
VOH
VOH
VOH
tASLCH
VOH
tCHASH
VOH
AS
(LBA)
VOL
tCSLCH
CS0 to CS7
tCHCSH
VOH
VOL
tASCH
A23 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
RD
VOH
VOL
tASRL
tRHAX
tRHDX
tRLDV
tDSRH
tAVDV
D31 to D00
VOH
VOL
tCHWL
VOH
VOL
tCHWH
tWLWH
WR0 to WR3
WR
VOH
tASWL
VOL
tWHAX
(at WR-control)
tWHDX
tDSWH
D31 to D00
VOH
VOL
tBLCH
VOH
VOL
Write
tCHBH
WR0 to WR3
(UUB, ULB,
LUB, LLB)
(at WR-control)
106
DS07-16502-5E
MB91301 Series
(5) BAA Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
BAA setup
tCHBAH
BAA hold
tCHBAL
Pin name
Condition
SYSCLK,
BAA
⎯
Value
Unit
Min
Max
tCYC / 2 − 6
⎯
ns
3
⎯
ns
Remarks
tCYC
VOH
VOH
MCLK
SYSCLK
tCHBAL
tCHBAH
BAA
DS07-16502-5E
107
MB91301 Series
(6) Ready Input Timings
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Symbol
Pin name
Condition
RDY setup time
→SYSCLK↓
tRDYS
SYSCLK
RDY
SYSCLK↓→
RDY hold time
tRDYH
SYSCLK
RDY
Parameter
Value
Unit
Min
Max
⎯
10
⎯
ns
⎯
0
⎯
ns
Remarks
tCYC
SYSCLK
MCLK
VOH
VOH
VOL
VOL
tRDYS
tRDYS
tRDYH
tRDYH
RDY
(Wait specified
by RDY)
VOH
VOL
VOH
VOL
RDY
(No wait specified
by RDY)
108
VOH
VOH
VOL
VOL
DS07-16502-5E
MB91301 Series
(7) Hold Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Symbol
Parameter
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
Pin floating
→BGRNT ↓time
tXHAL
BGRNT ↑→pin valid time
tHAHV
Pin name
Condition
SYSCLK,
BGRNT
⎯
BGRNT,
each pins
Value
Unit
Min
Max
⎯
6
ns
⎯
6
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Remarks
Note : The time from receiving BRQ to BGRNT changing is one cycle or more.
tCYC
SYSCLK
MCLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL
BGRNT
tCHBGH
VOH
VOL
tXHAL
tHAHV
Other pins
High-Z
DS07-16502-5E
109
MB91301 Series
(8) SDRAM Timing
(VCC = 3.0 V to 3.6 V , VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Output clock cycle time
tCYCSD
“H” level clock pulse width
tCHSD
“L” level clock pulse width
tCLSD
MCLKO↑→ output delay
time
tODSDCKE
Output hold time
tOHSDCKE
MCLKO↑→ output delay
time
tODSDRAS
Output hold time
tOHSDRAS
MCLKO↑→ output delay
time
tODSDCAS
Output hold time
tOHSDCAS
MCLKO↑→ output delay
time
tODSDWE
Output hold time
tOHSDWE
MCLK
Condition
⎯
MCLKE
SRAS
SCAS
SWE
⎯
MCLKO↑→ output delay
time
tODSDCS
Output hold time
tOHSDCS
MCLKO↑→ output delay
time
tODSDA
Output hold time
tOHSDA
MCLKO↑→ output delay
time
tODSDDQM
Output hold time
tOHSDDQM
MCLKO↑→ output delay
time
tODSDD
Output hold time
tOHSDD
Data input setup time
tISSDD
Data input hold time
tIHSDD
110
Pin name
CS6, CS7
A00 to A15
DQMUU,
DQMUL,
DQMLU,
DQMLL
D00 to D31
D00 to D31
⎯
Value
Unit
Min
Max
⎯
68
MHz
5
⎯
ns
5
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
⎯
11
ns
2
⎯
ns
4
⎯
ns
2
⎯
ns
Remarks
DS07-16502-5E
MB91301 Series
tCYCSD
MCLKO
tCHSD
tCLSD
MCLKO
tODSDCKE
tODSDRAS
tODSDCAS
tODSDWE
tODSDCS
tODSDA
tODSDDQM
MCLKE
SRAS
SCAS
SWE
CS6
CS7
A00 to A15
DQMUU
DQMUL
DQMLU
DQMLL
tOHSDCKE
tOHSDRAS
tOHSDCAS
tOHSDWE
tOHSDCS
tOHSDA
tOHSDDQM
tODSDD
D00 to D31
output
tOHSDD
D00 to D31
input
tISSDD
DS07-16502-5E
tIHSDD
111
MB91301 Series
(9) UART Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0 to SCK2
SCK↓ →SO delay time
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
Valid SI →SCK↑
tIVSH
SCK0 to SCK2,
SIN0 to SIN2
SCK↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
Parameter
Condition
Value
Unit
Min
Max
8 tCYCP
⎯
ns
−80
+80
ns
100
⎯
ns
SCK0 to SCK2,
SIN0 to SIN2
60
⎯
ns
tSHSL
SCK0 to SCK2
4 tCYCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK2
4 tCYCP
⎯
ns
SCK↓ →SOT delay time
tSLOV
SCK0 to SCK2,
SOT0 to SOT2
⎯
150
ns
Valid SIN→SCK↑
tIVSH
SCK0 to SCK2,
SIN0 to SIN2
60
⎯
ns
SCK↑→ valid SIN hold time
tSHIX
SCK0 to SCK2,
SIN0 to SIN2
60
⎯
ns
Internal
shift clock
mode
External
shift clock
mode
Remarks
Notes : • These are the AC ratings for CLK synchronous mode.
• tCYCP is the peripheral clock cycle time.
112
DS07-16502-5E
MB91301 Series
• Internal shift clock mode
tSCYC
SCK0 to SCK2
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT2
tIVSH
tSHIX
VOH
VOL
VOH
VOL
SIN0 to SIN2
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK2
VOL
VOL
VOL
tSLOV
SOT0 to SOT2
VOH
VOL
tIVSH
SIN0 to SIN2
DS07-16502-5E
VOH
VOL
tSHIX
VOH
VOL
113
MB91301 Series
(10) Reload Timer Clock and PPG Timer Input Timings
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Condition
tTIWH
tTIWL
TIN0 to TIN2,
PPG0 to PPG3,
TRG0 to TRG3
⎯
Input pulse width
Value
Min
Max
2 tCYCP*
⎯
Unit
Remarks
ns
* : tCYCP is the peripheral clock cycle time.
TIN0 to TIN2
PPG0 to PPG3
TRG0 to TRG3
VIH
VIH
VIL
VIL
tTIWL
tTIWH
(11) Trigger Input Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Condition
A/D activation trigger input time
tATGL
ATG
⎯
Value
Min
Max
5 tCYCP*
⎯
Unit
Remarks
ns
* : tCYCP is the peripheral clock cycle time.
tATGL
ATG
VIL
114
VIL
DS07-16502-5E
MB91301 Series
(12) DMA Controller Timing
(VCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = 0 °C to +70 °C)
[For edge detection] (Block/step transfer mode, burst transfer mode)
Value
SymParameter
Pin name
Condition
Unit
Remarks
bol
Min
Max
DREQ input pulse width
⎯
DREQ0, DREQ1
tDRWL
⎯
2 tCYC
ns
Note : When fCPT > fCP, tCYC becomes same as tCP.
[For level detection] (Demand transfer mode)
Parameter
Symbol
Pin name
DSTP setup time
tDREQS
SYSCLK,
DREQ0, DREQ1
DSTP hold time
tDREQH
SYSCLK,
DREQ0, DREQ1
Condition
Value
Unit
Min
Max
10
⎯
ns
0.0
⎯
ns
Remarks
⎯
[For all operation modes]
Parameter
DACK delay time
DEOP delay time
IORD delay time
IOWR delay time
DS07-16502-5E
Symbol
tCLDL
tCLDH
tCLEL
tCLEH
tCLIRL
tCLIRH
tCLIWL
tCLIWH
Pin name
Condition
Value
Min
Max
⎯
10
⎯
10
⎯
10
⎯
10
SYSCLK,
IORD
⎯
10
⎯
10
SYSCLK,
IOWR
⎯
10
⎯
10
SYSCLK, DACK0,
DACK1
SYSCLK, DEOP0,
DEOP1
⎯
Unit
Remarks
ns
ns
ns
ns
115
MB91301 Series
tCYC
SYSCLK
MCLK
VOH
VOH
VOL
VOL
VOL
tCLDL
tCLDH
VOH
DACK0, DACK1
VOL
tCLEH
tCLEL
VOH
DEOP0, DEOP1
VOL
tCLIRL
tCLIRH
VOH
IORD
VOL
tCLIWL
tCLIWH
VOH
IOWR
VOL
tDRWL
tDREQS
VOH
DREQ0, DREQ1
DREQ0, DREQ1
116
tDREQH
VOL
VOH
VOL
DS07-16502-5E
MB91301 Series
(13) I2C Timing
• At master mode operation
(AVCC = VCC = 3.3 ± 0.3 V, AVSS = VSS = 0.0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin
fSCL
Conditions
Typical mode
Fast mode*3
Unit
Remarks
Min
Max
Min
Max
SCL0, SCL1
0
100
0
400
kHz
“L” period of SCL clock tLOW
SCL0, SCL1
4.7
⎯
1.3
⎯
μs
“H” period of SCL clock tHIGH
SCL0, SCL1
4.0
⎯
0.6
⎯
μs
BUS free time between
“STOP condition” and
“START condition”
tBUS
SDA0, SDA1
4.7
⎯
1.3
⎯
μs
SCL↓→SDA output
delay time
tHDDAT
SCL0, SCL1,
SDA0, SDA1
⎯
5 × M*1
⎯
5 × M*1
ns
Setup time of “repeat
START condition”
SCL↑→SDA↓
tSUSTA
SCL0, SCL1,
SDA0, SDA1
4.7
⎯
0.6
⎯
μs
Hold time of “repeat
START condition”
SDA↓→SCL↓
tHDSTA
SCL0, SCL1,
SDA0, SDA1
4.0
⎯
0.6
⎯
After that, the
μs first clock pulse
is generated.
Setup time of “STOP
condition”
SCL↑→SDA↑
tSUSTO
SCL0, SCL1,
SDA0, SDA1
4.0
⎯
0.6
⎯
μs
SDA data input hold
time (vs. SCL↓)
tHDDAT SDA0, SDA1
2 × M*1
⎯
2 × M*1
⎯
μs
SDA data input setup
time (vs. SCL↑)
tSUDAT SDA0, SDA1
250
⎯
100*2
⎯
ns
SCL clock frequency
R = 1 kΩ,
C = 50 pF*4
*1 : M = resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a standard mode I2C bus system as long as the device
satisfies a requirement of “tSUDAT ≥ 250 ns”.
When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the
SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDATA) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.
DS07-16502-5E
117
MB91301 Series
• At slave mode operation
(AVCC = VCC = 3.3 ± 0.3 V, AVSS = VSS = 0.0 V, Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin
fSCL
Conditions
Typical mode
Fast mode*3
Unit
Remarks
Min
Max
Min
Max
SCL0, SCL1
0
100
0
400
kHz
“L” period of SCL clock tLOW
SCL0, SCL1
4.7
⎯
1.3
⎯
μs
“H” period of SCL clock tHIGH
SCL0, SCL1
4.0
⎯
0.6
⎯
μs
BUS free time between
“STOP condition” and
“START condition”
tBUS
SDA0, SDA1
4.7
⎯
1.3
⎯
μs
SCL↓→SDA output
delay time
tHDDAT
SCL0, SCL1,
SDA0, SDA1
⎯
5 × M*1
⎯
5 × M*1
ns
Setup time of “repeat
START condition”
SCL↑→SDA↓
tSUSTA
SCL0, SCL1,
SDA0, SDA1
4.7
⎯
0.6
⎯
μs
Hold time of “repeat
START condition”
SDA↓→SCL↓
tHDSTA
SCL0, SCL1,
SDA0, SDA1
4.0
⎯
0.6
⎯
After that, the
μs first clock pulse
is generated.
Setup time of “STOP
condition”
SCL↑→SDA↑
tSUSTO
SCL0, SCL1,
SDA0, SDA1
4.0
⎯
0.6
⎯
μs
SDA data input hold
time (vs. SCL↓)
tHDDAT SDA0, SDA1
2×
M*1
⎯
2×
M*1
⎯
μs
SDA data input setup
time (vs. SCL↑)
tHDSTA SDA0, SDA1
250
⎯
100*2
⎯
ns
SCL clock frequency
R = 1 kΩ,
C = 50 pF*4
*1 : M = resource clock cycle (ns)
*2 : A high-speed mode I2C bus device can be used for a standard mode I2C bus system as long as the device
satisfies a requirement of “tSUDAT ≥ 250 ns”.
When a certain device does not extend the “L” period of the SCL signal, the next data must be output to the
SDA line within 1250 ns (maximum SDA/SCL rise time + tSUDATA) in which the SCL line is released.
*3 : For use at over 100 kHz, set the resource clock frequency to at least 6 MHz.
*4 : R and C represent the pull-up resistor and load capacitor of the SCL and SDA output lines.
VOH
VOL
SDA
tBUS
tLOW
tHDSTA
VOH
SCL
VOL
tHDSTA
tSUDAT
tHDDAT
tSUSTA
tSUSTO
tHIGH
fSCL
118
DS07-16502-5E
MB91301 Series
(14)External Interrupt Input Timing
(VCC = 3.0 V to 3.6 V, VSS = AVss = 0 V, Ta = 0 °C to +70 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tINTWH
tINTWL
INT0 to INT7
NMI
⎯
Value
Unit
Remarks
⎯
ns
*1
⎯
μs
*2
Min
Max
3 tCYCP
1.0
*1:tCYCP is the peripheral clock cycle time. Excluding the stop mode
*2:In stop mode
t INTWL
INTx
NMI
DS07-16502-5E
VILS
t INTWH
VILS
VIHS
VIHS
119
MB91301 Series
5. Electrical Characteristics for the A/D Converter
(VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, AVRH = 3.0 V to 3.6 V , Ta = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Resolution
⎯
Total error
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
BIT
⎯
⎯
−8.5
⎯
+8.5
LSB
Linearity error
⎯
⎯
−3.0
⎯
+3.0
LSB
Differential linearity error
⎯
⎯
−2.5
⎯
+2.5
LSB
Zero transition error
VOT
AN0 to AN3
−8.0
+0.5
+8.0
LSB
Full-scale transition error
VFST
AN0 to AN3
AVRH − 8.0
⎯
⎯
μs
AVRH − 1.5 AVRH + 8.0
LSB
Conversion time*1
⎯
⎯
4.1 μs
machine
clock (CLKP)
34 MHz at
operating
Analog port input current
IAIN
AN0 to AN3
⎯
0.1
10
μA
Analog input voltage
VAIN
AN0 to AN3
AVss
⎯
AVRH
V
⎯
AVRH
AVss
⎯
AVCC
V
⎯
0.6
2
mA
⎯
⎯
10
μA
⎯
0.6
2
mA
⎯
⎯
10
μA
⎯
⎯
5
LSB
Reference voltage
Power supply current
Reference voltage supply current
Variation between channels
IA
AH 2
I *
IR
IRH*2
⎯
AVCC
AVRH
AN0 to AN3
*1 : For VCC = AVCC = 3.0 V to 3.6 V , machine clock = 34 MHz
*2 : Current during reset and in stop mode (VCC = AVCC = AVRH = 3.6 V)
Notes : • The relative error increases as AVRH becomes smaller.
• Ensure that the output impedance of the external circuit connected to the analog input meets the following
condition :
Output impedance of external circuit < 7 kΩ
If the output impedance of the external circuit is too high, the analog voltage sampling time may be too
short.
120
DS07-16502-5E
MB91301 Series
• About the external impedance of the analog input and its sampling time
• A/D converter with sample & hold circuit. If the external impedance is too high to keep sufficient sampling time,
the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D
conversion precision.
• Analog input equivalent circuit
R
Comparator
Analog input
C
During sampling : ON
R
C
8.1 kΩ (Max) 10.0 pF (Max)
MB91302A
Note : The values are reference.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the peripheral clock frequency and operating frequency or
decrease the external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 100 kΩ)
(External impedance = 0 kΩ to 20 kΩ)
MB91302A
External impedance (kΩ)
External impedance (kΩ)
MB91302A
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
Minimum sampling time (μs)
35
20
18
16
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
Minimum sampling time (μs)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• About errors
As |AVRH − AVSS| becomes smaller, values of relative errors grow larger.
DS07-16502-5E
121
MB91301 Series
6. Power-on ratings
Parameter
Symbol
Value
Min
Max
Unit
Power rise time
tr
⎯
38
ms
Power start time
Voff
⎯
0.1
V
Power end voltage
Von
2.0
⎯
V
Power shutdown time
toff
1
⎯
ms
tr
Remarks
Tilt = 0.05 V / ms
toff
Von
VCC
Voff
122
DS07-16502-5E
MB91301 Series
■ PIN STATUS IN EACH CPU STATE
• Terms used in the pin status list
• Input ready
Indicates that the input function can be used.
• Input 0 fixed
Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.
• Output Hi-Z
Indicates to put the pin in a high impedance state with the pin driving transistor disabled for driving.
• Output held
Indicates the output in the output state existing immediately before this mode is established.
If the device enters this mode with an internal output peripheral operating or while serving as an output port,
the output is performed by the internal peripheral or the port output is maintained, respectively.
• Previous state held
When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.
DS07-16502-5E
123
MB91301 Series
• Pin Status List (External bus : 32 bit bus width)
Pin no.
1 to 5
Port
name
P13 to P17
Specified
function
name
D11 to D15
Function
name
At initialization (INIT)
Function
name
Bus width
32 bit
Bus width
8 bit
D11 to D15
P13 to P17
8 to 15
P20 to P27
D16 to D23
D16 to D23
P20 to P27
18 to 25
P30 to P37
D24 to D31
D24 to D31
D24 to D31
28
P80
RDY
P80
P80
29
P81
BGRNT
P81
P81
30
P82
BRQ
P82
P82
RD
RD
RD
Initial
value
Output Hi-Z
Input ready
Output Hi-Z
Input ready
Stop mode
Sleep
mode
HIZ = 0
Bus released
(BGRNT)
HIZ = 1
CS shared
P : Previous P : Previous
state held
state held
F : Output
F : Output
held or
held or
Hi-Z
Hi-Z
Output
Hi-Z/
input 0
fixed
Output Hi-Z
CS not
shared
Output Hi-Z
P : Previous
state held
F : RDY input
P : Previous P : Previous
state held
state held
F : RDY input F : RDY input
P : Previous
state held Previous
F : H output state held
L output
L output
BRQ input
BRQ input
Output Hi-Z
Previous
state held
P : Previous
state held
F : BRQ input
invalid
Output
Hi-Z/
input 0
fixed
31
P83
32
P84
DQMUU/WR0 DQMUU/WR0 DQMUU/WR0
33
P85
DQMUL/WR1
DQMUL/WR1
P85
34
P86
DQMLU/WR2
DQMLU/WR2
P86
35
P87
DQMLL/WR3
DQMLL/WR3
P87
36
P90
SYSCLK
SYSCLK
SYSCLK
Asserted
P : Previous
: L output
state held
Negated
F : SYSCLK
: CLK output
output
P : Previous
state held
F : H or L output
Output
Hi-Z/
input 0
fixed
F : CLK
output
F : CLK
output
37
P91
MCLKE
MCLKE
MCLKE
H output
F : L output
F : Output
Hi-Z
Output Hi-Z
H output
38
P92
MCLK
MCLK
MCLK
Asserted
P : Previous P : Previous
: L output
F : Output
state held
state held
Negated
Hi-Z
F : H output F : H output
: CLK output
Output Hi-Z
F : CLK
output
39
P93
⎯
P93
P93
Output Hi-Z
Input ready
Previous
state held
Output
Hi-Z
Port
Function
Port
Function
40
P94
SRAS/LBA/
AS
P94
P94
Output Hi-Z
Input ready
P : Previous
state held H output
F : H output
Output
Hi-Z
Output Hi-Z
F : H output
41
P95
SCAS/BAA
P95
P95
Output Hi-Z
Input ready
P : Previous
state held H output
F : H output
Output
Hi-Z
Output Hi-Z
H output
42
P96
SWE/WR
P96
P96
Output Hi-Z
Input ready
P : Previous
state held Previous
state held
F : SWE
output
Output
Hi-Z/
input 0
fixed
Output Hi-Z
Previous
state held
45 to 52
P40 to P47
A00 to A07
A00 to A07
A00 to A07
55 to 62
P50 to P57
A08 to A15
A08 to A15
A08 to A15
64 to 67
P60 to P63
A16 to A19
A16 to A19
A16 to A19
68
P64
A20/SDA0
A20
A20
FF output
Output Hi-Z
P65
A21/SCL0
A21
A21
Output
Hi-Z/
input 0
fixed
Output Hi-Z
69
P : Previous
state held The same as
F : Address
stated left
output
70
P66
A22/SDA1
A22
A22
71
P67
A23/SCL1
A23
A23
76 to 79
⎯
AN3 to AN0
AN3 to AN0
AN3 to AN0
input invalid
Previous
state held
input
invalid
Previous
state held
Previous
state held
Output Hi-Z
Input ready
P : Previous P : Previous P : Output
state held
state held
Hi-Z
F : Normal
F : Input
F : Input
operation
ready
ready
Normal
operation
Normal
operation
81
PG0
INT0/ICU0
PG0
PG0
82
PG1
INT1/ICU1
PG1
PG1
83
PG2
INT2/ICU2
PG2
PG2
84
PG3
INT3/ICU3
PG3
PG3
H output
F : H output
P : Previous
Previous
state held
state held
F : H output
F : L output
Previous
state held
input invalid
(Continued)
124
DS07-16502-5E
MB91301 Series
(Continued)
Stop mode
At initialization (INIT)
Pin no.
Port
name
Specified
function
name
Function
name
Function
name
Bus width
32 bit
Bus width
8 bit
85
PG4
INT4/ATG/
FRCK
PG4
PG4
86
PG5
INT5/SIN2
PG5
PG5
87
PG6
INT6/SOT2
PG6
PG6
88
PG7
INT7/SCK2
PG7
PG7
90
PJ0
SIN0
PJ0
PJ0
91
PJ1
SOT0
PJ1
PJ1
92
PJ2
SCK0
PJ2
PJ2
93
PJ3
SIN1
PJ3
PJ3
94
PJ4
SOT1
PJ4
PJ4
95
PJ5
SCK1
PJ5
PJ5
96
PJ6
PPG0
PJ6
PJ6
97
PJ7
TRG0
PJ7
PJ7
98
PH0
TIN0
PH0
PH0
99
PH1
TIN1/PPG3
PH1
PH1
100
PH2
TIN2/TRG3
PH2
PH2
103
PB0
DREQ0
PB0
PB0
104
PB1
DACK0
PB1
PB1
105
PB2
DEOP0
PB2
PB2
106
PB3
DREQ1
PB3
PB3
107
PB4
DACK1/TRG1
PB4
PB4
108
PB5
DEOP1/PPG1
PB5
PB5
109
PB6
IOWR
PB6
PB6
110
PB7
IORD
PB7
PB7
122
PA0
CS0
CS0
CS0
123
PA1
CS1
CS1
CS1
124
PA2
CS2
CS2
CS2
125
PA3
CS3
CS3
CS3
126
PA4
CS4/TRG2
CS4
CS4
127
PA5
CS5/PPG2
CS5
CS5
128
PA6
CS6
CS6
CS6
129
PA7
132 to 139 P00 to P07
142 to 144 P10 to P12
CS7
CS7
CS7
D00 to D07
D00 to D07
P00 to P07
D08 to D10
D08 to D10
P10 to P12
Sleep
mode
Initial
value
Bus released
(BGRNT)
HIZ = 0
HIZ = 1
CS
shared
CS not
shared
Output Hi-Z
Input ready
P : Previous P : Previous P : Output
state held
state held
Hi-Z
F : Normal
F : Input
F : Input
operation
ready
ready
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output HiZ/input 0
fixed
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output HiZ/input 0
fixed
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held
F : Normal
operation
Output HiZ/input 0
fixed
Normal
operation
Normal
operation
Output
Hi-Z
F : SREN = F : SREN =
0:H
0:H
output,
output,
SREN =
SREN =
1 : Out1 : Output Hi-Z
put Hi-Z
Previous
state held
H output
H output
H output
Output Hi-Z
Input ready
P : Previous P : Previous
state held
state held Output HiF : Output
F : Output
Z/input 0
held or
held or
fixed
Hi-Z
Hi-Z
Output Hi-Z Output Hi-Z
P : General-purpose port selected, F : Specified function selected
Notes : • The bus width is determined after a mode vector fetch.
• The bus width at initialization time is 8 bits.
DS07-16502-5E
125
MB91301 Series
• Pin Status List (External bus : 16 bit bus width)
Pin no.
Port
name
Specified
function
name
Function
name
Bus width
16 bit
Bus width
8 bit
1 to 5
P13 to P17
D11 to D15
P13 to P17
P13 to P17
8 to 15
P20 to P27
D16 to D23
D16 to D23
P20 to P27
18 to 25
P30 to P37
D24 to D31
D24 to D31
D24 to D31
28
P80
RDY
P80
P80
29
P81
BGRNT
P81
P81
BRQ
P82
Stop mode
At initialization (INIT)
Function
name
Initial
value
Output Hi-Z
Input ready
Sleep
mode
P : Previous
state
held
F : Output
held or
Hi-Z
HIZ = 0
HIZ = 1
P : Previous
state held Output HiF : Output
Z/input 0
held or
fixed
Hi-Z
P : Previous
state held
F : RDY input
Output Hi-Z
Input ready
P : Previous
state held
F : H output
Previous
state held
Output HiZ/input 0
fixed
P : Previous
state held
F : BRQ
input invalid
P82
Bus released
(BGRNT)
CS
shared
CS not
shared
Output Hi-Z Output Hi-Z
P : Previous
state
held
F : RDY
input
P : Previous
state
held
F : RDY
input
L output
L output
BRQ input
BRQ input
30
P82
31
P83
RD
RD
RD
32
P84
DQMUU/WR0
DQMUU/WR0
DQMUU/WR0
33
P85
DQMUL/WR1
DQMUL/WR1
P85
34
P86
DQMLU/WR2
P86
P86
35
P87
DQMLL/WR3
P87
P87
36
P90
SYSCLK
SYSCLK
SYSCLK
Asserted
P : Previous P : Previous
: L output
state held
state held
Negated
F : SYSCLK F : H or L
: CLK output
output
output
Output HiZ/input 0
fixed
F : CLK
output
37
P91
MCLKE
MCLKE
MCLKE
H output
F : Output
Hi-Z
Output Hi-Z H output
38
P92
MCLK
MCLK
MCLK
39
P93
⎯
P93
40
P94
SRAS/LBA/
AS
41
P95
42
H output
F : H output
P : Previous
Previous
state held
state held
F : H output
F : L output
F : L output
Output Hi-Z Output Hi-Z
F : CLK
output
Asserted
P : Previous P : Previous
: L output
F : Output
state held
state held
Negated
Hi-Z
F : H output F : H output
: CLK output
Output Hi-Z
P93
Output Hi-Z
Input ready
Previous
state held
Previous
state held
Previous
state held
Output Hi-Z Output Hi-Z
P94
P94
Output Hi-Z
Input ready
P : Previous
state held
F : H output
H output
Output Hi-Z Output Hi-Z F : H output
SCAS/BAA
P95
P95
Output Hi-Z
Input ready
P : Previous
state held H output
F : H output
Output Hi-Z Output Hi-Z H output
P96
SWE/WR
P96
P96
Output Hi-Z
Input ready
P : Previous
state held Previous
F : SWE out- state held
put
Output HiZ/input 0
fixed
Output Hi-Z
FF output
P : Previous
state
held
F : Address
output
The same as
stated left
Output HiZ/input 0
fixed
Output Hi-Z Output Hi-Z
input invalid
Previous
state held
input invalid
input invalid
Previous
state held
45 to 52
P40 to P47
A00 to A07
A00 to A07
A00 to A07
55 to 62
P50 to P57
A08 to A15
A08 to A15
A08 to A15
64 to 67
P60 to P63
A16 to A19
A16 to A19
A16 to A19
68
P64
A20/SDA0
A20
A20
69
P65
A21/SCL0
A21
A21
70
P66
A22/SDA1
A22
A22
71
P67
A23/SCL1
A23
A23
76 to 79
⎯
AN3 to AN0
AN3 to AN0
AN3 to AN0
F : CLK
output
Previous
state held
Previous
state held
(Continued)
126
DS07-16502-5E
MB91301 Series
(Continued)
Pin no.
Port
name
Specified
function
name
Function
name
Function
name
Bus width
16 bit
Bus width
8 bit
81
PG0
INT0/ICU0
PG0
PG0
82
PG1
INT1/ICU1
PG1
PG1
83
PG2
INT2/ICU2
PG2
PG2
84
PG3
INT3/ICU3
PG3
PG3
85
PG4
INT4/ATG/
FRCK
PG4
PG4
86
PG5
INT5/SIN2
PG5
PG5
87
PG6
INT6/SOT2
PG6
PG6
88
PG7
INT7/SCK2
PG7
PG7
90
PJ0
SIN0
PJ0
PJ0
91
PJ1
SOT0
PJ1
PJ1
92
PJ2
SCK0
PJ2
PJ2
93
PJ3
SIN1
PJ3
PJ3
94
PJ4
SOT1
PJ4
PJ4
95
PJ5
SCK1
PJ5
PJ5
96
PJ6
PPG0
PJ6
PJ6
97
PJ7
TRG0
PJ7
PJ7
98
PH0
TIN0
PH0
PH0
99
PH1
TIN1/PPG3
PH1
PH1
100
PH2
TIN2/TRG3
PH2
PH2
103
PB0
DREQ0
PB0
PB0
104
PB1
DACK0
PB1
PB1
105
PB2
DEOP0
PB2
PB2
106
PB3
DREQ1
PB3
PB3
107
PB4
DACK1/TRG1
PB4
PB4
108
PB5
DEOP1/PPG1
PB5
PB5
109
PB6
IOWR
PB6
PB6
110
PB7
IORD
PB7
PB7
122
PA0
CS0
CS0
CS0
123
PA1
CS1
CS1
CS1
124
PA2
CS2
CS2
CS2
125
PA3
CS3
CS3
CS3
126
PA4
CS4/TRG2
CS4
CS4
127
PA5
CS5/PPG2
CS5
CS5
128
PA6
CS6
CS6
CS6
129
PA7
CS7
CS7
CS7
D00 to D07
P00 to P07
P00 to P07
132 to 139 P00 to P07
142 to 144 P10 to P12
D08 to D10
P10 to P12
Stop mode
At initialization (INIT)
P10 to P12
Sleep
mode
Initial
value
HIZ = 0
HIZ = 1
Bus released
(BGRNT)
CS
shared
CS not
shared
Output Hi-Z
Input ready
P : Previous P : Previous P : Output
state held
state held
Hi-Z
F : Normal
F : Input
F : Input
operation
ready
ready
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous P : Previous P : Output
state held
state held
Hi-Z
F : Normal
F : Input
F : Input
operation
ready
ready
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output
Hi-Z/input 0
fixed
Normal
operation
Normal
operation
H output
H output
F : SREN = F : SREN =
0:H
0:H
output,
output,
Output Hi-Z
SREN =
SREN =
1 : Out1 : Output Hi-Z
put Hi-Z
Output Hi-Z
Input ready
P : Previous P : Previous
state held
state held Output
F : Output
F : Output
Hi-Z/input 0
held or
held or
fixed
Hi-Z
Hi-Z
H output
Output Hi-Z Output Hi-Z
P : General-purpose port selected, F : Specified function selected
Notes : • The bus width is determined after a mode vector fetch.
• The bus width at initialization time is 8 bits.
DS07-16502-5E
127
MB91301 Series
• Pin Status List (External bus : 8 bit bus width)
Pin no.
Port
name
Specified
function
name
Function
name
Bus width
8 bit
Bus width
8 bit
1 to 5
P13 to P17
D11 to D15
P13 to P17
P13 to P17
8 to 15
P20 to P27
D16 to D23
P20 to P27
P20 to P27
18 to 25
P30 to P37
D24 to D31
D24 to D31
D24 to D31
28
P80
RDY
P80
P80
29
P81
BGRNT
P81
P81
BRQ
P82
Stop mode
At initialization (INIT)
Function
name
Initial
value
Output Hi-Z
Input ready
Output Hi-Z
Input ready
Sleep mode
HIZ = 0
CS
shared
CS not
shared
P : Previous
P : Previous
state held Output
state held
F : Output
Hi-Z/input
F : Output held
held or
0 fixed
or Hi-Z
Hi-Z
Output Hi-Z Output Hi-Z
P : Previous
state held
F : RDY input
P : Previous P : Previous
state
state
held
held
F : RDY
F : RDY
input
input
P : Previous
state held
F : H output
Previous
state held
P : Previous
state held
F : BRQ
input invalid
P82
HIZ = 1
Bus released
(BGRNT)
Output
Hi-Z/input
0 fixed
L output
L output
BRQ input
BRQ input
30
P82
31
P83
RD
RD
RD
32
P84
DQMUU/WR0
DQMUU/WR0
DQMUU/WR0
33
P85
DQMUL/WR1
P85
P85
34
P86
DQMLU/WR2
P86
P86
35
P87
DQMLL/WR3
P87
P87
36
P90
SYSCLK
SYSCLK
SYSCLK
37
P91
MCLKE
MCLKE
MCLKE
38
P92
MCLK
MCLK
MCLK
39
P93
⎯
P93
P93
Output Hi-Z
Input ready
Previous state Previous
held
state held
Previous
state held
Output Hi-Z Output Hi-Z
40
P94
SRAS/LBA/AS
P94
P94
Output Hi-Z
Input ready
P : Previous
state held
F : H output
H output
Output
Hi-Z
Output Hi-Z F : H output
41
P95
SCAS/BAA
P95
P95
Output Hi-Z
Input ready
P : Previous
state held
F : H output
H output
Output
Hi-Z
Output Hi-Z H output
42
P96
SWE/WR
P96
P96
Output Hi-Z
Input ready
P : Previous
Previous
state held
state held
F : SWE output
Output
Hi-Z/input
0 fixed
Output Hi-Z
FF output
P : Previous
state held
F : Address
output
H output
P : Previous
state held
F : H output
Previous
state held
Output Hi-Z Output Hi-Z
Asserted
P : Previous
: L output
state held
Negated
F : SYSCLK
: CLK output
output
P : Previous
Output
state held
Hi-Z/input
F : H or L
0 fixed
output
F : CLK
output
H output
F : L output
F : H output
F : L output
Asserted
P : Previous
: L output
state held
Negated
F : H output
: CLK output
F : Output
Hi-Z
P : Previous
F : Output
state held
Hi-Z
F : H output
F : CLK
output
Output Hi-Z H output
Output Hi-Z
F : CLK
output
Previous
state held
45 to 52
P40 to P47
A00 to A07
A00 to A07
A00 to A07
55 to 62
P50 to P57
A08 to A15
A08 to A15
A08 to A15
64 to 67
P60 to P63
A16 to A19
A16 to A19
A16 to A19
68
P64
A20/SDA0
A20
A20
69
P65
A21/SCL0
A21
A21
70
P66
A22/SDA1
A22
A22
71
P67
A23/SCL1
A23
A23
76 to 79
⎯
AN3 to AN0
AN3 to AN0
AN3 to AN0
input invalid
Previous state
input invalid
held
Previous
state held
Previous
state held
81
PG0
INT0/ICU0
PG0
PG0
Output Hi-Z
Input ready
P : Previous
P : Previous P : Output
state held
state held
Hi-Z
Normal
F : Normal op- F : Input
F : Input
operation
eration
ready
ready
Normal
operation
Output
The same as
Hi-Z/input
stated left
0 fixed
input
invalid
Output Hi-Z Output Hi-Z
(Continued)
128
DS07-16502-5E
MB91301 Series
(Continued)
Pin no.
Port
name
Specified
function
name
Function
name
Bus width
8 bit
At initialization (INIT)
Function
name
Bus width
8 bit
82
PG1
INT1/ICU1
PG1
PG1
83
PG2
INT2/ICU2
PG2
PG2
84
PG3
INT3/ICU3
PG3
PG3
85
PG4
INT4/ATG/
FRCK
PG4
PG4
86
PG5
INT5/SIN2
PG5
PG5
87
PG6
INT6/SOT2
PG6
PG6
88
PG7
INT7/SCK2
PG7
PG7
90
PJ0
SIN0
PJ0
PJ0
91
PJ1
SOT0
PJ1
PJ1
92
PJ2
SCK0
PJ2
PJ2
93
PJ3
SIN1
PJ3
PJ3
94
PJ4
SOT1
PJ4
PJ4
95
PJ5
SCK1
PJ5
PJ5
96
PJ6
PPG0
PJ6
PJ6
97
PJ7
TRG0
PJ7
PJ7
98
PH0
TIN0
PH0
PH0
99
PH1
TIN1/PPG3
PH1
PH1
100
PH2
TIN2/TRG3
PH2
PH2
103
PB0
DREQ0
PB0
PB0
PB1
104
PB1
DACK0
PB1
105
PB2
DEOP0
PB2
PB2
106
PB3
DREQ1
PB3
PB3
107
PB4
DACK1/TRG1
PB4
PB4
108
PB5
DEOP1/PPG1
PB5
PB5
109
PB6
IOWR
PB6
PB6
110
PB7
IORD
PB7
PB7
122
PA0
CS0
CS0
CS0
123
PA1
CS1
CS1
CS1
124
PA2
CS2
CS2
CS2
125
PA3
CS3
CS3
CS3
126
PA4
CS4/TRG2
CS4
CS4
127
PA5
CS5/PPG2
CS5
CS5
128
PA6
CS6
CS6
CS6
129
PA7
132 to 139 P00 to P07
142 to 144 P10 to P12
CS7
CS7
CS7
D00 to D07
P00 to P07
P00 to P07
D08 to D10
P10 to P12
P10 to P12
Stop mode
Sleep
mode
Initial
value
HIZ = 0
HIZ = 1
Output Hi-Z
Input ready
P : Previous P : Previous P : Output
state held
state held
Hi-Z
F : Normal
F : Input
F : Input
operation
ready
ready
Output Hi-Z
Input ready
Bus released
(BGRNT)
CS
shared
CS not
shared
Normal
operation
Normal
operation
P : Previous
state held Previous
F : Normal
state held
operation
Output
Normal
Hi-Z/input 0
operation
fixed
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output
Normal
Hi-Z/input 0
operation
fixed
Normal
operation
Output Hi-Z
Input ready
P : Previous
state held Previous
F : Normal
state held
operation
Output
Normal
Hi-Z/input 0
operation
fixed
Normal
operation
H output
H output
F : SREN = F : SREN =
0:H
0:H
output,
output,
Output Hi-Z
SREN =
SREN =
1 : Out1 : Output Hi-Z
put Hi-Z
Output Hi-Z
Input ready
P : Previous P : Previous
state held
state held Output
F : Output
F : Output
Hi-Z/input 0 Output Hi-Z Output Hi-Z
held or
held or
fixed
Hi-Z
Hi-Z
H output
P : General-purpose port selected, F : Specified function selected
Notes : • The bus width is determined after a mode vector fetch.
• The bus width at initialization time is 8 bits.
DS07-16502-5E
129
MB91301 Series
• Pin Status List (Single chip mode)
At initialization (INIT)
Pin no.
Port name
Specified function name
Function name
Initial value
Bus width
8 bit
Internal ROM
mode vector
(MD2-0 = 000)
Stop mode
Sleep mode
HIZ
=0
1 to 5
P13 to P17
⎯
P13 to P17
8 to 15
P20 to P27
⎯
P20 to P27
Previous state
held
Previous state
held
18 to 25
P30 to P37
⎯
P30 to P37
Output Hi-Z
Output Hi-Z
28
P80
⎯
P80
29
P81
⎯
P81
30
P82
⎯
P82
31
P83
⎯
P83
32
P84
⎯
P84
33
P85
⎯
P85
34
P86
⎯
P86
35
P87
⎯
P87
Previous state
held
Previous state
held
36
P90
⎯
P90
37
P91
⎯
P91
38
P92
⎯
P92
39
P93
⎯
P93
40
P94
SRAS
P94
41
P95
SCAS/BAA
P95
42
P96
SWE/WR
P96
45 to 52
P40 to P47
⎯
P40 to P47
55 to 62
P50 to P57
⎯
P50 to P57
64 to 67
P60 to P63
⎯
P60 to P63
68
P64
SDA0
P64
69
P65
SCL0
P65
70
P66
SDA1
P66
71
P67
SCL1
P67
76 to 79
⎯
AN0 to AN3
AN0 to AN3
Output Hi-Z/
Input ready
Output Hi-Z/
input 0 fixed
Output Hi-Z
81
PG0
INT0/ICU0
PG0
82
PG1
INT1/ICU1
PG1
83
PG2
INT2/ICU2
PG2
84
PG3
INT3/ICU3
PG3
85
PG4
INT4/ATG/FRCK
PG4
86
PG5
INT5/SIN2
PG5
87
PG6
INT6/SOT2
PG6
88
PG7
INT7/SCK2
PG7
90
PJ0
SIN0
PJ0
91
PJ1
SOT0
PJ1
92
PJ2
SCK0
PJ2
93
PJ3
SIN1
PJ3
94
PJ4
SOT1
PJ4
95
PJ5
SCK1
PJ5
HIZ = 1
Output Hi-Z
Previous state
held
Input invalid
Input invalid
Previous state
held
Output Hi-Z/
Input ready
input invalid
P : Output Hi-Z
F : Input ready
P : Previous state
held
F : Input ready
Previous
state held
Output Hi-Z/
input 0 fixed
(Continued)
130
DS07-16502-5E
MB91301 Series
(Continued)
At initialization (INIT)
Pin no.
Port name
Specified function name
Function name
Initial value
Bus width
8 bit
Internal ROM
mode vector
(MD2-0 = 000)
96
PJ6
PPG0
PJ6
97
PJ7
TRG0
PJ7
98
PH0
TIN0
PH0
99
PH1
TIN1/PPG3
PH1
100
PH2
TIN2/TRG3
PH2
103
PB0
⎯
PB0
104
PB1
⎯
PB1
105
PB2
⎯
PB2
106
PB3
⎯
PB3
107
PB4
TRG1
PB4
108
PB5
PPG1
PB5
109
PB6
⎯
PB6
110
PB7
⎯
PB7
122
PA0
⎯
PA0
123
PA1
⎯
PA1
124
PA2
⎯
PA2
125
PA3
⎯
PA3
126
PA4
TRG2
PA4
127
PA5
PPG2
PA5
128
PA6
⎯
PA6
129
PA7
⎯
PA7
132 to 139
P00 to P07
⎯
P00 to P07
142 to 144
P10 to P12
⎯
P10 to P12
Output Hi-Z/
Input ready
Stop mode
Sleep mode
HIZ
Previous state
held
=0
Previous state
held
HIZ = 1
Output Hi-Z/
input 0 fixed
P : General-purpose port selected, F : Specified function selected
Notes : • The bus width is determined after a mode vector fetch.
• The bus width at initialization time is 8 bits.
DS07-16502-5E
131
MB91301 Series
■ EXAMPLE CHARACTERISTICS
ICC − External VCC (PLL On)
Internal frequency = 68 MHz, Ta = + 25 °C
140
140
120
120
100
100
80
ICC
ICCS
60
ICC [mA]
ICC [mA]
ICC − Internal frequency (PLL On)
External VCC = 3.6 V, Ta = + 25 °C
80
40
40
20
20
0
2.7
0
10
20
30
40
50
60
70
80
3
3.3
3.6
3.9
Internal frequency [MHz]
External VCC [V]
VOL − External VCC
Internal frequency = 68 MHz, Ta = + 25 °C
VOH − External VCC
Internal frequency = 68 MHz, Ta = + 25 °C
0.8
4
0.6
3
VOH [V]
VOL [V]
0
ICC
ICCS
60
0.4
0.2
2
1
0
2.7
3
3.3
3.6
3.9
External VCC [V]
0
2.7
3
3.3
3.6
3.9
External VCC [V]
IIL − External VCC
Internal frequency = 68 MHz, Ta = + 25 °C
0
IIL [μA]
100
200
300
400
2.7
3
3.3
3.6
3.9
External VCC [V]
132
DS07-16502-5E
MB91301 Series
■ ORDERING IMFORMATION
Part No.
Package
MB91302APFF-G-001-BNDE1
MB91302APFF-G-010-BNDE1
MB91302APFF-G-020-BNDE1
Remarks
Without ROM
144-pin Plastic LQFP
(FPT-144P-M12)
MB91302APFF-G-XXX-BNDE1
Optional real time OS internal model
Built-in IPL (Internal Program Loader)
version
User ROM version
MB91V301A-RDK01*
179-pin Ceramic PGA
(PGA-179C-A03)
Development pack for MB91302A real
time OS internal model (MB91V301A
and CD-ROM for development)
MB91V301A
179-pin Ceramic PGA
(PGA-179C-A03)
Evaluation chip
* : In case of buying this product, it is necessary to make a contract with “MB91V301A-RDK01 Fujitsu software
product use contract”.
DS07-16502-5E
133
MB91301 Series
■ PACKAGE DIMENSIONS
144-pin plastic LQFP
(FPT-144P-M12)
144-pin plastic LQFP
(FPT-144P-M12)
Lead pitch
0.40 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP144-16×16-0.40
Note 1) * : These dimensions include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
+.016
*16.00 –0.10 .630 –.004 SQ
73
108
72
109
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
37
144
LEAD No.
1
"A"
0.60±0.15
(.024±.006)
36
0.40(.016)
0.18±0.035
.007±.001
+0.05
0.07(.003)
M
©2003-2008
FUJITSU MICROELECTRONICS LIMITED F144024S-c-3-4
C
2003 FUJITSU LIMITED F144024S-c-3-3
0.145 –0.03
.006
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
+.002
–.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
134
DS07-16502-5E
MB91301 Series
(Continued)
179-pin ceramic PGA
Lead pitch
2.54mm(100mil)
Pin matrix
15
Sealing method
Metal seal
(PGA-179C-A03)
179-pin ceramic PGA
(PGA-179C-A03)
2.54±0.25
(.100±.010)
35.56(1.400)
REF
1.27(.050)TYP DIA
INDEX
INDEX AREA
+0.18
0.46 –0.05 DIA
+.007
.018 –.002
1.27±0.25
(.050±.010)
38.10±0.51 SQ
(1.500±.020)
6.10(.240)
MAX
C
1994-2008 FUJITSU MICROELECTRONICS LIMITED R179004SC-3-3
+0.41
3.40 –0.36
+.016
.134 –.014
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-16502-5E
135
MB91301 Series
■ MAIN CHANGES IN THIS EDITION
Page
120
Section
Change Results
■ ELECTRICAL CHARACTERISTICS Corrected the footnote*2 as follows.
5. Electrical Characteristics for the A/D Current when A/D converter not operating and CPU in stop
Converter
mode → Current during reset and in stop mode
Corrected the sentence in “• About the external impedance of
the analog input and its sampling time” as follows.
121
To satisfy the A/D conversion precision standard, consider the
relationship between the external impedance and minimum
sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the
sampling time is longer than the minimum value.
→
To satisfy the A/D conversion precision standard, consider the
relationship between the external impedance and minimum
sampling time and either adjust the peripheral clock frequency
and operating frequency or decrease the external impedance
so that the sampling time is longer than the minimum value.
The vertical lines marked in the left side of the page show the changes.
136
DS07-16502-5E
MB91301 Series
MEMO
DS07-16502-5E
137
MB91301 Series
MEMO
138
DS07-16502-5E
MB91301 Series
MEMO
DS07-16502-5E
139
MB91301 Series
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